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/*
* Copyright 2019 Google Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__
#define __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__
#include "arch/arm/utility.hh"
#include "arch/generic/isa.hh"
namespace gem5
{
namespace Iris
{
class ISA : public BaseISA
{
public:
ISA(const Params &p) : BaseISA(p) {}
void serialize(CheckpointOut &cp) const override;
void copyRegsFrom(ThreadContext *src) override;
bool
inUserMode() const override
{
ArmISA::CPSR cpsr = tc->readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
return ArmISA::inUserMode(cpsr);
}
PCStateBase *
newPCState(Addr new_inst_addr=0) const override
{
return new ArmISA::PCState(new_inst_addr);
}
RegVal
readMiscRegNoEffect(RegIndex idx) const override
{
panic("readMiscRegNoEffect not implemented.");
}
RegVal
readMiscReg(RegIndex idx) override
{
panic("readMiscReg not implemented.");
}
void
setMiscRegNoEffect(RegIndex idx, RegVal val) override
{
panic("setMiscRegNoEffect not implemented.");
}
void
setMiscReg(RegIndex idx, RegVal val) override
{
panic("setMiscReg not implemented.");
}
};
} // namespace Iris
} // namespace gem5
#endif // __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__