src/mem/dramsys.hh

/*
 * Copyright (c) 2022 Fraunhofer IESE
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 * neither the name of the copyright holders nor the names of its
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 * this software without specific prior written permission.
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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#ifndef __MEM_DRAMSYS_H__
#define __MEM_DRAMSYS_H__

#include "DRAMSysConfiguration.h"
#include "mem/abstract_mem.hh"
#include "mem/dramsys_wrapper.hh"
#include "params/DRAMSys.hh"

namespace gem5
{

namespace memory
{

class DRAMSys : public AbstractMemory
{
    PARAMS(DRAMSys);
    sc_gem5::TlmTargetWrapper<32> tlmWrapper;

  public:
    DRAMSys(Params const &params)
        : AbstractMemory(params),
          tlmWrapper(dramSysWrapper.tSocket,
              params.name + ".tlm",
              InvalidPortID),
          config(DRAMSysConfiguration::from_path(
              params.configuration,
              params.resource_directory)),
          dramSysWrapper(params.name.c_str(),
            config,
            params.recordable,
            params.range)
    {
    }

    gem5::Port &getPort(const std::string &if_name, PortID idx) override
    {
        if (if_name != "tlm")
        {
            return AbstractMemory::getPort(if_name, idx);
        }

        return tlmWrapper;
    }

  private:
    DRAMSysConfiguration::Configuration config;
    DRAMSysWrapper dramSysWrapper;
};

} // namespace memory
} // namespace gem5

#endif // __MEM_DRAMSYS_HH__