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// Copyright (c) 2006-2007 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
def operand_types {{
'sb' : 'int8_t',
'ub' : 'uint8_t',
'shw' : 'int16_t',
'uhw' : 'uint16_t',
'sw' : 'int32_t',
'uw' : 'uint32_t',
'sdw' : 'int64_t',
'udw' : 'uint64_t',
'tudw' : 'std::array<uint64_t, 2>',
'tuw' : 'std::array<uint32_t, 2>',
'sf' : 'float',
'df' : 'double',
'pstate' : 'PSTATE',
'hpstate' : 'HPSTATE'
}};
output header {{
// A function to "decompress" double and quad floating point
// register numbers stuffed into 5 bit fields. These have their
// MSB put in the LSB position but are otherwise normal.
static inline unsigned int
dfpr(unsigned int regNum)
{
return (regNum & (~1)) | ((regNum & 1) << 5);
}
static inline unsigned int
dfprl(unsigned int regNum)
{
return dfpr(regNum) & (~0x1);
}
static inline unsigned int
dfprh(unsigned int regNum)
{
return dfpr(regNum) | 0x1;
}
}};
def operands {{
# Int regs default to unsigned, but code should not count on this.
# For clarity, descriptions that depend on unsigned behavior should
# explicitly specify '.uq'.
'Rd': IntRegOp('udw', 'RD', 'IsInteger', 1),
# The Rd from the previous window
'Rd_prev': IntRegOp('udw',
'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2),
# The Rd from the next window
'Rd_next': IntRegOp('udw',
'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3),
# For microcoded twin load instructions, RdTwin appears in the "code"
# for the instruction is replaced by RdLow or RdHigh by the format
# before it's processed by the iop.
# The low (even) register of a two register pair
'RdLow': IntRegOp('udw', 'RD & (~1)', 'IsInteger', 4),
# The high (odd) register of a two register pair
'RdHigh': IntRegOp('udw', 'RD | 1', 'IsInteger', 5),
'Rs1': IntRegOp('udw', 'RS1', 'IsInteger', 6),
'Rs2': IntRegOp('udw', 'RS2', 'IsInteger', 7),
# A microcode register. Right now, this is the only one.
'uReg0': IntRegOp('udw', 'INTREG_UREG0', 'IsInteger', 8),
# Because double and quad precision register numbers are decoded
# differently, they get different operands. The single precision versions
# have an s post pended to their name.
'Frds': FloatRegOp('sf', 'RD', 'IsFloating', 10),
#'Frd': FloatRegOp('df', 'dfpr(RD)', 'IsFloating', 10),
'Frd_low': FloatRegOp('uw', 'dfprl(RD)', 'IsFloating', 10),
'Frd_high': FloatRegOp('uw', 'dfprh(RD)', 'IsFloating', 10),
# Each Frd_N refers to the Nth double precision register from Frd.
# Note that this adds twice N to the register number.
#'Frd_0': FloatRegOp('df', 'dfpr(RD)', 'IsFloating', 10),
'Frd_0_low': FloatRegOp('uw', 'dfprl(RD)', 'IsFloating', 10),
'Frd_0_high': FloatRegOp('uw', 'dfprh(RD)', 'IsFloating', 10),
#'Frd_1': FloatRegOp('df', 'dfpr(RD) + 2', 'IsFloating', 10),
'Frd_1_low': FloatRegOp('uw', 'dfprl(RD) + 2', 'IsFloating', 10),
'Frd_1_high': FloatRegOp('uw', 'dfprh(RD) + 2', 'IsFloating', 10),
#'Frd_2': FloatRegOp('df', 'dfpr(RD) + 4', 'IsFloating', 10),
'Frd_2_low': FloatRegOp('uw', 'dfprl(RD) + 4', 'IsFloating', 10),
'Frd_2_high': FloatRegOp('uw', 'dfprh(RD) + 4', 'IsFloating', 10),
#'Frd_3': FloatRegOp('df', 'dfpr(RD) + 6', 'IsFloating', 10),
'Frd_3_low': FloatRegOp('uw', 'dfprl(RD) + 6', 'IsFloating', 10),
'Frd_3_high': FloatRegOp('uw', 'dfprh(RD) + 6', 'IsFloating', 10),
#'Frd_4': FloatRegOp('df', 'dfpr(RD) + 8', 'IsFloating', 10),
'Frd_4_low': FloatRegOp('uw', 'dfprl(RD) + 8', 'IsFloating', 10),
'Frd_4_high': FloatRegOp('uw', 'dfprh(RD) + 8', 'IsFloating', 10),
#'Frd_5': FloatRegOp('df', 'dfpr(RD) + 10', 'IsFloating', 10),
'Frd_5_low': FloatRegOp('uw', 'dfprl(RD) + 10', 'IsFloating', 10),
'Frd_5_high': FloatRegOp('uw', 'dfprh(RD) + 10', 'IsFloating', 10),
#'Frd_6': FloatRegOp('df', 'dfpr(RD) + 12', 'IsFloating', 10),
'Frd_6_low': FloatRegOp('uw', 'dfprl(RD) + 12', 'IsFloating', 10),
'Frd_6_high': FloatRegOp('uw', 'dfprh(RD) + 12', 'IsFloating', 10),
#'Frd_7': FloatRegOp('df', 'dfpr(RD) + 14', 'IsFloating', 10),
'Frd_7_low': FloatRegOp('uw', 'dfprl(RD) + 14', 'IsFloating', 10),
'Frd_7_high': FloatRegOp('uw', 'dfprh(RD) + 14', 'IsFloating', 10),
'Frs1s': FloatRegOp('sf', 'RS1', 'IsFloating', 11),
#'Frs1': FloatRegOp('df', 'dfpr(RS1)', 'IsFloating', 11),
'Frs1_low': FloatRegOp('uw', 'dfprl(RS1)', 'IsFloating', 11),
'Frs1_high': FloatRegOp('uw', 'dfprh(RS1)', 'IsFloating', 11),
'Frs2s': FloatRegOp('sf', 'RS2', 'IsFloating', 12),
#'Frs2': FloatRegOp('df', 'dfpr(RS2)', 'IsFloating', 12),
'Frs2_low': FloatRegOp('uw', 'dfprl(RS2)', 'IsFloating', 12),
'Frs2_high': FloatRegOp('uw', 'dfprh(RS2)', 'IsFloating', 12),
'PC': PCStateOp('udw', 'pc', (None, None, 'IsControl'), 30),
'NPC': PCStateOp('udw', 'npc', (None, None, 'IsControl'), 30),
'NNPC': PCStateOp('udw', 'nnpc',
(None, None, 'IsControl'), 30),
# Registers which are used explicitly in instructions
'R0': IntRegOp('udw', '0', None, 6),
'R1': IntRegOp('udw', '1', None, 7),
'R15': IntRegOp('udw', '15', 'IsInteger', 8),
'R16': IntRegOp('udw', '16', None, 9),
'O0': IntRegOp('udw', 'INTREG_O0', 'IsInteger', 10),
'O1': IntRegOp('udw', 'INTREG_O1', 'IsInteger', 11),
'O2': IntRegOp('udw', 'INTREG_O2', 'IsInteger', 12),
'O3': IntRegOp('udw', 'INTREG_O3', 'IsInteger', 13),
'O4': IntRegOp('udw', 'INTREG_O4', 'IsInteger', 14),
'O5': IntRegOp('udw', 'INTREG_O5', 'IsInteger', 15),
# Control registers
'Y': IntRegOp('udw', 'INTREG_Y', None, 40),
'Ccr': IntRegOp('udw', 'INTREG_CCR', None, 41),
'Asi': ControlRegOp('udw', 'MISCREG_ASI', None, 42),
'Fprs': ControlRegOp('udw', 'MISCREG_FPRS', None, 43),
'Pcr': ControlRegOp('udw', 'MISCREG_PCR', None, 44),
'Pic': ControlRegOp('udw', 'MISCREG_PIC', None, 45),
'Gsr': IntRegOp('udw', 'INTREG_GSR', None, 46),
'Softint': ControlRegOp('udw', 'MISCREG_SOFTINT', None, 47),
'SoftintSet': ControlRegOp('udw', 'MISCREG_SOFTINT_SET', None, 48),
'SoftintClr': ControlRegOp('udw', 'MISCREG_SOFTINT_CLR', None, 49),
'TickCmpr': ControlRegOp('udw', 'MISCREG_TICK_CMPR', None, 50),
'Stick': ControlRegOp('udw', 'MISCREG_STICK', None, 51),
'StickCmpr': ControlRegOp('udw', 'MISCREG_STICK_CMPR', None, 52),
'Tpc': ControlRegOp('udw', 'MISCREG_TPC', None, 53),
'Tnpc': ControlRegOp('udw', 'MISCREG_TNPC', None, 54),
'Tstate': ControlRegOp('udw', 'MISCREG_TSTATE', None, 55),
'Tt': ControlRegOp('udw', 'MISCREG_TT', None, 56),
'Tick': ControlRegOp('udw', 'MISCREG_TICK', None, 57),
'Tba': ControlRegOp('udw', 'MISCREG_TBA', None, 58),
'Pstate': ControlRegOp('pstate', 'MISCREG_PSTATE', None, 59),
'Tl': ControlRegOp('udw', 'MISCREG_TL', None, 60),
'Pil': ControlRegOp('udw', 'MISCREG_PIL', None, 61),
'Cwp': ControlRegOp('udw', 'MISCREG_CWP',
(None, None, ['IsSerializeAfter',
'IsSerializing',
'IsNonSpeculative']), 62),
'Cansave': IntRegOp('udw', 'INTREG_CANSAVE', None, 63),
'Canrestore': IntRegOp('udw', 'INTREG_CANRESTORE', None, 64),
'Cleanwin': IntRegOp('udw', 'INTREG_CLEANWIN', None, 65),
'Otherwin': IntRegOp('udw', 'INTREG_OTHERWIN', None, 66),
'Wstate': IntRegOp('udw', 'INTREG_WSTATE', None, 67),
'Gl': ControlRegOp('udw', 'MISCREG_GL', None, 68),
'Hpstate': ControlRegOp('hpstate', 'MISCREG_HPSTATE', None, 69),
'Htstate': ControlRegOp('udw', 'MISCREG_HTSTATE', None, 70),
'Hintp': ControlRegOp('udw', 'MISCREG_HINTP', None, 71),
'Htba': ControlRegOp('udw', 'MISCREG_HTBA', None, 72),
'HstickCmpr': ControlRegOp('udw', 'MISCREG_HSTICK_CMPR', None, 73),
'Hver': ControlRegOp('udw', 'MISCREG_HVER', None, 74),
'StrandStsReg': ControlRegOp('udw', 'MISCREG_STRAND_STS_REG',
None, 75),
'Fsr': ControlRegOp('udw', 'MISCREG_FSR',
(None, None, ['IsSerializeAfter',
'IsSerializing',
'IsNonSpeculative']), 80),
# Mem gets a large number so it's always last
'Mem': MemOp('udw', None, (None, 'IsLoad', 'IsStore'), 100)
}};