| # Copyright (c) 2015 Jason Power | |
| # All rights reserved. | |
| # | |
| # Redistribution and use in source and binary forms, with or without | |
| # modification, are permitted provided that the following conditions are | |
| # met: redistributions of source code must retain the above copyright | |
| # notice, this list of conditions and the following disclaimer; | |
| # redistributions in binary form must reproduce the above copyright | |
| # notice, this list of conditions and the following disclaimer in the | |
| # documentation and/or other materials provided with the distribution; | |
| # neither the name of the copyright holders nor the names of its | |
| # contributors may be used to endorse or promote products derived from | |
| # this software without specific prior written permission. | |
| # | |
| # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
| # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
| # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
| # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
| # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
| # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
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| # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| """ | |
| This is the ARM equivalent to `simple.py` (which is designed to run using the | |
| X86 ISA). More detailed documentation can be found in `simple.py`. | |
| """ | |
| import m5 | |
| from m5.objects import * | |
| system = System() | |
| system.clk_domain = SrcClockDomain() | |
| system.clk_domain.clock = "1GHz" | |
| system.clk_domain.voltage_domain = VoltageDomain() | |
| system.mem_mode = "timing" | |
| system.mem_ranges = [AddrRange("512MB")] | |
| system.cpu = ArmTimingSimpleCPU() | |
| system.membus = SystemXBar() | |
| system.cpu.icache_port = system.membus.cpu_side_ports | |
| system.cpu.dcache_port = system.membus.cpu_side_ports | |
| system.cpu.createInterruptController() | |
| system.mem_ctrl = MemCtrl() | |
| system.mem_ctrl.dram = DDR3_1600_8x8() | |
| system.mem_ctrl.dram.range = system.mem_ranges[0] | |
| system.mem_ctrl.port = system.membus.mem_side_ports | |
| system.system_port = system.membus.cpu_side_ports | |
| thispath = os.path.dirname(os.path.realpath(__file__)) | |
| binary = os.path.join( | |
| thispath, | |
| "../../../", | |
| "tests/test-progs/hello/bin/arm/linux/hello", | |
| ) | |
| system.workload = SEWorkload.init_compatible(binary) | |
| process = Process() | |
| process.cmd = [binary] | |
| system.cpu.workload = process | |
| system.cpu.createThreads() | |
| root = Root(full_system=False, system=system) | |
| m5.instantiate() | |
| print("Beginning simulation!") | |
| exit_event = m5.simulate() | |
| print("Exiting @ tick %i because %s" % (m5.curTick(), exit_event.getCause())) |