arch-sparc: Revamp the float registers.
Change-Id: Iec52e15f1529319345795496a82a37e1f0aeebae
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49769
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index 279bd1a..c1fd399 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -71,7 +71,7 @@
ISA::ISA(const Params &p) : BaseISA(p)
{
_regClasses.emplace_back(int_reg::NumRegs, debug::IntRegs);
- _regClasses.emplace_back(NumFloatRegs, debug::FloatRegs);
+ _regClasses.emplace_back(float_reg::NumRegs, debug::FloatRegs);
_regClasses.emplace_back(1, debug::IntRegs); // Not applicable for SPARC
_regClasses.emplace_back(2, debug::IntRegs); // Not applicable for SPARC
_regClasses.emplace_back(1, debug::IntRegs); // Not applicable for SPARC
@@ -253,8 +253,9 @@
// Then loop through the floating point registers.
- for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) {
- tc->setFloatReg(i, src->readFloatReg(i));
+ for (int i = 0; i < SparcISA::float_reg::NumArchRegs; ++i) {
+ RegId reg(FloatRegClass, i);
+ tc->setReg(reg, src->getReg(reg));
}
// Copy misc. registers
diff --git a/src/arch/sparc/regs/float.hh b/src/arch/sparc/regs/float.hh
index 3588090..78f4db5 100644
--- a/src/arch/sparc/regs/float.hh
+++ b/src/arch/sparc/regs/float.hh
@@ -35,9 +35,13 @@
namespace SparcISA
{
-const int NumFloatRegs = 64;
-const int NumFloatArchRegs = NumFloatRegs;
+namespace float_reg
+{
+const int NumRegs = 64;
+const int NumArchRegs = NumRegs;
+
+} // namespace float_reg
} // namespace SparcISA
} // namespace gem5
