src/cpu/testers/traffic_gen/exit_gen.hh

/*
 * Copyright (c) 2017-2018 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
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 * this software without specific prior written permission.
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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/**
 * @file
 * Declaration of the exit generator that ends the simulation
 */

#ifndef __CPU_TRAFFIC_GEN_EXIT_GEN_HH__
#define __CPU_TRAFFIC_GEN_EXIT_GEN_HH__

#include "base_gen.hh"

/**
 * The exit generator exits from the simulation
 * once entered.
 */
class ExitGen : public BaseGen
{

  public:

    ExitGen(SimObject &obj, MasterID master_id, Tick _duration)
        : BaseGen(obj, master_id, _duration)
    { }

    void enter();

    PacketPtr getNextPacket();

    Tick nextPacketTick(bool elastic, Tick delay) const;

};

#endif