src/mem/ruby/system/HTMSequencer.hh

/*
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 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
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#ifndef __MEM_RUBY_SYSTEM_HTMSEQUENCER_HH__
#define __MEM_RUBY_SYSTEM_HTMSEQUENCER_HH__

#include <cassert>
#include <iostream>

#include "mem/htm.hh"
#include "mem/ruby/protocol/HtmCallbackMode.hh"
#include "mem/ruby/protocol/HtmFailedInCacheReason.hh"
#include "mem/ruby/system/RubyPort.hh"
#include "mem/ruby/system/Sequencer.hh"
#include "params/RubyHTMSequencer.hh"

class HTMSequencer : public Sequencer
{
  public:
    HTMSequencer(const RubyHTMSequencerParams &p);
    ~HTMSequencer();

    // callback to acknowledge HTM requests and
    // notify cpu core when htm transaction fails in cache
    void htmCallback(Addr,
                     const HtmCallbackMode,
                     const HtmFailedInCacheReason);

    bool empty() const override;
    void print(std::ostream& out) const override;
    void regStats() override;
    void wakeup() override;

  private:
    /**
     * Htm return code conversion
     *
     * This helper is a hack meant to convert the autogenerated ruby
     * enum (HtmFailedInCacheReason) to the manually defined one
     * (HtmCacheFailure). This is needed since the cpu code would
     * otherwise have to include the ruby generated headers in order
     * to handle the htm return code.
    */
    HtmCacheFailure htmRetCodeConversion(const HtmFailedInCacheReason rc);

    void rubyHtmCallback(PacketPtr pkt, const HtmFailedInCacheReason fail_r);

    RequestStatus insertRequest(PacketPtr pkt,
                                RubyRequestType primary_type,
                                RubyRequestType secondary_type) override;

    // Private copy constructor and assignment operator
    HTMSequencer(const HTMSequencer& obj);
    HTMSequencer& operator=(const HTMSequencer& obj);

    // table/queue for hardware transactional memory commands
    // these do not have an address so a deque/queue is used instead.
    std::deque<SequencerRequest*> m_htmCmdRequestTable;

    Tick m_htmstart_tick;
    Counter m_htmstart_instruction;

    //! Histogram of cycle latencies of HTM transactions
    Stats::Histogram m_htm_transaction_cycles;
    //! Histogram of instruction lengths of HTM transactions
    Stats::Histogram m_htm_transaction_instructions;
    //! Causes for HTM transaction aborts
    Stats::Vector m_htm_transaction_abort_cause;
};

inline std::ostream&
operator<<(std::ostream& out, const HTMSequencer& obj)
{
    obj.print(out);
    out << std::flush;
    return out;
}

#endif // __MEM_RUBY_SYSTEM_HTMSEQUENCER_HH__