| commit | 69e3e508c72196003c744b4dce4b68d968726d2c | [log] [tgz] |
|---|---|---|
| author | Jason Lowe-Power <jason@lowepower.com> | Thu Sep 10 12:06:56 2020 -0700 |
| committer | Bobby R. Bruce <bbruce@ucdavis.edu> | Fri Sep 11 05:31:31 2020 +0000 |
| tree | 79f29dd27e4d692d18c131cb7625c7e40cdeaae8 | |
| parent | 28d41f213a83ce0ec2a65ff6227550662b022c8d [diff] |
tests: Update x86 system.py for MemCtrl interface Change-Id: If4103b197720f74df70d0a24602e2b3715936826 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34315 Maintainer: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: mike upton <michaelupton@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/tests/gem5/x86-boot-tests/system/system.py b/tests/gem5/x86-boot-tests/system/system.py index b050b6f..7b9bd68 100755 --- a/tests/gem5/x86-boot-tests/system/system.py +++ b/tests/gem5/x86-boot-tests/system/system.py
@@ -171,8 +171,8 @@ def _createMemoryControllers(self, num, cls): self.mem_cntrls = [ - cls(range = self.mem_ranges[0], - port = self.membus.master) + MemCtrl(dram = cls(range = self.mem_ranges[0]), + port = self.membus.master) for i in range(num) ]