x86: Mark translation as delayed in case of a hw page table walk
This information is used by the LSQ in the O3 cpu (since commit
"51becd2... cpu-o3: O3 LSQ Generalisation")
Change-Id: I35fe7e2f8428641d863af0e79e28b0b259fb0b00
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18508
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 33de058..84965b8 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -443,6 +443,8 @@
TLB::translate(req, tc, translation, mode, delayedResponse, true);
if (!delayedResponse)
translation->finish(fault, req, tc, mode);
+ else
+ translation->markDelayed();
}
Walker *
