commit 6d37f2877ef27dcec1eb1d39e7f06b3e2386bcb8
author Adrian Herrera <adrian.herrera@arm.com> Thu Dec 12 16:25:46 2019 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Mon Jan 06 15:44:49 2020 +0000
tree 6821eb4b45b8c204429a4acabb18d633244b86af
parent 44e3c95555b380f62c3fa4d878d78f26ad035475

dev-arm: GICv3, handle GICR_ICFGR0 WI behaviour

Architecture states write accesses to GICR_ICFGR0 are WI. This patch
implements handling of this behaviour instead of crashing as an invalid
offset. This is required to support certain software behaviour.

Change-Id: I1f8c57838566c360d243a925306ec35c64a920b2
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24063
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/dev/arm/gic_v3_redistributor.cc

diff --git a/src/dev/arm/gic_v3_redistributor.cc b/src/dev/arm/gic_v3_redistributor.cc
index 75fd9b3..f071c5b 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -579,6 +579,9 @@
 
         break;
 
+      case GICR_ICFGR0: // SGI Configuration Register
+        // WI
+        return;
       case GICR_ICFGR1: { // PPI Configuration Register
           int first_intid = Gicv3::SGI_MAX;