misc: Merge branch 'release-staging-v20.1.0.0' into develop
Change-Id: I1eacbc5719aa85c5a7650ec33fd99f673fdf443d
diff --git a/src/arch/arm/kvm/arm_cpu.hh b/src/arch/arm/kvm/arm_cpu.hh
index 28453d7..cc3c935 100644
--- a/src/arch/arm/kvm/arm_cpu.hh
+++ b/src/arch/arm/kvm/arm_cpu.hh
@@ -71,7 +71,7 @@
/** KVM ID */
const uint64_t id;
/** gem5 index */
- const IntRegIndex idx;
+ const ArmISA::IntRegIndex idx;
/** Name in debug output */
const char *name;
};
@@ -80,7 +80,7 @@
/** KVM ID */
const uint64_t id;
/** gem5 index */
- const MiscRegIndex idx;
+ const ArmISA::MiscRegIndex idx;
/** Name in debug output */
const char *name;
};
diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index b8ada8d..1001f81 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -42,6 +42,8 @@
#include "debug/KvmContext.hh"
#include "params/ArmV8KvmCPU.hh"
+using namespace ArmISA;
+
// Unlike gem5, kvm doesn't count the SP as a normal integer register,
// which means we only have 31 normal integer registers.
constexpr static unsigned NUM_XREGS = NUM_ARCH_INTREGS - 1;
diff --git a/src/arch/arm/kvm/armv8_cpu.hh b/src/arch/arm/kvm/armv8_cpu.hh
index 9870510..dae9fe7 100644
--- a/src/arch/arm/kvm/armv8_cpu.hh
+++ b/src/arch/arm/kvm/armv8_cpu.hh
@@ -93,27 +93,27 @@
protected:
/** Mapping between integer registers in gem5 and KVM */
struct IntRegInfo {
- IntRegInfo(uint64_t _kvm, IntRegIndex _idx, const char *_name)
+ IntRegInfo(uint64_t _kvm, ArmISA::IntRegIndex _idx, const char *_name)
: kvm(_kvm), idx(_idx), name(_name) {}
/** Register index in KVM */
uint64_t kvm;
/** Register index in gem5 */
- IntRegIndex idx;
+ ArmISA::IntRegIndex idx;
/** Name to use in debug dumps */
const char *name;
};
/** Mapping between misc registers in gem5 and registers in KVM */
struct MiscRegInfo {
- MiscRegInfo(uint64_t _kvm, MiscRegIndex _idx, const char *_name,
- bool _is_device = false)
+ MiscRegInfo(uint64_t _kvm, ArmISA::MiscRegIndex _idx,
+ const char *_name, bool _is_device = false)
: kvm(_kvm), idx(_idx), name(_name), is_device(_is_device) {}
/** Register index in KVM */
uint64_t kvm;
/** Register index in gem5 */
- MiscRegIndex idx;
+ ArmISA::MiscRegIndex idx;
/** Name to use in debug dumps */
const char *name;
/** is device register? (needs 'effectful' state update) */
@@ -137,7 +137,7 @@
/** Mapping between gem5 misc registers and registers in kvm */
static const std::vector<ArmV8KvmCPU::MiscRegInfo> miscRegMap;
/** Device registers (needing "effectful" MiscReg writes) */
- static const std::set<MiscRegIndex> deviceRegSet;
+ static const std::set<ArmISA::MiscRegIndex> deviceRegSet;
/** Mapping between gem5 ID misc registers and registers in kvm */
static const std::vector<ArmV8KvmCPU::MiscRegInfo> miscRegIdMap;
diff --git a/src/arch/arm/kvm/base_cpu.cc b/src/arch/arm/kvm/base_cpu.cc
index 04c5d0f..6fd2651 100644
--- a/src/arch/arm/kvm/base_cpu.cc
+++ b/src/arch/arm/kvm/base_cpu.cc
@@ -45,6 +45,8 @@
#include "params/BaseArmKvmCPU.hh"
#include "params/GenericTimer.hh"
+using namespace ArmISA;
+
#define INTERRUPT_ID(type, vcpu, irq) ( \
((type) << KVM_ARM_IRQ_TYPE_SHIFT) | \
((vcpu) << KVM_ARM_IRQ_VCPU_SHIFT) | \
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index c9e8ae6..ad91f3a 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -194,13 +194,13 @@
def connectCachedPorts(self, bus):
for p in self._cached_ports:
- exec('self.%s = bus.cpu_side_ports' % p)
+ exec('self.%s = bus.slave' % p)
def connectUncachedPorts(self, bus):
for p in self._uncached_interrupt_response_ports:
- exec('self.%s = bus.mem_side_ports' % p)
+ exec('self.%s = bus.master' % p)
for p in self._uncached_interrupt_request_ports:
- exec('self.%s = bus.cpu_side_ports' % p)
+ exec('self.%s = bus.slave' % p)
def connectAllPorts(self, cached_bus, uncached_bus = None):
self.connectCachedPorts(cached_bus)
diff --git a/src/cpu/tmp.ipynb b/src/cpu/tmp.ipynb
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/cpu/tmp.ipynb
diff --git a/src/dev/x86/i82094aa.cc b/src/dev/x86/i82094aa.cc
index c7817dc..bb28a8a 100644
--- a/src/dev/x86/i82094aa.cc
+++ b/src/dev/x86/i82094aa.cc
@@ -79,7 +79,7 @@
Port &
X86ISA::I82094AA::getPort(const std::string &if_name, PortID idx)
{
- if (if_name == "int_request")
+ if (if_name == "int_requestor")
return intRequestPort;
if (if_name == "inputs")
return *inputs.at(idx);
diff --git a/src/mem/ruby/slicc_interface/Controller.py b/src/mem/ruby/slicc_interface/Controller.py
index 2c6c655..1f9c0db 100644
--- a/src/mem/ruby/slicc_interface/Controller.py
+++ b/src/mem/ruby/slicc_interface/Controller.py
@@ -66,5 +66,8 @@
Param.Cycles(1, "Default latency for requests added to the " \
"mandatory queue on top-level controllers")
- memory = RequestPort("Port for attaching a memory controller")
+ memory_out_port = RequestPort("Port for attaching a memory controller")
+ memory = DeprecatedParam(memory_out_port, "The request port for Ruby "
+ "memory output to the main memory is now called `memory_out_port`")
+
system = Param.System(Parent.any, "system object parameter")
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index 4fc41c9..fc011cc 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -61,13 +61,13 @@
memResponsePort(csprintf("%s-mem-response-port", name()), this,
p->ruby_system->getAccessBackingStore(), -1,
p->no_retry_on_stall),
- gotAddrRanges(p->port_request_ports_connection_count),
+ gotAddrRanges(p->port_interrupt_out_port_connection_count),
m_isCPUSequencer(p->is_cpu_sequencer)
{
assert(m_version != -1);
// create the response ports based on the number of connected ports
- for (size_t i = 0; i < p->port_response_ports_connection_count; ++i) {
+ for (size_t i = 0; i < p->port_in_ports_connection_count; ++i) {
response_ports.push_back(new MemResponsePort(csprintf
("%s.response_ports%d", name(), i), this,
p->ruby_system->getAccessBackingStore(),
@@ -75,7 +75,7 @@
}
// create the request ports based on the number of connected ports
- for (size_t i = 0; i < p->port_request_ports_connection_count; ++i) {
+ for (size_t i = 0; i < p->port_interrupt_out_port_connection_count; ++i) {
request_ports.push_back(new PioRequestPort(csprintf(
"%s.request_ports%d", name(), i), this));
}
@@ -99,7 +99,7 @@
return memResponsePort;
} else if (if_name == "pio_response_port") {
return pioResponsePort;
- } else if (if_name == "request_ports") {
+ } else if (if_name == "interrupt_out_port") {
// used by the x86 CPUs to connect the interrupt PIO and interrupt
// response port
if (idx >= static_cast<PortID>(request_ports.size())) {
@@ -107,7 +107,7 @@
}
return *request_ports[idx];
- } else if (if_name == "response_ports") {
+ } else if (if_name == "in_ports") {
// used by the CPUs to connect the caches to the interconnect, and
// for the x86 case also the interrupt request port
if (idx >= static_cast<PortID>(response_ports.size())) {
diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py
index 6869fc2..0a28d36 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -35,18 +35,26 @@
cxx_header = "mem/ruby/system/RubyPort.hh"
version = Param.Int(0, "")
- response_ports = VectorResponsePort("CPU response port")
- slave = DeprecatedParam(response_ports,
- '`slave` is now called `response_ports`')
- request_ports = VectorRequestPort("CPU request port")
- master = DeprecatedParam(request_ports,
- '`master` is now called `request_ports`')
+ in_ports = VectorResponsePort("CPU side of this RubyPort/Sequencer. "
+ "The CPU request ports should be connected to this. If a CPU "
+ "has multiple ports (e.g., I/D ports) all of the ports for a "
+ "single CPU can connect to one RubyPort.")
+ slave = DeprecatedParam(in_ports,
+ '`slave` is now called `in_port`')
+
+ interrupt_out_port = VectorRequestPort("Port to connect to x86 interrupt "
+ "controller to send the CPU requests from outside.")
+ master = DeprecatedParam(interrupt_out_port,
+ '`master` is now called `interrupt_out_port`')
+
pio_request_port = RequestPort("Ruby pio request port")
pio_master_port = DeprecatedParam(pio_request_port,
'`pio_master_port` is now called `pio_request_port`')
+
mem_request_port = RequestPort("Ruby mem request port")
mem_master_port = DeprecatedParam(mem_request_port,
'`mem_master_port` is now called `mem_request_port`')
+
pio_response_port = ResponsePort("Ruby pio response port")
pio_slave_port = DeprecatedParam(pio_response_port,
'`pio_slave_port` is now called `pio_response_port`')
diff --git a/tests/gem5/learning_gem5/part1_test.py b/tests/gem5/learning_gem5/part1_test.py
index b57ba17..f8363ac 100644
--- a/tests/gem5/learning_gem5/part1_test.py
+++ b/tests/gem5/learning_gem5/part1_test.py
@@ -38,16 +38,6 @@
valid_isas=('X86', 'RISCV', 'ARM'),
)
-# The "long" simple tests.
-gem5_verify_config(
- name='simple_test',
- verifiers = (),
- config=joinpath(config_path, 'simple.py'),
- config_args = [],
- length = constants.long_tag,
- valid_isas=('MIPS',),
-)
-
# The "quick" two level tests.
gem5_verify_config(
name='two_level_test',
@@ -57,14 +47,3 @@
length = constants.quick_tag,
valid_isas=('X86', 'RISCV', 'ARM'),
)
-
-# The "long" two level tests.
-gem5_verify_config(
- name='two_level_test',
- verifiers = (),
- config=joinpath(config_path, 'two_level.py'),
- config_args = [],
- length = constants.long_tag,
- valid_isas=('MIPS',),
-)
-
