mem: implement ThreadBridge
ThreadBridge is used for communication between two SimObjects from
different threads (EventQueue).
Change-Id: I3e00df9184404599dfacef64b505cd0b64ee46aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65071
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/mem/SConscript b/src/mem/SConscript
index ad42fe8..3bcfc0d 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -67,6 +67,7 @@
SimObject('SerialLink.py', sim_objects=['SerialLink'])
SimObject('MemDelay.py', sim_objects=['MemDelay', 'SimpleMemDelay'])
SimObject('PortTerminator.py', sim_objects=['PortTerminator'])
+SimObject('ThreadBridge.py', sim_objects=['ThreadBridge'])
Source('abstract_mem.cc')
Source('addr_mapper.cc')
@@ -93,6 +94,7 @@
Source('snoop_filter.cc')
Source('stack_dist_calc.cc')
Source('sys_bridge.cc')
+Source('thread_bridge.cc')
Source('token_port.cc')
Source('tport.cc')
Source('xbar.cc')
diff --git a/src/mem/ThreadBridge.py b/src/mem/ThreadBridge.py
new file mode 100644
index 0000000..f0ee089
--- /dev/null
+++ b/src/mem/ThreadBridge.py
@@ -0,0 +1,60 @@
+# Copyright 2022 Google, LLC
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.SimObject import SimObject
+from m5.params import *
+
+
+class ThreadBridge(SimObject):
+ """Bridge for SimObjects from different threads (EventQueues)
+
+ When two SimObjects running on two separate threads (EventQueues), an
+ access from one side to the other side could easily cause event scheduled
+ on the wrong event queue.
+
+ ThreadBridge is used to migrate the EventQueue to the one used by
+ ThreadBridge itself before sending transation to the other side to avoid
+ the issue. The receiver side is expected to use the same EventQueue that
+ the ThreadBridge is using.
+
+ Given that this is only used for simulation speed accelerating, only the
+ atomic and functional access are supported.
+
+ Example:
+
+ sys.initator = Initiator(eventq_index=0)
+ sys.target = Target(eventq_index=1)
+ sys.bridge = ThreadBridge(eventq_index=1)
+
+ sys.initator.out_port = sys.bridge.in_port
+ sys.bridge.out_port = sys.target.in_port
+ """
+
+ type = "ThreadBridge"
+ cxx_header = "mem/thread_bridge.hh"
+ cxx_class = "gem5::ThreadBridge"
+
+ in_port = ResponsePort("Incoming port")
+ out_port = RequestPort("Outgoing port")
diff --git a/src/mem/thread_bridge.cc b/src/mem/thread_bridge.cc
new file mode 100644
index 0000000..3f76ef4
--- /dev/null
+++ b/src/mem/thread_bridge.cc
@@ -0,0 +1,121 @@
+/*
+ * Copyright 2022 Google, LLC
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "mem/thread_bridge.hh"
+
+#include "base/trace.hh"
+#include "sim/eventq.hh"
+
+namespace gem5
+{
+
+ThreadBridge::ThreadBridge(const ThreadBridgeParams &p)
+ : SimObject(p), in_port_("in_port", *this), out_port_("out_port", *this)
+{
+}
+
+ThreadBridge::IncomingPort::IncomingPort(const std::string &name,
+ ThreadBridge &device)
+ : ResponsePort(name, &device), device_(device)
+{
+}
+
+AddrRangeList
+ThreadBridge::IncomingPort::getAddrRanges() const
+{
+ return device_.out_port_.getAddrRanges();
+}
+
+// TimingResponseProtocol
+bool
+ThreadBridge::IncomingPort::recvTimingReq(PacketPtr pkt)
+{
+ panic("ThreadBridge only supports atomic/functional access.");
+}
+void
+ThreadBridge::IncomingPort::recvRespRetry()
+{
+ panic("ThreadBridge only supports atomic/functional access.");
+}
+
+// AtomicResponseProtocol
+Tick
+ThreadBridge::IncomingPort::recvAtomicBackdoor(PacketPtr pkt,
+ MemBackdoorPtr &backdoor)
+{
+ panic("ThreadBridge only supports atomic/functional access.");
+}
+Tick
+ThreadBridge::IncomingPort::recvAtomic(PacketPtr pkt)
+{
+ EventQueue::ScopedMigration migrate(device_.eventQueue());
+ return device_.out_port_.sendAtomic(pkt);
+}
+
+// FunctionalResponseProtocol
+void
+ThreadBridge::IncomingPort::recvFunctional(PacketPtr pkt)
+{
+ EventQueue::ScopedMigration migrate(device_.eventQueue());
+ device_.out_port_.sendFunctional(pkt);
+}
+
+ThreadBridge::OutgoingPort::OutgoingPort(const std::string &name,
+ ThreadBridge &device)
+ : RequestPort(name, &device), device_(device)
+{
+}
+
+void
+ThreadBridge::OutgoingPort::recvRangeChange()
+{
+ device_.in_port_.sendRangeChange();
+}
+
+// TimingRequestProtocol
+bool
+ThreadBridge::OutgoingPort::recvTimingResp(PacketPtr pkt)
+{
+ panic("ThreadBridge only supports atomic/functional access.");
+}
+void
+ThreadBridge::OutgoingPort::recvReqRetry()
+{
+ panic("ThreadBridge only supports atomic/functional access.");
+}
+
+Port &
+ThreadBridge::getPort(const std::string &if_name, PortID idx)
+{
+ if (if_name == "in_port")
+ return in_port_;
+ if (if_name == "out_port")
+ return out_port_;
+ return SimObject::getPort(if_name, idx);
+}
+
+} // namespace gem5
diff --git a/src/mem/thread_bridge.hh b/src/mem/thread_bridge.hh
new file mode 100644
index 0000000..28c9591
--- /dev/null
+++ b/src/mem/thread_bridge.hh
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2022 Google, LLC.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MEM_THREAD_BRIDGE_HH__
+#define __MEM_THREAD_BRIDGE_HH__
+
+#include "mem/port.hh"
+#include "params/ThreadBridge.hh"
+#include "sim/sim_object.hh"
+
+namespace gem5
+{
+
+class ThreadBridge : public SimObject
+{
+ public:
+ explicit ThreadBridge(const ThreadBridgeParams &p);
+
+ Port &getPort(const std::string &if_name,
+ PortID idx = InvalidPortID) override;
+
+ private:
+ class IncomingPort : public ResponsePort
+ {
+ public:
+ IncomingPort(const std::string &name, ThreadBridge &device);
+ AddrRangeList getAddrRanges() const override;
+
+ // TimingResponseProtocol
+ bool recvTimingReq(PacketPtr pkt) override;
+ void recvRespRetry() override;
+
+ // AtomicResponseProtocol
+ Tick recvAtomicBackdoor(PacketPtr pkt,
+ MemBackdoorPtr &backdoor) override;
+ Tick recvAtomic(PacketPtr pkt) override;
+
+ // FunctionalResponseProtocol
+ void recvFunctional(PacketPtr pkt) override;
+
+ private:
+ ThreadBridge &device_;
+ };
+
+ class OutgoingPort : public RequestPort
+ {
+ public:
+ OutgoingPort(const std::string &name, ThreadBridge &device);
+ void recvRangeChange() override;
+
+ // TimingRequestProtocol
+ bool recvTimingResp(PacketPtr pkt) override;
+ void recvReqRetry() override;
+
+ private:
+ ThreadBridge &device_;
+ };
+
+ IncomingPort in_port_;
+ OutgoingPort out_port_;
+};
+
+} // namespace gem5
+#endif // __MEM_THREAD_BRIDGE_HH__
