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# Author: Matteo Andreozzi
from m5.params import *
from m5.objects.QoSMemCtrl import *
from m5.objects.QoSMemSinkInterface import *
class QoSMemSinkCtrl(QoSMemCtrl):
type = 'QoSMemSinkCtrl'
cxx_header = "mem/qos/mem_sink.hh"
cxx_class = 'gem5::qos::MemSinkCtrl'
port = ResponsePort("Response ports")
interface = Param.QoSMemSinkInterface(QoSMemSinkInterface(),
"Interface to memory")
# the basic configuration of the controller architecture, note
# that each entry corresponds to a burst for the specific DRAM
# configuration (e.g. x32 with burst length 8 is 32 bytes) and not
# the cacheline size or request/packet size
write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
# memory packet size
memory_packet_size = Param.MemorySize("32B", "Memory packet size")
# request latency - minimum timing between requests
request_latency = Param.Latency("20ns", "Memory latency between requests")
# response latency - time to issue a response once a request is serviced
response_latency = Param.Latency("20ns", "Memory response latency")