| # -*- mode:python -*- | |
| # Copyright (c) 2021 Huawei International | |
| # Copyright (c) 2022 EXAscale Performance SYStems (EXAPSYS) | |
| # All rights reserved. | |
| # | |
| # Redistribution and use in source and binary forms, with or without | |
| # modification, are permitted provided that the following conditions are | |
| # met: redistributions of source code must retain the above copyright | |
| # notice, this list of conditions and the following disclaimer; | |
| # redistributions in binary form must reproduce the above copyright | |
| # notice, this list of conditions and the following disclaimer in the | |
| # documentation and/or other materials provided with the distribution; | |
| # neither the name of the copyright holders nor the names of its | |
| # contributors may be used to endorse or promote products derived from | |
| # this software without specific prior written permission. | |
| # | |
| # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
| # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
| # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
| # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
| # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
| # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
| # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
| # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| Import('*') | |
| SimObject('HiFive.py', sim_objects=['HiFive', 'GenericRiscvPciHost'], | |
| tags='riscv isa') | |
| SimObject('LupV.py', sim_objects=['LupV'], tags='riscv isa') | |
| SimObject('Clint.py', sim_objects=['Clint'], tags='riscv isa') | |
| SimObject('PlicDevice.py', sim_objects=['PlicIntDevice'], tags='riscv isa') | |
| SimObject('Plic.py', sim_objects=['Plic'], tags='riscv isa') | |
| SimObject('RTC.py', sim_objects=['RiscvRTC'], tags='riscv isa') | |
| SimObject('RiscvVirtIOMMIO.py', sim_objects=['RiscvMmioVirtIO'], | |
| tags='riscv isa') | |
| DebugFlag('Clint', tags='riscv isa') | |
| DebugFlag('Plic', tags='riscv isa') | |
| DebugFlag('VirtIOMMIO', tags='riscv isa') | |
| Source('pci_host.cc', tags='riscv isa') | |
| Source('hifive.cc', tags='riscv isa') | |
| Source('lupv.cc', tags='riscv isa') | |
| Source('clint.cc', tags='riscv isa') | |
| Source('plic_device.cc', tags='riscv isa') | |
| Source('plic.cc', tags='riscv isa') | |
| Source('rtc.cc', tags='riscv isa') | |
| Source('vio_mmio.cc', tags='riscv isa') |