src/systemc/core/SystemC.py

# Copyright 2018 Google, Inc.
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from m5.SimObject import SimObject, cxxMethod

# This class represents the systemc kernel. There should be exactly one in the
# simulation. It receives gem5 SimObject lifecycle callbacks (init, regStats,
# etc.) and manages the lifecycle of the systemc simulation accordingly.
class SystemC_Kernel(SimObject):
    type = 'SystemC_Kernel'
    cxx_class = 'sc_gem5::Kernel'
    cxx_header = 'systemc/core/kernel.hh'

# This class represents systemc sc_object instances in python config files. It
# inherits from SimObject in python, but the c++ version, sc_core::sc_object,
# doesn't inherit from gem5's c++ SimObject class.
class SystemC_ScObject(SimObject):
    type = 'SystemC_ScObject'
    abstract = True
    cxx_class = 'sc_core::sc_object'
    cxx_header = 'systemc/ext/core/sc_object.hh'

    # Clear cxx_base to stop the c++ binding code from assuming
    # sc_core::sc_object inherits from SimObject, even though SystemC_ScObject
    # does on the python side.
    cxx_base = None

    # Hide the cxx_exports from SimObject since we don't inherit from
    # SimObject on the c++ side and so don't have those methods to call down
    # into.
    locals().update({
        method.name: (lambda *a, **k: None) for method in SimObject.cxx_exports
    })

class SystemC_ScModule(SystemC_ScObject):
    type = 'SystemC_ScModule'
    abstract = True
    cxx_class = 'sc_core::sc_module'
    cxx_header = 'systemc/ext/core/sc_module.hh'

    @cxxMethod(return_value_policy="reference", cxx_name="gem5_getPort")
    def getPort(self, if_name, iex):
        return None