cpu: add a new instruction type 'Atomic'
This patch adds a new flag named 'Atomic' to support ISA implementations
that use AtomicOpFunctor to handle atomic instructions instead of a
pair of locking load and unlocking store.
Change-Id: I1fbee6e54432396cb49dfc59ad9006b75812d115
Reviewed-on: https://gem5-review.googlesource.com/8187
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
diff --git a/src/cpu/StaticInstFlags.py b/src/cpu/StaticInstFlags.py
index 55ef456..170ca6d 100644
--- a/src/cpu/StaticInstFlags.py
+++ b/src/cpu/StaticInstFlags.py
@@ -64,6 +64,7 @@
'IsMemRef', # References memory (load, store, or prefetch)
'IsLoad', # Reads from memory (load or prefetch).
'IsStore', # Writes to memory.
+ 'IsAtomic', # Does atomic RMW to memory.
'IsStoreConditional', # Store conditional instruction.
'IsIndexed', # Accesses memory with an indexed address
# computation
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 2c08a3c..93cafd6 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -505,6 +505,7 @@
bool isMemRef() const { return staticInst->isMemRef(); }
bool isLoad() const { return staticInst->isLoad(); }
bool isStore() const { return staticInst->isStore(); }
+ bool isAtomic() const { return staticInst->isAtomic(); }
bool isStoreConditional() const
{ return staticInst->isStoreConditional(); }
bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 84b3525..16b5ffd 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -144,6 +144,7 @@
bool isMemRef() const { return flags[IsMemRef]; }
bool isLoad() const { return flags[IsLoad]; }
bool isStore() const { return flags[IsStore]; }
+ bool isAtomic() const { return flags[IsAtomic]; }
bool isStoreConditional() const { return flags[IsStoreConditional]; }
bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
bool isDataPrefetch() const { return flags[IsDataPrefetch]; }