cpu: Make the ThreadContext a PCEventScope.
Both the thread and system's PCEventQueue are checked when appropriate.
Change-Id: I16c371339c91a37b5641860d974e546a30e23e13
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22105
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh b/src/arch/arm/fastmodel/iris/thread_context.hh
index 5be5e71..13ab29c 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -93,6 +93,9 @@
const std::string &iris_path);
virtual ~ThreadContext();
+ bool schedule(PCEvent *e) override { return false; }
+ bool remove(PCEvent *e) override { return false; }
+
virtual Counter
totalInsts()
{
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 95ea3f7..81bf4c1 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -413,6 +413,7 @@
do {
oldpc = thread->instAddr();
system->pcEventQueue.service(oldpc, tc);
+ thread->pcEventQueue.service(oldpc, tc);
count++;
} while (oldpc != thread->instAddr());
if (count > 1) {
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 2e5f31d..a7199d1 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -89,6 +89,8 @@
CheckerCPU *checkerCPU;
public:
+ bool schedule(PCEvent *e) override { return actualTC->schedule(e); }
+ bool remove(PCEvent *e) override { return actualTC->remove(e); }
BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); }
diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index a9d51b7..5bf3120 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -842,6 +842,7 @@
do {
oldPC = thread->instAddr();
cpu.system->pcEventQueue.service(oldPC, thread);
+ cpu.threads[thread_id]->pcEventQueue.service(oldPC, thread);
num_pc_event_checks++;
} while (oldPC != thread->instAddr());
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index df43945..23f10fe 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1114,6 +1114,8 @@
oldpc = pc[tid].instAddr();
cpu->system->pcEventQueue.service(
oldpc, thread[tid]->getTC());
+ thread[tid]->pcEventQueue.service(
+ oldpc, thread[tid]->getTC());
count++;
} while (oldpc != pc[tid].instAddr());
if (count > 1) {
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 9029aba..2ec559f 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -75,6 +75,17 @@
/** Pointer to the CPU. */
O3CPU *cpu;
+ bool
+ schedule(PCEvent *e) override
+ {
+ return thread->pcEventQueue.schedule(e);
+ }
+ bool
+ remove(PCEvent *e) override
+ {
+ return thread->pcEventQueue.remove(e);
+ }
+
/** Pointer to the thread state that this TC corrseponds to. */
O3ThreadState<Impl> *thread;
diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh
index 4b4f51e..b2c9296 100644
--- a/src/cpu/o3/thread_state.hh
+++ b/src/cpu/o3/thread_state.hh
@@ -72,7 +72,10 @@
private:
/** Pointer to the CPU. */
O3CPU *cpu;
+
public:
+ PCEventQueue pcEventQueue;
+
/* This variable controls if writes to a thread context should cause a all
* dynamic/speculative state to be thrown away. Nominally this is the
* desired behavior because the external thread context write has updated
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index df3d981..8cecf70 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -145,6 +145,8 @@
do {
oldpc = pc;
system->pcEventQueue.service(oldpc, threadContexts[curThread]);
+ threadInfo[curThread]->thread->pcEventQueue.service(
+ oldpc, threadContexts[curThread]);
pc = threadInfo[curThread]->thread->instAddr();
} while (oldpc != pc);
}
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 301e18d..86d31b2 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -126,6 +126,8 @@
return csprintf("%s.[tid:%i]", baseCpu->name(), threadId());
}
+ PCEventQueue pcEventQueue;
+
System *system;
BaseTLB *itb;
@@ -188,6 +190,9 @@
* ThreadContext interface functions.
******************************************/
+ bool schedule(PCEvent *e) override { return pcEventQueue.schedule(e); }
+ bool remove(PCEvent *e) override { return pcEventQueue.remove(e); }
+
BaseCPU *getCpuPtr() override { return baseCpu; }
int cpuId() const override { return ThreadState::cpuId(); }
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 0bd2930..749b4ca 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -51,6 +51,7 @@
#include "arch/types.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
+#include "cpu/pc_event.hh"
#include "cpu/reg_class.hh"
// @todo: Figure out a more architecture independent way to obtain the ITB and
@@ -88,7 +89,7 @@
* interface; the ExecContext is a more implicit interface that must
* be implemented so that the ISA can access whatever state it needs.
*/
-class ThreadContext
+class ThreadContext : public PCEventScope
{
protected:
typedef TheISA::MachInst MachInst;
