sim: Add HTM Generic Fault
JIRA: https://gem5.atlassian.net/browse/GEM5-587
Change-Id: Iedbf06d25330a92790123805cff50d57b613a7a5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30325
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/sim/faults.cc b/src/sim/faults.cc
index b6468ea..d4d3c11 100644
--- a/src/sim/faults.cc
+++ b/src/sim/faults.cc
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
@@ -28,6 +40,8 @@
#include "sim/faults.hh"
+#include "arch/decoder.hh"
+#include "arch/locked_mem.hh"
#include "base/logging.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
@@ -90,3 +104,24 @@
{
panic("Alignment fault when accessing virtual address %#x\n", vaddr);
}
+
+void GenericHtmFailureFault::invoke(ThreadContext *tc,
+ const StaticInstPtr &inst)
+{
+ // reset decoder
+ TheISA::Decoder* dcdr = tc->getDecoderPtr();
+ dcdr->reset();
+
+ // restore transaction checkpoint
+ const auto& checkpoint = tc->getHtmCheckpointPtr();
+ assert(checkpoint);
+ assert(checkpoint->valid());
+
+ checkpoint->restore(tc, getHtmFailureFaultCause());
+
+ // reset the global monitor
+ TheISA::globalClearExclusive(tc);
+
+ // send abort packet to ruby (in final breath)
+ tc->htmAbortTransaction(htmUid, cause);
+}
diff --git a/src/sim/faults.hh b/src/sim/faults.hh
index 62817f0..2a96ce9 100644
--- a/src/sim/faults.hh
+++ b/src/sim/faults.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
@@ -31,6 +43,7 @@
#include "base/types.hh"
#include "cpu/static_inst.hh"
+#include "mem/htm.hh"
#include "sim/stats.hh"
class ThreadContext;
@@ -44,7 +57,6 @@
virtual FaultName name() const = 0;
virtual void invoke(ThreadContext * tc, const StaticInstPtr &inst=
StaticInst::nullStaticInstPtr);
-
virtual ~FaultBase() {};
};
@@ -121,4 +133,23 @@
Addr getFaultVAddr() const { return vaddr; }
};
+class GenericHtmFailureFault : public FaultBase
+{
+ protected:
+ uint64_t htmUid; // unique identifier used for debugging
+ HtmFailureFaultCause cause;
+
+ public:
+ GenericHtmFailureFault(uint64_t htm_uid, HtmFailureFaultCause _cause)
+ : htmUid(htm_uid), cause(_cause)
+ {}
+
+ FaultName name() const override { return "Generic HTM failure fault"; }
+
+ uint64_t getHtmUid() const { return htmUid; }
+ HtmFailureFaultCause getHtmFailureFaultCause() const { return cause; }
+ void invoke(ThreadContext *tc, const StaticInstPtr &inst =
+ StaticInst::nullStaticInstPtr) override;
+};
+
#endif // __FAULTS_HH__
