commit 791092663183bcf01468ca84b6d3c177f0cf7fc7
author Jiasen Huang <jiasen.hjs@alibaba-inc.com> Mon Dec 20 12:50:39 2021 +0800
committer Huang Jiasen <jiasen.hjs@alibaba-inc.com> Wed Dec 22 01:02:22 2021 +0000
tree 9b259e6e4ac9065c89ad8b9827ca14820cbfa865
parent 0d1a40602f918eff84c0e8028bb369e8ead4a496

mem-cache: Set prefetch bit if the blk comes from Prefetch only.

Original logic setting prefetch inside serviceMSHRTargets
did not exclude the blks that both came from CORE and Prefetch

Change-Id: Iab56b9266eb64baf972b160774aca0823faea458
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54364
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>

src/mem/cache/cache.cc

diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 3c24343..466aeec 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -693,11 +693,16 @@
     bool is_invalidate = pkt->isInvalidate() &&
         !mshr->wasWholeLineWrite;
 
+    bool from_core = false;
+    bool from_pref = false;
+
     MSHR::TargetList targets = mshr->extractServiceableTargets(pkt);
     for (auto &target: targets) {
         Packet *tgt_pkt = target.pkt;
         switch (target.source) {
           case MSHR::Target::FromCPU:
+            from_core = true;
+
             Tick completion_time;
             // Here we charge on completion_time the delay of the xbar if the
             // packet comes from it, charged on headerDelay.
@@ -852,8 +857,8 @@
 
           case MSHR::Target::FromPrefetcher:
             assert(tgt_pkt->cmd == MemCmd::HardPFReq);
-            if (blk)
-                blk->setPrefetched();
+            from_pref = true;
+
             delete tgt_pkt;
             break;
 
@@ -882,6 +887,10 @@
         }
     }
 
+    if (blk && !from_core && from_pref) {
+        blk->setPrefetched();
+    }
+
     maintainClusivity(targets.hasFromCache, blk);
 
     if (blk && blk->isValid()) {

src/mem/cache/noncoherent_cache.cc

diff --git a/src/mem/cache/noncoherent_cache.cc b/src/mem/cache/noncoherent_cache.cc
index 314025f..9e95a20 100644
--- a/src/mem/cache/noncoherent_cache.cc
+++ b/src/mem/cache/noncoherent_cache.cc
@@ -245,6 +245,9 @@
     // First offset for critical word first calculations
     const int initial_offset = mshr->getTarget()->pkt->getOffset(blkSize);
 
+    bool from_core = false;
+    bool from_pref = false;
+
     MSHR::TargetList targets = mshr->extractServiceableTargets(pkt);
     for (auto &target: targets) {
         Packet *tgt_pkt = target.pkt;
@@ -254,6 +257,8 @@
             // handle deferred requests comming from a cache or core
             // above
 
+            from_core = true;
+
             Tick completion_time;
             // Here we charge on completion_time the delay of the xbar if the
             // packet comes from it, charged on headerDelay.
@@ -292,8 +297,7 @@
             // attached to this cache
             assert(tgt_pkt->cmd == MemCmd::HardPFReq);
 
-            if (blk)
-                blk->setPrefetched();
+            from_pref = true;
 
             // We have filled the block and the prefetcher does not
             // require responses.
@@ -307,6 +311,10 @@
         }
     }
 
+    if (blk && !from_core && from_pref) {
+        blk->setPrefetched();
+    }
+
     // Reponses are filling and bring in writable blocks, therefore
     // there should be no deferred targets and all the non-deferred
     // targets are now serviced.