commit 7ac4607385f8490b2a12acaef73f2f31583160f0
author Jordi Vaquero <jordi.vaquero@metempsy.com> Mon Jan 13 10:47:55 2020 +0100
committer Jordi Vaquero <jordi.vaquero@metempsy.com> Mon Jan 20 14:04:11 2020 +0000
tree 2e87b310965ee93fc00e5b3275832d87d5b15cf5
parent af02aa6a0dc89f22dd0d3b37c3fcc63c61d91417

arch-arm: Fix EL2 target exception level for SP alignment fault.

This commit fixes the target exception Level EL2 for alignmemt fault, it
is based on HCR_EL2.tge bit.

Change-Id: Ief78b2aa0c86f1c3d9a5d3ca00121d163a9d6a86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24303
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/faults.cc

diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 5a7b8e8..bd38fdc 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1541,6 +1541,14 @@
 SPAlignmentFault::SPAlignmentFault()
 {}
 
+bool
+SPAlignmentFault::routeToHyp(ThreadContext *tc) const
+{
+    assert(from64);
+    HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+    return EL2Enabled(tc) && hcr.tge==1;
+}
+
 SystemError::SystemError()
 {}
 

src/arch/arm/faults.hh

diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 3f61bc7..508fd03 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -571,6 +571,7 @@
 {
   public:
     SPAlignmentFault();
+    bool routeToHyp(ThreadContext *tc) const override;
 };
 
 /// System error (AArch64 only)