commit 7c0ab07ee2b3ee5d313b7830c10530965a2b436b
author Giacomo Travaglini <giacomo.travaglini@arm.com> Mon Oct 03 09:48:34 2022 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Mon Oct 03 17:45:10 2022 +0000
tree 0bb3a0332c8b080ead893851f50292575e59c246
parent 336e732d54b6314e3f50da8afa5d4232af9b4fea

dev-arm: Fix GICv3 GICD_ITARGETSR address range

According to the GICv3 manual, GICD_ITARGETSR address range goes from
0x0800 to 0x0c00 (as already implemented in the GICv2 model [1])

[1]: https://github.com/gem5/gem5/blob/v22.0.0.0/\
    src/dev/arm/gic_v2.cc#L64

Change-Id: I064e91d070d1a7b79f41a06ffd2197e4c07dae32
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64074
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/dev/arm/gic_v3_distributor.cc

diff --git a/src/dev/arm/gic_v3_distributor.cc b/src/dev/arm/gic_v3_distributor.cc
index 820f8bc..1cb485c 100644
--- a/src/dev/arm/gic_v3_distributor.cc
+++ b/src/dev/arm/gic_v3_distributor.cc
@@ -60,7 +60,7 @@
 const AddrRange Gicv3Distributor::GICD_ISACTIVER (0x0300, 0x0380);
 const AddrRange Gicv3Distributor::GICD_ICACTIVER (0x0380, 0x0400);
 const AddrRange Gicv3Distributor::GICD_IPRIORITYR(0x0400, 0x0800);
-const AddrRange Gicv3Distributor::GICD_ITARGETSR (0x0800, 0x0900);
+const AddrRange Gicv3Distributor::GICD_ITARGETSR (0x0800, 0x0c00);
 const AddrRange Gicv3Distributor::GICD_ICFGR     (0x0c00, 0x0d00);
 const AddrRange Gicv3Distributor::GICD_IGRPMODR  (0x0d00, 0x0d80);
 const AddrRange Gicv3Distributor::GICD_NSACR     (0x0e00, 0x0f00);