commit 7ded9b414c6cb6d8c39dcb36f3605a720ca3e336
author Daniel R. Carvalho <odanrc@yahoo.com.br> Tue Jun 08 14:27:27 2021 -0300
committer Daniel Carvalho <odanrc@yahoo.com.br> Wed Jul 07 23:18:59 2021 +0000
tree 9bff73dfc2e202685e71b2107f72a2571e68127f
parent 444cbe625006a2a47f54621b28a16d5bcd66a3e9

arch-arm: Rename debug variables

Pave the way for a "debug" namespace.

Change-Id: I1796711cbde527269637b30b0b09cd06c9e25fa1
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47304
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/faults.cc

diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index adb1207..d81651b 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1103,16 +1103,16 @@
         } else if (stage2) {
             tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf);
             tc->setMiscReg(T::HFarIndex,  OVAddr);
-        } else if (debug > ArmFault::NODEBUG) {
+        } else if (debugType > ArmFault::NODEBUG) {
             DBGDS32 Rext =  tc->readMiscReg(MISCREG_DBGDSCRext);
             tc->setMiscReg(T::FarIndex, faultAddr);
-            if (debug == ArmFault::BRKPOINT){
+            if (debugType == ArmFault::BRKPOINT){
                 Rext.moe = 0x1;
-            } else if (debug == ArmFault::VECTORCATCH){
+            } else if (debugType == ArmFault::VECTORCATCH){
                 Rext.moe = 0x5;
-            } else if (debug > ArmFault::VECTORCATCH) {
+            } else if (debugType > ArmFault::VECTORCATCH) {
                 Rext.moe = 0xa;
-                fsr.cm = (debug == ArmFault::WPOINT_CM)? 1 : 0;
+                fsr.cm = (debugType == ArmFault::WPOINT_CM)? 1 : 0;
             }
 
             tc->setMiscReg(T::FsrIndex, fsr);

src/arch/arm/faults.hh

diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index da05eb9..6d5411f 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -456,7 +456,7 @@
     bool stage2;
     bool s1ptw;
     ArmFault::TranMethod tranMethod;
-    ArmFault::DebugType debug;
+    ArmFault::DebugType debugType;
 
   public:
     AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain,
@@ -465,7 +465,8 @@
                ArmFault::DebugType _debug = ArmFault::NODEBUG) :
         faultAddr(_faultAddr), OVAddr(0), write(_write),
         domain(_domain), source(_source), srcEncoded(0),
-        stage2(_stage2), s1ptw(false), tranMethod(_tranMethod), debug(_debug)
+        stage2(_stage2), s1ptw(false), tranMethod(_tranMethod),
+        debugType(_debug)
     {}
 
     bool getFaultVAddr(Addr &va) const override;

src/arch/arm/self_debug.cc

diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index e8d00ed..551abbb 100644
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -96,8 +96,7 @@
         if (p.enable && p.isActive(pc) &&(!to32 || !p.onUse)) {
             const DBGBCR ctr = p.getControlReg(tc);
             if (p.isEnabled(tc, el, ctr.hmc, ctr.ssc, ctr.pmc)) {
-                bool debug = p.test(tc, pc, el, ctr, false);
-                if (debug){
+                if (p.test(tc, pc, el, ctr, false)) {
                     if (to32)
                         p.onUse = true;
                     return triggerException(tc, pc);
@@ -138,8 +137,7 @@
     for (auto &p: arWatchPoints){
         idxtmp ++;
         if (p.enable) {
-            bool debug = p.test(tc, vaddr, el, write, atomic, size);
-            if (debug){
+            if (p.test(tc, vaddr, el, write, atomic, size)) {
                 return triggerWatchpointException(tc, vaddr, write, cm);
             }
         }
@@ -212,12 +210,8 @@
 bool
 BrkPoint::testLinkedBk(ThreadContext *tc, Addr vaddr, ExceptionLevel el)
 {
-    bool debug = false;
     const DBGBCR ctr = getControlReg(tc);
-    if ((ctr.bt & 0x1) && enable) {
-        debug = test(tc, vaddr, el, ctr, true);
-    }
-    return debug;
+    return ((ctr.bt & 0x1) && enable) && test(tc, vaddr, el, ctr, true);
 }
 
 bool
@@ -730,12 +724,12 @@
         return NoFault;
 
     ExceptionLevel el = (ExceptionLevel) currEL(tc);
-    bool debug;
+    bool do_debug;
     if (fault == nullptr)
-        debug = vcExcpt->addressMatching(tc, addr, el);
+        do_debug = vcExcpt->addressMatching(tc, addr, el);
     else
-        debug = vcExcpt->exceptionTrapping(tc, el, fault);
-    if (debug) {
+        do_debug = vcExcpt->exceptionTrapping(tc, el, fault);
+    if (do_debug) {
         if (enableTdeTge) {
             return std::make_shared<HypervisorTrap>(0, 0x22,
                                         EC_PREFETCH_ABORT_TO_HYP);