src/arch/power/isa/operands.isa

// -*- mode:c++ -*-

// Copyright (c) 2009 The University of Edinburgh
// Copyright (c) 2021 IBM Corporation
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def operand_types {{
    'sb' : 'int8_t',
    'ub' : 'uint8_t',
    'sh' : 'int16_t',
    'uh' : 'uint16_t',
    'sw' : 'int32_t',
    'uw' : 'uint32_t',
    'sd' : 'int64_t',
    'ud' : 'uint64_t',
    'sf' : 'float',
    'df' : 'double'
}};

def operands {{
    # General Purpose Integer Reg Operands
    'Rs': ('IntReg', 'ud', 'RS', 'IsInteger', 1),
    'Ra': ('IntReg', 'ud', 'RA', 'IsInteger', 2),
    'Rb': ('IntReg', 'ud', 'RB', 'IsInteger', 3),
    'Rc': ('IntReg', 'ud', 'RC', 'IsInteger', 4),
    'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 5),

    # General Purpose Floating Point Reg Operands
    'Fa': ('FloatReg', 'df', 'FRA', 'IsFloating', 1),
    'Fb': ('FloatReg', 'df', 'FRB', 'IsFloating', 2),
    'Fc': ('FloatReg', 'df', 'FRC', 'IsFloating', 3),
    'Fs': ('FloatReg', 'df', 'FRS', 'IsFloating', 4),
    'Ft': ('FloatReg', 'df', 'FRT', 'IsFloating', 5),

    # Memory Operand
    'Mem': ('Mem', 'ud', None, (None, 'IsLoad', 'IsStore'), 8),

    # Program counter and next
    'CIA': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 9),
    'NIA': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 9),

    # Control registers
    'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9),
    'LR': ('IntReg', 'ud', 'INTREG_LR', 'IsInteger', 9),
    'CTR': ('IntReg', 'ud', 'INTREG_CTR', 'IsInteger', 9),
    'TAR': ('IntReg', 'ud', 'INTREG_TAR', 'IsInteger', 9),
    'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9),
    'MSR': ('IntReg', 'ud', 'INTREG_MSR', 'IsInteger', 9),

    # Setting as IntReg so things are stored as an integer, not double
    'FPSCR': ('IntReg', 'uw', 'INTREG_FPSCR', 'IsFloating', 9),

    # Registers for linked loads and stores
    'Rsv': ('IntReg', 'uw', 'INTREG_RSV', 'IsInteger', 9),
    'RsvLen': ('IntReg', 'uw', 'INTREG_RSV_LEN', 'IsInteger', 9),
    'RsvAddr': ('IntReg', 'ud', 'INTREG_RSV_ADDR', 'IsInteger', 9),
}};