commit 7f89594029c41934b8d342ac61e07b5369dee883
author Giacomo Travaglini <giacomo.travaglini@arm.com> Fri Aug 23 12:20:29 2019 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Fri Sep 06 11:53:49 2019 +0000
tree 994cef7a8bf7b7187777b48d0174ce0d3d55f764
parent 983f667dc38e2d14896712b39932c349f00ed1ec

dev-arm: Cpu interface groupEnabled check for global enable

Gicv3CPUInterface::groupEnabled should check for global enable flags at
distributor level:
- Gicv3Distributor.EnableGrp0
- Gicv3Distributor.EnableGrp1S
- Gicv3Distributor.EnableGrp1NS

Change-Id: I1c855b0e4c2bc8f1cd0a8f086b9450f516177b08
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20617
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/dev/arm/gic_v3_cpu_interface.cc

diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc
index d2b397a..c6c1b14 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -2276,19 +2276,19 @@
       case Gicv3::G0S: {
         ICC_IGRPEN0_EL1 icc_igrpen0_el1 =
             isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1);
-        return icc_igrpen0_el1.Enable;
+        return icc_igrpen0_el1.Enable && distributor->EnableGrp0;
       }
 
       case Gicv3::G1S: {
         ICC_IGRPEN1_EL1 icc_igrpen1_el1_s =
             isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S);
-        return icc_igrpen1_el1_s.Enable;
+        return icc_igrpen1_el1_s.Enable && distributor->EnableGrp1S;
       }
 
       case Gicv3::G1NS: {
         ICC_IGRPEN1_EL1 icc_igrpen1_el1_ns =
             isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS);
-        return icc_igrpen1_el1_ns.Enable;
+        return icc_igrpen1_el1_ns.Enable && distributor->EnableGrp1NS;
       }
 
       default: