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// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
// Copyright (c) 2015 Advanced Micro Devices, Inc.
// All rights reserved.
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2007 The Regents of The University of Michigan
// Copyright (c) 2012 Mark D. Hill and David A. Wood
// Copyright (c) 2012-2013 Advanced Micro Devices, Inc.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
def operand_types {{
'sb' : 'int8_t',
'ub' : 'uint8_t',
'sw' : 'int16_t',
'uw' : 'uint16_t',
'sdw' : 'int32_t',
'udw' : 'uint32_t',
'sqw' : 'int64_t',
'uqw' : 'uint64_t',
'u2qw' : 'std::array<uint64_t, 2>',
'sf' : 'float',
'df' : 'double',
}};
let {{
def intReg(idx, id):
return ('IntReg', 'uqw', idx, 'IsInteger', id)
def pickedReg(idx, id, size='dataSize'):
return ('IntReg', 'uqw', idx, 'IsInteger', id,
'pick(xc->readIntRegOperand(this, %(op_idx)s), '
'%(reg_idx)s, ' + size + ')')
def signedPickedReg(idx, id, size='dataSize'):
return ('IntReg', 'uqw', idx, 'IsInteger', id,
'signedPick(xc->readIntRegOperand(this, %(op_idx)s), '
'%(reg_idx)s, ' + size + ')')
def floatReg(idx, id):
return ('FloatReg', 'df', idx, 'IsFloating', id)
def ccReg(idx, id):
return ('CCReg', 'uqw', idx, None, id)
def controlReg(idx, id, ctype = 'uqw'):
return ('ControlReg', ctype, idx,
(None, None, ['IsSerializeAfter',
'IsSerializing',
'IsNonSpeculative']),
id)
def squashCheckReg(idx, id, check, ctype = 'uqw'):
return ('ControlReg', ctype, idx,
(None, None, ['((%s) ? ' % check+ \
'IsSquashAfter : IsSerializeAfter)',
'IsSerializing',
'IsNonSpeculative']),
id)
def squashCReg(idx, id, ctype = 'uqw'):
return squashCheckReg(idx, id, 'true', ctype)
def squashCSReg(idx, id, ctype = 'uqw'):
return squashCheckReg(idx, id, 'dest == X86ISA::SEGMENT_REG_CS', ctype)
def squashCR0Reg(idx, id, ctype = 'uqw'):
return squashCheckReg(idx, id, 'dest == 0', ctype)
}};
def operands {{
'SrcReg1': intReg('src1', 1),
'PSrcReg1': pickedReg('src1', 1),
'PMSrcReg1': pickedReg('src1', 1, 'srcSize'),
'SPSrcReg1': signedPickedReg('src1', 1),
'SrcReg2': intReg('src2', 2),
'PSrcReg2': pickedReg('src2', 2),
'SPSrcReg2': signedPickedReg('src2', 2),
'Index': intReg('index', 3),
'Base': intReg('base', 4),
'DestReg': intReg('dest', 5),
'Data': intReg('data', 6),
'PData': pickedReg('data', 6),
'DataLow': intReg('dataLow', 6),
'DataHi': intReg('dataHi', 6),
'ProdLow': intReg('X86ISA::INTREG_PRODLOW', 7),
'ProdHi': intReg('X86ISA::INTREG_PRODHI', 8),
'Quotient': intReg('X86ISA::INTREG_QUOTIENT', 9),
'Remainder': intReg('X86ISA::INTREG_REMAINDER', 10),
'Divisor': intReg('X86ISA::INTREG_DIVISOR', 11),
'DoubleBits': intReg('X86ISA::INTREG_DOUBLEBITS', 11),
'Rax': intReg('X86ISA::INTREG_RAX', 12),
'Rbx': intReg('X86ISA::INTREG_RBX', 13),
'Rcx': intReg('X86ISA::INTREG_RCX', 14),
'Rdx': intReg('X86ISA::INTREG_RDX', 15),
'Rsp': intReg('X86ISA::INTREG_RSP', 16),
'Rbp': intReg('X86ISA::INTREG_RBP', 17),
'Rsi': intReg('X86ISA::INTREG_RSI', 18),
'Rdi': intReg('X86ISA::INTREG_RDI', 19),
'R8': intReg('X86ISA::INTREG_R8', 20),
'R9': intReg('X86ISA::INTREG_R9', 21),
'FpSrcReg1': floatReg('src1', 22),
'FpSrcReg2': floatReg('src2', 23),
'FpDestReg': floatReg('dest', 24),
'FpData': floatReg('data', 25),
'RIP': ('PCState', 'uqw', 'pc',
(None, None, 'IsControl'), 50),
'NRIP': ('PCState', 'uqw', 'npc',
(None, None, 'IsControl'), 50),
'nuIP': ('PCState', 'uqw', 'nupc',
(None, None, 'IsControl'), 50),
# These registers hold the condition code portion of the flag
# register. The nccFlagBits version holds the rest.
'ccFlagBits': ccReg('X86ISA::CCREG_ZAPS', 60),
'cfofBits': ccReg('X86ISA::CCREG_CFOF', 61),
'dfBit': ccReg('X86ISA::CCREG_DF', 62),
'ecfBit': ccReg('X86ISA::CCREG_ECF', 63),
'ezfBit': ccReg('X86ISA::CCREG_EZF', 64),
# These Pred registers are to be used where reading the portions of
# condition code registers is possibly optional, depending on how the
# check evaluates. There are two checks being specified, one tests if
# a register needs to be read, the other tests whether the register
# needs to be written to. It is unlikely that these would need to be
# used in the actual operation of the instruction. It is expected
# that these are used only in the flag code.
# Rationale behind the checks: at times, we need to partially update
# the condition code bits in a register. So we read the register even
# in the case when the all the bits will be written, or none of the
# bits will be written. The read predicate checks if any of the bits
# would be retained, the write predicate checks if any of the bits
# are being written.
'PredccFlagBits': ('CCReg', 'uqw', '(X86ISA::CCREG_ZAPS)', None,
60, None, None,
'''(((ext & (X86ISA::PFBit | X86ISA::AFBit |
X86ISA::ZFBit | X86ISA::SFBit)) !=
(X86ISA::PFBit | X86ISA::AFBit |
X86ISA::ZFBit | X86ISA::SFBit)) &&
((ext & (X86ISA::PFBit | X86ISA::AFBit |
X86ISA::ZFBit | X86ISA::SFBit)) != 0))''',
'''((ext & (X86ISA::PFBit | X86ISA::AFBit |
X86ISA::ZFBit | X86ISA::SFBit)) != 0)'''),
'PredcfofBits': ('CCReg', 'uqw', '(X86ISA::CCREG_CFOF)', None,
61, None, None, '''(((ext & X86ISA::CFBit) == 0 ||
(ext & X86ISA::OFBit) == 0) &&
((ext & (X86ISA::CFBit | X86ISA::OFBit)) != 0))''',
'((ext & (X86ISA::CFBit | X86ISA::OFBit)) != 0)'),
'PreddfBit': ('CCReg', 'uqw', '(X86ISA::CCREG_DF)', None,
62, None, None, '(false)', '((ext & X86ISA::DFBit) != 0)'),
'PredecfBit': ('CCReg', 'uqw', '(X86ISA::CCREG_ECF)', None,
63, None, None, '(false)', '((ext & X86ISA::ECFBit) != 0)'),
'PredezfBit': ('CCReg', 'uqw', '(X86ISA::CCREG_EZF)', None,
64, None, None, '(false)', '((ext & X86ISA::EZFBit) != 0)'),
# These register should needs to be more protected so that later
# instructions don't map their indexes with an old value.
'nccFlagBits': controlReg('X86ISA::MISCREG_RFLAGS', 65),
# Registers related to the state of x87 floating point unit.
'TOP': controlReg('X86ISA::MISCREG_X87_TOP', 66, ctype='ub'),
'FSW': controlReg('X86ISA::MISCREG_FSW', 67, ctype='uw'),
'FTW': controlReg('X86ISA::MISCREG_FTW', 68, ctype='uw'),
'FCW': controlReg('X86ISA::MISCREG_FCW', 69, ctype='uw'),
# The segment base as used by memory instructions.
'SegBase': controlReg('X86ISA::MISCREG_SEG_EFF_BASE(segment)',
70),
# Operands to get and set registers indexed by the operands of the
# original instruction.
'ControlDest': squashCR0Reg('X86ISA::MISCREG_CR(dest)', 100),
'ControlSrc1': controlReg('X86ISA::MISCREG_CR(src1)', 101),
'DebugDest': controlReg('X86ISA::MISCREG_DR(dest)', 102),
'DebugSrc1': controlReg('X86ISA::MISCREG_DR(src1)', 103),
'SegBaseDest': squashCSReg('X86ISA::MISCREG_SEG_BASE(dest)', 104),
'SegBaseSrc1': controlReg('X86ISA::MISCREG_SEG_BASE(src1)', 105),
'SegLimitDest': squashCSReg('X86ISA::MISCREG_SEG_LIMIT(dest)', 106),
'SegLimitSrc1': controlReg('X86ISA::MISCREG_SEG_LIMIT(src1)', 107),
'SegSelDest': controlReg('X86ISA::MISCREG_SEG_SEL(dest)', 108),
'SegSelSrc1': controlReg('X86ISA::MISCREG_SEG_SEL(src1)', 109),
'SegAttrDest': squashCSReg('X86ISA::MISCREG_SEG_ATTR(dest)', 110),
'SegAttrSrc1': controlReg('X86ISA::MISCREG_SEG_ATTR(src1)', 111),
# Operands to access specific control registers directly.
'EferOp': squashCReg('X86ISA::MISCREG_EFER', 200),
'CR4Op': controlReg('X86ISA::MISCREG_CR4', 201),
'DR7Op': controlReg('X86ISA::MISCREG_DR7', 202),
'LDTRBase': controlReg('X86ISA::MISCREG_TSL_BASE', 203),
'LDTRLimit': controlReg('X86ISA::MISCREG_TSL_LIMIT', 204),
'LDTRSel': controlReg('X86ISA::MISCREG_TSL', 205),
'GDTRBase': controlReg('X86ISA::MISCREG_TSG_BASE', 206),
'GDTRLimit': controlReg('X86ISA::MISCREG_TSG_LIMIT', 207),
'CSBase': squashCReg('X86ISA::MISCREG_CS_EFF_BASE', 208),
'CSAttr': squashCReg('X86ISA::MISCREG_CS_ATTR', 209),
'MiscRegDest': controlReg('dest', 210),
'MiscRegSrc1': controlReg('src1', 211),
'TscOp': controlReg('X86ISA::MISCREG_TSC', 212),
'M5Reg': squashCReg('X86ISA::MISCREG_M5_REG', 213),
'Mem': ('Mem', 'uqw', None, \
(None, 'IsLoad', 'IsStore'), 300)
}};