src/arch/riscv/isa/formats/fp.isa

// -*- mode:c++ -*-

// Copyright (c) 2015 Riscv Developers
// Copyright (c) 2016-2017 The University of Virginia
// Copyright (c) 2020 Barkhausen Institut
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

////////////////////////////////////////////////////////////////////
//
// Floating point operation instructions
//
def template FloatExecute {{
    Fault %(class_name)s::execute(ExecContext *xc,
        Trace::InstRecord *traceData) const
    {
        Fault fault = NoFault;

        STATUS status = xc->readMiscReg(MISCREG_STATUS);
        if (status.fs == FPUStatus::OFF)
            fault = make_shared<IllegalInstFault>("FPU is off", machInst);

        %(op_decl)s;
        %(op_rd)s;
        if (fault == NoFault) {
            switch (ROUND_MODE) {
            case 0x0:
                std::fesetround(FE_TONEAREST);
                break;
            case 0x1:
                std::fesetround(FE_TOWARDZERO);
                break;
            case 0x2:
                std::fesetround(FE_DOWNWARD);
                break;
            case 0x3:
                std::fesetround(FE_UPWARD);
                break;
            case 0x4:
                // Round to nearest, ties to max magnitude not implemented
                fault = make_shared<IllegalFrmFault>(ROUND_MODE, machInst);
                break;
            case 0x7: {
                uint8_t frm = xc->readMiscReg(MISCREG_FRM);
                switch (frm) {
                case 0x0:
                    std::fesetround(FE_TONEAREST);
                    break;
                case 0x1:
                    std::fesetround(FE_TOWARDZERO);
                    break;
                case 0x2:
                    std::fesetround(FE_DOWNWARD);
                    break;
                case 0x3:
                    std::fesetround(FE_UPWARD);
                    break;
                case 0x4:
                    // Round to nearest, ties to max magnitude not implemented
                    fault = make_shared<IllegalFrmFault>(ROUND_MODE, machInst);
                    break;
                default:
                    fault = std::make_shared<IllegalFrmFault>(frm, machInst);
                    break;
                }
                break;
            }
            default:
                fault = std::make_shared<IllegalFrmFault>(ROUND_MODE,
                                                          machInst);
                break;
            }

            if (fault == NoFault) {
                RegVal FFLAGS = xc->readMiscReg(MISCREG_FFLAGS);
                std::feclearexcept(FE_ALL_EXCEPT);
                %(code)s;
                if (std::fetestexcept(FE_INEXACT)) {
                    FFLAGS |= FloatInexact;
                }
                if (std::fetestexcept(FE_UNDERFLOW)) {
                    FFLAGS |= FloatUnderflow;
                }
                if (std::fetestexcept(FE_OVERFLOW)) {
                    FFLAGS |= FloatOverflow;
                }
                if (std::fetestexcept(FE_DIVBYZERO)) {
                    FFLAGS |= FloatDivZero;
                }
                if (std::fetestexcept(FE_INVALID)) {
                    FFLAGS |= FloatInvalid;
                }
                xc->setMiscReg(MISCREG_FFLAGS, FFLAGS);
            }

            if (fault == NoFault) {
                %(op_wb)s;
            }
        }
        return fault;
    }
}};

def format FPROp(code, *opt_flags) {{
    iop = InstObjParams(name, Name, 'RegOp', code, opt_flags)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = FloatExecute.subst(iop)
}};