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# Copyright (c) 2021 The Regents of the University of California
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#
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# neither the name of the copyright holders nor the names of its
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"""
This tests the gem5 memory components with a simple traffic generator.
TODO: At present all the Single Channel memory components are tested. This
should be expanded to included DRAMSIM3 memory systems.
"""
from testlib import *
def test_memory(
generator: str, cache: str, module: str, memory: str, *args
) -> None:
protocol_map = {"NoCache": None, "MESITwoLevel": "MESI_Two_Level"}
tag_map = {
"NoCache": constants.quick_tag,
"MESITwoLevel": constants.long_tag,
}
gem5_verify_config(
name="test-memory-"
+ generator
+ "."
+ cache
+ "."
+ module
+ "."
+ memory,
fixtures=(),
verifiers=(),
config=joinpath(
config.base_dir,
"tests",
"gem5",
"configs",
"simple_traffic_run.py",
),
config_args=[
generator,
cache,
module,
memory,
]
+ list(args),
valid_isas=(constants.null_tag,),
protocol=protocol_map[cache],
valid_hosts=constants.supported_hosts,
length=tag_map[cache],
)
test_memory(
"LinearGenerator",
"NoCache",
"gem5.components.memory.single_channel",
"SingleChannelDDR3_1600",
"512MiB",
)
test_memory(
"LinearGenerator",
"NoCache",
"gem5.components.memory.single_channel",
"SingleChannelDDR3_2133",
"512MiB",
)
test_memory(
"LinearGenerator",
"NoCache",
"gem5.components.memory.single_channel",
"SingleChannelDDR4_2400",
"512MiB",
)
test_memory(
"LinearGenerator",
"NoCache",
"gem5.components.memory.single_channel",
"SingleChannelLPDDR3_1600",
"512MiB",
)
test_memory(
"LinearGenerator",
"NoCache",
"gem5.components.memory.single_channel",
"SingleChannelHBM",
"512MiB",
)
test_memory(
"RandomGenerator",
"NoCache",
"gem5.components.memory.single_channel",
"SingleChannelDDR3_1600",
"512MiB",
)
test_memory(
"RandomGenerator",
"NoCache",
"gem5.components.memory.single_channel",
"SingleChannelDDR3_2133",
"512MiB",
)
test_memory(
"RandomGenerator",
"NoCache",
"gem5.components.memory.single_channel",
"SingleChannelDDR4_2400",
"512MiB",
)
test_memory(
"RandomGenerator",
"NoCache",
"gem5.components.memory.single_channel",
"SingleChannelLPDDR3_1600",
"512MiB",
)
test_memory(
"RandomGenerator",
"NoCache",
"gem5.components.memory.single_channel",
"SingleChannelHBM",
"512MiB",
)
test_memory(
"LinearGenerator",
"MESITwoLevel",
"gem5.components.memory.single_channel",
"SingleChannelDDR3_1600",
"512MiB",
)
test_memory(
"LinearGenerator",
"MESITwoLevel",
"gem5.components.memory.single_channel",
"SingleChannelDDR3_2133",
"512MiB",
)
test_memory(
"LinearGenerator",
"MESITwoLevel",
"gem5.components.memory.single_channel",
"SingleChannelDDR4_2400",
"512MiB",
)
test_memory(
"LinearGenerator",
"MESITwoLevel",
"gem5.components.memory.single_channel",
"SingleChannelLPDDR3_1600",
"512MiB",
)
test_memory(
"LinearGenerator",
"MESITwoLevel",
"gem5.components.memory.single_channel",
"SingleChannelHBM",
"512MiB",
)
test_memory(
"RandomGenerator",
"MESITwoLevel",
"gem5.components.memory.single_channel",
"SingleChannelDDR3_1600",
"512MiB",
)
test_memory(
"RandomGenerator",
"MESITwoLevel",
"gem5.components.memory.single_channel",
"SingleChannelDDR3_2133",
"512MiB",
)
test_memory(
"RandomGenerator",
"MESITwoLevel",
"gem5.components.memory.single_channel",
"SingleChannelDDR4_2400",
"512MiB",
)
test_memory(
"RandomGenerator",
"MESITwoLevel",
"gem5.components.memory.single_channel",
"SingleChannelLPDDR3_1600",
"512MiB",
)
test_memory(
"RandomGenerator",
"MESITwoLevel",
"gem5.components.memory.single_channel",
"SingleChannelHBM",
"512MiB",
)