fastmodel: add setResetAddr interface
setResetAddr interface allows us to change the reset addr of fastmodel
cores. This will enable us to simulate hard reset or even complicated
boot sequence.
Change-Id: I0de828a4cd693119c0b44c74866efc1fffa81ace
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53326
Reviewed-by: Earl Ou <shunhsingou@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc b/src/arch/arm/fastmodel/CortexA76/evs.cc
index 4e0add6..4b25014 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -64,6 +64,13 @@
}
template <class Types>
+void
+ScxEvsCortexA76<Types>::setResetAddr(int core, Addr addr, bool secure)
+{
+ panic("Not implemented for A76.");
+}
+
+template <class Types>
ScxEvsCortexA76<Types>::ScxEvsCortexA76(
const sc_core::sc_module_name &mod_name, const Params &p) :
Base(mod_name), amba(Base::amba, p.name + ".amba", -1),
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh b/src/arch/arm/fastmodel/CortexA76/evs.hh
index f0e2ef5..37f8363 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -113,6 +113,8 @@
void setSysCounterFrq(uint64_t sys_counter_frq) override;
void setCluster(SimObject *cluster) override;
+
+ void setResetAddr(int core, Addr addr, bool secure) override;
};
struct ScxEvsCortexA76x1Types
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc b/src/arch/arm/fastmodel/CortexR52/evs.cc
index 7f992f2..5dcda4e 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -63,6 +63,13 @@
}
template <class Types>
+void
+ScxEvsCortexR52<Types>::setResetAddr(int core, Addr addr, bool secure)
+{
+ panic("Not implemented for R52.");
+}
+
+template <class Types>
ScxEvsCortexR52<Types>::CorePins::CorePins(Evs *_evs, int _cpu) :
name(csprintf("%s.cpu%s", _evs->name(), _cpu)),
evs(_evs), cpu(_cpu),
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh b/src/arch/arm/fastmodel/CortexR52/evs.hh
index 20870df..a616a4d 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -156,6 +156,8 @@
void setSysCounterFrq(uint64_t sys_counter_frq) override;
void setCluster(SimObject *cluster) override;
+
+ void setResetAddr(int core, Addr addr, bool secure) override;
};
struct ScxEvsCortexR52x1Types
diff --git a/src/arch/arm/fastmodel/iris/cpu.hh b/src/arch/arm/fastmodel/iris/cpu.hh
index 5cb8820..b43eb8e 100644
--- a/src/arch/arm/fastmodel/iris/cpu.hh
+++ b/src/arch/arm/fastmodel/iris/cpu.hh
@@ -51,6 +51,7 @@
virtual void setClkPeriod(Tick clk_period) = 0;
virtual void setSysCounterFrq(uint64_t sys_counter_frq) = 0;
virtual void setCluster(SimObject *cluster) = 0;
+ virtual void setResetAddr(int core, Addr addr, bool secure) = 0;
};
// This CPU class adds some mechanisms which help attach the gem5 and fast
@@ -86,6 +87,12 @@
Counter totalInsts() const override;
Counter totalOps() const override { return totalInsts(); }
+ virtual void
+ setResetAddr(Addr addr, bool secure = false)
+ {
+ panic("%s not implemented.", __FUNCTION__);
+ }
+
protected:
sc_core::sc_module *evs;
// Hold casted pointer to *evs.
