arch-arm: Using explicit invalidation in TLB
When setting TLB related MiscRegs, using explicit TLB regs invalidation
rather than implicit switch-case fallthrough
Change-Id: Ia1a7358b6d54dda3811be1c5ce5d676f8c518c4d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10041
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 899cda9..dfd523c 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2016 ARM Limited
+ * Copyright (c) 2010-2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -1695,8 +1695,11 @@
} else {
newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
}
+ // Invalidate TLB MiscReg
+ getITBPtr(tc)->invalidateMiscReg();
+ getDTBPtr(tc)->invalidateMiscReg();
+ break;
}
- M5_FALLTHROUGH;
case MISCREG_TTBR0:
case MISCREG_TTBR1:
{
@@ -1709,15 +1712,12 @@
newVal = (newVal & (~ttbrMask));
}
}
- }
- M5_FALLTHROUGH;
- case MISCREG_SCTLR_EL1:
- {
+ // Invalidate TLB MiscReg
getITBPtr(tc)->invalidateMiscReg();
getDTBPtr(tc)->invalidateMiscReg();
- setMiscRegNoEffect(misc_reg, newVal);
+ break;
}
- M5_FALLTHROUGH;
+ case MISCREG_SCTLR_EL1:
case MISCREG_CONTEXTIDR:
case MISCREG_PRRR:
case MISCREG_NMRR:
