| // Copyright (c) 2017 ARM Limited |
| // All rights reserved |
| // |
| // The license below extends only to copyright in the software and shall |
| // not be construed as granting a license to any other intellectual |
| // property including but not limited to intellectual property relating |
| // to a hardware implementation of the functionality of the software |
| // licensed hereunder. You may use the software subject to the license |
| // terms below provided that you ensure that this notice is replicated |
| // unmodified and in its entirety in all distributions of the software, |
| // modified or unmodified, in source code or in binary form. |
| // |
| // Redistribution and use in source and binary forms, with or without |
| // modification, are permitted provided that the following conditions are |
| // met: redistributions of source code must retain the above copyright |
| // notice, this list of conditions and the following disclaimer; |
| // redistributions in binary form must reproduce the above copyright |
| // notice, this list of conditions and the following disclaimer in the |
| // documentation and/or other materials provided with the distribution; |
| // neither the name of the copyright holders nor the names of its |
| // contributors may be used to endorse or promote products derived from |
| // this software without specific prior written permission. |
| // |
| // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| // |
| // Authors: Giacomo Gabrielli |
| |
| def template SveMemFillSpillOpDeclare {{ |
| class %(class_name)s : public %(base_class)s |
| { |
| protected: |
| typedef uint8_t TPElem; |
| typedef uint8_t RegElemType; |
| typedef uint8_t MemElemType; |
| |
| public: |
| %(class_name)s(ExtMachInst machInst, |
| IntRegIndex _dest, IntRegIndex _base, uint64_t _imm) |
| : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, |
| _dest, _base, _imm) |
| { |
| %(constructor)s; |
| } |
| |
| Fault execute(ExecContext *, Trace::InstRecord *) const; |
| Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; |
| Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; |
| |
| virtual void |
| annotateFault(ArmFault *fault) { |
| %(fa_code)s |
| } |
| }; |
| }}; |
| |
| def template SveContigMemSSOpDeclare {{ |
| %(tpl_header)s |
| class %(class_name)s : public %(base_class)s |
| { |
| protected: |
| typedef RegElemType TPElem; |
| |
| public: |
| %(class_name)s(const char* mnem, ExtMachInst machInst, |
| IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base, |
| IntRegIndex _offset) |
| : %(base_class)s(mnem, machInst, %(op_class)s, |
| _dest, _gp, _base, _offset) |
| { |
| %(constructor)s; |
| } |
| |
| Fault execute(ExecContext *, Trace::InstRecord *) const; |
| Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; |
| Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; |
| |
| virtual void |
| annotateFault(ArmFault *fault) { |
| %(fa_code)s |
| } |
| }; |
| }}; |
| |
| def template SveContigMemSIOpDeclare {{ |
| %(tpl_header)s |
| class %(class_name)s : public %(base_class)s |
| { |
| protected: |
| typedef RegElemType TPElem; |
| |
| public: |
| %(class_name)s(const char* mnem, ExtMachInst machInst, |
| IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base, |
| uint64_t _imm) |
| : %(base_class)s(mnem, machInst, %(op_class)s, |
| _dest, _gp, _base, _imm) |
| { |
| %(constructor)s; |
| } |
| |
| Fault execute(ExecContext *, Trace::InstRecord *) const; |
| Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; |
| Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; |
| |
| virtual void |
| annotateFault(ArmFault *fault) { |
| %(fa_code)s |
| } |
| }; |
| }}; |
| |
| def template SveContigMemExecDeclare {{ |
| template |
| Fault %(class_name)s%(tpl_args)s::execute(ExecContext *, |
| Trace::InstRecord *) const; |
| |
| template |
| Fault %(class_name)s%(tpl_args)s::initiateAcc(ExecContext *, |
| Trace::InstRecord *) const; |
| |
| template |
| Fault %(class_name)s%(tpl_args)s::completeAcc(PacketPtr, |
| ExecContext *, Trace::InstRecord *) const; |
| }}; |
| |
| def template SveContigLoadExecute {{ |
| %(tpl_header)s |
| Fault %(class_name)s%(tpl_args)s::execute(ExecContext *xc, |
| Trace::InstRecord *traceData) const |
| { |
| Addr EA; |
| Fault fault = NoFault; |
| bool aarch64 M5_VAR_USED = true; |
| unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>( |
| xc->tcBase()); |
| |
| %(op_decl)s; |
| %(op_rd)s; |
| %(ea_code)s; |
| |
| TheISA::VecRegContainer memData; |
| auto memDataView = memData.as<MemElemType>(); |
| |
| if (fault == NoFault) { |
| fault = xc->readMem(EA, memData.raw_ptr<uint8_t>(), memAccessSize, |
| this->memAccessFlags); |
| %(memacc_code)s; |
| } |
| |
| if (fault == NoFault) { |
| %(op_wb)s; |
| } |
| |
| return fault; |
| } |
| }}; |
| |
| def template SveContigLoadInitiateAcc {{ |
| %(tpl_header)s |
| Fault %(class_name)s%(tpl_args)s::initiateAcc(ExecContext *xc, |
| Trace::InstRecord *traceData) const |
| { |
| Addr EA; |
| Fault fault = NoFault; |
| bool aarch64 M5_VAR_USED = true; |
| unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>( |
| xc->tcBase()); |
| |
| %(op_src_decl)s; |
| %(op_rd)s; |
| |
| %(ea_code)s; |
| |
| if (fault == NoFault) { |
| fault = xc->initiateMemRead(EA, memAccessSize, |
| this->memAccessFlags); |
| } |
| |
| return fault; |
| } |
| }}; |
| |
| def template SveContigLoadCompleteAcc {{ |
| %(tpl_header)s |
| Fault %(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt, |
| ExecContext *xc, Trace::InstRecord *traceData) const |
| { |
| Fault fault = NoFault; |
| bool aarch64 M5_VAR_USED = true; |
| unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>( |
| xc->tcBase()); |
| |
| %(op_decl)s; |
| %(op_rd)s; |
| |
| TheISA::VecRegContainer memData; |
| auto memDataView = memData.as<MemElemType>(); |
| |
| memcpy(memData.raw_ptr<uint8_t>(), pkt->getPtr<uint8_t>(), |
| pkt->getSize()); |
| |
| if (fault == NoFault) { |
| %(memacc_code)s; |
| } |
| |
| if (fault == NoFault) { |
| %(op_wb)s; |
| } |
| |
| return fault; |
| } |
| }}; |
| |
| def template SveContigStoreExecute {{ |
| %(tpl_header)s |
| Fault %(class_name)s%(tpl_args)s::execute(ExecContext *xc, |
| Trace::InstRecord *traceData) const |
| { |
| Addr EA; |
| Fault fault = NoFault; |
| bool aarch64 M5_VAR_USED = true; |
| unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>( |
| xc->tcBase()); |
| |
| %(op_decl)s; |
| %(op_rd)s; |
| %(ea_code)s; |
| |
| TheISA::VecRegContainer memData; |
| auto memDataView = memData.as<MemElemType>(); |
| |
| %(wren_code)s; |
| |
| if (fault == NoFault) { |
| %(memacc_code)s; |
| } |
| |
| if (fault == NoFault) { |
| fault = xc->writeMem(memData.raw_ptr<uint8_t>(), memAccessSize, EA, |
| this->memAccessFlags, NULL, wrEn); |
| } |
| |
| if (fault == NoFault) { |
| %(op_wb)s; |
| } |
| |
| return fault; |
| } |
| }}; |
| |
| def template SveContigStoreInitiateAcc {{ |
| %(tpl_header)s |
| Fault %(class_name)s%(tpl_args)s::initiateAcc(ExecContext *xc, |
| Trace::InstRecord *traceData) const |
| { |
| Addr EA; |
| Fault fault = NoFault; |
| bool aarch64 M5_VAR_USED = true; |
| unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>( |
| xc->tcBase()); |
| |
| %(op_decl)s; |
| %(op_rd)s; |
| %(ea_code)s; |
| |
| TheISA::VecRegContainer memData; |
| auto memDataView = memData.as<MemElemType>(); |
| |
| %(wren_code)s; |
| |
| if (fault == NoFault) { |
| %(memacc_code)s; |
| } |
| |
| if (fault == NoFault) { |
| fault = xc->writeMem(memData.raw_ptr<uint8_t>(), memAccessSize, EA, |
| this->memAccessFlags, NULL, wrEn); |
| } |
| |
| return fault; |
| } |
| }}; |
| |
| def template SveContigStoreCompleteAcc {{ |
| %(tpl_header)s |
| Fault %(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt, |
| ExecContext *xc, Trace::InstRecord *traceData) const |
| { |
| return NoFault; |
| } |
| }}; |
| |
| def template SveLoadAndReplExecute {{ |
| %(tpl_header)s |
| Fault %(class_name)s%(tpl_args)s::execute(ExecContext *xc, |
| Trace::InstRecord *traceData) const |
| { |
| Addr EA; |
| Fault fault = NoFault; |
| bool aarch64 M5_VAR_USED = true; |
| unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>( |
| xc->tcBase()); |
| |
| %(op_decl)s; |
| %(op_rd)s; |
| %(ea_code)s; |
| |
| MemElemType memData; |
| |
| if (fault == NoFault) { |
| fault = readMemAtomic(xc, traceData, EA, memData, |
| this->memAccessFlags); |
| %(memacc_code)s; |
| } |
| |
| if (fault == NoFault) { |
| %(op_wb)s; |
| } |
| |
| return fault; |
| } |
| }}; |
| |
| def template SveLoadAndReplInitiateAcc {{ |
| %(tpl_header)s |
| Fault %(class_name)s%(tpl_args)s::initiateAcc(ExecContext *xc, |
| Trace::InstRecord *traceData) const |
| { |
| Addr EA; |
| Fault fault = NoFault; |
| bool aarch64 M5_VAR_USED = true; |
| |
| %(op_src_decl)s; |
| %(op_rd)s; |
| |
| %(ea_code)s; |
| |
| MemElemType memData; |
| |
| if (fault == NoFault) { |
| fault = initiateMemRead(xc, traceData, EA, memData, |
| this->memAccessFlags); |
| } |
| |
| return fault; |
| } |
| }}; |
| |
| def template SveLoadAndReplCompleteAcc {{ |
| %(tpl_header)s |
| Fault %(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt, |
| ExecContext *xc, Trace::InstRecord *traceData) const |
| { |
| Fault fault = NoFault; |
| bool aarch64 M5_VAR_USED = true; |
| unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>( |
| xc->tcBase()); |
| |
| %(op_decl)s; |
| %(op_rd)s; |
| |
| MemElemType memData; |
| getMem(pkt, memData, traceData); |
| |
| if (fault == NoFault) { |
| %(memacc_code)s; |
| } |
| |
| if (fault == NoFault) { |
| %(op_wb)s; |
| } |
| |
| return fault; |
| } |
| }}; |
| |
