commit 8fb933841ff17d91231342f4b56f11bee6e08b09
author Giacomo Travaglini <giacomo.travaglini@arm.com> Mon Feb 17 14:27:46 2020 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Mon Feb 17 23:30:14 2020 +0000
tree e824b68427e8a1869c79c798e8cf1773e5f55747
parent c73048df0d701d094f500daf60843cf61ca1e487

arch-arm: Fix ArmKVM build

BaseInterrupts don't have a checkRaw method.
This was breaking gem5 compilation on a Arm machine

Change-Id: I8717b1bcf64ed14e8a0f63a9dcaca6041dbea4d3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25431
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/kvm/arm_cpu.cc

diff --git a/src/arch/arm/kvm/arm_cpu.cc b/src/arch/arm/kvm/arm_cpu.cc
index 80576a2..24f7be8 100644
--- a/src/arch/arm/kvm/arm_cpu.cc
+++ b/src/arch/arm/kvm/arm_cpu.cc
@@ -45,6 +45,7 @@
 #include <cerrno>
 #include <memory>
 
+#include "arch/arm/interrupts.hh"
 #include "arch/registers.hh"
 #include "cpu/kvm/base.hh"
 #include "debug/Kvm.hh"
@@ -270,8 +271,9 @@
 Tick
 ArmKvmCPU::kvmRun(Tick ticks)
 {
-    bool simFIQ(interrupts[0]->checkRaw(INT_FIQ));
-    bool simIRQ(interrupts[0]->checkRaw(INT_IRQ));
+    auto interrupt = static_cast<ArmISA::Interrupts *>(interrupts[0]);
+    const bool simFIQ(interrupt->checkRaw(INT_FIQ));
+    const bool simIRQ(interrupt->checkRaw(INT_IRQ));
 
     if (fiqAsserted != simFIQ) {
         fiqAsserted = simFIQ;

src/arch/arm/kvm/base_cpu.cc

diff --git a/src/arch/arm/kvm/base_cpu.cc b/src/arch/arm/kvm/base_cpu.cc
index 7659650..c99e853 100644
--- a/src/arch/arm/kvm/base_cpu.cc
+++ b/src/arch/arm/kvm/base_cpu.cc
@@ -41,6 +41,7 @@
 
 #include <linux/kvm.h>
 
+#include "arch/arm/interrupts.hh"
 #include "debug/KvmInt.hh"
 #include "params/BaseArmKvmCPU.hh"
 
@@ -88,8 +89,9 @@
 Tick
 BaseArmKvmCPU::kvmRun(Tick ticks)
 {
-    const bool simFIQ(interrupts[0]->checkRaw(INT_FIQ));
-    const bool simIRQ(interrupts[0]->checkRaw(INT_IRQ));
+    auto interrupt = static_cast<ArmISA::Interrupts *>(interrupts[0]);
+    const bool simFIQ(interrupt->checkRaw(INT_FIQ));
+    const bool simIRQ(interrupt->checkRaw(INT_IRQ));
 
     if (!vm.hasKernelIRQChip()) {
         if (fiqAsserted != simFIQ) {