arch-gcn3: Add files for arch gcn3 (GPU machine ISA)
Decoder: gpu_decoder.hh and decoder.cc:
The decoder is defined in these files. The decoder
is implemented as a lookup table of function pointers
where each decode function will decode to a unique
ISA instruction, or do some sub-decoding to infer
the next decode function to call.
The format for each OP encoding is defined in the
header file.
Registers:
registers.[hh|cc] define the special registers and
operand selector values, which are used to map
operands to registers/special values. many
convenience functions are also provides to determine
the source/type of an operand, for example vector
vs. scalar, register operand vs. constant, etc.
GPU ISA:
Some special GPU ISA state is maintained in gpu_isa.hh
and isa.cc. This class is used to hold some special
registers and values that can be used as operands
by ISA instructions. Eventually more ISA-specific
state should be moved here, and out of the WF class.
Vector Operands:
The operands for GCN3 instructions are defined in
operand.hh. This file defines both scalar and
vector operands wth GCN3 specific semantics. The
vector operand class is desgned around the generic
vec_reg.hh that is already present in gem5.
Instructions:
The GCN3 instructions are defined and implemented
throughout gpu_static_inst.[hh|cc], instructions.[hh|cc],
op_encodings.[hh|cc], and inst_util.hh. GCN3 instructions
all fall under one of the OP encoding types; for example
scalar memory operands are of the type SMEM, vector
ALU instructions can be VOP3, VOP2, etc. The base code
common to all instructions of a certain OP encoding type
is implemented in the OP encodings files, which includes
operand information, disassembly methods, encoding type,
etc.
Each individual ISA isntruction is implemented as
a class object in instructions.[hh|cc] and are derived
from one of the OP encoding types. The instructions.cc
file is primarily for the execute() methods of each
individual instruction, and the header file provides
the class definition and a few instruction specific
API calls.
Note that these instruction classes were auto-generated
but not using the gem5 ISA description language. A
custom ISA description was used and that cannot be released
publicly, therefore we are providing them already in C++.
Change-Id: I14d2a02d6b87109f41341c8f50a69a2cca9f3d14
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28127
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/MAINTAINERS b/MAINTAINERS
index 1a46a70..5e5ec13 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -28,6 +28,7 @@
arch-arm:
Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini <giacomo.travaglini@arm.com>
+arch-gcn3:
arch-hsail:
Tony Gutierrez <anthony.gutierrez@amd.com>
arch-mips:
diff --git a/src/arch/gcn3/SConscript b/src/arch/gcn3/SConscript
new file mode 100644
index 0000000..f438cdb
--- /dev/null
+++ b/src/arch/gcn3/SConscript
@@ -0,0 +1,47 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# For use for simulation and test purposes only
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from this
+# software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Anthony Gutierrez
+
+import sys
+
+Import('*')
+
+if env['TARGET_GPU_ISA'] == 'gcn3':
+ Source('decoder.cc')
+ Source('insts/gpu_static_inst.cc')
+ Source('insts/instructions.cc')
+ Source('insts/op_encodings.cc')
+ Source('isa.cc')
+ Source('registers.cc')
+ DebugFlag('GCN3', 'Debug flag for GCN3 GPU ISA')
diff --git a/src/arch/gcn3/SConsopts b/src/arch/gcn3/SConsopts
new file mode 100644
index 0000000..b6bcc39
--- /dev/null
+++ b/src/arch/gcn3/SConsopts
@@ -0,0 +1,38 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2015, 2017 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# For use for simulation and test purposes only
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from this
+# software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Anthony Gutierrez
+
+Import('*')
+
+all_gpu_isa_list.append('gcn3')
diff --git a/src/arch/gcn3/decoder.cc b/src/arch/gcn3/decoder.cc
new file mode 100644
index 0000000..87578f9
--- /dev/null
+++ b/src/arch/gcn3/decoder.cc
@@ -0,0 +1,10816 @@
+/*
+ * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * For use for simulation and test purposes only
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: John Slice
+ * Anthony Gutierrez
+ */
+
+#include "arch/gcn3/gpu_decoder.hh"
+
+#include <vector>
+
+#include "arch/gcn3/insts/gpu_static_inst.hh"
+#include "arch/gcn3/insts/instructions.hh"
+
+namespace Gcn3ISA
+{
+ Decoder::Decoder()
+ {
+ } // Decoder
+
+ Decoder::~Decoder()
+ {
+ } // ~Decoder
+
+ IsaDecodeMethod Decoder::tableDecodePrimary[] = {
+ &Decoder::decode_OP_VOP2__V_CNDMASK_B32,
+ &Decoder::decode_OP_VOP2__V_CNDMASK_B32,
+ &Decoder::decode_OP_VOP2__V_CNDMASK_B32,
+ &Decoder::decode_OP_VOP2__V_CNDMASK_B32,
+ &Decoder::decode_OP_VOP2__V_ADD_F32,
+ &Decoder::decode_OP_VOP2__V_ADD_F32,
+ &Decoder::decode_OP_VOP2__V_ADD_F32,
+ &Decoder::decode_OP_VOP2__V_ADD_F32,
+ &Decoder::decode_OP_VOP2__V_SUB_F32,
+ &Decoder::decode_OP_VOP2__V_SUB_F32,
+ &Decoder::decode_OP_VOP2__V_SUB_F32,
+ &Decoder::decode_OP_VOP2__V_SUB_F32,
+ &Decoder::decode_OP_VOP2__V_SUBREV_F32,
+ &Decoder::decode_OP_VOP2__V_SUBREV_F32,
+ &Decoder::decode_OP_VOP2__V_SUBREV_F32,
+ &Decoder::decode_OP_VOP2__V_SUBREV_F32,
+ &Decoder::decode_OP_VOP2__V_MUL_LEGACY_F32,
+ &Decoder::decode_OP_VOP2__V_MUL_LEGACY_F32,
+ &Decoder::decode_OP_VOP2__V_MUL_LEGACY_F32,
+ &Decoder::decode_OP_VOP2__V_MUL_LEGACY_F32,
+ &Decoder::decode_OP_VOP2__V_MUL_F32,
+ &Decoder::decode_OP_VOP2__V_MUL_F32,
+ &Decoder::decode_OP_VOP2__V_MUL_F32,
+ &Decoder::decode_OP_VOP2__V_MUL_F32,
+ &Decoder::decode_OP_VOP2__V_MUL_I32_I24,
+ &Decoder::decode_OP_VOP2__V_MUL_I32_I24,
+ &Decoder::decode_OP_VOP2__V_MUL_I32_I24,
+ &Decoder::decode_OP_VOP2__V_MUL_I32_I24,
+ &Decoder::decode_OP_VOP2__V_MUL_HI_I32_I24,
+ &Decoder::decode_OP_VOP2__V_MUL_HI_I32_I24,
+ &Decoder::decode_OP_VOP2__V_MUL_HI_I32_I24,
+ &Decoder::decode_OP_VOP2__V_MUL_HI_I32_I24,
+ &Decoder::decode_OP_VOP2__V_MUL_U32_U24,
+ &Decoder::decode_OP_VOP2__V_MUL_U32_U24,
+ &Decoder::decode_OP_VOP2__V_MUL_U32_U24,
+ &Decoder::decode_OP_VOP2__V_MUL_U32_U24,
+ &Decoder::decode_OP_VOP2__V_MUL_HI_U32_U24,
+ &Decoder::decode_OP_VOP2__V_MUL_HI_U32_U24,
+ &Decoder::decode_OP_VOP2__V_MUL_HI_U32_U24,
+ &Decoder::decode_OP_VOP2__V_MUL_HI_U32_U24,
+ &Decoder::decode_OP_VOP2__V_MIN_F32,
+ &Decoder::decode_OP_VOP2__V_MIN_F32,
+ &Decoder::decode_OP_VOP2__V_MIN_F32,
+ &Decoder::decode_OP_VOP2__V_MIN_F32,
+ &Decoder::decode_OP_VOP2__V_MAX_F32,
+ &Decoder::decode_OP_VOP2__V_MAX_F32,
+ &Decoder::decode_OP_VOP2__V_MAX_F32,
+ &Decoder::decode_OP_VOP2__V_MAX_F32,
+ &Decoder::decode_OP_VOP2__V_MIN_I32,
+ &Decoder::decode_OP_VOP2__V_MIN_I32,
+ &Decoder::decode_OP_VOP2__V_MIN_I32,
+ &Decoder::decode_OP_VOP2__V_MIN_I32,
+ &Decoder::decode_OP_VOP2__V_MAX_I32,
+ &Decoder::decode_OP_VOP2__V_MAX_I32,
+ &Decoder::decode_OP_VOP2__V_MAX_I32,
+ &Decoder::decode_OP_VOP2__V_MAX_I32,
+ &Decoder::decode_OP_VOP2__V_MIN_U32,
+ &Decoder::decode_OP_VOP2__V_MIN_U32,
+ &Decoder::decode_OP_VOP2__V_MIN_U32,
+ &Decoder::decode_OP_VOP2__V_MIN_U32,
+ &Decoder::decode_OP_VOP2__V_MAX_U32,
+ &Decoder::decode_OP_VOP2__V_MAX_U32,
+ &Decoder::decode_OP_VOP2__V_MAX_U32,
+ &Decoder::decode_OP_VOP2__V_MAX_U32,
+ &Decoder::decode_OP_VOP2__V_LSHRREV_B32,
+ &Decoder::decode_OP_VOP2__V_LSHRREV_B32,
+ &Decoder::decode_OP_VOP2__V_LSHRREV_B32,
+ &Decoder::decode_OP_VOP2__V_LSHRREV_B32,
+ &Decoder::decode_OP_VOP2__V_ASHRREV_I32,
+ &Decoder::decode_OP_VOP2__V_ASHRREV_I32,
+ &Decoder::decode_OP_VOP2__V_ASHRREV_I32,
+ &Decoder::decode_OP_VOP2__V_ASHRREV_I32,
+ &Decoder::decode_OP_VOP2__V_LSHLREV_B32,
+ &Decoder::decode_OP_VOP2__V_LSHLREV_B32,
+ &Decoder::decode_OP_VOP2__V_LSHLREV_B32,
+ &Decoder::decode_OP_VOP2__V_LSHLREV_B32,
+ &Decoder::decode_OP_VOP2__V_AND_B32,
+ &Decoder::decode_OP_VOP2__V_AND_B32,
+ &Decoder::decode_OP_VOP2__V_AND_B32,
+ &Decoder::decode_OP_VOP2__V_AND_B32,
+ &Decoder::decode_OP_VOP2__V_OR_B32,
+ &Decoder::decode_OP_VOP2__V_OR_B32,
+ &Decoder::decode_OP_VOP2__V_OR_B32,
+ &Decoder::decode_OP_VOP2__V_OR_B32,
+ &Decoder::decode_OP_VOP2__V_XOR_B32,
+ &Decoder::decode_OP_VOP2__V_XOR_B32,
+ &Decoder::decode_OP_VOP2__V_XOR_B32,
+ &Decoder::decode_OP_VOP2__V_XOR_B32,
+ &Decoder::decode_OP_VOP2__V_MAC_F32,
+ &Decoder::decode_OP_VOP2__V_MAC_F32,
+ &Decoder::decode_OP_VOP2__V_MAC_F32,
+ &Decoder::decode_OP_VOP2__V_MAC_F32,
+ &Decoder::decode_OP_VOP2__V_MADMK_F32,
+ &Decoder::decode_OP_VOP2__V_MADMK_F32,
+ &Decoder::decode_OP_VOP2__V_MADMK_F32,
+ &Decoder::decode_OP_VOP2__V_MADMK_F32,
+ &Decoder::decode_OP_VOP2__V_MADAK_F32,
+ &Decoder::decode_OP_VOP2__V_MADAK_F32,
+ &Decoder::decode_OP_VOP2__V_MADAK_F32,
+ &Decoder::decode_OP_VOP2__V_MADAK_F32,
+ &Decoder::decode_OP_VOP2__V_ADD_U32,
+ &Decoder::decode_OP_VOP2__V_ADD_U32,
+ &Decoder::decode_OP_VOP2__V_ADD_U32,
+ &Decoder::decode_OP_VOP2__V_ADD_U32,
+ &Decoder::decode_OP_VOP2__V_SUB_U32,
+ &Decoder::decode_OP_VOP2__V_SUB_U32,
+ &Decoder::decode_OP_VOP2__V_SUB_U32,
+ &Decoder::decode_OP_VOP2__V_SUB_U32,
+ &Decoder::decode_OP_VOP2__V_SUBREV_U32,
+ &Decoder::decode_OP_VOP2__V_SUBREV_U32,
+ &Decoder::decode_OP_VOP2__V_SUBREV_U32,
+ &Decoder::decode_OP_VOP2__V_SUBREV_U32,
+ &Decoder::decode_OP_VOP2__V_ADDC_U32,
+ &Decoder::decode_OP_VOP2__V_ADDC_U32,
+ &Decoder::decode_OP_VOP2__V_ADDC_U32,
+ &Decoder::decode_OP_VOP2__V_ADDC_U32,
+ &Decoder::decode_OP_VOP2__V_SUBB_U32,
+ &Decoder::decode_OP_VOP2__V_SUBB_U32,
+ &Decoder::decode_OP_VOP2__V_SUBB_U32,
+ &Decoder::decode_OP_VOP2__V_SUBB_U32,
+ &Decoder::decode_OP_VOP2__V_SUBBREV_U32,
+ &Decoder::decode_OP_VOP2__V_SUBBREV_U32,
+ &Decoder::decode_OP_VOP2__V_SUBBREV_U32,
+ &Decoder::decode_OP_VOP2__V_SUBBREV_U32,
+ &Decoder::decode_OP_VOP2__V_ADD_F16,
+ &Decoder::decode_OP_VOP2__V_ADD_F16,
+ &Decoder::decode_OP_VOP2__V_ADD_F16,
+ &Decoder::decode_OP_VOP2__V_ADD_F16,
+ &Decoder::decode_OP_VOP2__V_SUB_F16,
+ &Decoder::decode_OP_VOP2__V_SUB_F16,
+ &Decoder::decode_OP_VOP2__V_SUB_F16,
+ &Decoder::decode_OP_VOP2__V_SUB_F16,
+ &Decoder::decode_OP_VOP2__V_SUBREV_F16,
+ &Decoder::decode_OP_VOP2__V_SUBREV_F16,
+ &Decoder::decode_OP_VOP2__V_SUBREV_F16,
+ &Decoder::decode_OP_VOP2__V_SUBREV_F16,
+ &Decoder::decode_OP_VOP2__V_MUL_F16,
+ &Decoder::decode_OP_VOP2__V_MUL_F16,
+ &Decoder::decode_OP_VOP2__V_MUL_F16,
+ &Decoder::decode_OP_VOP2__V_MUL_F16,
+ &Decoder::decode_OP_VOP2__V_MAC_F16,
+ &Decoder::decode_OP_VOP2__V_MAC_F16,
+ &Decoder::decode_OP_VOP2__V_MAC_F16,
+ &Decoder::decode_OP_VOP2__V_MAC_F16,
+ &Decoder::decode_OP_VOP2__V_MADMK_F16,
+ &Decoder::decode_OP_VOP2__V_MADMK_F16,
+ &Decoder::decode_OP_VOP2__V_MADMK_F16,
+ &Decoder::decode_OP_VOP2__V_MADMK_F16,
+ &Decoder::decode_OP_VOP2__V_MADAK_F16,
+ &Decoder::decode_OP_VOP2__V_MADAK_F16,
+ &Decoder::decode_OP_VOP2__V_MADAK_F16,
+ &Decoder::decode_OP_VOP2__V_MADAK_F16,
+ &Decoder::decode_OP_VOP2__V_ADD_U16,
+ &Decoder::decode_OP_VOP2__V_ADD_U16,
+ &Decoder::decode_OP_VOP2__V_ADD_U16,
+ &Decoder::decode_OP_VOP2__V_ADD_U16,
+ &Decoder::decode_OP_VOP2__V_SUB_U16,
+ &Decoder::decode_OP_VOP2__V_SUB_U16,
+ &Decoder::decode_OP_VOP2__V_SUB_U16,
+ &Decoder::decode_OP_VOP2__V_SUB_U16,
+ &Decoder::decode_OP_VOP2__V_SUBREV_U16,
+ &Decoder::decode_OP_VOP2__V_SUBREV_U16,
+ &Decoder::decode_OP_VOP2__V_SUBREV_U16,
+ &Decoder::decode_OP_VOP2__V_SUBREV_U16,
+ &Decoder::decode_OP_VOP2__V_MUL_LO_U16,
+ &Decoder::decode_OP_VOP2__V_MUL_LO_U16,
+ &Decoder::decode_OP_VOP2__V_MUL_LO_U16,
+ &Decoder::decode_OP_VOP2__V_MUL_LO_U16,
+ &Decoder::decode_OP_VOP2__V_LSHLREV_B16,
+ &Decoder::decode_OP_VOP2__V_LSHLREV_B16,
+ &Decoder::decode_OP_VOP2__V_LSHLREV_B16,
+ &Decoder::decode_OP_VOP2__V_LSHLREV_B16,
+ &Decoder::decode_OP_VOP2__V_LSHRREV_B16,
+ &Decoder::decode_OP_VOP2__V_LSHRREV_B16,
+ &Decoder::decode_OP_VOP2__V_LSHRREV_B16,
+ &Decoder::decode_OP_VOP2__V_LSHRREV_B16,
+ &Decoder::decode_OP_VOP2__V_ASHRREV_I16,
+ &Decoder::decode_OP_VOP2__V_ASHRREV_I16,
+ &Decoder::decode_OP_VOP2__V_ASHRREV_I16,
+ &Decoder::decode_OP_VOP2__V_ASHRREV_I16,
+ &Decoder::decode_OP_VOP2__V_MAX_F16,
+ &Decoder::decode_OP_VOP2__V_MAX_F16,
+ &Decoder::decode_OP_VOP2__V_MAX_F16,
+ &Decoder::decode_OP_VOP2__V_MAX_F16,
+ &Decoder::decode_OP_VOP2__V_MIN_F16,
+ &Decoder::decode_OP_VOP2__V_MIN_F16,
+ &Decoder::decode_OP_VOP2__V_MIN_F16,
+ &Decoder::decode_OP_VOP2__V_MIN_F16,
+ &Decoder::decode_OP_VOP2__V_MAX_U16,
+ &Decoder::decode_OP_VOP2__V_MAX_U16,
+ &Decoder::decode_OP_VOP2__V_MAX_U16,
+ &Decoder::decode_OP_VOP2__V_MAX_U16,
+ &Decoder::decode_OP_VOP2__V_MAX_I16,
+ &Decoder::decode_OP_VOP2__V_MAX_I16,
+ &Decoder::decode_OP_VOP2__V_MAX_I16,
+ &Decoder::decode_OP_VOP2__V_MAX_I16,
+ &Decoder::decode_OP_VOP2__V_MIN_U16,
+ &Decoder::decode_OP_VOP2__V_MIN_U16,
+ &Decoder::decode_OP_VOP2__V_MIN_U16,
+ &Decoder::decode_OP_VOP2__V_MIN_U16,
+ &Decoder::decode_OP_VOP2__V_MIN_I16,
+ &Decoder::decode_OP_VOP2__V_MIN_I16,
+ &Decoder::decode_OP_VOP2__V_MIN_I16,
+ &Decoder::decode_OP_VOP2__V_MIN_I16,
+ &Decoder::decode_OP_VOP2__V_LDEXP_F16,
+ &Decoder::decode_OP_VOP2__V_LDEXP_F16,
+ &Decoder::decode_OP_VOP2__V_LDEXP_F16,
+ &Decoder::decode_OP_VOP2__V_LDEXP_F16,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::subDecode_OP_VOPC,
+ &Decoder::subDecode_OP_VOPC,
+ &Decoder::subDecode_OP_VOPC,
+ &Decoder::subDecode_OP_VOPC,
+ &Decoder::subDecode_OP_VOP1,
+ &Decoder::subDecode_OP_VOP1,
+ &Decoder::subDecode_OP_VOP1,
+ &Decoder::subDecode_OP_VOP1,
+ &Decoder::decode_OP_SOP2__S_ADD_U32,
+ &Decoder::decode_OP_SOP2__S_SUB_U32,
+ &Decoder::decode_OP_SOP2__S_ADD_I32,
+ &Decoder::decode_OP_SOP2__S_SUB_I32,
+ &Decoder::decode_OP_SOP2__S_ADDC_U32,
+ &Decoder::decode_OP_SOP2__S_SUBB_U32,
+ &Decoder::decode_OP_SOP2__S_MIN_I32,
+ &Decoder::decode_OP_SOP2__S_MIN_U32,
+ &Decoder::decode_OP_SOP2__S_MAX_I32,
+ &Decoder::decode_OP_SOP2__S_MAX_U32,
+ &Decoder::decode_OP_SOP2__S_CSELECT_B32,
+ &Decoder::decode_OP_SOP2__S_CSELECT_B64,
+ &Decoder::decode_OP_SOP2__S_AND_B32,
+ &Decoder::decode_OP_SOP2__S_AND_B64,
+ &Decoder::decode_OP_SOP2__S_OR_B32,
+ &Decoder::decode_OP_SOP2__S_OR_B64,
+ &Decoder::decode_OP_SOP2__S_XOR_B32,
+ &Decoder::decode_OP_SOP2__S_XOR_B64,
+ &Decoder::decode_OP_SOP2__S_ANDN2_B32,
+ &Decoder::decode_OP_SOP2__S_ANDN2_B64,
+ &Decoder::decode_OP_SOP2__S_ORN2_B32,
+ &Decoder::decode_OP_SOP2__S_ORN2_B64,
+ &Decoder::decode_OP_SOP2__S_NAND_B32,
+ &Decoder::decode_OP_SOP2__S_NAND_B64,
+ &Decoder::decode_OP_SOP2__S_NOR_B32,
+ &Decoder::decode_OP_SOP2__S_NOR_B64,
+ &Decoder::decode_OP_SOP2__S_XNOR_B32,
+ &Decoder::decode_OP_SOP2__S_XNOR_B64,
+ &Decoder::decode_OP_SOP2__S_LSHL_B32,
+ &Decoder::decode_OP_SOP2__S_LSHL_B64,
+ &Decoder::decode_OP_SOP2__S_LSHR_B32,
+ &Decoder::decode_OP_SOP2__S_LSHR_B64,
+ &Decoder::decode_OP_SOP2__S_ASHR_I32,
+ &Decoder::decode_OP_SOP2__S_ASHR_I64,
+ &Decoder::decode_OP_SOP2__S_BFM_B32,
+ &Decoder::decode_OP_SOP2__S_BFM_B64,
+ &Decoder::decode_OP_SOP2__S_MUL_I32,
+ &Decoder::decode_OP_SOP2__S_BFE_U32,
+ &Decoder::decode_OP_SOP2__S_BFE_I32,
+ &Decoder::decode_OP_SOP2__S_BFE_U64,
+ &Decoder::decode_OP_SOP2__S_BFE_I64,
+ &Decoder::decode_OP_SOP2__S_CBRANCH_G_FORK,
+ &Decoder::decode_OP_SOP2__S_ABSDIFF_I32,
+ &Decoder::decode_OP_SOP2__S_RFE_RESTORE_B64,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_SOPK__S_MOVK_I32,
+ &Decoder::decode_OP_SOPK__S_CMOVK_I32,
+ &Decoder::decode_OP_SOPK__S_CMPK_EQ_I32,
+ &Decoder::decode_OP_SOPK__S_CMPK_LG_I32,
+ &Decoder::decode_OP_SOPK__S_CMPK_GT_I32,
+ &Decoder::decode_OP_SOPK__S_CMPK_GE_I32,
+ &Decoder::decode_OP_SOPK__S_CMPK_LT_I32,
+ &Decoder::decode_OP_SOPK__S_CMPK_LE_I32,
+ &Decoder::decode_OP_SOPK__S_CMPK_EQ_U32,
+ &Decoder::decode_OP_SOPK__S_CMPK_LG_U32,
+ &Decoder::decode_OP_SOPK__S_CMPK_GT_U32,
+ &Decoder::decode_OP_SOPK__S_CMPK_GE_U32,
+ &Decoder::decode_OP_SOPK__S_CMPK_LT_U32,
+ &Decoder::decode_OP_SOPK__S_CMPK_LE_U32,
+ &Decoder::decode_OP_SOPK__S_ADDK_I32,
+ &Decoder::decode_OP_SOPK__S_MULK_I32,
+ &Decoder::decode_OP_SOPK__S_CBRANCH_I_FORK,
+ &Decoder::decode_OP_SOPK__S_GETREG_B32,
+ &Decoder::decode_OP_SOPK__S_SETREG_B32,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_SOPK__S_SETREG_IMM32_B32,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::subDecode_OP_SOP1,
+ &Decoder::subDecode_OP_SOPC,
+ &Decoder::subDecode_OP_SOPP,
+ &Decoder::subDecode_OP_SMEM,
+ &Decoder::subDecode_OP_SMEM,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_EXP,
+ &Decoder::decode_OP_EXP,
+ &Decoder::decode_OP_EXP,
+ &Decoder::decode_OP_EXP,
+ &Decoder::decode_OP_EXP,
+ &Decoder::decode_OP_EXP,
+ &Decoder::decode_OP_EXP,
+ &Decoder::decode_OP_EXP,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::subDecode_OPU_VOP3,
+ &Decoder::subDecode_OPU_VOP3,
+ &Decoder::subDecode_OPU_VOP3,
+ &Decoder::subDecode_OPU_VOP3,
+ &Decoder::subDecode_OPU_VOP3,
+ &Decoder::subDecode_OPU_VOP3,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::subDecode_OP_VINTRP,
+ &Decoder::subDecode_OP_VINTRP,
+ &Decoder::subDecode_OP_VINTRP,
+ &Decoder::subDecode_OP_VINTRP,
+ &Decoder::subDecode_OP_VINTRP,
+ &Decoder::subDecode_OP_VINTRP,
+ &Decoder::subDecode_OP_VINTRP,
+ &Decoder::subDecode_OP_VINTRP,
+ &Decoder::subDecode_OP_DS,
+ &Decoder::subDecode_OP_DS,
+ &Decoder::subDecode_OP_DS,
+ &Decoder::subDecode_OP_DS,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::subDecode_OP_FLAT,
+ &Decoder::decode_invalid,
+ &Decoder::subDecode_OP_FLAT,
+ &Decoder::subDecode_OP_FLAT,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::subDecode_OP_MUBUF,
+ &Decoder::subDecode_OP_MUBUF,
+ &Decoder::subDecode_OP_MUBUF,
+ &Decoder::subDecode_OP_MUBUF,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::subDecode_OP_MTBUF,
+ &Decoder::subDecode_OP_MTBUF,
+ &Decoder::subDecode_OP_MTBUF,
+ &Decoder::subDecode_OP_MTBUF,
+ &Decoder::subDecode_OP_MTBUF,
+ &Decoder::subDecode_OP_MTBUF,
+ &Decoder::subDecode_OP_MTBUF,
+ &Decoder::subDecode_OP_MTBUF,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::subDecode_OP_MIMG,
+ &Decoder::subDecode_OP_MIMG,
+ &Decoder::subDecode_OP_MIMG,
+ &Decoder::subDecode_OP_MIMG,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid
+ };
+
+ IsaDecodeMethod Decoder::tableSubDecode_OPU_VOP3[] = {
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OPU_VOP3__V_CMP_CLASS_F32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F32,
+ &Decoder::decode_OPU_VOP3__V_CMP_CLASS_F64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F64,
+ &Decoder::decode_OPU_VOP3__V_CMP_CLASS_F16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F16,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OPU_VOP3__V_CMP_F_F16,
+ &Decoder::decode_OPU_VOP3__V_CMP_LT_F16,
+ &Decoder::decode_OPU_VOP3__V_CMP_EQ_F16,
+ &Decoder::decode_OPU_VOP3__V_CMP_LE_F16,
+ &Decoder::decode_OPU_VOP3__V_CMP_GT_F16,
+ &Decoder::decode_OPU_VOP3__V_CMP_LG_F16,
+ &Decoder::decode_OPU_VOP3__V_CMP_GE_F16,
+ &Decoder::decode_OPU_VOP3__V_CMP_O_F16,
+ &Decoder::decode_OPU_VOP3__V_CMP_U_F16,
+ &Decoder::decode_OPU_VOP3__V_CMP_NGE_F16,
+ &Decoder::decode_OPU_VOP3__V_CMP_NLG_F16,
+ &Decoder::decode_OPU_VOP3__V_CMP_NGT_F16,
+ &Decoder::decode_OPU_VOP3__V_CMP_NLE_F16,
+ &Decoder::decode_OPU_VOP3__V_CMP_NEQ_F16,
+ &Decoder::decode_OPU_VOP3__V_CMP_NLT_F16,
+ &Decoder::decode_OPU_VOP3__V_CMP_TRU_F16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_F_F16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_LT_F16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_EQ_F16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_LE_F16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_GT_F16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_LG_F16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_GE_F16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_O_F16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_U_F16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NGE_F16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NLG_F16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NGT_F16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NLE_F16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NLT_F16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_TRU_F16,
+ &Decoder::decode_OPU_VOP3__V_CMP_F_F32,
+ &Decoder::decode_OPU_VOP3__V_CMP_LT_F32,
+ &Decoder::decode_OPU_VOP3__V_CMP_EQ_F32,
+ &Decoder::decode_OPU_VOP3__V_CMP_LE_F32,
+ &Decoder::decode_OPU_VOP3__V_CMP_GT_F32,
+ &Decoder::decode_OPU_VOP3__V_CMP_LG_F32,
+ &Decoder::decode_OPU_VOP3__V_CMP_GE_F32,
+ &Decoder::decode_OPU_VOP3__V_CMP_O_F32,
+ &Decoder::decode_OPU_VOP3__V_CMP_U_F32,
+ &Decoder::decode_OPU_VOP3__V_CMP_NGE_F32,
+ &Decoder::decode_OPU_VOP3__V_CMP_NLG_F32,
+ &Decoder::decode_OPU_VOP3__V_CMP_NGT_F32,
+ &Decoder::decode_OPU_VOP3__V_CMP_NLE_F32,
+ &Decoder::decode_OPU_VOP3__V_CMP_NEQ_F32,
+ &Decoder::decode_OPU_VOP3__V_CMP_NLT_F32,
+ &Decoder::decode_OPU_VOP3__V_CMP_TRU_F32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_F_F32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_LT_F32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_EQ_F32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_LE_F32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_GT_F32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_LG_F32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_GE_F32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_O_F32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_U_F32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NGE_F32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NLG_F32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NGT_F32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NLE_F32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NLT_F32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_TRU_F32,
+ &Decoder::decode_OPU_VOP3__V_CMP_F_F64,
+ &Decoder::decode_OPU_VOP3__V_CMP_LT_F64,
+ &Decoder::decode_OPU_VOP3__V_CMP_EQ_F64,
+ &Decoder::decode_OPU_VOP3__V_CMP_LE_F64,
+ &Decoder::decode_OPU_VOP3__V_CMP_GT_F64,
+ &Decoder::decode_OPU_VOP3__V_CMP_LG_F64,
+ &Decoder::decode_OPU_VOP3__V_CMP_GE_F64,
+ &Decoder::decode_OPU_VOP3__V_CMP_O_F64,
+ &Decoder::decode_OPU_VOP3__V_CMP_U_F64,
+ &Decoder::decode_OPU_VOP3__V_CMP_NGE_F64,
+ &Decoder::decode_OPU_VOP3__V_CMP_NLG_F64,
+ &Decoder::decode_OPU_VOP3__V_CMP_NGT_F64,
+ &Decoder::decode_OPU_VOP3__V_CMP_NLE_F64,
+ &Decoder::decode_OPU_VOP3__V_CMP_NEQ_F64,
+ &Decoder::decode_OPU_VOP3__V_CMP_NLT_F64,
+ &Decoder::decode_OPU_VOP3__V_CMP_TRU_F64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_F_F64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_LT_F64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_EQ_F64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_LE_F64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_GT_F64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_LG_F64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_GE_F64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_O_F64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_U_F64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NGE_F64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NLG_F64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NGT_F64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NLE_F64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NLT_F64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_TRU_F64,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OPU_VOP3__V_CMP_F_I16,
+ &Decoder::decode_OPU_VOP3__V_CMP_LT_I16,
+ &Decoder::decode_OPU_VOP3__V_CMP_EQ_I16,
+ &Decoder::decode_OPU_VOP3__V_CMP_LE_I16,
+ &Decoder::decode_OPU_VOP3__V_CMP_GT_I16,
+ &Decoder::decode_OPU_VOP3__V_CMP_NE_I16,
+ &Decoder::decode_OPU_VOP3__V_CMP_GE_I16,
+ &Decoder::decode_OPU_VOP3__V_CMP_T_I16,
+ &Decoder::decode_OPU_VOP3__V_CMP_F_U16,
+ &Decoder::decode_OPU_VOP3__V_CMP_LT_U16,
+ &Decoder::decode_OPU_VOP3__V_CMP_EQ_U16,
+ &Decoder::decode_OPU_VOP3__V_CMP_LE_U16,
+ &Decoder::decode_OPU_VOP3__V_CMP_GT_U16,
+ &Decoder::decode_OPU_VOP3__V_CMP_NE_U16,
+ &Decoder::decode_OPU_VOP3__V_CMP_GE_U16,
+ &Decoder::decode_OPU_VOP3__V_CMP_T_U16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_F_I16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_LT_I16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_EQ_I16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_LE_I16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_GT_I16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NE_I16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_GE_I16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_T_I16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_F_U16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_LT_U16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_EQ_U16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_LE_U16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_GT_U16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NE_U16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_GE_U16,
+ &Decoder::decode_OPU_VOP3__V_CMPX_T_U16,
+ &Decoder::decode_OPU_VOP3__V_CMP_F_I32,
+ &Decoder::decode_OPU_VOP3__V_CMP_LT_I32,
+ &Decoder::decode_OPU_VOP3__V_CMP_EQ_I32,
+ &Decoder::decode_OPU_VOP3__V_CMP_LE_I32,
+ &Decoder::decode_OPU_VOP3__V_CMP_GT_I32,
+ &Decoder::decode_OPU_VOP3__V_CMP_NE_I32,
+ &Decoder::decode_OPU_VOP3__V_CMP_GE_I32,
+ &Decoder::decode_OPU_VOP3__V_CMP_T_I32,
+ &Decoder::decode_OPU_VOP3__V_CMP_F_U32,
+ &Decoder::decode_OPU_VOP3__V_CMP_LT_U32,
+ &Decoder::decode_OPU_VOP3__V_CMP_EQ_U32,
+ &Decoder::decode_OPU_VOP3__V_CMP_LE_U32,
+ &Decoder::decode_OPU_VOP3__V_CMP_GT_U32,
+ &Decoder::decode_OPU_VOP3__V_CMP_NE_U32,
+ &Decoder::decode_OPU_VOP3__V_CMP_GE_U32,
+ &Decoder::decode_OPU_VOP3__V_CMP_T_U32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_F_I32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_LT_I32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_EQ_I32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_LE_I32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_GT_I32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NE_I32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_GE_I32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_T_I32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_F_U32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_LT_U32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_EQ_U32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_LE_U32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_GT_U32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NE_U32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_GE_U32,
+ &Decoder::decode_OPU_VOP3__V_CMPX_T_U32,
+ &Decoder::decode_OPU_VOP3__V_CMP_F_I64,
+ &Decoder::decode_OPU_VOP3__V_CMP_LT_I64,
+ &Decoder::decode_OPU_VOP3__V_CMP_EQ_I64,
+ &Decoder::decode_OPU_VOP3__V_CMP_LE_I64,
+ &Decoder::decode_OPU_VOP3__V_CMP_GT_I64,
+ &Decoder::decode_OPU_VOP3__V_CMP_NE_I64,
+ &Decoder::decode_OPU_VOP3__V_CMP_GE_I64,
+ &Decoder::decode_OPU_VOP3__V_CMP_T_I64,
+ &Decoder::decode_OPU_VOP3__V_CMP_F_U64,
+ &Decoder::decode_OPU_VOP3__V_CMP_LT_U64,
+ &Decoder::decode_OPU_VOP3__V_CMP_EQ_U64,
+ &Decoder::decode_OPU_VOP3__V_CMP_LE_U64,
+ &Decoder::decode_OPU_VOP3__V_CMP_GT_U64,
+ &Decoder::decode_OPU_VOP3__V_CMP_NE_U64,
+ &Decoder::decode_OPU_VOP3__V_CMP_GE_U64,
+ &Decoder::decode_OPU_VOP3__V_CMP_T_U64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_F_I64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_LT_I64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_EQ_I64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_LE_I64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_GT_I64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NE_I64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_GE_I64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_T_I64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_F_U64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_LT_U64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_EQ_U64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_LE_U64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_GT_U64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_NE_U64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_GE_U64,
+ &Decoder::decode_OPU_VOP3__V_CMPX_T_U64,
+ &Decoder::decode_OPU_VOP3__V_CNDMASK_B32,
+ &Decoder::decode_OPU_VOP3__V_ADD_F32,
+ &Decoder::decode_OPU_VOP3__V_SUB_F32,
+ &Decoder::decode_OPU_VOP3__V_SUBREV_F32,
+ &Decoder::decode_OPU_VOP3__V_MUL_LEGACY_F32,
+ &Decoder::decode_OPU_VOP3__V_MUL_F32,
+ &Decoder::decode_OPU_VOP3__V_MUL_I32_I24,
+ &Decoder::decode_OPU_VOP3__V_MUL_HI_I32_I24,
+ &Decoder::decode_OPU_VOP3__V_MUL_U32_U24,
+ &Decoder::decode_OPU_VOP3__V_MUL_HI_U32_U24,
+ &Decoder::decode_OPU_VOP3__V_MIN_F32,
+ &Decoder::decode_OPU_VOP3__V_MAX_F32,
+ &Decoder::decode_OPU_VOP3__V_MIN_I32,
+ &Decoder::decode_OPU_VOP3__V_MAX_I32,
+ &Decoder::decode_OPU_VOP3__V_MIN_U32,
+ &Decoder::decode_OPU_VOP3__V_MAX_U32,
+ &Decoder::decode_OPU_VOP3__V_LSHRREV_B32,
+ &Decoder::decode_OPU_VOP3__V_ASHRREV_I32,
+ &Decoder::decode_OPU_VOP3__V_LSHLREV_B32,
+ &Decoder::decode_OPU_VOP3__V_AND_B32,
+ &Decoder::decode_OPU_VOP3__V_OR_B32,
+ &Decoder::decode_OPU_VOP3__V_XOR_B32,
+ &Decoder::decode_OPU_VOP3__V_MAC_F32,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OPU_VOP3__V_ADD_U32,
+ &Decoder::decode_OPU_VOP3__V_SUB_U32,
+ &Decoder::decode_OPU_VOP3__V_SUBREV_U32,
+ &Decoder::decode_OPU_VOP3__V_ADDC_U32,
+ &Decoder::decode_OPU_VOP3__V_SUBB_U32,
+ &Decoder::decode_OPU_VOP3__V_SUBBREV_U32,
+ &Decoder::decode_OPU_VOP3__V_ADD_F16,
+ &Decoder::decode_OPU_VOP3__V_SUB_F16,
+ &Decoder::decode_OPU_VOP3__V_SUBREV_F16,
+ &Decoder::decode_OPU_VOP3__V_MUL_F16,
+ &Decoder::decode_OPU_VOP3__V_MAC_F16,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OPU_VOP3__V_ADD_U16,
+ &Decoder::decode_OPU_VOP3__V_SUB_U16,
+ &Decoder::decode_OPU_VOP3__V_SUBREV_U16,
+ &Decoder::decode_OPU_VOP3__V_MUL_LO_U16,
+ &Decoder::decode_OPU_VOP3__V_LSHLREV_B16,
+ &Decoder::decode_OPU_VOP3__V_LSHRREV_B16,
+ &Decoder::decode_OPU_VOP3__V_ASHRREV_I16,
+ &Decoder::decode_OPU_VOP3__V_MAX_F16,
+ &Decoder::decode_OPU_VOP3__V_MIN_F16,
+ &Decoder::decode_OPU_VOP3__V_MAX_U16,
+ &Decoder::decode_OPU_VOP3__V_MAX_I16,
+ &Decoder::decode_OPU_VOP3__V_MIN_U16,
+ &Decoder::decode_OPU_VOP3__V_MIN_I16,
+ &Decoder::decode_OPU_VOP3__V_LDEXP_F16,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OPU_VOP3__V_NOP,
+ &Decoder::decode_OPU_VOP3__V_MOV_B32,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OPU_VOP3__V_CVT_I32_F64,
+ &Decoder::decode_OPU_VOP3__V_CVT_F64_I32,
+ &Decoder::decode_OPU_VOP3__V_CVT_F32_I32,
+ &Decoder::decode_OPU_VOP3__V_CVT_F32_U32,
+ &Decoder::decode_OPU_VOP3__V_CVT_U32_F32,
+ &Decoder::decode_OPU_VOP3__V_CVT_I32_F32,
+ &Decoder::decode_OPU_VOP3__V_MOV_FED_B32,
+ &Decoder::decode_OPU_VOP3__V_CVT_F16_F32,
+ &Decoder::decode_OPU_VOP3__V_CVT_F32_F16,
+ &Decoder::decode_OPU_VOP3__V_CVT_RPI_I32_F32,
+ &Decoder::decode_OPU_VOP3__V_CVT_FLR_I32_F32,
+ &Decoder::decode_OPU_VOP3__V_CVT_OFF_F32_I4,
+ &Decoder::decode_OPU_VOP3__V_CVT_F32_F64,
+ &Decoder::decode_OPU_VOP3__V_CVT_F64_F32,
+ &Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE0,
+ &Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE1,
+ &Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE2,
+ &Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE3,
+ &Decoder::decode_OPU_VOP3__V_CVT_U32_F64,
+ &Decoder::decode_OPU_VOP3__V_CVT_F64_U32,
+ &Decoder::decode_OPU_VOP3__V_TRUNC_F64,
+ &Decoder::decode_OPU_VOP3__V_CEIL_F64,
+ &Decoder::decode_OPU_VOP3__V_RNDNE_F64,
+ &Decoder::decode_OPU_VOP3__V_FLOOR_F64,
+ &Decoder::decode_OPU_VOP3__V_FRACT_F32,
+ &Decoder::decode_OPU_VOP3__V_TRUNC_F32,
+ &Decoder::decode_OPU_VOP3__V_CEIL_F32,
+ &Decoder::decode_OPU_VOP3__V_RNDNE_F32,
+ &Decoder::decode_OPU_VOP3__V_FLOOR_F32,
+ &Decoder::decode_OPU_VOP3__V_EXP_F32,
+ &Decoder::decode_OPU_VOP3__V_LOG_F32,
+ &Decoder::decode_OPU_VOP3__V_RCP_F32,
+ &Decoder::decode_OPU_VOP3__V_RCP_IFLAG_F32,
+ &Decoder::decode_OPU_VOP3__V_RSQ_F32,
+ &Decoder::decode_OPU_VOP3__V_RCP_F64,
+ &Decoder::decode_OPU_VOP3__V_RSQ_F64,
+ &Decoder::decode_OPU_VOP3__V_SQRT_F32,
+ &Decoder::decode_OPU_VOP3__V_SQRT_F64,
+ &Decoder::decode_OPU_VOP3__V_SIN_F32,
+ &Decoder::decode_OPU_VOP3__V_COS_F32,
+ &Decoder::decode_OPU_VOP3__V_NOT_B32,
+ &Decoder::decode_OPU_VOP3__V_BFREV_B32,
+ &Decoder::decode_OPU_VOP3__V_FFBH_U32,
+ &Decoder::decode_OPU_VOP3__V_FFBL_B32,
+ &Decoder::decode_OPU_VOP3__V_FFBH_I32,
+ &Decoder::decode_OPU_VOP3__V_FREXP_EXP_I32_F64,
+ &Decoder::decode_OPU_VOP3__V_FREXP_MANT_F64,
+ &Decoder::decode_OPU_VOP3__V_FRACT_F64,
+ &Decoder::decode_OPU_VOP3__V_FREXP_EXP_I32_F32,
+ &Decoder::decode_OPU_VOP3__V_FREXP_MANT_F32,
+ &Decoder::decode_OPU_VOP3__V_CLREXCP,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OPU_VOP3__V_CVT_F16_U16,
+ &Decoder::decode_OPU_VOP3__V_CVT_F16_I16,
+ &Decoder::decode_OPU_VOP3__V_CVT_U16_F16,
+ &Decoder::decode_OPU_VOP3__V_CVT_I16_F16,
+ &Decoder::decode_OPU_VOP3__V_RCP_F16,
+ &Decoder::decode_OPU_VOP3__V_SQRT_F16,
+ &Decoder::decode_OPU_VOP3__V_RSQ_F16,
+ &Decoder::decode_OPU_VOP3__V_LOG_F16,
+ &Decoder::decode_OPU_VOP3__V_EXP_F16,
+ &Decoder::decode_OPU_VOP3__V_FREXP_MANT_F16,
+ &Decoder::decode_OPU_VOP3__V_FREXP_EXP_I16_F16,
+ &Decoder::decode_OPU_VOP3__V_FLOOR_F16,
+ &Decoder::decode_OPU_VOP3__V_CEIL_F16,
+ &Decoder::decode_OPU_VOP3__V_TRUNC_F16,
+ &Decoder::decode_OPU_VOP3__V_RNDNE_F16,
+ &Decoder::decode_OPU_VOP3__V_FRACT_F16,
+ &Decoder::decode_OPU_VOP3__V_SIN_F16,
+ &Decoder::decode_OPU_VOP3__V_COS_F16,
+ &Decoder::decode_OPU_VOP3__V_EXP_LEGACY_F32,
+ &Decoder::decode_OPU_VOP3__V_LOG_LEGACY_F32,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OPU_VOP3__V_MAD_LEGACY_F32,
+ &Decoder::decode_OPU_VOP3__V_MAD_F32,
+ &Decoder::decode_OPU_VOP3__V_MAD_I32_I24,
+ &Decoder::decode_OPU_VOP3__V_MAD_U32_U24,
+ &Decoder::decode_OPU_VOP3__V_CUBEID_F32,
+ &Decoder::decode_OPU_VOP3__V_CUBESC_F32,
+ &Decoder::decode_OPU_VOP3__V_CUBETC_F32,
+ &Decoder::decode_OPU_VOP3__V_CUBEMA_F32,
+ &Decoder::decode_OPU_VOP3__V_BFE_U32,
+ &Decoder::decode_OPU_VOP3__V_BFE_I32,
+ &Decoder::decode_OPU_VOP3__V_BFI_B32,
+ &Decoder::decode_OPU_VOP3__V_FMA_F32,
+ &Decoder::decode_OPU_VOP3__V_FMA_F64,
+ &Decoder::decode_OPU_VOP3__V_LERP_U8,
+ &Decoder::decode_OPU_VOP3__V_ALIGNBIT_B32,
+ &Decoder::decode_OPU_VOP3__V_ALIGNBYTE_B32,
+ &Decoder::decode_OPU_VOP3__V_MIN3_F32,
+ &Decoder::decode_OPU_VOP3__V_MIN3_I32,
+ &Decoder::decode_OPU_VOP3__V_MIN3_U32,
+ &Decoder::decode_OPU_VOP3__V_MAX3_F32,
+ &Decoder::decode_OPU_VOP3__V_MAX3_I32,
+ &Decoder::decode_OPU_VOP3__V_MAX3_U32,
+ &Decoder::decode_OPU_VOP3__V_MED3_F32,
+ &Decoder::decode_OPU_VOP3__V_MED3_I32,
+ &Decoder::decode_OPU_VOP3__V_MED3_U32,
+ &Decoder::decode_OPU_VOP3__V_SAD_U8,
+ &Decoder::decode_OPU_VOP3__V_SAD_HI_U8,
+ &Decoder::decode_OPU_VOP3__V_SAD_U16,
+ &Decoder::decode_OPU_VOP3__V_SAD_U32,
+ &Decoder::decode_OPU_VOP3__V_CVT_PK_U8_F32,
+ &Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F32,
+ &Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F64,
+ &Decoder::decode_OPU_VOP3__V_DIV_SCALE_F32,
+ &Decoder::decode_OPU_VOP3__V_DIV_SCALE_F64,
+ &Decoder::decode_OPU_VOP3__V_DIV_FMAS_F32,
+ &Decoder::decode_OPU_VOP3__V_DIV_FMAS_F64,
+ &Decoder::decode_OPU_VOP3__V_MSAD_U8,
+ &Decoder::decode_OPU_VOP3__V_QSAD_PK_U16_U8,
+ &Decoder::decode_OPU_VOP3__V_MQSAD_PK_U16_U8,
+ &Decoder::decode_OPU_VOP3__V_MQSAD_U32_U8,
+ &Decoder::decode_OPU_VOP3__V_MAD_U64_U32,
+ &Decoder::decode_OPU_VOP3__V_MAD_I64_I32,
+ &Decoder::decode_OPU_VOP3__V_MAD_F16,
+ &Decoder::decode_OPU_VOP3__V_MAD_U16,
+ &Decoder::decode_OPU_VOP3__V_MAD_I16,
+ &Decoder::decode_OPU_VOP3__V_PERM_B32,
+ &Decoder::decode_OPU_VOP3__V_FMA_F16,
+ &Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F16,
+ &Decoder::decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OPU_VOP3__V_INTERP_P1_F32,
+ &Decoder::decode_OPU_VOP3__V_INTERP_P2_F32,
+ &Decoder::decode_OPU_VOP3__V_INTERP_MOV_F32,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OPU_VOP3__V_INTERP_P1LL_F16,
+ &Decoder::decode_OPU_VOP3__V_INTERP_P1LV_F16,
+ &Decoder::decode_OPU_VOP3__V_INTERP_P2_F16,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OPU_VOP3__V_ADD_F64,
+ &Decoder::decode_OPU_VOP3__V_MUL_F64,
+ &Decoder::decode_OPU_VOP3__V_MIN_F64,
+ &Decoder::decode_OPU_VOP3__V_MAX_F64,
+ &Decoder::decode_OPU_VOP3__V_LDEXP_F64,
+ &Decoder::decode_OPU_VOP3__V_MUL_LO_U32,
+ &Decoder::decode_OPU_VOP3__V_MUL_HI_U32,
+ &Decoder::decode_OPU_VOP3__V_MUL_HI_I32,
+ &Decoder::decode_OPU_VOP3__V_LDEXP_F32,
+ &Decoder::decode_OPU_VOP3__V_READLANE_B32,
+ &Decoder::decode_OPU_VOP3__V_WRITELANE_B32,
+ &Decoder::decode_OPU_VOP3__V_BCNT_U32_B32,
+ &Decoder::decode_OPU_VOP3__V_MBCNT_LO_U32_B32,
+ &Decoder::decode_OPU_VOP3__V_MBCNT_HI_U32_B32,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OPU_VOP3__V_LSHLREV_B64,
+ &Decoder::decode_OPU_VOP3__V_LSHRREV_B64,
+ &Decoder::decode_OPU_VOP3__V_ASHRREV_I64,
+ &Decoder::decode_OPU_VOP3__V_TRIG_PREOP_F64,
+ &Decoder::decode_OPU_VOP3__V_BFM_B32,
+ &Decoder::decode_OPU_VOP3__V_CVT_PKNORM_I16_F32,
+ &Decoder::decode_OPU_VOP3__V_CVT_PKNORM_U16_F32,
+ &Decoder::decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32,
+ &Decoder::decode_OPU_VOP3__V_CVT_PK_U16_U32,
+ &Decoder::decode_OPU_VOP3__V_CVT_PK_I16_I32,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid
+ };
+
+ IsaDecodeMethod Decoder::tableSubDecode_OP_DS[] = {
+ &Decoder::decode_OP_DS__DS_ADD_U32,
+ &Decoder::decode_OP_DS__DS_SUB_U32,
+ &Decoder::decode_OP_DS__DS_RSUB_U32,
+ &Decoder::decode_OP_DS__DS_INC_U32,
+ &Decoder::decode_OP_DS__DS_DEC_U32,
+ &Decoder::decode_OP_DS__DS_MIN_I32,
+ &Decoder::decode_OP_DS__DS_MAX_I32,
+ &Decoder::decode_OP_DS__DS_MIN_U32,
+ &Decoder::decode_OP_DS__DS_MAX_U32,
+ &Decoder::decode_OP_DS__DS_AND_B32,
+ &Decoder::decode_OP_DS__DS_OR_B32,
+ &Decoder::decode_OP_DS__DS_XOR_B32,
+ &Decoder::decode_OP_DS__DS_MSKOR_B32,
+ &Decoder::decode_OP_DS__DS_WRITE_B32,
+ &Decoder::decode_OP_DS__DS_WRITE2_B32,
+ &Decoder::decode_OP_DS__DS_WRITE2ST64_B32,
+ &Decoder::decode_OP_DS__DS_CMPST_B32,
+ &Decoder::decode_OP_DS__DS_CMPST_F32,
+ &Decoder::decode_OP_DS__DS_MIN_F32,
+ &Decoder::decode_OP_DS__DS_MAX_F32,
+ &Decoder::decode_OP_DS__DS_NOP,
+ &Decoder::decode_OP_DS__DS_ADD_F32,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_DS__DS_WRITE_B8,
+ &Decoder::decode_OP_DS__DS_WRITE_B16,
+ &Decoder::decode_OP_DS__DS_ADD_RTN_U32,
+ &Decoder::decode_OP_DS__DS_SUB_RTN_U32,
+ &Decoder::decode_OP_DS__DS_RSUB_RTN_U32,
+ &Decoder::decode_OP_DS__DS_INC_RTN_U32,
+ &Decoder::decode_OP_DS__DS_DEC_RTN_U32,
+ &Decoder::decode_OP_DS__DS_MIN_RTN_I32,
+ &Decoder::decode_OP_DS__DS_MAX_RTN_I32,
+ &Decoder::decode_OP_DS__DS_MIN_RTN_U32,
+ &Decoder::decode_OP_DS__DS_MAX_RTN_U32,
+ &Decoder::decode_OP_DS__DS_AND_RTN_B32,
+ &Decoder::decode_OP_DS__DS_OR_RTN_B32,
+ &Decoder::decode_OP_DS__DS_XOR_RTN_B32,
+ &Decoder::decode_OP_DS__DS_MSKOR_RTN_B32,
+ &Decoder::decode_OP_DS__DS_WRXCHG_RTN_B32,
+ &Decoder::decode_OP_DS__DS_WRXCHG2_RTN_B32,
+ &Decoder::decode_OP_DS__DS_WRXCHG2ST64_RTN_B32,
+ &Decoder::decode_OP_DS__DS_CMPST_RTN_B32,
+ &Decoder::decode_OP_DS__DS_CMPST_RTN_F32,
+ &Decoder::decode_OP_DS__DS_MIN_RTN_F32,
+ &Decoder::decode_OP_DS__DS_MAX_RTN_F32,
+ &Decoder::decode_OP_DS__DS_WRAP_RTN_B32,
+ &Decoder::decode_OP_DS__DS_ADD_RTN_F32,
+ &Decoder::decode_OP_DS__DS_READ_B32,
+ &Decoder::decode_OP_DS__DS_READ2_B32,
+ &Decoder::decode_OP_DS__DS_READ2ST64_B32,
+ &Decoder::decode_OP_DS__DS_READ_I8,
+ &Decoder::decode_OP_DS__DS_READ_U8,
+ &Decoder::decode_OP_DS__DS_READ_I16,
+ &Decoder::decode_OP_DS__DS_READ_U16,
+ &Decoder::decode_OP_DS__DS_SWIZZLE_B32,
+ &Decoder::decode_OP_DS__DS_PERMUTE_B32,
+ &Decoder::decode_OP_DS__DS_BPERMUTE_B32,
+ &Decoder::decode_OP_DS__DS_ADD_U64,
+ &Decoder::decode_OP_DS__DS_SUB_U64,
+ &Decoder::decode_OP_DS__DS_RSUB_U64,
+ &Decoder::decode_OP_DS__DS_INC_U64,
+ &Decoder::decode_OP_DS__DS_DEC_U64,
+ &Decoder::decode_OP_DS__DS_MIN_I64,
+ &Decoder::decode_OP_DS__DS_MAX_I64,
+ &Decoder::decode_OP_DS__DS_MIN_U64,
+ &Decoder::decode_OP_DS__DS_MAX_U64,
+ &Decoder::decode_OP_DS__DS_AND_B64,
+ &Decoder::decode_OP_DS__DS_OR_B64,
+ &Decoder::decode_OP_DS__DS_XOR_B64,
+ &Decoder::decode_OP_DS__DS_MSKOR_B64,
+ &Decoder::decode_OP_DS__DS_WRITE_B64,
+ &Decoder::decode_OP_DS__DS_WRITE2_B64,
+ &Decoder::decode_OP_DS__DS_WRITE2ST64_B64,
+ &Decoder::decode_OP_DS__DS_CMPST_B64,
+ &Decoder::decode_OP_DS__DS_CMPST_F64,
+ &Decoder::decode_OP_DS__DS_MIN_F64,
+ &Decoder::decode_OP_DS__DS_MAX_F64,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_DS__DS_ADD_RTN_U64,
+ &Decoder::decode_OP_DS__DS_SUB_RTN_U64,
+ &Decoder::decode_OP_DS__DS_RSUB_RTN_U64,
+ &Decoder::decode_OP_DS__DS_INC_RTN_U64,
+ &Decoder::decode_OP_DS__DS_DEC_RTN_U64,
+ &Decoder::decode_OP_DS__DS_MIN_RTN_I64,
+ &Decoder::decode_OP_DS__DS_MAX_RTN_I64,
+ &Decoder::decode_OP_DS__DS_MIN_RTN_U64,
+ &Decoder::decode_OP_DS__DS_MAX_RTN_U64,
+ &Decoder::decode_OP_DS__DS_AND_RTN_B64,
+ &Decoder::decode_OP_DS__DS_OR_RTN_B64,
+ &Decoder::decode_OP_DS__DS_XOR_RTN_B64,
+ &Decoder::decode_OP_DS__DS_MSKOR_RTN_B64,
+ &Decoder::decode_OP_DS__DS_WRXCHG_RTN_B64,
+ &Decoder::decode_OP_DS__DS_WRXCHG2_RTN_B64,
+ &Decoder::decode_OP_DS__DS_WRXCHG2ST64_RTN_B64,
+ &Decoder::decode_OP_DS__DS_CMPST_RTN_B64,
+ &Decoder::decode_OP_DS__DS_CMPST_RTN_F64,
+ &Decoder::decode_OP_DS__DS_MIN_RTN_F64,
+ &Decoder::decode_OP_DS__DS_MAX_RTN_F64,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_DS__DS_READ_B64,
+ &Decoder::decode_OP_DS__DS_READ2_B64,
+ &Decoder::decode_OP_DS__DS_READ2ST64_B64,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_DS__DS_CONDXCHG32_RTN_B64,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_DS__DS_ADD_SRC2_U32,
+ &Decoder::decode_OP_DS__DS_SUB_SRC2_U32,
+ &Decoder::decode_OP_DS__DS_RSUB_SRC2_U32,
+ &Decoder::decode_OP_DS__DS_INC_SRC2_U32,
+ &Decoder::decode_OP_DS__DS_DEC_SRC2_U32,
+ &Decoder::decode_OP_DS__DS_MIN_SRC2_I32,
+ &Decoder::decode_OP_DS__DS_MAX_SRC2_I32,
+ &Decoder::decode_OP_DS__DS_MIN_SRC2_U32,
+ &Decoder::decode_OP_DS__DS_MAX_SRC2_U32,
+ &Decoder::decode_OP_DS__DS_AND_SRC2_B32,
+ &Decoder::decode_OP_DS__DS_OR_SRC2_B32,
+ &Decoder::decode_OP_DS__DS_XOR_SRC2_B32,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_DS__DS_WRITE_SRC2_B32,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_DS__DS_MIN_SRC2_F32,
+ &Decoder::decode_OP_DS__DS_MAX_SRC2_F32,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_DS__DS_ADD_SRC2_F32,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_DS__DS_GWS_SEMA_RELEASE_ALL,
+ &Decoder::decode_OP_DS__DS_GWS_INIT,
+ &Decoder::decode_OP_DS__DS_GWS_SEMA_V,
+ &Decoder::decode_OP_DS__DS_GWS_SEMA_BR,
+ &Decoder::decode_OP_DS__DS_GWS_SEMA_P,
+ &Decoder::decode_OP_DS__DS_GWS_BARRIER,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_DS__DS_CONSUME,
+ &Decoder::decode_OP_DS__DS_APPEND,
+ &Decoder::decode_OP_DS__DS_ORDERED_COUNT,
+ &Decoder::decode_OP_DS__DS_ADD_SRC2_U64,
+ &Decoder::decode_OP_DS__DS_SUB_SRC2_U64,
+ &Decoder::decode_OP_DS__DS_RSUB_SRC2_U64,
+ &Decoder::decode_OP_DS__DS_INC_SRC2_U64,
+ &Decoder::decode_OP_DS__DS_DEC_SRC2_U64,
+ &Decoder::decode_OP_DS__DS_MIN_SRC2_I64,
+ &Decoder::decode_OP_DS__DS_MAX_SRC2_I64,
+ &Decoder::decode_OP_DS__DS_MIN_SRC2_U64,
+ &Decoder::decode_OP_DS__DS_MAX_SRC2_U64,
+ &Decoder::decode_OP_DS__DS_AND_SRC2_B64,
+ &Decoder::decode_OP_DS__DS_OR_SRC2_B64,
+ &Decoder::decode_OP_DS__DS_XOR_SRC2_B64,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_DS__DS_WRITE_SRC2_B64,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_DS__DS_MIN_SRC2_F64,
+ &Decoder::decode_OP_DS__DS_MAX_SRC2_F64,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_DS__DS_WRITE_B96,
+ &Decoder::decode_OP_DS__DS_WRITE_B128,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_DS__DS_READ_B96,
+ &Decoder::decode_OP_DS__DS_READ_B128
+ };
+
+ IsaDecodeMethod Decoder::tableSubDecode_OP_FLAT[] = {
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_FLAT__FLAT_LOAD_UBYTE,
+ &Decoder::decode_OP_FLAT__FLAT_LOAD_SBYTE,
+ &Decoder::decode_OP_FLAT__FLAT_LOAD_USHORT,
+ &Decoder::decode_OP_FLAT__FLAT_LOAD_SSHORT,
+ &Decoder::decode_OP_FLAT__FLAT_LOAD_DWORD,
+ &Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX2,
+ &Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX3,
+ &Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX4,
+ &Decoder::decode_OP_FLAT__FLAT_STORE_BYTE,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_FLAT__FLAT_STORE_SHORT,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_FLAT__FLAT_STORE_DWORD,
+ &Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX2,
+ &Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX3,
+ &Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX4,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_SWAP,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_ADD,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_SUB,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMIN,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMIN,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMAX,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMAX,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_AND,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_OR,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_XOR,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_INC,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_DEC,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_SWAP_X2,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP_X2,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_ADD_X2,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_SUB_X2,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMIN_X2,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMIN_X2,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMAX_X2,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMAX_X2,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_AND_X2,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_OR_X2,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_XOR_X2,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_INC_X2,
+ &Decoder::decode_OP_FLAT__FLAT_ATOMIC_DEC_X2,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid
+ };
+
+ IsaDecodeMethod Decoder::tableSubDecode_OP_MIMG[] = {
+ &Decoder::decode_OP_MIMG__IMAGE_LOAD,
+ &Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP,
+ &Decoder::decode_OP_MIMG__IMAGE_LOAD_PCK,
+ &Decoder::decode_OP_MIMG__IMAGE_LOAD_PCK_SGN,
+ &Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP_PCK,
+ &Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP_PCK_SGN,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_MIMG__IMAGE_STORE,
+ &Decoder::decode_OP_MIMG__IMAGE_STORE_MIP,
+ &Decoder::decode_OP_MIMG__IMAGE_STORE_PCK,
+ &Decoder::decode_OP_MIMG__IMAGE_STORE_MIP_PCK,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_MIMG__IMAGE_GET_RESINFO,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SWAP,
+ &Decoder::decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP,
+ &Decoder::decode_OP_MIMG__IMAGE_ATOMIC_ADD,
+ &Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SUB,
+ &Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SMIN,
+ &Decoder::decode_OP_MIMG__IMAGE_ATOMIC_UMIN,
+ &Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SMAX,
+ &Decoder::decode_OP_MIMG__IMAGE_ATOMIC_UMAX,
+ &Decoder::decode_OP_MIMG__IMAGE_ATOMIC_AND,
+ &Decoder::decode_OP_MIMG__IMAGE_ATOMIC_OR,
+ &Decoder::decode_OP_MIMG__IMAGE_ATOMIC_XOR,
+ &Decoder::decode_OP_MIMG__IMAGE_ATOMIC_INC,
+ &Decoder::decode_OP_MIMG__IMAGE_ATOMIC_DEC,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CL,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_CL,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_L,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_CL,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_LZ,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CL,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_L,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_LZ,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_O,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CL_O,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_O,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_CL_O,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_L_O,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_O,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_CL_O,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_LZ_O,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_O,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CL_O,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_O,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL_O,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_L_O,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_O,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL_O,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_CL,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_L,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_B,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_CL,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_LZ,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_C,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_CL,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_L,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_CL,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_LZ,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_O,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_CL_O,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_L_O,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_O,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_CL_O,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_LZ_O,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_O,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_CL_O,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_L_O,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_O,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_CL_O,
+ &Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_LZ_O,
+ &Decoder::decode_OP_MIMG__IMAGE_GET_LOD,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_CL,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_O,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_CL_O,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_O,
+ &Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL_O,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid
+ };
+
+ IsaDecodeMethod Decoder::tableSubDecode_OP_MTBUF[] = {
+ &Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_X,
+ &Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XY,
+ &Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZ,
+ &Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZW,
+ &Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_X,
+ &Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XY,
+ &Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZ,
+ &Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZW,
+ &Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_X,
+ &Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY,
+ &Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ,
+ &Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW,
+ &Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_X,
+ &Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XY,
+ &Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ,
+ &Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
+ };
+
+ IsaDecodeMethod Decoder::tableSubDecode_OP_MUBUF[] = {
+ &Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_X,
+ &Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XY,
+ &Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZ,
+ &Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZW,
+ &Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_X,
+ &Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XY,
+ &Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZ,
+ &Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZW,
+ &Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_X,
+ &Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XY,
+ &Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ,
+ &Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW,
+ &Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_X,
+ &Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XY,
+ &Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ,
+ &Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW,
+ &Decoder::decode_OP_MUBUF__BUFFER_LOAD_UBYTE,
+ &Decoder::decode_OP_MUBUF__BUFFER_LOAD_SBYTE,
+ &Decoder::decode_OP_MUBUF__BUFFER_LOAD_USHORT,
+ &Decoder::decode_OP_MUBUF__BUFFER_LOAD_SSHORT,
+ &Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORD,
+ &Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX2,
+ &Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX3,
+ &Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX4,
+ &Decoder::decode_OP_MUBUF__BUFFER_STORE_BYTE,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_MUBUF__BUFFER_STORE_SHORT,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORD,
+ &Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX2,
+ &Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX3,
+ &Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX4,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD,
+ &Decoder::decode_OP_MUBUF__BUFFER_WBINVL1,
+ &Decoder::decode_OP_MUBUF__BUFFER_WBINVL1_VOL,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SWAP,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_ADD,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SUB,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMIN,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMIN,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMAX,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMAX,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_AND,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_OR,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_XOR,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_INC,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_DEC,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SWAP_X2,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_ADD_X2,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SUB_X2,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMIN_X2,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMIN_X2,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMAX_X2,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMAX_X2,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_AND_X2,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_OR_X2,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_XOR_X2,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_INC_X2,
+ &Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_DEC_X2,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid
+ };
+
+ IsaDecodeMethod Decoder::tableSubDecode_OP_SMEM[] = {
+ &Decoder::decode_OP_SMEM__S_LOAD_DWORD,
+ &Decoder::decode_OP_SMEM__S_LOAD_DWORDX2,
+ &Decoder::decode_OP_SMEM__S_LOAD_DWORDX4,
+ &Decoder::decode_OP_SMEM__S_LOAD_DWORDX8,
+ &Decoder::decode_OP_SMEM__S_LOAD_DWORDX16,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORD,
+ &Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2,
+ &Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4,
+ &Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX8,
+ &Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX16,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_SMEM__S_STORE_DWORD,
+ &Decoder::decode_OP_SMEM__S_STORE_DWORDX2,
+ &Decoder::decode_OP_SMEM__S_STORE_DWORDX4,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORD,
+ &Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORDX2,
+ &Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORDX4,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_SMEM__S_DCACHE_INV,
+ &Decoder::decode_OP_SMEM__S_DCACHE_WB,
+ &Decoder::decode_OP_SMEM__S_DCACHE_INV_VOL,
+ &Decoder::decode_OP_SMEM__S_DCACHE_WB_VOL,
+ &Decoder::decode_OP_SMEM__S_MEMTIME,
+ &Decoder::decode_OP_SMEM__S_MEMREALTIME,
+ &Decoder::decode_OP_SMEM__S_ATC_PROBE,
+ &Decoder::decode_OP_SMEM__S_ATC_PROBE_BUFFER,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid
+ };
+
+ IsaDecodeMethod Decoder::tableSubDecode_OP_SOP1[] = {
+ &Decoder::decode_OP_SOP1__S_MOV_B32,
+ &Decoder::decode_OP_SOP1__S_MOV_B64,
+ &Decoder::decode_OP_SOP1__S_CMOV_B32,
+ &Decoder::decode_OP_SOP1__S_CMOV_B64,
+ &Decoder::decode_OP_SOP1__S_NOT_B32,
+ &Decoder::decode_OP_SOP1__S_NOT_B64,
+ &Decoder::decode_OP_SOP1__S_WQM_B32,
+ &Decoder::decode_OP_SOP1__S_WQM_B64,
+ &Decoder::decode_OP_SOP1__S_BREV_B32,
+ &Decoder::decode_OP_SOP1__S_BREV_B64,
+ &Decoder::decode_OP_SOP1__S_BCNT0_I32_B32,
+ &Decoder::decode_OP_SOP1__S_BCNT0_I32_B64,
+ &Decoder::decode_OP_SOP1__S_BCNT1_I32_B32,
+ &Decoder::decode_OP_SOP1__S_BCNT1_I32_B64,
+ &Decoder::decode_OP_SOP1__S_FF0_I32_B32,
+ &Decoder::decode_OP_SOP1__S_FF0_I32_B64,
+ &Decoder::decode_OP_SOP1__S_FF1_I32_B32,
+ &Decoder::decode_OP_SOP1__S_FF1_I32_B64,
+ &Decoder::decode_OP_SOP1__S_FLBIT_I32_B32,
+ &Decoder::decode_OP_SOP1__S_FLBIT_I32_B64,
+ &Decoder::decode_OP_SOP1__S_FLBIT_I32,
+ &Decoder::decode_OP_SOP1__S_FLBIT_I32_I64,
+ &Decoder::decode_OP_SOP1__S_SEXT_I32_I8,
+ &Decoder::decode_OP_SOP1__S_SEXT_I32_I16,
+ &Decoder::decode_OP_SOP1__S_BITSET0_B32,
+ &Decoder::decode_OP_SOP1__S_BITSET0_B64,
+ &Decoder::decode_OP_SOP1__S_BITSET1_B32,
+ &Decoder::decode_OP_SOP1__S_BITSET1_B64,
+ &Decoder::decode_OP_SOP1__S_GETPC_B64,
+ &Decoder::decode_OP_SOP1__S_SETPC_B64,
+ &Decoder::decode_OP_SOP1__S_SWAPPC_B64,
+ &Decoder::decode_OP_SOP1__S_RFE_B64,
+ &Decoder::decode_OP_SOP1__S_AND_SAVEEXEC_B64,
+ &Decoder::decode_OP_SOP1__S_OR_SAVEEXEC_B64,
+ &Decoder::decode_OP_SOP1__S_XOR_SAVEEXEC_B64,
+ &Decoder::decode_OP_SOP1__S_ANDN2_SAVEEXEC_B64,
+ &Decoder::decode_OP_SOP1__S_ORN2_SAVEEXEC_B64,
+ &Decoder::decode_OP_SOP1__S_NAND_SAVEEXEC_B64,
+ &Decoder::decode_OP_SOP1__S_NOR_SAVEEXEC_B64,
+ &Decoder::decode_OP_SOP1__S_XNOR_SAVEEXEC_B64,
+ &Decoder::decode_OP_SOP1__S_QUADMASK_B32,
+ &Decoder::decode_OP_SOP1__S_QUADMASK_B64,
+ &Decoder::decode_OP_SOP1__S_MOVRELS_B32,
+ &Decoder::decode_OP_SOP1__S_MOVRELS_B64,
+ &Decoder::decode_OP_SOP1__S_MOVRELD_B32,
+ &Decoder::decode_OP_SOP1__S_MOVRELD_B64,
+ &Decoder::decode_OP_SOP1__S_CBRANCH_JOIN,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_SOP1__S_ABS_I32,
+ &Decoder::decode_OP_SOP1__S_MOV_FED_B32,
+ &Decoder::decode_OP_SOP1__S_SET_GPR_IDX_IDX,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid
+ };
+
+ IsaDecodeMethod Decoder::tableSubDecode_OP_SOPC[] = {
+ &Decoder::decode_OP_SOPC__S_CMP_EQ_I32,
+ &Decoder::decode_OP_SOPC__S_CMP_LG_I32,
+ &Decoder::decode_OP_SOPC__S_CMP_GT_I32,
+ &Decoder::decode_OP_SOPC__S_CMP_GE_I32,
+ &Decoder::decode_OP_SOPC__S_CMP_LT_I32,
+ &Decoder::decode_OP_SOPC__S_CMP_LE_I32,
+ &Decoder::decode_OP_SOPC__S_CMP_EQ_U32,
+ &Decoder::decode_OP_SOPC__S_CMP_LG_U32,
+ &Decoder::decode_OP_SOPC__S_CMP_GT_U32,
+ &Decoder::decode_OP_SOPC__S_CMP_GE_U32,
+ &Decoder::decode_OP_SOPC__S_CMP_LT_U32,
+ &Decoder::decode_OP_SOPC__S_CMP_LE_U32,
+ &Decoder::decode_OP_SOPC__S_BITCMP0_B32,
+ &Decoder::decode_OP_SOPC__S_BITCMP1_B32,
+ &Decoder::decode_OP_SOPC__S_BITCMP0_B64,
+ &Decoder::decode_OP_SOPC__S_BITCMP1_B64,
+ &Decoder::decode_OP_SOPC__S_SETVSKIP,
+ &Decoder::decode_OP_SOPC__S_SET_GPR_IDX_ON,
+ &Decoder::decode_OP_SOPC__S_CMP_EQ_U64,
+ &Decoder::decode_OP_SOPC__S_CMP_LG_U64,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid
+ };
+
+ IsaDecodeMethod Decoder::tableSubDecode_OP_SOPP[] = {
+ &Decoder::decode_OP_SOPP__S_NOP,
+ &Decoder::decode_OP_SOPP__S_ENDPGM,
+ &Decoder::decode_OP_SOPP__S_BRANCH,
+ &Decoder::decode_OP_SOPP__S_WAKEUP,
+ &Decoder::decode_OP_SOPP__S_CBRANCH_SCC0,
+ &Decoder::decode_OP_SOPP__S_CBRANCH_SCC1,
+ &Decoder::decode_OP_SOPP__S_CBRANCH_VCCZ,
+ &Decoder::decode_OP_SOPP__S_CBRANCH_VCCNZ,
+ &Decoder::decode_OP_SOPP__S_CBRANCH_EXECZ,
+ &Decoder::decode_OP_SOPP__S_CBRANCH_EXECNZ,
+ &Decoder::decode_OP_SOPP__S_BARRIER,
+ &Decoder::decode_OP_SOPP__S_SETKILL,
+ &Decoder::decode_OP_SOPP__S_WAITCNT,
+ &Decoder::decode_OP_SOPP__S_SETHALT,
+ &Decoder::decode_OP_SOPP__S_SLEEP,
+ &Decoder::decode_OP_SOPP__S_SETPRIO,
+ &Decoder::decode_OP_SOPP__S_SENDMSG,
+ &Decoder::decode_OP_SOPP__S_SENDMSGHALT,
+ &Decoder::decode_OP_SOPP__S_TRAP,
+ &Decoder::decode_OP_SOPP__S_ICACHE_INV,
+ &Decoder::decode_OP_SOPP__S_INCPERFLEVEL,
+ &Decoder::decode_OP_SOPP__S_DECPERFLEVEL,
+ &Decoder::decode_OP_SOPP__S_TTRACEDATA,
+ &Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS,
+ &Decoder::decode_OP_SOPP__S_CBRANCH_CDBGUSER,
+ &Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS_OR_USER,
+ &Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS_AND_USER,
+ &Decoder::decode_OP_SOPP__S_ENDPGM_SAVED,
+ &Decoder::decode_OP_SOPP__S_SET_GPR_IDX_OFF,
+ &Decoder::decode_OP_SOPP__S_SET_GPR_IDX_MODE,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid
+ };
+
+ IsaDecodeMethod Decoder::tableSubDecode_OP_VINTRP[] = {
+ &Decoder::decode_OP_VINTRP__V_INTERP_P1_F32,
+ &Decoder::decode_OP_VINTRP__V_INTERP_P2_F32,
+ &Decoder::decode_OP_VINTRP__V_INTERP_MOV_F32,
+ &Decoder::decode_invalid
+ };
+
+ IsaDecodeMethod Decoder::tableSubDecode_OP_VOP1[] = {
+ &Decoder::decode_OP_VOP1__V_NOP,
+ &Decoder::decode_OP_VOP1__V_MOV_B32,
+ &Decoder::decode_OP_VOP1__V_READFIRSTLANE_B32,
+ &Decoder::decode_OP_VOP1__V_CVT_I32_F64,
+ &Decoder::decode_OP_VOP1__V_CVT_F64_I32,
+ &Decoder::decode_OP_VOP1__V_CVT_F32_I32,
+ &Decoder::decode_OP_VOP1__V_CVT_F32_U32,
+ &Decoder::decode_OP_VOP1__V_CVT_U32_F32,
+ &Decoder::decode_OP_VOP1__V_CVT_I32_F32,
+ &Decoder::decode_OP_VOP1__V_MOV_FED_B32,
+ &Decoder::decode_OP_VOP1__V_CVT_F16_F32,
+ &Decoder::decode_OP_VOP1__V_CVT_F32_F16,
+ &Decoder::decode_OP_VOP1__V_CVT_RPI_I32_F32,
+ &Decoder::decode_OP_VOP1__V_CVT_FLR_I32_F32,
+ &Decoder::decode_OP_VOP1__V_CVT_OFF_F32_I4,
+ &Decoder::decode_OP_VOP1__V_CVT_F32_F64,
+ &Decoder::decode_OP_VOP1__V_CVT_F64_F32,
+ &Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE0,
+ &Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE1,
+ &Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE2,
+ &Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE3,
+ &Decoder::decode_OP_VOP1__V_CVT_U32_F64,
+ &Decoder::decode_OP_VOP1__V_CVT_F64_U32,
+ &Decoder::decode_OP_VOP1__V_TRUNC_F64,
+ &Decoder::decode_OP_VOP1__V_CEIL_F64,
+ &Decoder::decode_OP_VOP1__V_RNDNE_F64,
+ &Decoder::decode_OP_VOP1__V_FLOOR_F64,
+ &Decoder::decode_OP_VOP1__V_FRACT_F32,
+ &Decoder::decode_OP_VOP1__V_TRUNC_F32,
+ &Decoder::decode_OP_VOP1__V_CEIL_F32,
+ &Decoder::decode_OP_VOP1__V_RNDNE_F32,
+ &Decoder::decode_OP_VOP1__V_FLOOR_F32,
+ &Decoder::decode_OP_VOP1__V_EXP_F32,
+ &Decoder::decode_OP_VOP1__V_LOG_F32,
+ &Decoder::decode_OP_VOP1__V_RCP_F32,
+ &Decoder::decode_OP_VOP1__V_RCP_IFLAG_F32,
+ &Decoder::decode_OP_VOP1__V_RSQ_F32,
+ &Decoder::decode_OP_VOP1__V_RCP_F64,
+ &Decoder::decode_OP_VOP1__V_RSQ_F64,
+ &Decoder::decode_OP_VOP1__V_SQRT_F32,
+ &Decoder::decode_OP_VOP1__V_SQRT_F64,
+ &Decoder::decode_OP_VOP1__V_SIN_F32,
+ &Decoder::decode_OP_VOP1__V_COS_F32,
+ &Decoder::decode_OP_VOP1__V_NOT_B32,
+ &Decoder::decode_OP_VOP1__V_BFREV_B32,
+ &Decoder::decode_OP_VOP1__V_FFBH_U32,
+ &Decoder::decode_OP_VOP1__V_FFBL_B32,
+ &Decoder::decode_OP_VOP1__V_FFBH_I32,
+ &Decoder::decode_OP_VOP1__V_FREXP_EXP_I32_F64,
+ &Decoder::decode_OP_VOP1__V_FREXP_MANT_F64,
+ &Decoder::decode_OP_VOP1__V_FRACT_F64,
+ &Decoder::decode_OP_VOP1__V_FREXP_EXP_I32_F32,
+ &Decoder::decode_OP_VOP1__V_FREXP_MANT_F32,
+ &Decoder::decode_OP_VOP1__V_CLREXCP,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_VOP1__V_CVT_F16_U16,
+ &Decoder::decode_OP_VOP1__V_CVT_F16_I16,
+ &Decoder::decode_OP_VOP1__V_CVT_U16_F16,
+ &Decoder::decode_OP_VOP1__V_CVT_I16_F16,
+ &Decoder::decode_OP_VOP1__V_RCP_F16,
+ &Decoder::decode_OP_VOP1__V_SQRT_F16,
+ &Decoder::decode_OP_VOP1__V_RSQ_F16,
+ &Decoder::decode_OP_VOP1__V_LOG_F16,
+ &Decoder::decode_OP_VOP1__V_EXP_F16,
+ &Decoder::decode_OP_VOP1__V_FREXP_MANT_F16,
+ &Decoder::decode_OP_VOP1__V_FREXP_EXP_I16_F16,
+ &Decoder::decode_OP_VOP1__V_FLOOR_F16,
+ &Decoder::decode_OP_VOP1__V_CEIL_F16,
+ &Decoder::decode_OP_VOP1__V_TRUNC_F16,
+ &Decoder::decode_OP_VOP1__V_RNDNE_F16,
+ &Decoder::decode_OP_VOP1__V_FRACT_F16,
+ &Decoder::decode_OP_VOP1__V_SIN_F16,
+ &Decoder::decode_OP_VOP1__V_COS_F16,
+ &Decoder::decode_OP_VOP1__V_EXP_LEGACY_F32,
+ &Decoder::decode_OP_VOP1__V_LOG_LEGACY_F32,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid
+ };
+
+ IsaDecodeMethod Decoder::tableSubDecode_OP_VOPC[] = {
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_VOPC__V_CMP_CLASS_F32,
+ &Decoder::decode_OP_VOPC__V_CMPX_CLASS_F32,
+ &Decoder::decode_OP_VOPC__V_CMP_CLASS_F64,
+ &Decoder::decode_OP_VOPC__V_CMPX_CLASS_F64,
+ &Decoder::decode_OP_VOPC__V_CMP_CLASS_F16,
+ &Decoder::decode_OP_VOPC__V_CMPX_CLASS_F16,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_VOPC__V_CMP_F_F16,
+ &Decoder::decode_OP_VOPC__V_CMP_LT_F16,
+ &Decoder::decode_OP_VOPC__V_CMP_EQ_F16,
+ &Decoder::decode_OP_VOPC__V_CMP_LE_F16,
+ &Decoder::decode_OP_VOPC__V_CMP_GT_F16,
+ &Decoder::decode_OP_VOPC__V_CMP_LG_F16,
+ &Decoder::decode_OP_VOPC__V_CMP_GE_F16,
+ &Decoder::decode_OP_VOPC__V_CMP_O_F16,
+ &Decoder::decode_OP_VOPC__V_CMP_U_F16,
+ &Decoder::decode_OP_VOPC__V_CMP_NGE_F16,
+ &Decoder::decode_OP_VOPC__V_CMP_NLG_F16,
+ &Decoder::decode_OP_VOPC__V_CMP_NGT_F16,
+ &Decoder::decode_OP_VOPC__V_CMP_NLE_F16,
+ &Decoder::decode_OP_VOPC__V_CMP_NEQ_F16,
+ &Decoder::decode_OP_VOPC__V_CMP_NLT_F16,
+ &Decoder::decode_OP_VOPC__V_CMP_TRU_F16,
+ &Decoder::decode_OP_VOPC__V_CMPX_F_F16,
+ &Decoder::decode_OP_VOPC__V_CMPX_LT_F16,
+ &Decoder::decode_OP_VOPC__V_CMPX_EQ_F16,
+ &Decoder::decode_OP_VOPC__V_CMPX_LE_F16,
+ &Decoder::decode_OP_VOPC__V_CMPX_GT_F16,
+ &Decoder::decode_OP_VOPC__V_CMPX_LG_F16,
+ &Decoder::decode_OP_VOPC__V_CMPX_GE_F16,
+ &Decoder::decode_OP_VOPC__V_CMPX_O_F16,
+ &Decoder::decode_OP_VOPC__V_CMPX_U_F16,
+ &Decoder::decode_OP_VOPC__V_CMPX_NGE_F16,
+ &Decoder::decode_OP_VOPC__V_CMPX_NLG_F16,
+ &Decoder::decode_OP_VOPC__V_CMPX_NGT_F16,
+ &Decoder::decode_OP_VOPC__V_CMPX_NLE_F16,
+ &Decoder::decode_OP_VOPC__V_CMPX_NEQ_F16,
+ &Decoder::decode_OP_VOPC__V_CMPX_NLT_F16,
+ &Decoder::decode_OP_VOPC__V_CMPX_TRU_F16,
+ &Decoder::decode_OP_VOPC__V_CMP_F_F32,
+ &Decoder::decode_OP_VOPC__V_CMP_LT_F32,
+ &Decoder::decode_OP_VOPC__V_CMP_EQ_F32,
+ &Decoder::decode_OP_VOPC__V_CMP_LE_F32,
+ &Decoder::decode_OP_VOPC__V_CMP_GT_F32,
+ &Decoder::decode_OP_VOPC__V_CMP_LG_F32,
+ &Decoder::decode_OP_VOPC__V_CMP_GE_F32,
+ &Decoder::decode_OP_VOPC__V_CMP_O_F32,
+ &Decoder::decode_OP_VOPC__V_CMP_U_F32,
+ &Decoder::decode_OP_VOPC__V_CMP_NGE_F32,
+ &Decoder::decode_OP_VOPC__V_CMP_NLG_F32,
+ &Decoder::decode_OP_VOPC__V_CMP_NGT_F32,
+ &Decoder::decode_OP_VOPC__V_CMP_NLE_F32,
+ &Decoder::decode_OP_VOPC__V_CMP_NEQ_F32,
+ &Decoder::decode_OP_VOPC__V_CMP_NLT_F32,
+ &Decoder::decode_OP_VOPC__V_CMP_TRU_F32,
+ &Decoder::decode_OP_VOPC__V_CMPX_F_F32,
+ &Decoder::decode_OP_VOPC__V_CMPX_LT_F32,
+ &Decoder::decode_OP_VOPC__V_CMPX_EQ_F32,
+ &Decoder::decode_OP_VOPC__V_CMPX_LE_F32,
+ &Decoder::decode_OP_VOPC__V_CMPX_GT_F32,
+ &Decoder::decode_OP_VOPC__V_CMPX_LG_F32,
+ &Decoder::decode_OP_VOPC__V_CMPX_GE_F32,
+ &Decoder::decode_OP_VOPC__V_CMPX_O_F32,
+ &Decoder::decode_OP_VOPC__V_CMPX_U_F32,
+ &Decoder::decode_OP_VOPC__V_CMPX_NGE_F32,
+ &Decoder::decode_OP_VOPC__V_CMPX_NLG_F32,
+ &Decoder::decode_OP_VOPC__V_CMPX_NGT_F32,
+ &Decoder::decode_OP_VOPC__V_CMPX_NLE_F32,
+ &Decoder::decode_OP_VOPC__V_CMPX_NEQ_F32,
+ &Decoder::decode_OP_VOPC__V_CMPX_NLT_F32,
+ &Decoder::decode_OP_VOPC__V_CMPX_TRU_F32,
+ &Decoder::decode_OP_VOPC__V_CMP_F_F64,
+ &Decoder::decode_OP_VOPC__V_CMP_LT_F64,
+ &Decoder::decode_OP_VOPC__V_CMP_EQ_F64,
+ &Decoder::decode_OP_VOPC__V_CMP_LE_F64,
+ &Decoder::decode_OP_VOPC__V_CMP_GT_F64,
+ &Decoder::decode_OP_VOPC__V_CMP_LG_F64,
+ &Decoder::decode_OP_VOPC__V_CMP_GE_F64,
+ &Decoder::decode_OP_VOPC__V_CMP_O_F64,
+ &Decoder::decode_OP_VOPC__V_CMP_U_F64,
+ &Decoder::decode_OP_VOPC__V_CMP_NGE_F64,
+ &Decoder::decode_OP_VOPC__V_CMP_NLG_F64,
+ &Decoder::decode_OP_VOPC__V_CMP_NGT_F64,
+ &Decoder::decode_OP_VOPC__V_CMP_NLE_F64,
+ &Decoder::decode_OP_VOPC__V_CMP_NEQ_F64,
+ &Decoder::decode_OP_VOPC__V_CMP_NLT_F64,
+ &Decoder::decode_OP_VOPC__V_CMP_TRU_F64,
+ &Decoder::decode_OP_VOPC__V_CMPX_F_F64,
+ &Decoder::decode_OP_VOPC__V_CMPX_LT_F64,
+ &Decoder::decode_OP_VOPC__V_CMPX_EQ_F64,
+ &Decoder::decode_OP_VOPC__V_CMPX_LE_F64,
+ &Decoder::decode_OP_VOPC__V_CMPX_GT_F64,
+ &Decoder::decode_OP_VOPC__V_CMPX_LG_F64,
+ &Decoder::decode_OP_VOPC__V_CMPX_GE_F64,
+ &Decoder::decode_OP_VOPC__V_CMPX_O_F64,
+ &Decoder::decode_OP_VOPC__V_CMPX_U_F64,
+ &Decoder::decode_OP_VOPC__V_CMPX_NGE_F64,
+ &Decoder::decode_OP_VOPC__V_CMPX_NLG_F64,
+ &Decoder::decode_OP_VOPC__V_CMPX_NGT_F64,
+ &Decoder::decode_OP_VOPC__V_CMPX_NLE_F64,
+ &Decoder::decode_OP_VOPC__V_CMPX_NEQ_F64,
+ &Decoder::decode_OP_VOPC__V_CMPX_NLT_F64,
+ &Decoder::decode_OP_VOPC__V_CMPX_TRU_F64,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_invalid,
+ &Decoder::decode_OP_VOPC__V_CMP_F_I16,
+ &Decoder::decode_OP_VOPC__V_CMP_LT_I16,
+ &Decoder::decode_OP_VOPC__V_CMP_EQ_I16,
+ &Decoder::decode_OP_VOPC__V_CMP_LE_I16,
+ &Decoder::decode_OP_VOPC__V_CMP_GT_I16,
+ &Decoder::decode_OP_VOPC__V_CMP_NE_I16,
+ &Decoder::decode_OP_VOPC__V_CMP_GE_I16,
+ &Decoder::decode_OP_VOPC__V_CMP_T_I16,
+ &Decoder::decode_OP_VOPC__V_CMP_F_U16,
+ &Decoder::decode_OP_VOPC__V_CMP_LT_U16,
+ &Decoder::decode_OP_VOPC__V_CMP_EQ_U16,
+ &Decoder::decode_OP_VOPC__V_CMP_LE_U16,
+ &Decoder::decode_OP_VOPC__V_CMP_GT_U16,
+ &Decoder::decode_OP_VOPC__V_CMP_NE_U16,
+ &Decoder::decode_OP_VOPC__V_CMP_GE_U16,
+ &Decoder::decode_OP_VOPC__V_CMP_T_U16,
+ &Decoder::decode_OP_VOPC__V_CMPX_F_I16,
+ &Decoder::decode_OP_VOPC__V_CMPX_LT_I16,
+ &Decoder::decode_OP_VOPC__V_CMPX_EQ_I16,
+ &Decoder::decode_OP_VOPC__V_CMPX_LE_I16,
+ &Decoder::decode_OP_VOPC__V_CMPX_GT_I16,
+ &Decoder::decode_OP_VOPC__V_CMPX_NE_I16,
+ &Decoder::decode_OP_VOPC__V_CMPX_GE_I16,
+ &Decoder::decode_OP_VOPC__V_CMPX_T_I16,
+ &Decoder::decode_OP_VOPC__V_CMPX_F_U16,
+ &Decoder::decode_OP_VOPC__V_CMPX_LT_U16,
+ &Decoder::decode_OP_VOPC__V_CMPX_EQ_U16,
+ &Decoder::decode_OP_VOPC__V_CMPX_LE_U16,
+ &Decoder::decode_OP_VOPC__V_CMPX_GT_U16,
+ &Decoder::decode_OP_VOPC__V_CMPX_NE_U16,
+ &Decoder::decode_OP_VOPC__V_CMPX_GE_U16,
+ &Decoder::decode_OP_VOPC__V_CMPX_T_U16,
+ &Decoder::decode_OP_VOPC__V_CMP_F_I32,
+ &Decoder::decode_OP_VOPC__V_CMP_LT_I32,
+ &Decoder::decode_OP_VOPC__V_CMP_EQ_I32,
+ &Decoder::decode_OP_VOPC__V_CMP_LE_I32,
+ &Decoder::decode_OP_VOPC__V_CMP_GT_I32,
+ &Decoder::decode_OP_VOPC__V_CMP_NE_I32,
+ &Decoder::decode_OP_VOPC__V_CMP_GE_I32,
+ &Decoder::decode_OP_VOPC__V_CMP_T_I32,
+ &Decoder::decode_OP_VOPC__V_CMP_F_U32,
+ &Decoder::decode_OP_VOPC__V_CMP_LT_U32,
+ &Decoder::decode_OP_VOPC__V_CMP_EQ_U32,
+ &Decoder::decode_OP_VOPC__V_CMP_LE_U32,
+ &Decoder::decode_OP_VOPC__V_CMP_GT_U32,
+ &Decoder::decode_OP_VOPC__V_CMP_NE_U32,
+ &Decoder::decode_OP_VOPC__V_CMP_GE_U32,
+ &Decoder::decode_OP_VOPC__V_CMP_T_U32,
+ &Decoder::decode_OP_VOPC__V_CMPX_F_I32,
+ &Decoder::decode_OP_VOPC__V_CMPX_LT_I32,
+ &Decoder::decode_OP_VOPC__V_CMPX_EQ_I32,
+ &Decoder::decode_OP_VOPC__V_CMPX_LE_I32,
+ &Decoder::decode_OP_VOPC__V_CMPX_GT_I32,
+ &Decoder::decode_OP_VOPC__V_CMPX_NE_I32,
+ &Decoder::decode_OP_VOPC__V_CMPX_GE_I32,
+ &Decoder::decode_OP_VOPC__V_CMPX_T_I32,
+ &Decoder::decode_OP_VOPC__V_CMPX_F_U32,
+ &Decoder::decode_OP_VOPC__V_CMPX_LT_U32,
+ &Decoder::decode_OP_VOPC__V_CMPX_EQ_U32,
+ &Decoder::decode_OP_VOPC__V_CMPX_LE_U32,
+ &Decoder::decode_OP_VOPC__V_CMPX_GT_U32,
+ &Decoder::decode_OP_VOPC__V_CMPX_NE_U32,
+ &Decoder::decode_OP_VOPC__V_CMPX_GE_U32,
+ &Decoder::decode_OP_VOPC__V_CMPX_T_U32,
+ &Decoder::decode_OP_VOPC__V_CMP_F_I64,
+ &Decoder::decode_OP_VOPC__V_CMP_LT_I64,
+ &Decoder::decode_OP_VOPC__V_CMP_EQ_I64,
+ &Decoder::decode_OP_VOPC__V_CMP_LE_I64,
+ &Decoder::decode_OP_VOPC__V_CMP_GT_I64,
+ &Decoder::decode_OP_VOPC__V_CMP_NE_I64,
+ &Decoder::decode_OP_VOPC__V_CMP_GE_I64,
+ &Decoder::decode_OP_VOPC__V_CMP_T_I64,
+ &Decoder::decode_OP_VOPC__V_CMP_F_U64,
+ &Decoder::decode_OP_VOPC__V_CMP_LT_U64,
+ &Decoder::decode_OP_VOPC__V_CMP_EQ_U64,
+ &Decoder::decode_OP_VOPC__V_CMP_LE_U64,
+ &Decoder::decode_OP_VOPC__V_CMP_GT_U64,
+ &Decoder::decode_OP_VOPC__V_CMP_NE_U64,
+ &Decoder::decode_OP_VOPC__V_CMP_GE_U64,
+ &Decoder::decode_OP_VOPC__V_CMP_T_U64,
+ &Decoder::decode_OP_VOPC__V_CMPX_F_I64,
+ &Decoder::decode_OP_VOPC__V_CMPX_LT_I64,
+ &Decoder::decode_OP_VOPC__V_CMPX_EQ_I64,
+ &Decoder::decode_OP_VOPC__V_CMPX_LE_I64,
+ &Decoder::decode_OP_VOPC__V_CMPX_GT_I64,
+ &Decoder::decode_OP_VOPC__V_CMPX_NE_I64,
+ &Decoder::decode_OP_VOPC__V_CMPX_GE_I64,
+ &Decoder::decode_OP_VOPC__V_CMPX_T_I64,
+ &Decoder::decode_OP_VOPC__V_CMPX_F_U64,
+ &Decoder::decode_OP_VOPC__V_CMPX_LT_U64,
+ &Decoder::decode_OP_VOPC__V_CMPX_EQ_U64,
+ &Decoder::decode_OP_VOPC__V_CMPX_LE_U64,
+ &Decoder::decode_OP_VOPC__V_CMPX_GT_U64,
+ &Decoder::decode_OP_VOPC__V_CMPX_NE_U64,
+ &Decoder::decode_OP_VOPC__V_CMPX_GE_U64,
+ &Decoder::decode_OP_VOPC__V_CMPX_T_U64,
+ };
+
+ GPUStaticInst*
+ Decoder::decode(MachInst mach_inst)
+ {
+ InFmt_SOP1 *enc = &mach_inst->iFmt_SOP1;
+ IsaDecodeMethod method = tableDecodePrimary[enc->ENCODING];
+ return (this->*method)(mach_inst);
+ } // decode
+
+ GPUStaticInst*
+ Decoder::subDecode_OP_VOPC(MachInst iFmt)
+ {
+ InFmt_VOPC *enc = &iFmt->iFmt_VOPC;
+ IsaDecodeMethod method = tableSubDecode_OP_VOPC[enc->OP];
+ return (this->*method)(iFmt);
+ } // subDecode_OP_VOPC
+
+ GPUStaticInst*
+ Decoder::subDecode_OP_VOP1(MachInst iFmt)
+ {
+ InFmt_VOP1 *enc = &iFmt->iFmt_VOP1;
+ IsaDecodeMethod method = tableSubDecode_OP_VOP1[enc->OP];
+ return (this->*method)(iFmt);
+ } // subDecode_OP_VOP1
+
+ GPUStaticInst*
+ Decoder::subDecode_OP_SOP1(MachInst iFmt)
+ {
+ InFmt_SOP1 *enc = &iFmt->iFmt_SOP1;
+ IsaDecodeMethod method = tableSubDecode_OP_SOP1[enc->OP];
+ return (this->*method)(iFmt);
+ } // subDecode_OP_SOP1
+
+ GPUStaticInst*
+ Decoder::subDecode_OP_SOPC(MachInst iFmt)
+ {
+ InFmt_SOPC *enc = &iFmt->iFmt_SOPC;
+ IsaDecodeMethod method = tableSubDecode_OP_SOPC[enc->OP];
+ return (this->*method)(iFmt);
+ } // subDecode_OP_SOPC
+
+ GPUStaticInst*
+ Decoder::subDecode_OP_SOPP(MachInst iFmt)
+ {
+ InFmt_SOPP *enc = &iFmt->iFmt_SOPP;
+ IsaDecodeMethod method = tableSubDecode_OP_SOPP[enc->OP];
+ return (this->*method)(iFmt);
+ } // subDecode_OP_SOPP
+
+ GPUStaticInst*
+ Decoder::subDecode_OP_SMEM(MachInst iFmt)
+ {
+ InFmt_SMEM *enc = &iFmt->iFmt_SMEM;
+ IsaDecodeMethod method = tableSubDecode_OP_SMEM[enc->OP];
+ return (this->*method)(iFmt);
+ } // subDecode_OP_SMEM
+
+ GPUStaticInst*
+ Decoder::subDecode_OPU_VOP3(MachInst iFmt)
+ {
+ InFmt_VOP3 *enc = &iFmt->iFmt_VOP3;
+ IsaDecodeMethod method = tableSubDecode_OPU_VOP3[enc->OP];
+ return (this->*method)(iFmt);
+ } // subDecode_OPU_VOP3
+
+ GPUStaticInst*
+ Decoder::subDecode_OP_VINTRP(MachInst iFmt)
+ {
+ InFmt_VINTRP *enc = &iFmt->iFmt_VINTRP;
+ IsaDecodeMethod method = tableSubDecode_OP_VINTRP[enc->OP];
+ return (this->*method)(iFmt);
+ } // subDecode_OP_VINTRP
+
+ GPUStaticInst*
+ Decoder::subDecode_OP_DS(MachInst iFmt)
+ {
+ InFmt_DS *enc = &iFmt->iFmt_DS;
+ IsaDecodeMethod method = tableSubDecode_OP_DS[enc->OP];
+ return (this->*method)(iFmt);
+ } // subDecode_OP_DS
+
+ GPUStaticInst*
+ Decoder::subDecode_OP_FLAT(MachInst iFmt)
+ {
+ InFmt_FLAT *enc = &iFmt->iFmt_FLAT;
+ IsaDecodeMethod method = tableSubDecode_OP_FLAT[enc->OP];
+ return (this->*method)(iFmt);
+ } // subDecode_OP_FLAT
+
+ GPUStaticInst*
+ Decoder::subDecode_OP_MUBUF(MachInst iFmt)
+ {
+ InFmt_MUBUF *enc = &iFmt->iFmt_MUBUF;
+ IsaDecodeMethod method = tableSubDecode_OP_MUBUF[enc->OP];
+ return (this->*method)(iFmt);
+ } // subDecode_OP_MUBUF
+
+ GPUStaticInst*
+ Decoder::subDecode_OP_MTBUF(MachInst iFmt)
+ {
+ InFmt_MTBUF *enc = &iFmt->iFmt_MTBUF;
+ IsaDecodeMethod method = tableSubDecode_OP_MTBUF[enc->OP];
+ return (this->*method)(iFmt);
+ } // subDecode_OP_MTBUF
+
+ GPUStaticInst*
+ Decoder::subDecode_OP_MIMG(MachInst iFmt)
+ {
+ InFmt_MIMG *enc = &iFmt->iFmt_MIMG;
+ IsaDecodeMethod method = tableSubDecode_OP_MIMG[enc->OP];
+ return (this->*method)(iFmt);
+ } // subDecode_OP_MIMG
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_CNDMASK_B32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_CNDMASK_B32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_CNDMASK_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_ADD_F32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_ADD_F32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_ADD_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_SUB_F32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_SUB_F32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_SUB_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_SUBREV_F32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_SUBREV_F32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_SUBREV_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MUL_LEGACY_F32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MUL_LEGACY_F32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MUL_LEGACY_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MUL_F32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MUL_F32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MUL_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MUL_I32_I24(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MUL_I32_I24(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MUL_I32_I24
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MUL_HI_I32_I24(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MUL_HI_I32_I24(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MUL_HI_I32_I24
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MUL_U32_U24(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MUL_U32_U24(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MUL_U32_U24
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MUL_HI_U32_U24(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MUL_HI_U32_U24(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MUL_HI_U32_U24
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MIN_F32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MIN_F32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MIN_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MAX_F32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MAX_F32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MAX_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MIN_I32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MIN_I32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MIN_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MAX_I32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MAX_I32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MAX_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MIN_U32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MIN_U32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MIN_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MAX_U32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MAX_U32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MAX_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_LSHRREV_B32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_LSHRREV_B32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_LSHRREV_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_ASHRREV_I32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_ASHRREV_I32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_ASHRREV_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_LSHLREV_B32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_LSHLREV_B32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_LSHLREV_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_AND_B32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_AND_B32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_AND_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_OR_B32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_OR_B32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_OR_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_XOR_B32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_XOR_B32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_XOR_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MAC_F32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MAC_F32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MAC_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MADMK_F32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MADMK_F32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MADMK_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MADAK_F32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MADAK_F32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MADAK_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_ADD_U32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_ADD_U32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_ADD_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_SUB_U32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_SUB_U32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_SUB_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_SUBREV_U32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_SUBREV_U32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_SUBREV_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_ADDC_U32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_ADDC_U32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_ADDC_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_SUBB_U32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_SUBB_U32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_SUBB_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_SUBBREV_U32(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_SUBBREV_U32(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_SUBBREV_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_ADD_F16(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_ADD_F16(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_ADD_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_SUB_F16(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_SUB_F16(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_SUB_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_SUBREV_F16(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_SUBREV_F16(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_SUBREV_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MUL_F16(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MUL_F16(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MUL_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MAC_F16(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MAC_F16(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MAC_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MADMK_F16(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MADMK_F16(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MADMK_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MADAK_F16(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MADAK_F16(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MADAK_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_ADD_U16(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_ADD_U16(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_ADD_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_SUB_U16(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_SUB_U16(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_SUB_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_SUBREV_U16(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_SUBREV_U16(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_SUBREV_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MUL_LO_U16(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MUL_LO_U16(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MUL_LO_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_LSHLREV_B16(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_LSHLREV_B16(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_LSHLREV_B16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_LSHRREV_B16(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_LSHRREV_B16(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_LSHRREV_B16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_ASHRREV_I16(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_ASHRREV_I16(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_ASHRREV_I16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MAX_F16(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MAX_F16(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MAX_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MIN_F16(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MIN_F16(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MIN_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MAX_U16(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MAX_U16(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MAX_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MAX_I16(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MAX_I16(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MAX_I16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MIN_U16(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MIN_U16(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MIN_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_MIN_I16(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_MIN_I16(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_MIN_I16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP2__V_LDEXP_F16(MachInst iFmt)
+ {
+ return new Inst_VOP2__V_LDEXP_F16(&iFmt->iFmt_VOP2);
+ } // decode_OP_VOP2__V_LDEXP_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_ADD_U32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_ADD_U32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_ADD_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_SUB_U32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_SUB_U32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_SUB_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_ADD_I32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_ADD_I32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_ADD_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_SUB_I32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_SUB_I32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_SUB_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_ADDC_U32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_ADDC_U32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_ADDC_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_SUBB_U32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_SUBB_U32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_SUBB_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_MIN_I32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_MIN_I32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_MIN_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_MIN_U32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_MIN_U32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_MIN_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_MAX_I32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_MAX_I32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_MAX_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_MAX_U32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_MAX_U32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_MAX_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_CSELECT_B32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_CSELECT_B32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_CSELECT_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_CSELECT_B64(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_CSELECT_B64(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_CSELECT_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_AND_B32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_AND_B32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_AND_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_AND_B64(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_AND_B64(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_AND_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_OR_B32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_OR_B32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_OR_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_OR_B64(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_OR_B64(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_OR_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_XOR_B32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_XOR_B32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_XOR_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_XOR_B64(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_XOR_B64(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_XOR_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_ANDN2_B32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_ANDN2_B32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_ANDN2_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_ANDN2_B64(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_ANDN2_B64(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_ANDN2_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_ORN2_B32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_ORN2_B32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_ORN2_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_ORN2_B64(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_ORN2_B64(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_ORN2_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_NAND_B32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_NAND_B32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_NAND_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_NAND_B64(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_NAND_B64(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_NAND_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_NOR_B32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_NOR_B32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_NOR_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_NOR_B64(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_NOR_B64(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_NOR_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_XNOR_B32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_XNOR_B32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_XNOR_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_XNOR_B64(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_XNOR_B64(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_XNOR_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_LSHL_B32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_LSHL_B32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_LSHL_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_LSHL_B64(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_LSHL_B64(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_LSHL_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_LSHR_B32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_LSHR_B32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_LSHR_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_LSHR_B64(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_LSHR_B64(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_LSHR_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_ASHR_I32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_ASHR_I32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_ASHR_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_ASHR_I64(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_ASHR_I64(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_ASHR_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_BFM_B32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_BFM_B32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_BFM_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_BFM_B64(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_BFM_B64(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_BFM_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_MUL_I32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_MUL_I32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_MUL_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_BFE_U32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_BFE_U32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_BFE_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_BFE_I32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_BFE_I32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_BFE_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_BFE_U64(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_BFE_U64(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_BFE_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_BFE_I64(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_BFE_I64(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_BFE_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_CBRANCH_G_FORK(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_CBRANCH_G_FORK(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_CBRANCH_G_FORK
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_ABSDIFF_I32(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_ABSDIFF_I32(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_ABSDIFF_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP2__S_RFE_RESTORE_B64(MachInst iFmt)
+ {
+ return new Inst_SOP2__S_RFE_RESTORE_B64(&iFmt->iFmt_SOP2);
+ } // decode_OP_SOP2__S_RFE_RESTORE_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPK__S_MOVK_I32(MachInst iFmt)
+ {
+ return new Inst_SOPK__S_MOVK_I32(&iFmt->iFmt_SOPK);
+ } // decode_OP_SOPK__S_MOVK_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPK__S_CMOVK_I32(MachInst iFmt)
+ {
+ return new Inst_SOPK__S_CMOVK_I32(&iFmt->iFmt_SOPK);
+ } // decode_OP_SOPK__S_CMOVK_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPK__S_CMPK_EQ_I32(MachInst iFmt)
+ {
+ return new Inst_SOPK__S_CMPK_EQ_I32(&iFmt->iFmt_SOPK);
+ } // decode_OP_SOPK__S_CMPK_EQ_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPK__S_CMPK_LG_I32(MachInst iFmt)
+ {
+ return new Inst_SOPK__S_CMPK_LG_I32(&iFmt->iFmt_SOPK);
+ } // decode_OP_SOPK__S_CMPK_LG_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPK__S_CMPK_GT_I32(MachInst iFmt)
+ {
+ return new Inst_SOPK__S_CMPK_GT_I32(&iFmt->iFmt_SOPK);
+ } // decode_OP_SOPK__S_CMPK_GT_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPK__S_CMPK_GE_I32(MachInst iFmt)
+ {
+ return new Inst_SOPK__S_CMPK_GE_I32(&iFmt->iFmt_SOPK);
+ } // decode_OP_SOPK__S_CMPK_GE_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPK__S_CMPK_LT_I32(MachInst iFmt)
+ {
+ return new Inst_SOPK__S_CMPK_LT_I32(&iFmt->iFmt_SOPK);
+ } // decode_OP_SOPK__S_CMPK_LT_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPK__S_CMPK_LE_I32(MachInst iFmt)
+ {
+ return new Inst_SOPK__S_CMPK_LE_I32(&iFmt->iFmt_SOPK);
+ } // decode_OP_SOPK__S_CMPK_LE_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPK__S_CMPK_EQ_U32(MachInst iFmt)
+ {
+ return new Inst_SOPK__S_CMPK_EQ_U32(&iFmt->iFmt_SOPK);
+ } // decode_OP_SOPK__S_CMPK_EQ_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPK__S_CMPK_LG_U32(MachInst iFmt)
+ {
+ return new Inst_SOPK__S_CMPK_LG_U32(&iFmt->iFmt_SOPK);
+ } // decode_OP_SOPK__S_CMPK_LG_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPK__S_CMPK_GT_U32(MachInst iFmt)
+ {
+ return new Inst_SOPK__S_CMPK_GT_U32(&iFmt->iFmt_SOPK);
+ } // decode_OP_SOPK__S_CMPK_GT_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPK__S_CMPK_GE_U32(MachInst iFmt)
+ {
+ return new Inst_SOPK__S_CMPK_GE_U32(&iFmt->iFmt_SOPK);
+ } // decode_OP_SOPK__S_CMPK_GE_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPK__S_CMPK_LT_U32(MachInst iFmt)
+ {
+ return new Inst_SOPK__S_CMPK_LT_U32(&iFmt->iFmt_SOPK);
+ } // decode_OP_SOPK__S_CMPK_LT_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPK__S_CMPK_LE_U32(MachInst iFmt)
+ {
+ return new Inst_SOPK__S_CMPK_LE_U32(&iFmt->iFmt_SOPK);
+ } // decode_OP_SOPK__S_CMPK_LE_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPK__S_ADDK_I32(MachInst iFmt)
+ {
+ return new Inst_SOPK__S_ADDK_I32(&iFmt->iFmt_SOPK);
+ } // decode_OP_SOPK__S_ADDK_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPK__S_MULK_I32(MachInst iFmt)
+ {
+ return new Inst_SOPK__S_MULK_I32(&iFmt->iFmt_SOPK);
+ } // decode_OP_SOPK__S_MULK_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPK__S_CBRANCH_I_FORK(MachInst iFmt)
+ {
+ return new Inst_SOPK__S_CBRANCH_I_FORK(&iFmt->iFmt_SOPK);
+ } // decode_OP_SOPK__S_CBRANCH_I_FORK
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPK__S_GETREG_B32(MachInst iFmt)
+ {
+ return new Inst_SOPK__S_GETREG_B32(&iFmt->iFmt_SOPK);
+ } // decode_OP_SOPK__S_GETREG_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPK__S_SETREG_B32(MachInst iFmt)
+ {
+ return new Inst_SOPK__S_SETREG_B32(&iFmt->iFmt_SOPK);
+ } // decode_OP_SOPK__S_SETREG_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPK__S_SETREG_IMM32_B32(MachInst iFmt)
+ {
+ return new Inst_SOPK__S_SETREG_IMM32_B32(&iFmt->iFmt_SOPK);
+ } // decode_OP_SOPK__S_SETREG_IMM32_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_EXP(MachInst iFmt)
+ {
+ return new Inst_EXP__EXP(&iFmt->iFmt_EXP);
+ } // decode_OP_EXP
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_CLASS_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_CLASS_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_CLASS_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_CLASS_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_CLASS_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_CLASS_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_CLASS_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_CLASS_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_CLASS_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_CLASS_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_CLASS_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_CLASS_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_CLASS_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_CLASS_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_CLASS_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_F_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_F_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_F_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_LT_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_LT_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_LT_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_EQ_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_EQ_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_EQ_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_LE_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_LE_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_LE_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_GT_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_GT_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_GT_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_LG_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_LG_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_LG_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_GE_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_GE_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_GE_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_O_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_O_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_O_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_U_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_U_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_U_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NGE_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NGE_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NGE_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NLG_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NLG_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NLG_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NGT_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NGT_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NGT_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NLE_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NLE_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NLE_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NEQ_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NEQ_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NEQ_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NLT_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NLT_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NLT_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_TRU_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_TRU_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_TRU_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_F_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_F_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_F_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_LT_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_LT_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_LT_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_EQ_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_EQ_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_EQ_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_LE_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_LE_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_LE_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_GT_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_GT_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_GT_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_LG_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_LG_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_LG_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_GE_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_GE_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_GE_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_O_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_O_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_O_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_U_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_U_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_U_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NGE_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NGE_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NGE_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NLG_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NLG_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NLG_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NGT_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NGT_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NGT_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NLE_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NLE_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NLE_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NEQ_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NEQ_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NLT_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NLT_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NLT_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_TRU_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_TRU_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_TRU_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_F_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_F_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_F_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_LT_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_LT_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_LT_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_EQ_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_EQ_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_EQ_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_LE_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_LE_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_LE_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_GT_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_GT_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_GT_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_LG_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_LG_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_LG_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_GE_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_GE_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_GE_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_O_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_O_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_O_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_U_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_U_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_U_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NGE_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NGE_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NGE_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NLG_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NLG_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NLG_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NGT_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NGT_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NGT_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NLE_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NLE_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NLE_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NEQ_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NEQ_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NEQ_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NLT_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NLT_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NLT_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_TRU_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_TRU_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_TRU_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_F_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_F_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_F_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_LT_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_LT_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_LT_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_EQ_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_EQ_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_EQ_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_LE_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_LE_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_LE_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_GT_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_GT_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_GT_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_LG_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_LG_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_LG_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_GE_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_GE_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_GE_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_O_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_O_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_O_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_U_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_U_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_U_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NGE_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NGE_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NGE_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NLG_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NLG_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NLG_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NGT_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NGT_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NGT_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NLE_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NLE_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NLE_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NEQ_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NEQ_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NLT_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NLT_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NLT_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_TRU_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_TRU_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_TRU_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_F_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_F_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_F_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_LT_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_LT_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_LT_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_EQ_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_EQ_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_EQ_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_LE_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_LE_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_LE_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_GT_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_GT_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_GT_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_LG_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_LG_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_LG_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_GE_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_GE_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_GE_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_O_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_O_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_O_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_U_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_U_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_U_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NGE_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NGE_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NGE_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NLG_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NLG_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NLG_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NGT_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NGT_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NGT_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NLE_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NLE_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NLE_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NEQ_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NEQ_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NEQ_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NLT_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NLT_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NLT_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_TRU_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_TRU_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_TRU_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_F_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_F_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_F_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_LT_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_LT_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_LT_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_EQ_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_EQ_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_EQ_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_LE_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_LE_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_LE_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_GT_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_GT_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_GT_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_LG_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_LG_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_LG_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_GE_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_GE_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_GE_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_O_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_O_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_O_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_U_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_U_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_U_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NGE_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NGE_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NGE_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NLG_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NLG_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NLG_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NGT_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NGT_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NGT_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NLE_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NLE_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NLE_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NEQ_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NEQ_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NLT_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NLT_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NLT_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_TRU_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_TRU_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_TRU_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_F_I16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_F_I16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_F_I16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_LT_I16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_LT_I16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_LT_I16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_EQ_I16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_EQ_I16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_EQ_I16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_LE_I16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_LE_I16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_LE_I16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_GT_I16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_GT_I16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_GT_I16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NE_I16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NE_I16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NE_I16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_GE_I16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_GE_I16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_GE_I16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_T_I16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_T_I16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_T_I16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_F_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_F_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_F_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_LT_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_LT_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_LT_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_EQ_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_EQ_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_EQ_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_LE_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_LE_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_LE_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_GT_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_GT_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_GT_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NE_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NE_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NE_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_GE_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_GE_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_GE_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_T_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_T_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_T_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_F_I16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_F_I16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_F_I16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_LT_I16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_LT_I16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_LT_I16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_EQ_I16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_EQ_I16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_EQ_I16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_LE_I16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_LE_I16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_LE_I16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_GT_I16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_GT_I16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_GT_I16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NE_I16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NE_I16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NE_I16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_GE_I16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_GE_I16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_GE_I16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_T_I16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_T_I16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_T_I16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_F_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_F_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_F_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_LT_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_LT_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_LT_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_EQ_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_EQ_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_EQ_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_LE_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_LE_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_LE_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_GT_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_GT_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_GT_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NE_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NE_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NE_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_GE_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_GE_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_GE_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_T_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_T_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_T_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_F_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_F_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_F_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_LT_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_LT_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_LT_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_EQ_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_EQ_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_EQ_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_LE_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_LE_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_LE_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_GT_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_GT_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_GT_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NE_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NE_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NE_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_GE_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_GE_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_GE_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_T_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_T_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_T_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_F_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_F_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_F_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_LT_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_LT_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_LT_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_EQ_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_EQ_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_EQ_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_LE_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_LE_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_LE_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_GT_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_GT_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_GT_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NE_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NE_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NE_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_GE_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_GE_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_GE_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_T_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_T_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_T_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_F_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_F_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_F_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_LT_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_LT_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_LT_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_EQ_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_EQ_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_EQ_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_LE_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_LE_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_LE_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_GT_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_GT_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_GT_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NE_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NE_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NE_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_GE_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_GE_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_GE_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_T_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_T_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_T_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_F_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_F_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_F_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_LT_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_LT_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_LT_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_EQ_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_EQ_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_EQ_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_LE_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_LE_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_LE_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_GT_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_GT_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_GT_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NE_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NE_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NE_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_GE_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_GE_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_GE_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_T_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_T_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_T_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_F_I64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_F_I64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_F_I64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_LT_I64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_LT_I64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_LT_I64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_EQ_I64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_EQ_I64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_EQ_I64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_LE_I64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_LE_I64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_LE_I64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_GT_I64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_GT_I64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_GT_I64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NE_I64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NE_I64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NE_I64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_GE_I64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_GE_I64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_GE_I64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_T_I64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_T_I64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_T_I64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_F_U64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_F_U64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_F_U64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_LT_U64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_LT_U64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_LT_U64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_EQ_U64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_EQ_U64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_EQ_U64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_LE_U64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_LE_U64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_LE_U64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_GT_U64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_GT_U64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_GT_U64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_NE_U64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_NE_U64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_NE_U64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_GE_U64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_GE_U64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_GE_U64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMP_T_U64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMP_T_U64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMP_T_U64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_F_I64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_F_I64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_F_I64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_LT_I64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_LT_I64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_LT_I64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_EQ_I64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_EQ_I64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_EQ_I64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_LE_I64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_LE_I64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_LE_I64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_GT_I64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_GT_I64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_GT_I64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NE_I64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NE_I64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NE_I64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_GE_I64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_GE_I64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_GE_I64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_T_I64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_T_I64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_T_I64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_F_U64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_F_U64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_F_U64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_LT_U64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_LT_U64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_LT_U64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_EQ_U64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_EQ_U64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_EQ_U64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_LE_U64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_LE_U64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_LE_U64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_GT_U64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_GT_U64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_GT_U64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_NE_U64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_NE_U64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_NE_U64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_GE_U64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_GE_U64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_GE_U64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CMPX_T_U64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CMPX_T_U64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CMPX_T_U64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CNDMASK_B32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CNDMASK_B32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CNDMASK_B32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_ADD_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_ADD_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_ADD_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_SUB_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_SUB_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_SUB_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_SUBREV_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_SUBREV_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_SUBREV_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MUL_LEGACY_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MUL_LEGACY_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MUL_LEGACY_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MUL_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MUL_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MUL_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MUL_I32_I24(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MUL_I32_I24(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MUL_I32_I24
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MUL_HI_I32_I24(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MUL_HI_I32_I24(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MUL_HI_I32_I24
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MUL_U32_U24(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MUL_U32_U24(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MUL_U32_U24
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MUL_HI_U32_U24(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MUL_HI_U32_U24(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MUL_HI_U32_U24
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MIN_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MIN_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MIN_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MAX_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MAX_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MAX_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MIN_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MIN_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MIN_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MAX_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MAX_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MAX_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MIN_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MIN_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MIN_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MAX_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MAX_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MAX_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_LSHRREV_B32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_LSHRREV_B32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_LSHRREV_B32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_ASHRREV_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_ASHRREV_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_ASHRREV_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_LSHLREV_B32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_LSHLREV_B32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_LSHLREV_B32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_AND_B32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_AND_B32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_AND_B32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_OR_B32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_OR_B32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_OR_B32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_XOR_B32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_XOR_B32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_XOR_B32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MAC_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MAC_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MAC_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_ADD_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_ADD_U32(&iFmt->iFmt_VOP3_SDST_ENC);
+ } // decode_OPU_VOP3__V_ADD_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_SUB_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_SUB_U32(&iFmt->iFmt_VOP3_SDST_ENC);
+ } // decode_OPU_VOP3__V_SUB_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_SUBREV_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_SUBREV_U32(&iFmt->iFmt_VOP3_SDST_ENC);
+ } // decode_OPU_VOP3__V_SUBREV_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_ADDC_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_ADDC_U32(&iFmt->iFmt_VOP3_SDST_ENC);
+ } // decode_OPU_VOP3__V_ADDC_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_SUBB_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_SUBB_U32(&iFmt->iFmt_VOP3_SDST_ENC);
+ } // decode_OPU_VOP3__V_SUBB_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_SUBBREV_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_SUBBREV_U32(&iFmt->iFmt_VOP3_SDST_ENC);
+ } // decode_OPU_VOP3__V_SUBBREV_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_ADD_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_ADD_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_ADD_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_SUB_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_SUB_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_SUB_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_SUBREV_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_SUBREV_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_SUBREV_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MUL_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MUL_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MUL_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MAC_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MAC_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MAC_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_ADD_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_ADD_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_ADD_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_SUB_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_SUB_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_SUB_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_SUBREV_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_SUBREV_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_SUBREV_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MUL_LO_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MUL_LO_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MUL_LO_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_LSHLREV_B16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_LSHLREV_B16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_LSHLREV_B16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_LSHRREV_B16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_LSHRREV_B16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_LSHRREV_B16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_ASHRREV_I16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_ASHRREV_I16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_ASHRREV_I16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MAX_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MAX_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MAX_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MIN_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MIN_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MIN_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MAX_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MAX_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MAX_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MAX_I16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MAX_I16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MAX_I16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MIN_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MIN_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MIN_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MIN_I16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MIN_I16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MIN_I16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_LDEXP_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_LDEXP_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_LDEXP_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_NOP(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_NOP(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_NOP
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MOV_B32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MOV_B32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MOV_B32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_I32_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_I32_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_I32_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_F64_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_F64_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_F64_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_F32_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_F32_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_F32_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_F32_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_F32_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_F32_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_U32_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_U32_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_U32_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_I32_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_I32_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_I32_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MOV_FED_B32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MOV_FED_B32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MOV_FED_B32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_F16_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_F16_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_F16_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_F32_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_F32_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_F32_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_RPI_I32_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_RPI_I32_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_RPI_I32_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_FLR_I32_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_FLR_I32_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_FLR_I32_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_OFF_F32_I4(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_OFF_F32_I4(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_OFF_F32_I4
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_F32_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_F32_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_F32_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_F64_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_F64_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_F64_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE0(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_F32_UBYTE0(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_F32_UBYTE0
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE1(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_F32_UBYTE1(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_F32_UBYTE1
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE2(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_F32_UBYTE2(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_F32_UBYTE2
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE3(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_F32_UBYTE3(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_F32_UBYTE3
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_U32_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_U32_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_U32_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_F64_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_F64_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_F64_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_TRUNC_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_TRUNC_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_TRUNC_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CEIL_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CEIL_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CEIL_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_RNDNE_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_RNDNE_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_RNDNE_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_FLOOR_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_FLOOR_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_FLOOR_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_FRACT_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_FRACT_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_FRACT_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_TRUNC_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_TRUNC_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_TRUNC_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CEIL_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CEIL_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CEIL_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_RNDNE_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_RNDNE_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_RNDNE_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_FLOOR_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_FLOOR_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_FLOOR_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_EXP_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_EXP_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_EXP_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_LOG_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_LOG_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_LOG_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_RCP_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_RCP_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_RCP_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_RCP_IFLAG_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_RCP_IFLAG_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_RCP_IFLAG_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_RSQ_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_RSQ_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_RSQ_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_RCP_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_RCP_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_RCP_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_RSQ_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_RSQ_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_RSQ_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_SQRT_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_SQRT_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_SQRT_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_SQRT_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_SQRT_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_SQRT_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_SIN_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_SIN_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_SIN_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_COS_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_COS_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_COS_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_NOT_B32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_NOT_B32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_NOT_B32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_BFREV_B32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_BFREV_B32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_BFREV_B32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_FFBH_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_FFBH_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_FFBH_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_FFBL_B32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_FFBL_B32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_FFBL_B32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_FFBH_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_FFBH_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_FFBH_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_FREXP_EXP_I32_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_FREXP_EXP_I32_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_FREXP_EXP_I32_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_FREXP_MANT_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_FREXP_MANT_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_FREXP_MANT_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_FRACT_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_FRACT_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_FRACT_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_FREXP_EXP_I32_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_FREXP_EXP_I32_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_FREXP_EXP_I32_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_FREXP_MANT_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_FREXP_MANT_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_FREXP_MANT_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CLREXCP(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CLREXCP(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CLREXCP
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_F16_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_F16_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_F16_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_F16_I16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_F16_I16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_F16_I16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_U16_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_U16_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_U16_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_I16_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_I16_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_I16_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_RCP_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_RCP_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_RCP_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_SQRT_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_SQRT_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_SQRT_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_RSQ_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_RSQ_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_RSQ_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_LOG_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_LOG_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_LOG_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_EXP_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_EXP_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_EXP_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_FREXP_MANT_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_FREXP_MANT_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_FREXP_MANT_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_FREXP_EXP_I16_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_FREXP_EXP_I16_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_FREXP_EXP_I16_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_FLOOR_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_FLOOR_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_FLOOR_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CEIL_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CEIL_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CEIL_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_TRUNC_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_TRUNC_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_TRUNC_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_RNDNE_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_RNDNE_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_RNDNE_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_FRACT_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_FRACT_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_FRACT_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_SIN_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_SIN_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_SIN_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_COS_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_COS_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_COS_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_EXP_LEGACY_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_EXP_LEGACY_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_EXP_LEGACY_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_LOG_LEGACY_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_LOG_LEGACY_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_LOG_LEGACY_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MAD_LEGACY_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MAD_LEGACY_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MAD_LEGACY_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MAD_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MAD_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MAD_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MAD_I32_I24(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MAD_I32_I24(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MAD_I32_I24
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MAD_U32_U24(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MAD_U32_U24(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MAD_U32_U24
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CUBEID_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CUBEID_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CUBEID_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CUBESC_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CUBESC_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CUBESC_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CUBETC_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CUBETC_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CUBETC_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CUBEMA_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CUBEMA_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CUBEMA_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_BFE_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_BFE_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_BFE_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_BFE_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_BFE_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_BFE_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_BFI_B32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_BFI_B32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_BFI_B32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_FMA_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_FMA_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_FMA_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_FMA_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_FMA_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_FMA_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_LERP_U8(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_LERP_U8(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_LERP_U8
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_ALIGNBIT_B32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_ALIGNBIT_B32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_ALIGNBIT_B32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_ALIGNBYTE_B32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_ALIGNBYTE_B32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_ALIGNBYTE_B32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MIN3_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MIN3_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MIN3_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MIN3_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MIN3_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MIN3_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MIN3_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MIN3_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MIN3_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MAX3_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MAX3_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MAX3_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MAX3_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MAX3_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MAX3_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MAX3_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MAX3_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MAX3_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MED3_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MED3_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MED3_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MED3_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MED3_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MED3_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MED3_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MED3_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MED3_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_SAD_U8(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_SAD_U8(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_SAD_U8
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_SAD_HI_U8(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_SAD_HI_U8(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_SAD_HI_U8
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_SAD_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_SAD_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_SAD_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_SAD_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_SAD_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_SAD_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_PK_U8_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_PK_U8_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_PK_U8_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_DIV_FIXUP_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_DIV_FIXUP_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_DIV_FIXUP_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_DIV_FIXUP_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_DIV_SCALE_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_DIV_SCALE_F32(&iFmt->iFmt_VOP3_SDST_ENC);
+ } // decode_OPU_VOP3__V_DIV_SCALE_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_DIV_SCALE_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_DIV_SCALE_F64(&iFmt->iFmt_VOP3_SDST_ENC);
+ } // decode_OPU_VOP3__V_DIV_SCALE_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_DIV_FMAS_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_DIV_FMAS_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_DIV_FMAS_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_DIV_FMAS_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_DIV_FMAS_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_DIV_FMAS_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MSAD_U8(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MSAD_U8(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MSAD_U8
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_QSAD_PK_U16_U8(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_QSAD_PK_U16_U8(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_QSAD_PK_U16_U8
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MQSAD_PK_U16_U8(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MQSAD_PK_U16_U8(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MQSAD_PK_U16_U8
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MQSAD_U32_U8(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MQSAD_U32_U8(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MQSAD_U32_U8
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MAD_U64_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MAD_U64_U32(&iFmt->iFmt_VOP3_SDST_ENC);
+ } // decode_OPU_VOP3__V_MAD_U64_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MAD_I64_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MAD_I64_I32(&iFmt->iFmt_VOP3_SDST_ENC);
+ } // decode_OPU_VOP3__V_MAD_I64_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MAD_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MAD_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MAD_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MAD_U16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MAD_U16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MAD_U16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MAD_I16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MAD_I16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MAD_I16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_PERM_B32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_PERM_B32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_PERM_B32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_FMA_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_FMA_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_FMA_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_DIV_FIXUP_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_DIV_FIXUP_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_PKACCUM_U8_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_INTERP_P1_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_INTERP_P1_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_INTERP_P1_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_INTERP_P2_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_INTERP_P2_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_INTERP_P2_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_INTERP_MOV_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_INTERP_MOV_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_INTERP_MOV_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_INTERP_P1LL_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_INTERP_P1LL_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_INTERP_P1LL_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_INTERP_P1LV_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_INTERP_P1LV_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_INTERP_P1LV_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_INTERP_P2_F16(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_INTERP_P2_F16(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_INTERP_P2_F16
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_ADD_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_ADD_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_ADD_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MUL_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MUL_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MUL_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MIN_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MIN_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MIN_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MAX_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MAX_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MAX_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_LDEXP_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_LDEXP_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_LDEXP_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MUL_LO_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MUL_LO_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MUL_LO_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MUL_HI_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MUL_HI_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MUL_HI_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MUL_HI_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MUL_HI_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MUL_HI_I32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_LDEXP_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_LDEXP_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_LDEXP_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_READLANE_B32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_READLANE_B32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_READLANE_B32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_WRITELANE_B32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_WRITELANE_B32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_WRITELANE_B32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_BCNT_U32_B32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_BCNT_U32_B32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_BCNT_U32_B32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MBCNT_LO_U32_B32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MBCNT_LO_U32_B32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MBCNT_LO_U32_B32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_MBCNT_HI_U32_B32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_MBCNT_HI_U32_B32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_MBCNT_HI_U32_B32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_LSHLREV_B64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_LSHLREV_B64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_LSHLREV_B64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_LSHRREV_B64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_LSHRREV_B64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_LSHRREV_B64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_ASHRREV_I64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_ASHRREV_I64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_ASHRREV_I64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_TRIG_PREOP_F64(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_TRIG_PREOP_F64(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_TRIG_PREOP_F64
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_BFM_B32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_BFM_B32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_BFM_B32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_PKNORM_I16_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_PKNORM_I16_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_PKNORM_I16_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_PKNORM_U16_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_PKNORM_U16_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_PKNORM_U16_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_PKRTZ_F16_F32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_PK_U16_U32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_PK_U16_U32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_PK_U16_U32
+
+ GPUStaticInst*
+ Decoder::decode_OPU_VOP3__V_CVT_PK_I16_I32(MachInst iFmt)
+ {
+ return new Inst_VOP3__V_CVT_PK_I16_I32(&iFmt->iFmt_VOP3);
+ } // decode_OPU_VOP3__V_CVT_PK_I16_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_ADD_U32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_ADD_U32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_ADD_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_SUB_U32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_SUB_U32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_SUB_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_RSUB_U32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_RSUB_U32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_RSUB_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_INC_U32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_INC_U32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_INC_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_DEC_U32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_DEC_U32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_DEC_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MIN_I32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MIN_I32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MIN_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MAX_I32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MAX_I32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MAX_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MIN_U32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MIN_U32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MIN_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MAX_U32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MAX_U32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MAX_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_AND_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_AND_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_AND_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_OR_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_OR_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_OR_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_XOR_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_XOR_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_XOR_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MSKOR_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MSKOR_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MSKOR_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_WRITE_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_WRITE_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_WRITE_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_WRITE2_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_WRITE2_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_WRITE2_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_WRITE2ST64_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_WRITE2ST64_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_WRITE2ST64_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_CMPST_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_CMPST_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_CMPST_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_CMPST_F32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_CMPST_F32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_CMPST_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MIN_F32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MIN_F32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MIN_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MAX_F32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MAX_F32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MAX_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_NOP(MachInst iFmt)
+ {
+ return new Inst_DS__DS_NOP(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_NOP
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_ADD_F32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_ADD_F32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_ADD_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_WRITE_B8(MachInst iFmt)
+ {
+ return new Inst_DS__DS_WRITE_B8(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_WRITE_B8
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_WRITE_B16(MachInst iFmt)
+ {
+ return new Inst_DS__DS_WRITE_B16(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_WRITE_B16
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_ADD_RTN_U32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_ADD_RTN_U32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_ADD_RTN_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_SUB_RTN_U32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_SUB_RTN_U32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_SUB_RTN_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_RSUB_RTN_U32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_RSUB_RTN_U32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_RSUB_RTN_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_INC_RTN_U32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_INC_RTN_U32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_INC_RTN_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_DEC_RTN_U32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_DEC_RTN_U32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_DEC_RTN_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MIN_RTN_I32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MIN_RTN_I32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MIN_RTN_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MAX_RTN_I32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MAX_RTN_I32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MAX_RTN_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MIN_RTN_U32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MIN_RTN_U32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MIN_RTN_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MAX_RTN_U32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MAX_RTN_U32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MAX_RTN_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_AND_RTN_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_AND_RTN_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_AND_RTN_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_OR_RTN_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_OR_RTN_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_OR_RTN_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_XOR_RTN_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_XOR_RTN_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_XOR_RTN_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MSKOR_RTN_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MSKOR_RTN_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MSKOR_RTN_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_WRXCHG_RTN_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_WRXCHG_RTN_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_WRXCHG_RTN_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_WRXCHG2_RTN_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_WRXCHG2_RTN_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_WRXCHG2_RTN_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_WRXCHG2ST64_RTN_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_WRXCHG2ST64_RTN_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_WRXCHG2ST64_RTN_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_CMPST_RTN_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_CMPST_RTN_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_CMPST_RTN_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_CMPST_RTN_F32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_CMPST_RTN_F32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_CMPST_RTN_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MIN_RTN_F32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MIN_RTN_F32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MIN_RTN_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MAX_RTN_F32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MAX_RTN_F32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MAX_RTN_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_WRAP_RTN_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_WRAP_RTN_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_WRAP_RTN_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_ADD_RTN_F32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_ADD_RTN_F32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_ADD_RTN_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_READ_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_READ_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_READ_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_READ2_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_READ2_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_READ2_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_READ2ST64_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_READ2ST64_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_READ2ST64_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_READ_I8(MachInst iFmt)
+ {
+ return new Inst_DS__DS_READ_I8(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_READ_I8
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_READ_U8(MachInst iFmt)
+ {
+ return new Inst_DS__DS_READ_U8(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_READ_U8
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_READ_I16(MachInst iFmt)
+ {
+ return new Inst_DS__DS_READ_I16(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_READ_I16
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_READ_U16(MachInst iFmt)
+ {
+ return new Inst_DS__DS_READ_U16(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_READ_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_SWIZZLE_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_SWIZZLE_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_SWIZZLE_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_PERMUTE_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_PERMUTE_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_PERMUTE_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_BPERMUTE_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_BPERMUTE_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_BPERMUTE_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_ADD_U64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_ADD_U64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_ADD_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_SUB_U64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_SUB_U64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_SUB_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_RSUB_U64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_RSUB_U64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_RSUB_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_INC_U64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_INC_U64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_INC_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_DEC_U64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_DEC_U64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_DEC_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MIN_I64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MIN_I64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MIN_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MAX_I64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MAX_I64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MAX_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MIN_U64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MIN_U64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MIN_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MAX_U64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MAX_U64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MAX_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_AND_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_AND_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_AND_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_OR_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_OR_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_OR_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_XOR_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_XOR_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_XOR_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MSKOR_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MSKOR_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MSKOR_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_WRITE_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_WRITE_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_WRITE_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_WRITE2_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_WRITE2_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_WRITE2_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_WRITE2ST64_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_WRITE2ST64_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_WRITE2ST64_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_CMPST_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_CMPST_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_CMPST_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_CMPST_F64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_CMPST_F64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_CMPST_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MIN_F64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MIN_F64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MIN_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MAX_F64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MAX_F64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MAX_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_ADD_RTN_U64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_ADD_RTN_U64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_ADD_RTN_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_SUB_RTN_U64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_SUB_RTN_U64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_SUB_RTN_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_RSUB_RTN_U64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_RSUB_RTN_U64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_RSUB_RTN_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_INC_RTN_U64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_INC_RTN_U64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_INC_RTN_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_DEC_RTN_U64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_DEC_RTN_U64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_DEC_RTN_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MIN_RTN_I64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MIN_RTN_I64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MIN_RTN_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MAX_RTN_I64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MAX_RTN_I64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MAX_RTN_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MIN_RTN_U64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MIN_RTN_U64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MIN_RTN_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MAX_RTN_U64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MAX_RTN_U64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MAX_RTN_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_AND_RTN_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_AND_RTN_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_AND_RTN_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_OR_RTN_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_OR_RTN_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_OR_RTN_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_XOR_RTN_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_XOR_RTN_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_XOR_RTN_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MSKOR_RTN_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MSKOR_RTN_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MSKOR_RTN_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_WRXCHG_RTN_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_WRXCHG_RTN_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_WRXCHG_RTN_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_WRXCHG2_RTN_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_WRXCHG2_RTN_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_WRXCHG2_RTN_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_WRXCHG2ST64_RTN_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_WRXCHG2ST64_RTN_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_WRXCHG2ST64_RTN_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_CMPST_RTN_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_CMPST_RTN_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_CMPST_RTN_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_CMPST_RTN_F64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_CMPST_RTN_F64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_CMPST_RTN_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MIN_RTN_F64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MIN_RTN_F64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MIN_RTN_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MAX_RTN_F64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MAX_RTN_F64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MAX_RTN_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_READ_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_READ_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_READ_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_READ2_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_READ2_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_READ2_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_READ2ST64_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_READ2ST64_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_READ2ST64_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_CONDXCHG32_RTN_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_CONDXCHG32_RTN_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_CONDXCHG32_RTN_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_ADD_SRC2_U32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_ADD_SRC2_U32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_ADD_SRC2_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_SUB_SRC2_U32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_SUB_SRC2_U32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_SUB_SRC2_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_RSUB_SRC2_U32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_RSUB_SRC2_U32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_RSUB_SRC2_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_INC_SRC2_U32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_INC_SRC2_U32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_INC_SRC2_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_DEC_SRC2_U32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_DEC_SRC2_U32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_DEC_SRC2_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MIN_SRC2_I32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MIN_SRC2_I32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MIN_SRC2_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MAX_SRC2_I32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MAX_SRC2_I32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MAX_SRC2_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MIN_SRC2_U32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MIN_SRC2_U32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MIN_SRC2_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MAX_SRC2_U32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MAX_SRC2_U32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MAX_SRC2_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_AND_SRC2_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_AND_SRC2_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_AND_SRC2_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_OR_SRC2_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_OR_SRC2_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_OR_SRC2_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_XOR_SRC2_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_XOR_SRC2_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_XOR_SRC2_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_WRITE_SRC2_B32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_WRITE_SRC2_B32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_WRITE_SRC2_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MIN_SRC2_F32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MIN_SRC2_F32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MIN_SRC2_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MAX_SRC2_F32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MAX_SRC2_F32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MAX_SRC2_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_ADD_SRC2_F32(MachInst iFmt)
+ {
+ return new Inst_DS__DS_ADD_SRC2_F32(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_ADD_SRC2_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_GWS_SEMA_RELEASE_ALL(MachInst iFmt)
+ {
+ return new Inst_DS__DS_GWS_SEMA_RELEASE_ALL(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_GWS_SEMA_RELEASE_ALL
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_GWS_INIT(MachInst iFmt)
+ {
+ return new Inst_DS__DS_GWS_INIT(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_GWS_INIT
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_GWS_SEMA_V(MachInst iFmt)
+ {
+ return new Inst_DS__DS_GWS_SEMA_V(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_GWS_SEMA_V
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_GWS_SEMA_BR(MachInst iFmt)
+ {
+ return new Inst_DS__DS_GWS_SEMA_BR(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_GWS_SEMA_BR
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_GWS_SEMA_P(MachInst iFmt)
+ {
+ return new Inst_DS__DS_GWS_SEMA_P(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_GWS_SEMA_P
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_GWS_BARRIER(MachInst iFmt)
+ {
+ return new Inst_DS__DS_GWS_BARRIER(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_GWS_BARRIER
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_CONSUME(MachInst iFmt)
+ {
+ return new Inst_DS__DS_CONSUME(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_CONSUME
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_APPEND(MachInst iFmt)
+ {
+ return new Inst_DS__DS_APPEND(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_APPEND
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_ORDERED_COUNT(MachInst iFmt)
+ {
+ return new Inst_DS__DS_ORDERED_COUNT(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_ORDERED_COUNT
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_ADD_SRC2_U64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_ADD_SRC2_U64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_ADD_SRC2_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_SUB_SRC2_U64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_SUB_SRC2_U64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_SUB_SRC2_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_RSUB_SRC2_U64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_RSUB_SRC2_U64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_RSUB_SRC2_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_INC_SRC2_U64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_INC_SRC2_U64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_INC_SRC2_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_DEC_SRC2_U64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_DEC_SRC2_U64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_DEC_SRC2_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MIN_SRC2_I64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MIN_SRC2_I64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MIN_SRC2_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MAX_SRC2_I64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MAX_SRC2_I64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MAX_SRC2_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MIN_SRC2_U64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MIN_SRC2_U64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MIN_SRC2_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MAX_SRC2_U64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MAX_SRC2_U64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MAX_SRC2_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_AND_SRC2_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_AND_SRC2_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_AND_SRC2_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_OR_SRC2_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_OR_SRC2_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_OR_SRC2_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_XOR_SRC2_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_XOR_SRC2_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_XOR_SRC2_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_WRITE_SRC2_B64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_WRITE_SRC2_B64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_WRITE_SRC2_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MIN_SRC2_F64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MIN_SRC2_F64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MIN_SRC2_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_MAX_SRC2_F64(MachInst iFmt)
+ {
+ return new Inst_DS__DS_MAX_SRC2_F64(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_MAX_SRC2_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_WRITE_B96(MachInst iFmt)
+ {
+ return new Inst_DS__DS_WRITE_B96(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_WRITE_B96
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_WRITE_B128(MachInst iFmt)
+ {
+ return new Inst_DS__DS_WRITE_B128(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_WRITE_B128
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_READ_B96(MachInst iFmt)
+ {
+ return new Inst_DS__DS_READ_B96(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_READ_B96
+
+ GPUStaticInst*
+ Decoder::decode_OP_DS__DS_READ_B128(MachInst iFmt)
+ {
+ return new Inst_DS__DS_READ_B128(&iFmt->iFmt_DS);
+ } // decode_OP_DS__DS_READ_B128
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_LOAD_UBYTE(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_LOAD_UBYTE(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_LOAD_UBYTE
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_LOAD_SBYTE(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_LOAD_SBYTE(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_LOAD_SBYTE
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_LOAD_USHORT(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_LOAD_USHORT(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_LOAD_USHORT
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_LOAD_SSHORT(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_LOAD_SSHORT(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_LOAD_SSHORT
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_LOAD_DWORD(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_LOAD_DWORD(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_LOAD_DWORD
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX2(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_LOAD_DWORDX2(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_LOAD_DWORDX2
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX3(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_LOAD_DWORDX3(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_LOAD_DWORDX3
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX4(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_LOAD_DWORDX4(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_LOAD_DWORDX4
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_STORE_BYTE(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_STORE_BYTE(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_STORE_BYTE
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_STORE_SHORT(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_STORE_SHORT(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_STORE_SHORT
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_STORE_DWORD(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_STORE_DWORD(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_STORE_DWORD
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX2(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_STORE_DWORDX2(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_STORE_DWORDX2
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX3(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_STORE_DWORDX3(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_STORE_DWORDX3
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX4(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_STORE_DWORDX4(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_STORE_DWORDX4
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_SWAP(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_SWAP(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_SWAP
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_CMPSWAP(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_ADD(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_ADD(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_ADD
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_SUB(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_SUB(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_SUB
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMIN(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_SMIN(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_SMIN
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMIN(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_UMIN(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_UMIN
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMAX(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_SMAX(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_SMAX
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMAX(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_UMAX(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_UMAX
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_AND(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_AND(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_AND
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_OR(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_OR(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_OR
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_XOR(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_XOR(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_XOR
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_INC(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_INC(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_INC
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_DEC(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_DEC(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_DEC
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_SWAP_X2(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_SWAP_X2(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_SWAP_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP_X2(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_ADD_X2(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_ADD_X2(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_ADD_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_SUB_X2(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_SUB_X2(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_SUB_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMIN_X2(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_SMIN_X2(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_SMIN_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMIN_X2(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_UMIN_X2(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_UMIN_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMAX_X2(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_SMAX_X2(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_SMAX_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMAX_X2(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_UMAX_X2(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_UMAX_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_AND_X2(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_AND_X2(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_AND_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_OR_X2(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_OR_X2(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_OR_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_XOR_X2(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_XOR_X2(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_XOR_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_INC_X2(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_INC_X2(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_INC_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_FLAT__FLAT_ATOMIC_DEC_X2(MachInst iFmt)
+ {
+ return new Inst_FLAT__FLAT_ATOMIC_DEC_X2(&iFmt->iFmt_FLAT);
+ } // decode_OP_FLAT__FLAT_ATOMIC_DEC_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_LOAD(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_LOAD(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_LOAD
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_LOAD_MIP(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_LOAD_MIP
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_LOAD_PCK(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_LOAD_PCK(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_LOAD_PCK
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_LOAD_PCK_SGN(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_LOAD_PCK_SGN(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_LOAD_PCK_SGN
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP_PCK(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_LOAD_MIP_PCK(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_LOAD_MIP_PCK
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP_PCK_SGN(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_LOAD_MIP_PCK_SGN
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_STORE(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_STORE(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_STORE
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_STORE_MIP(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_STORE_MIP(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_STORE_MIP
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_STORE_PCK(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_STORE_PCK(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_STORE_PCK
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_STORE_MIP_PCK(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_STORE_MIP_PCK(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_STORE_MIP_PCK
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GET_RESINFO(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GET_RESINFO(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GET_RESINFO
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SWAP(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_ATOMIC_SWAP(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_ATOMIC_SWAP
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_ATOMIC_CMPSWAP(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_ATOMIC_ADD(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_ATOMIC_ADD(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_ATOMIC_ADD
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SUB(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_ATOMIC_SUB(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_ATOMIC_SUB
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SMIN(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_ATOMIC_SMIN(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_ATOMIC_SMIN
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_ATOMIC_UMIN(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_ATOMIC_UMIN(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_ATOMIC_UMIN
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SMAX(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_ATOMIC_SMAX(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_ATOMIC_SMAX
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_ATOMIC_UMAX(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_ATOMIC_UMAX(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_ATOMIC_UMAX
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_ATOMIC_AND(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_ATOMIC_AND(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_ATOMIC_AND
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_ATOMIC_OR(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_ATOMIC_OR(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_ATOMIC_OR
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_ATOMIC_XOR(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_ATOMIC_XOR(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_ATOMIC_XOR
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_ATOMIC_INC(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_ATOMIC_INC(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_ATOMIC_INC
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_ATOMIC_DEC(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_ATOMIC_DEC(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_ATOMIC_DEC
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CL(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_CL(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_CL
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_D(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_D
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_CL(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_D_CL(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_D_CL
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_L(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_L(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_L
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_B(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_B
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_CL(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_B_CL(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_B_CL
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_LZ(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_LZ(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_LZ
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_C(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_C
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CL(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_C_CL(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_C_CL
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_C_D(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_C_D
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_C_D_CL(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_L(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_C_L(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_C_L
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_C_B(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_C_B
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_C_B_CL(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_LZ(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_C_LZ(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_C_LZ
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CL_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_CL_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_CL_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_D_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_D_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_CL_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_D_CL_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_D_CL_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_L_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_L_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_L_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_B_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_B_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_CL_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_B_CL_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_B_CL_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_LZ_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_LZ_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_LZ_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_C_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_C_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CL_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_C_CL_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_C_CL_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_C_D_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_C_D_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_L_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_C_L_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_C_L_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_C_B_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_C_B_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_C_LZ_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_CL(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_CL(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_CL
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_L(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_L(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_L
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_B(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_B(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_B
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_CL(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_B_CL(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_B_CL
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_LZ(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_LZ(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_LZ
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_C(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_C(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_C
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_CL(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_C_CL(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_C_CL
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_L(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_C_L(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_C_L
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_C_B(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_C_B
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_CL(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_C_B_CL(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_C_B_CL
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_LZ(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_C_LZ(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_C_LZ
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_CL_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_CL_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_CL_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_L_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_L_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_L_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_B_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_B_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_CL_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_B_CL_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_B_CL_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_LZ_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_LZ_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_LZ_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_C_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_C_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_CL_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_C_CL_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_C_CL_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_L_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_C_L_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_C_L_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_C_B_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_C_B_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_CL_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_C_B_CL_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_C_B_CL_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_LZ_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GATHER4_C_LZ_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GATHER4_C_LZ_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_GET_LOD(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_GET_LOD(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_GET_LOD
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_CD(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_CD
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_CL(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_CD_CL(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_CD_CL
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_C_CD(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_C_CD_CL(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_CD_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_CD_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_CL_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_CD_CL_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_CD_CL_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_C_CD_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL_O(MachInst iFmt)
+ {
+ return new Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O(&iFmt->iFmt_MIMG);
+ } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL_O
+
+ GPUStaticInst*
+ Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_X(MachInst iFmt)
+ {
+ return new Inst_MTBUF__TBUFFER_LOAD_FORMAT_X(&iFmt->iFmt_MTBUF);
+ } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_X
+
+ GPUStaticInst*
+ Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XY(MachInst iFmt)
+ {
+ return new Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY(&iFmt->iFmt_MTBUF);
+ } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XY
+
+ GPUStaticInst*
+ Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZ(MachInst iFmt)
+ {
+ return new Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ(&iFmt->iFmt_MTBUF);
+ } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
+
+ GPUStaticInst*
+ Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZW(MachInst iFmt)
+ {
+ return new Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW(&iFmt->iFmt_MTBUF);
+ } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
+
+ GPUStaticInst*
+ Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_X(MachInst iFmt)
+ {
+ return new Inst_MTBUF__TBUFFER_STORE_FORMAT_X(&iFmt->iFmt_MTBUF);
+ } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_X
+
+ GPUStaticInst*
+ Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XY(MachInst iFmt)
+ {
+ return new Inst_MTBUF__TBUFFER_STORE_FORMAT_XY(&iFmt->iFmt_MTBUF);
+ } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XY
+
+ GPUStaticInst*
+ Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZ(MachInst iFmt)
+ {
+ return new Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ(&iFmt->iFmt_MTBUF);
+ } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZ
+
+ GPUStaticInst*
+ Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZW(MachInst iFmt)
+ {
+ return new Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW(&iFmt->iFmt_MTBUF);
+ } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZW
+
+ GPUStaticInst*
+ Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_X(MachInst iFmt)
+ {
+ return new Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X(&iFmt->iFmt_MTBUF);
+ } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
+
+ GPUStaticInst*
+ Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY(MachInst iFmt)
+ {
+ return new Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY(&iFmt->iFmt_MTBUF);
+ } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
+
+ GPUStaticInst*
+ Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ(MachInst iFmt)
+ {
+ return new Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ(&iFmt->iFmt_MTBUF);
+ } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
+
+ GPUStaticInst*
+ Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW(MachInst iFmt)
+ {
+ return new Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW(&iFmt->iFmt_MTBUF);
+ } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
+
+ GPUStaticInst*
+ Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_X(MachInst iFmt)
+ {
+ return new Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X(&iFmt->iFmt_MTBUF);
+ } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_X
+
+ GPUStaticInst*
+ Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XY(MachInst iFmt)
+ {
+ return new Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY(&iFmt->iFmt_MTBUF);
+ } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
+
+ GPUStaticInst*
+ Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ(MachInst iFmt)
+ {
+ return new Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ(&iFmt->iFmt_MTBUF);
+ } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
+
+ GPUStaticInst*
+ Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW(MachInst iFmt)
+ {
+ return new
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW(&iFmt->iFmt_MTBUF);
+ } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_X(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_LOAD_FORMAT_X(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_X
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XY(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_LOAD_FORMAT_XY(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XY
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZ(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZ
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZW(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZW
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_X(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_STORE_FORMAT_X(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_X
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XY(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_STORE_FORMAT_XY(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_XY
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZ(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZ
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZW(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZW
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_X(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_X
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XY(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_X(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_X
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XY(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XY
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_LOAD_UBYTE(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_LOAD_UBYTE(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_LOAD_UBYTE
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_LOAD_SBYTE(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_LOAD_SBYTE(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_LOAD_SBYTE
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_LOAD_USHORT(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_LOAD_USHORT(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_LOAD_USHORT
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_LOAD_SSHORT(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_LOAD_SSHORT(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_LOAD_SSHORT
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORD(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_LOAD_DWORD(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_LOAD_DWORD
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX2(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_LOAD_DWORDX2(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_LOAD_DWORDX2
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX3(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_LOAD_DWORDX3(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_LOAD_DWORDX3
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX4(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_LOAD_DWORDX4(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_LOAD_DWORDX4
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_STORE_BYTE(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_STORE_BYTE(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_STORE_BYTE
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_STORE_SHORT(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_STORE_SHORT(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_STORE_SHORT
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORD(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_STORE_DWORD(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_STORE_DWORD
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX2(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_STORE_DWORDX2(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_STORE_DWORDX2
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX3(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_STORE_DWORDX3(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_STORE_DWORDX3
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX4(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_STORE_DWORDX4(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_STORE_DWORDX4
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_STORE_LDS_DWORD(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_WBINVL1(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_WBINVL1(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_WBINVL1
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_WBINVL1_VOL(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_WBINVL1_VOL(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_WBINVL1_VOL
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SWAP(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_SWAP(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_SWAP
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_ADD(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_ADD(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_ADD
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SUB(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_SUB(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_SUB
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMIN(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_SMIN(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_SMIN
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMIN(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_UMIN(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_UMIN
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMAX(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_SMAX(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_SMAX
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMAX(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_UMAX(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_UMAX
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_AND(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_AND(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_AND
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_OR(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_OR(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_OR
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_XOR(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_XOR(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_XOR
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_INC(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_INC(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_INC
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_DEC(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_DEC(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_DEC
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SWAP_X2(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_SWAP_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_ADD_X2(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_ADD_X2(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_ADD_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SUB_X2(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_SUB_X2(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_SUB_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMIN_X2(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_SMIN_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMIN_X2(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_UMIN_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMAX_X2(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_SMAX_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMAX_X2(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_UMAX_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_AND_X2(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_AND_X2(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_AND_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_OR_X2(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_OR_X2(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_OR_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_XOR_X2(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_XOR_X2(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_XOR_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_INC_X2(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_INC_X2(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_INC_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_DEC_X2(MachInst iFmt)
+ {
+ return new Inst_MUBUF__BUFFER_ATOMIC_DEC_X2(&iFmt->iFmt_MUBUF);
+ } // decode_OP_MUBUF__BUFFER_ATOMIC_DEC_X2
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_LOAD_DWORD(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_LOAD_DWORD(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_LOAD_DWORD
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_LOAD_DWORDX2(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_LOAD_DWORDX2(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_LOAD_DWORDX2
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_LOAD_DWORDX4(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_LOAD_DWORDX4(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_LOAD_DWORDX4
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_LOAD_DWORDX8(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_LOAD_DWORDX8(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_LOAD_DWORDX8
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_LOAD_DWORDX16(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_LOAD_DWORDX16(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_LOAD_DWORDX16
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORD(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_BUFFER_LOAD_DWORD(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_BUFFER_LOAD_DWORD
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_BUFFER_LOAD_DWORDX2(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_BUFFER_LOAD_DWORDX4(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX8(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_BUFFER_LOAD_DWORDX8(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX8
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX16(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_BUFFER_LOAD_DWORDX16(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX16
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_STORE_DWORD(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_STORE_DWORD(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_STORE_DWORD
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_STORE_DWORDX2(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_STORE_DWORDX2(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_STORE_DWORDX2
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_STORE_DWORDX4(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_STORE_DWORDX4(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_STORE_DWORDX4
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORD(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_BUFFER_STORE_DWORD(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_BUFFER_STORE_DWORD
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORDX2(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_BUFFER_STORE_DWORDX2(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_BUFFER_STORE_DWORDX2
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORDX4(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_BUFFER_STORE_DWORDX4(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_BUFFER_STORE_DWORDX4
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_DCACHE_INV(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_DCACHE_INV(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_DCACHE_INV
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_DCACHE_WB(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_DCACHE_WB(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_DCACHE_WB
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_DCACHE_INV_VOL(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_DCACHE_INV_VOL(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_DCACHE_INV_VOL
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_DCACHE_WB_VOL(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_DCACHE_WB_VOL(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_DCACHE_WB_VOL
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_MEMTIME(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_MEMTIME(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_MEMTIME
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_MEMREALTIME(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_MEMREALTIME(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_MEMREALTIME
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_ATC_PROBE(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_ATC_PROBE(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_ATC_PROBE
+
+ GPUStaticInst*
+ Decoder::decode_OP_SMEM__S_ATC_PROBE_BUFFER(MachInst iFmt)
+ {
+ return new Inst_SMEM__S_ATC_PROBE_BUFFER(&iFmt->iFmt_SMEM);
+ } // decode_OP_SMEM__S_ATC_PROBE_BUFFER
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_MOV_B32(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_MOV_B32(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_MOV_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_MOV_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_MOV_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_MOV_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_CMOV_B32(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_CMOV_B32(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_CMOV_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_CMOV_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_CMOV_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_CMOV_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_NOT_B32(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_NOT_B32(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_NOT_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_NOT_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_NOT_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_NOT_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_WQM_B32(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_WQM_B32(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_WQM_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_WQM_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_WQM_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_WQM_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_BREV_B32(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_BREV_B32(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_BREV_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_BREV_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_BREV_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_BREV_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_BCNT0_I32_B32(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_BCNT0_I32_B32(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_BCNT0_I32_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_BCNT0_I32_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_BCNT0_I32_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_BCNT0_I32_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_BCNT1_I32_B32(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_BCNT1_I32_B32(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_BCNT1_I32_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_BCNT1_I32_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_BCNT1_I32_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_BCNT1_I32_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_FF0_I32_B32(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_FF0_I32_B32(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_FF0_I32_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_FF0_I32_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_FF0_I32_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_FF0_I32_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_FF1_I32_B32(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_FF1_I32_B32(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_FF1_I32_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_FF1_I32_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_FF1_I32_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_FF1_I32_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_FLBIT_I32_B32(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_FLBIT_I32_B32(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_FLBIT_I32_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_FLBIT_I32_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_FLBIT_I32_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_FLBIT_I32_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_FLBIT_I32(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_FLBIT_I32(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_FLBIT_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_FLBIT_I32_I64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_FLBIT_I32_I64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_FLBIT_I32_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_SEXT_I32_I8(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_SEXT_I32_I8(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_SEXT_I32_I8
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_SEXT_I32_I16(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_SEXT_I32_I16(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_SEXT_I32_I16
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_BITSET0_B32(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_BITSET0_B32(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_BITSET0_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_BITSET0_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_BITSET0_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_BITSET0_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_BITSET1_B32(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_BITSET1_B32(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_BITSET1_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_BITSET1_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_BITSET1_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_BITSET1_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_GETPC_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_GETPC_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_GETPC_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_SETPC_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_SETPC_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_SETPC_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_SWAPPC_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_SWAPPC_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_SWAPPC_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_RFE_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_RFE_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_RFE_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_AND_SAVEEXEC_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_AND_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_AND_SAVEEXEC_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_OR_SAVEEXEC_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_OR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_OR_SAVEEXEC_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_XOR_SAVEEXEC_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_XOR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_XOR_SAVEEXEC_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_ANDN2_SAVEEXEC_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_ANDN2_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_ANDN2_SAVEEXEC_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_ORN2_SAVEEXEC_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_ORN2_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_ORN2_SAVEEXEC_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_NAND_SAVEEXEC_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_NAND_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_NAND_SAVEEXEC_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_NOR_SAVEEXEC_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_NOR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_NOR_SAVEEXEC_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_XNOR_SAVEEXEC_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_XNOR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_XNOR_SAVEEXEC_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_QUADMASK_B32(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_QUADMASK_B32(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_QUADMASK_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_QUADMASK_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_QUADMASK_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_QUADMASK_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_MOVRELS_B32(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_MOVRELS_B32(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_MOVRELS_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_MOVRELS_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_MOVRELS_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_MOVRELS_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_MOVRELD_B32(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_MOVRELD_B32(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_MOVRELD_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_MOVRELD_B64(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_MOVRELD_B64(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_MOVRELD_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_CBRANCH_JOIN(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_CBRANCH_JOIN(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_CBRANCH_JOIN
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_ABS_I32(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_ABS_I32(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_ABS_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_MOV_FED_B32(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_MOV_FED_B32(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_MOV_FED_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOP1__S_SET_GPR_IDX_IDX(MachInst iFmt)
+ {
+ return new Inst_SOP1__S_SET_GPR_IDX_IDX(&iFmt->iFmt_SOP1);
+ } // decode_OP_SOP1__S_SET_GPR_IDX_IDX
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPC__S_CMP_EQ_I32(MachInst iFmt)
+ {
+ return new Inst_SOPC__S_CMP_EQ_I32(&iFmt->iFmt_SOPC);
+ } // decode_OP_SOPC__S_CMP_EQ_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPC__S_CMP_LG_I32(MachInst iFmt)
+ {
+ return new Inst_SOPC__S_CMP_LG_I32(&iFmt->iFmt_SOPC);
+ } // decode_OP_SOPC__S_CMP_LG_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPC__S_CMP_GT_I32(MachInst iFmt)
+ {
+ return new Inst_SOPC__S_CMP_GT_I32(&iFmt->iFmt_SOPC);
+ } // decode_OP_SOPC__S_CMP_GT_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPC__S_CMP_GE_I32(MachInst iFmt)
+ {
+ return new Inst_SOPC__S_CMP_GE_I32(&iFmt->iFmt_SOPC);
+ } // decode_OP_SOPC__S_CMP_GE_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPC__S_CMP_LT_I32(MachInst iFmt)
+ {
+ return new Inst_SOPC__S_CMP_LT_I32(&iFmt->iFmt_SOPC);
+ } // decode_OP_SOPC__S_CMP_LT_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPC__S_CMP_LE_I32(MachInst iFmt)
+ {
+ return new Inst_SOPC__S_CMP_LE_I32(&iFmt->iFmt_SOPC);
+ } // decode_OP_SOPC__S_CMP_LE_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPC__S_CMP_EQ_U32(MachInst iFmt)
+ {
+ return new Inst_SOPC__S_CMP_EQ_U32(&iFmt->iFmt_SOPC);
+ } // decode_OP_SOPC__S_CMP_EQ_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPC__S_CMP_LG_U32(MachInst iFmt)
+ {
+ return new Inst_SOPC__S_CMP_LG_U32(&iFmt->iFmt_SOPC);
+ } // decode_OP_SOPC__S_CMP_LG_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPC__S_CMP_GT_U32(MachInst iFmt)
+ {
+ return new Inst_SOPC__S_CMP_GT_U32(&iFmt->iFmt_SOPC);
+ } // decode_OP_SOPC__S_CMP_GT_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPC__S_CMP_GE_U32(MachInst iFmt)
+ {
+ return new Inst_SOPC__S_CMP_GE_U32(&iFmt->iFmt_SOPC);
+ } // decode_OP_SOPC__S_CMP_GE_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPC__S_CMP_LT_U32(MachInst iFmt)
+ {
+ return new Inst_SOPC__S_CMP_LT_U32(&iFmt->iFmt_SOPC);
+ } // decode_OP_SOPC__S_CMP_LT_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPC__S_CMP_LE_U32(MachInst iFmt)
+ {
+ return new Inst_SOPC__S_CMP_LE_U32(&iFmt->iFmt_SOPC);
+ } // decode_OP_SOPC__S_CMP_LE_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPC__S_BITCMP0_B32(MachInst iFmt)
+ {
+ return new Inst_SOPC__S_BITCMP0_B32(&iFmt->iFmt_SOPC);
+ } // decode_OP_SOPC__S_BITCMP0_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPC__S_BITCMP1_B32(MachInst iFmt)
+ {
+ return new Inst_SOPC__S_BITCMP1_B32(&iFmt->iFmt_SOPC);
+ } // decode_OP_SOPC__S_BITCMP1_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPC__S_BITCMP0_B64(MachInst iFmt)
+ {
+ return new Inst_SOPC__S_BITCMP0_B64(&iFmt->iFmt_SOPC);
+ } // decode_OP_SOPC__S_BITCMP0_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPC__S_BITCMP1_B64(MachInst iFmt)
+ {
+ return new Inst_SOPC__S_BITCMP1_B64(&iFmt->iFmt_SOPC);
+ } // decode_OP_SOPC__S_BITCMP1_B64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPC__S_SETVSKIP(MachInst iFmt)
+ {
+ return new Inst_SOPC__S_SETVSKIP(&iFmt->iFmt_SOPC);
+ } // decode_OP_SOPC__S_SETVSKIP
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPC__S_SET_GPR_IDX_ON(MachInst iFmt)
+ {
+ return new Inst_SOPC__S_SET_GPR_IDX_ON(&iFmt->iFmt_SOPC);
+ } // decode_OP_SOPC__S_SET_GPR_IDX_ON
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPC__S_CMP_EQ_U64(MachInst iFmt)
+ {
+ return new Inst_SOPC__S_CMP_EQ_U64(&iFmt->iFmt_SOPC);
+ } // decode_OP_SOPC__S_CMP_EQ_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPC__S_CMP_LG_U64(MachInst iFmt)
+ {
+ return new Inst_SOPC__S_CMP_LG_U64(&iFmt->iFmt_SOPC);
+ } // decode_OP_SOPC__S_CMP_LG_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_NOP(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_NOP(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_NOP
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_ENDPGM(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_ENDPGM(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_ENDPGM
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_BRANCH(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_BRANCH(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_BRANCH
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_WAKEUP(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_WAKEUP(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_WAKEUP
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_CBRANCH_SCC0(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_CBRANCH_SCC0(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_CBRANCH_SCC0
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_CBRANCH_SCC1(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_CBRANCH_SCC1(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_CBRANCH_SCC1
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_CBRANCH_VCCZ(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_CBRANCH_VCCZ(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_CBRANCH_VCCZ
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_CBRANCH_VCCNZ(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_CBRANCH_VCCNZ(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_CBRANCH_VCCNZ
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_CBRANCH_EXECZ(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_CBRANCH_EXECZ(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_CBRANCH_EXECZ
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_CBRANCH_EXECNZ(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_CBRANCH_EXECNZ(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_CBRANCH_EXECNZ
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_BARRIER(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_BARRIER(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_BARRIER
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_SETKILL(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_SETKILL(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_SETKILL
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_WAITCNT(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_WAITCNT(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_WAITCNT
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_SETHALT(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_SETHALT(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_SETHALT
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_SLEEP(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_SLEEP(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_SLEEP
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_SETPRIO(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_SETPRIO(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_SETPRIO
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_SENDMSG(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_SENDMSG(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_SENDMSG
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_SENDMSGHALT(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_SENDMSGHALT(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_SENDMSGHALT
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_TRAP(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_TRAP(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_TRAP
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_ICACHE_INV(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_ICACHE_INV(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_ICACHE_INV
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_INCPERFLEVEL(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_INCPERFLEVEL(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_INCPERFLEVEL
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_DECPERFLEVEL(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_DECPERFLEVEL(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_DECPERFLEVEL
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_TTRACEDATA(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_TTRACEDATA(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_TTRACEDATA
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_CBRANCH_CDBGSYS(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_CBRANCH_CDBGSYS
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_CBRANCH_CDBGUSER(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_CBRANCH_CDBGUSER(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_CBRANCH_CDBGUSER
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS_OR_USER(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_CBRANCH_CDBGSYS_OR_USER(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_CBRANCH_CDBGSYS_OR_USER
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS_AND_USER(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_CBRANCH_CDBGSYS_AND_USER(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_CBRANCH_CDBGSYS_AND_USER
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_ENDPGM_SAVED(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_ENDPGM_SAVED(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_ENDPGM_SAVED
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_SET_GPR_IDX_OFF(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_SET_GPR_IDX_OFF(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_SET_GPR_IDX_OFF
+
+ GPUStaticInst*
+ Decoder::decode_OP_SOPP__S_SET_GPR_IDX_MODE(MachInst iFmt)
+ {
+ return new Inst_SOPP__S_SET_GPR_IDX_MODE(&iFmt->iFmt_SOPP);
+ } // decode_OP_SOPP__S_SET_GPR_IDX_MODE
+
+ GPUStaticInst*
+ Decoder::decode_OP_VINTRP__V_INTERP_P1_F32(MachInst iFmt)
+ {
+ return new Inst_VINTRP__V_INTERP_P1_F32(&iFmt->iFmt_VINTRP);
+ } // decode_OP_VINTRP__V_INTERP_P1_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VINTRP__V_INTERP_P2_F32(MachInst iFmt)
+ {
+ return new Inst_VINTRP__V_INTERP_P2_F32(&iFmt->iFmt_VINTRP);
+ } // decode_OP_VINTRP__V_INTERP_P2_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VINTRP__V_INTERP_MOV_F32(MachInst iFmt)
+ {
+ return new Inst_VINTRP__V_INTERP_MOV_F32(&iFmt->iFmt_VINTRP);
+ } // decode_OP_VINTRP__V_INTERP_MOV_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_NOP(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_NOP(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_NOP
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_MOV_B32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_MOV_B32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_MOV_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_READFIRSTLANE_B32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_READFIRSTLANE_B32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_READFIRSTLANE_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_I32_F64(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_I32_F64(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_I32_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_F64_I32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_F64_I32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_F64_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_F32_I32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_F32_I32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_F32_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_F32_U32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_F32_U32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_F32_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_U32_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_U32_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_U32_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_I32_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_I32_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_I32_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_MOV_FED_B32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_MOV_FED_B32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_MOV_FED_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_F16_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_F16_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_F16_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_F32_F16(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_F32_F16(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_F32_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_RPI_I32_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_RPI_I32_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_RPI_I32_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_FLR_I32_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_FLR_I32_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_FLR_I32_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_OFF_F32_I4(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_OFF_F32_I4(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_OFF_F32_I4
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_F32_F64(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_F32_F64(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_F32_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_F64_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_F64_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_F64_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE0(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_F32_UBYTE0(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_F32_UBYTE0
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE1(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_F32_UBYTE1(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_F32_UBYTE1
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE2(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_F32_UBYTE2(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_F32_UBYTE2
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE3(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_F32_UBYTE3(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_F32_UBYTE3
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_U32_F64(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_U32_F64(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_U32_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_F64_U32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_F64_U32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_F64_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_TRUNC_F64(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_TRUNC_F64(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_TRUNC_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CEIL_F64(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CEIL_F64(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CEIL_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_RNDNE_F64(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_RNDNE_F64(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_RNDNE_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_FLOOR_F64(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_FLOOR_F64(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_FLOOR_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_FRACT_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_FRACT_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_FRACT_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_TRUNC_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_TRUNC_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_TRUNC_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CEIL_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CEIL_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CEIL_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_RNDNE_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_RNDNE_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_RNDNE_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_FLOOR_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_FLOOR_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_FLOOR_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_EXP_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_EXP_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_EXP_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_LOG_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_LOG_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_LOG_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_RCP_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_RCP_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_RCP_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_RCP_IFLAG_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_RCP_IFLAG_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_RCP_IFLAG_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_RSQ_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_RSQ_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_RSQ_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_RCP_F64(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_RCP_F64(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_RCP_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_RSQ_F64(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_RSQ_F64(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_RSQ_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_SQRT_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_SQRT_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_SQRT_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_SQRT_F64(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_SQRT_F64(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_SQRT_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_SIN_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_SIN_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_SIN_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_COS_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_COS_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_COS_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_NOT_B32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_NOT_B32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_NOT_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_BFREV_B32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_BFREV_B32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_BFREV_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_FFBH_U32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_FFBH_U32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_FFBH_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_FFBL_B32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_FFBL_B32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_FFBL_B32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_FFBH_I32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_FFBH_I32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_FFBH_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_FREXP_EXP_I32_F64(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_FREXP_EXP_I32_F64(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_FREXP_EXP_I32_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_FREXP_MANT_F64(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_FREXP_MANT_F64(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_FREXP_MANT_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_FRACT_F64(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_FRACT_F64(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_FRACT_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_FREXP_EXP_I32_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_FREXP_EXP_I32_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_FREXP_EXP_I32_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_FREXP_MANT_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_FREXP_MANT_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_FREXP_MANT_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CLREXCP(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CLREXCP(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CLREXCP
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_F16_U16(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_F16_U16(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_F16_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_F16_I16(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_F16_I16(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_F16_I16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_U16_F16(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_U16_F16(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_U16_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CVT_I16_F16(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CVT_I16_F16(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CVT_I16_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_RCP_F16(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_RCP_F16(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_RCP_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_SQRT_F16(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_SQRT_F16(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_SQRT_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_RSQ_F16(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_RSQ_F16(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_RSQ_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_LOG_F16(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_LOG_F16(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_LOG_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_EXP_F16(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_EXP_F16(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_EXP_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_FREXP_MANT_F16(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_FREXP_MANT_F16(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_FREXP_MANT_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_FREXP_EXP_I16_F16(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_FREXP_EXP_I16_F16(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_FREXP_EXP_I16_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_FLOOR_F16(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_FLOOR_F16(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_FLOOR_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_CEIL_F16(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_CEIL_F16(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_CEIL_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_TRUNC_F16(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_TRUNC_F16(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_TRUNC_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_RNDNE_F16(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_RNDNE_F16(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_RNDNE_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_FRACT_F16(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_FRACT_F16(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_FRACT_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_SIN_F16(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_SIN_F16(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_SIN_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_COS_F16(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_COS_F16(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_COS_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_EXP_LEGACY_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_EXP_LEGACY_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_EXP_LEGACY_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOP1__V_LOG_LEGACY_F32(MachInst iFmt)
+ {
+ return new Inst_VOP1__V_LOG_LEGACY_F32(&iFmt->iFmt_VOP1);
+ } // decode_OP_VOP1__V_LOG_LEGACY_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_CLASS_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_CLASS_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_CLASS_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_CLASS_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_CLASS_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_CLASS_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_CLASS_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_CLASS_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_CLASS_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_CLASS_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_CLASS_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_CLASS_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_CLASS_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_CLASS_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_CLASS_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_CLASS_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_CLASS_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_CLASS_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_F_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_F_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_F_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_LT_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_LT_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_LT_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_EQ_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_EQ_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_EQ_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_LE_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_LE_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_LE_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_GT_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_GT_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_GT_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_LG_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_LG_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_LG_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_GE_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_GE_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_GE_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_O_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_O_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_O_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_U_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_U_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_U_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NGE_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NGE_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NGE_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NLG_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NLG_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NLG_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NGT_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NGT_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NGT_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NLE_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NLE_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NLE_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NEQ_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NEQ_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NEQ_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NLT_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NLT_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NLT_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_TRU_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_TRU_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_TRU_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_F_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_F_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_F_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_LT_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_LT_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_LT_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_EQ_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_EQ_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_EQ_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_LE_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_LE_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_LE_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_GT_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_GT_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_GT_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_LG_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_LG_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_LG_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_GE_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_GE_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_GE_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_O_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_O_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_O_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_U_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_U_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_U_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NGE_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NGE_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NGE_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NLG_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NLG_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NLG_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NGT_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NGT_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NGT_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NLE_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NLE_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NLE_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NEQ_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NEQ_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NEQ_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NLT_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NLT_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NLT_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_TRU_F16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_TRU_F16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_TRU_F16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_F_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_F_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_F_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_LT_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_LT_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_LT_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_EQ_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_EQ_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_EQ_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_LE_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_LE_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_LE_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_GT_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_GT_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_GT_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_LG_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_LG_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_LG_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_GE_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_GE_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_GE_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_O_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_O_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_O_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_U_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_U_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_U_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NGE_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NGE_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NGE_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NLG_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NLG_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NLG_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NGT_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NGT_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NGT_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NLE_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NLE_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NLE_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NEQ_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NEQ_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NEQ_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NLT_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NLT_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NLT_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_TRU_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_TRU_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_TRU_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_F_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_F_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_F_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_LT_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_LT_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_LT_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_EQ_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_EQ_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_EQ_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_LE_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_LE_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_LE_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_GT_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_GT_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_GT_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_LG_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_LG_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_LG_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_GE_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_GE_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_GE_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_O_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_O_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_O_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_U_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_U_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_U_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NGE_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NGE_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NGE_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NLG_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NLG_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NLG_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NGT_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NGT_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NGT_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NLE_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NLE_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NLE_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NEQ_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NEQ_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NEQ_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NLT_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NLT_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NLT_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_TRU_F32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_TRU_F32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_TRU_F32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_F_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_F_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_F_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_LT_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_LT_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_LT_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_EQ_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_EQ_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_EQ_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_LE_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_LE_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_LE_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_GT_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_GT_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_GT_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_LG_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_LG_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_LG_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_GE_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_GE_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_GE_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_O_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_O_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_O_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_U_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_U_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_U_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NGE_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NGE_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NGE_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NLG_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NLG_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NLG_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NGT_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NGT_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NGT_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NLE_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NLE_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NLE_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NEQ_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NEQ_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NEQ_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NLT_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NLT_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NLT_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_TRU_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_TRU_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_TRU_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_F_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_F_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_F_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_LT_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_LT_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_LT_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_EQ_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_EQ_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_EQ_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_LE_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_LE_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_LE_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_GT_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_GT_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_GT_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_LG_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_LG_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_LG_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_GE_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_GE_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_GE_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_O_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_O_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_O_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_U_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_U_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_U_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NGE_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NGE_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NGE_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NLG_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NLG_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NLG_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NGT_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NGT_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NGT_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NLE_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NLE_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NLE_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NEQ_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NEQ_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NEQ_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NLT_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NLT_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NLT_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_TRU_F64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_TRU_F64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_TRU_F64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_F_I16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_F_I16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_F_I16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_LT_I16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_LT_I16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_LT_I16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_EQ_I16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_EQ_I16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_EQ_I16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_LE_I16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_LE_I16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_LE_I16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_GT_I16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_GT_I16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_GT_I16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NE_I16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NE_I16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NE_I16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_GE_I16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_GE_I16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_GE_I16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_T_I16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_T_I16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_T_I16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_F_U16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_F_U16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_F_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_LT_U16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_LT_U16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_LT_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_EQ_U16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_EQ_U16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_EQ_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_LE_U16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_LE_U16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_LE_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_GT_U16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_GT_U16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_GT_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NE_U16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NE_U16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NE_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_GE_U16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_GE_U16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_GE_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_T_U16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_T_U16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_T_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_F_I16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_F_I16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_F_I16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_LT_I16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_LT_I16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_LT_I16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_EQ_I16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_EQ_I16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_EQ_I16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_LE_I16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_LE_I16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_LE_I16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_GT_I16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_GT_I16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_GT_I16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NE_I16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NE_I16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NE_I16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_GE_I16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_GE_I16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_GE_I16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_T_I16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_T_I16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_T_I16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_F_U16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_F_U16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_F_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_LT_U16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_LT_U16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_LT_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_EQ_U16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_EQ_U16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_EQ_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_LE_U16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_LE_U16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_LE_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_GT_U16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_GT_U16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_GT_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NE_U16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NE_U16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NE_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_GE_U16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_GE_U16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_GE_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_T_U16(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_T_U16(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_T_U16
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_F_I32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_F_I32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_F_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_LT_I32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_LT_I32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_LT_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_EQ_I32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_EQ_I32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_EQ_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_LE_I32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_LE_I32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_LE_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_GT_I32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_GT_I32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_GT_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NE_I32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NE_I32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NE_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_GE_I32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_GE_I32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_GE_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_T_I32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_T_I32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_T_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_F_U32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_F_U32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_F_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_LT_U32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_LT_U32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_LT_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_EQ_U32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_EQ_U32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_EQ_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_LE_U32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_LE_U32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_LE_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_GT_U32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_GT_U32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_GT_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NE_U32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NE_U32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NE_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_GE_U32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_GE_U32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_GE_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_T_U32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_T_U32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_T_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_F_I32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_F_I32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_F_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_LT_I32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_LT_I32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_LT_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_EQ_I32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_EQ_I32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_EQ_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_LE_I32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_LE_I32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_LE_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_GT_I32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_GT_I32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_GT_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NE_I32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NE_I32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NE_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_GE_I32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_GE_I32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_GE_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_T_I32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_T_I32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_T_I32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_F_U32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_F_U32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_F_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_LT_U32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_LT_U32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_LT_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_EQ_U32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_EQ_U32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_EQ_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_LE_U32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_LE_U32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_LE_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_GT_U32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_GT_U32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_GT_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NE_U32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NE_U32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NE_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_GE_U32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_GE_U32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_GE_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_T_U32(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_T_U32(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_T_U32
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_F_I64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_F_I64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_F_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_LT_I64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_LT_I64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_LT_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_EQ_I64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_EQ_I64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_EQ_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_LE_I64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_LE_I64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_LE_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_GT_I64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_GT_I64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_GT_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NE_I64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NE_I64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NE_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_GE_I64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_GE_I64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_GE_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_T_I64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_T_I64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_T_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_F_U64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_F_U64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_F_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_LT_U64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_LT_U64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_LT_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_EQ_U64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_EQ_U64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_EQ_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_LE_U64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_LE_U64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_LE_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_GT_U64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_GT_U64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_GT_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_NE_U64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_NE_U64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_NE_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_GE_U64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_GE_U64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_GE_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMP_T_U64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMP_T_U64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMP_T_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_F_I64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_F_I64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_F_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_LT_I64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_LT_I64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_LT_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_EQ_I64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_EQ_I64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_EQ_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_LE_I64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_LE_I64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_LE_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_GT_I64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_GT_I64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_GT_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NE_I64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NE_I64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NE_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_GE_I64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_GE_I64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_GE_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_T_I64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_T_I64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_T_I64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_F_U64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_F_U64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_F_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_LT_U64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_LT_U64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_LT_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_EQ_U64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_EQ_U64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_EQ_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_LE_U64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_LE_U64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_LE_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_GT_U64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_GT_U64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_GT_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_NE_U64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_NE_U64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_NE_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_GE_U64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_GE_U64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_GE_U64
+
+ GPUStaticInst*
+ Decoder::decode_OP_VOPC__V_CMPX_T_U64(MachInst iFmt)
+ {
+ return new Inst_VOPC__V_CMPX_T_U64(&iFmt->iFmt_VOPC);
+ } // decode_OP_VOPC__V_CMPX_T_U64
+
+ GPUStaticInst*
+ Decoder::decode_invalid(MachInst iFmt)
+ {
+ fatal("Invalid opcode encountered: %#x\n", iFmt->imm_u32);
+
+ return nullptr;
+ }
+} // namespace Gcn3ISA
diff --git a/src/arch/gcn3/gpu_decoder.hh b/src/arch/gcn3/gpu_decoder.hh
new file mode 100644
index 0000000..b561263
--- /dev/null
+++ b/src/arch/gcn3/gpu_decoder.hh
@@ -0,0 +1,1647 @@
+/*
+ * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * For use for simulation and test purposes only
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: John Slice
+ * Anthony Gutierrez
+ */
+
+#ifndef __ARCH_GCN3_DECODER_HH__
+#define __ARCH_GCN3_DECODER_HH__
+
+#include <string>
+#include <vector>
+
+#include "arch/gcn3/gpu_types.hh"
+
+class GPUStaticInst;
+
+namespace Gcn3ISA
+{
+ class Decoder;
+ union InstFormat;
+
+ using IsaDecodeMethod = GPUStaticInst*(Decoder::*)(MachInst);
+
+ class Decoder
+ {
+ public:
+ Decoder();
+ ~Decoder();
+
+ GPUStaticInst* decode(MachInst mach_inst);
+
+ private:
+ static IsaDecodeMethod tableDecodePrimary[512];
+ static IsaDecodeMethod tableSubDecode_OPU_VOP3[768];
+ static IsaDecodeMethod tableSubDecode_OP_DS[256];
+ static IsaDecodeMethod tableSubDecode_OP_FLAT[128];
+ static IsaDecodeMethod tableSubDecode_OP_MIMG[128];
+ static IsaDecodeMethod tableSubDecode_OP_MTBUF[16];
+ static IsaDecodeMethod tableSubDecode_OP_MUBUF[128];
+ static IsaDecodeMethod tableSubDecode_OP_SMEM[64];
+ static IsaDecodeMethod tableSubDecode_OP_SOP1[256];
+ static IsaDecodeMethod tableSubDecode_OP_SOPC[128];
+ static IsaDecodeMethod tableSubDecode_OP_SOPP[128];
+ static IsaDecodeMethod tableSubDecode_OP_VINTRP[4];
+ static IsaDecodeMethod tableSubDecode_OP_VOP1[256];
+ static IsaDecodeMethod tableSubDecode_OP_VOPC[256];
+
+ GPUStaticInst* decode_OPU_VOP3__V_ADDC_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_ADD_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_ADD_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_ADD_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_ADD_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_ADD_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_ALIGNBIT_B32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_ALIGNBYTE_B32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_AND_B32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_ASHRREV_I16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_ASHRREV_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_ASHRREV_I64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_BCNT_U32_B32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_BFE_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_BFE_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_BFI_B32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_BFM_B32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_BFREV_B32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CEIL_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CEIL_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CEIL_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CLREXCP(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_CLASS_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_CLASS_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_CLASS_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_EQ_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_EQ_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_EQ_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_EQ_I16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_EQ_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_EQ_I64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_EQ_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_EQ_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_EQ_U64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_F_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_F_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_F_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_F_I16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_F_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_F_I64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_F_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_F_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_F_U64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_GE_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_GE_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_GE_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_GE_I16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_GE_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_GE_I64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_GE_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_GE_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_GE_U64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_GT_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_GT_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_GT_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_GT_I16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_GT_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_GT_I64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_GT_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_GT_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_GT_U64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_LE_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_LE_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_LE_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_LE_I16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_LE_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_LE_I64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_LE_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_LE_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_LE_U64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_LG_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_LG_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_LG_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_LT_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_LT_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_LT_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_LT_I16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_LT_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_LT_I64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_LT_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_LT_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_LT_U64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NEQ_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NEQ_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NEQ_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NE_I16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NE_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NE_I64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NE_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NE_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NE_U64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NGE_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NGE_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NGE_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NGT_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NGT_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NGT_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NLE_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NLE_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NLE_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NLG_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NLG_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NLG_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NLT_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NLT_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_NLT_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_O_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_O_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_O_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_TRU_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_TRU_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_TRU_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_T_I16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_T_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_T_I64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_T_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_T_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_T_U64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_U_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_U_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMPX_U_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_CLASS_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_CLASS_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_CLASS_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_EQ_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_EQ_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_EQ_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_EQ_I16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_EQ_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_EQ_I64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_EQ_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_EQ_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_EQ_U64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_F_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_F_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_F_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_F_I16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_F_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_F_I64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_F_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_F_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_F_U64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_GE_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_GE_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_GE_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_GE_I16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_GE_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_GE_I64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_GE_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_GE_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_GE_U64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_GT_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_GT_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_GT_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_GT_I16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_GT_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_GT_I64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_GT_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_GT_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_GT_U64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_LE_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_LE_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_LE_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_LE_I16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_LE_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_LE_I64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_LE_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_LE_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_LE_U64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_LG_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_LG_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_LG_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_LT_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_LT_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_LT_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_LT_I16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_LT_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_LT_I64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_LT_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_LT_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_LT_U64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NEQ_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NEQ_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NEQ_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NE_I16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NE_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NE_I64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NE_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NE_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NE_U64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NGE_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NGE_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NGE_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NGT_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NGT_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NGT_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NLE_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NLE_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NLE_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NLG_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NLG_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NLG_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NLT_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NLT_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_NLT_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_O_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_O_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_O_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_TRU_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_TRU_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_TRU_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_T_I16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_T_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_T_I64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_T_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_T_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_T_U64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_U_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_U_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CMP_U_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CNDMASK_B32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_COS_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_COS_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CUBEID_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CUBEMA_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CUBESC_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CUBETC_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_F16_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_F16_I16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_F16_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_F32_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_F32_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_F32_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_F32_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_F32_UBYTE0(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_F32_UBYTE1(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_F32_UBYTE2(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_F32_UBYTE3(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_F64_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_F64_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_F64_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_FLR_I32_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_I16_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_I32_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_I32_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_OFF_F32_I4(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_PKNORM_I16_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_PKNORM_U16_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_PK_I16_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_PK_U16_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_PK_U8_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_RPI_I32_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_U16_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_U32_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_CVT_U32_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_DIV_FIXUP_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_DIV_FIXUP_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_DIV_FIXUP_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_DIV_FMAS_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_DIV_FMAS_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_DIV_SCALE_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_DIV_SCALE_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_EXP_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_EXP_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_EXP_LEGACY_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_FFBH_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_FFBH_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_FFBL_B32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_FLOOR_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_FLOOR_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_FLOOR_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_FMA_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_FMA_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_FMA_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_FRACT_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_FRACT_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_FRACT_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_FREXP_EXP_I16_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_FREXP_EXP_I32_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_FREXP_EXP_I32_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_FREXP_MANT_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_FREXP_MANT_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_FREXP_MANT_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_INTERP_MOV_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_INTERP_P1LL_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_INTERP_P1LV_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_INTERP_P1_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_INTERP_P2_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_INTERP_P2_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_LDEXP_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_LDEXP_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_LDEXP_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_LERP_U8(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_LOG_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_LOG_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_LOG_LEGACY_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_LSHLREV_B16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_LSHLREV_B32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_LSHLREV_B64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_LSHRREV_B16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_LSHRREV_B32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_LSHRREV_B64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MAC_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MAC_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MAD_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MAD_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MAD_I16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MAD_I32_I24(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MAD_I64_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MAD_LEGACY_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MAD_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MAD_U32_U24(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MAD_U64_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MAX3_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MAX3_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MAX3_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MAX_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MAX_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MAX_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MAX_I16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MAX_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MAX_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MAX_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MBCNT_HI_U32_B32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MBCNT_LO_U32_B32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MED3_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MED3_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MED3_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MIN3_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MIN3_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MIN3_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MIN_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MIN_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MIN_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MIN_I16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MIN_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MIN_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MIN_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MOV_B32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MOV_FED_B32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MQSAD_PK_U16_U8(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MQSAD_U32_U8(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MSAD_U8(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MUL_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MUL_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MUL_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MUL_HI_I32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MUL_HI_I32_I24(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MUL_HI_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MUL_HI_U32_U24(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MUL_I32_I24(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MUL_LEGACY_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MUL_LO_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MUL_LO_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_MUL_U32_U24(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_NOP(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_NOT_B32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_OR_B32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_PERM_B32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_QSAD_PK_U16_U8(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_RCP_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_RCP_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_RCP_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_RCP_IFLAG_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_READLANE_B32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_RNDNE_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_RNDNE_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_RNDNE_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_RSQ_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_RSQ_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_RSQ_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_SAD_HI_U8(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_SAD_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_SAD_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_SAD_U8(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_SIN_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_SIN_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_SQRT_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_SQRT_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_SQRT_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_SUBBREV_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_SUBB_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_SUBREV_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_SUBREV_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_SUBREV_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_SUBREV_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_SUB_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_SUB_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_SUB_U16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_SUB_U32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_TRIG_PREOP_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_TRUNC_F16(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_TRUNC_F32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_TRUNC_F64(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_WRITELANE_B32(MachInst);
+ GPUStaticInst* decode_OPU_VOP3__V_XOR_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_ADD_F32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_ADD_RTN_F32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_ADD_RTN_U32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_ADD_RTN_U64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_ADD_SRC2_F32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_ADD_SRC2_U32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_ADD_SRC2_U64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_ADD_U32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_ADD_U64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_AND_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_AND_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_AND_RTN_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_AND_RTN_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_AND_SRC2_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_AND_SRC2_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_APPEND(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_BPERMUTE_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_CMPST_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_CMPST_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_CMPST_F32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_CMPST_F64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_CMPST_RTN_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_CMPST_RTN_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_CMPST_RTN_F32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_CMPST_RTN_F64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_CONDXCHG32_RTN_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_CONSUME(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_DEC_RTN_U32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_DEC_RTN_U64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_DEC_SRC2_U32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_DEC_SRC2_U64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_DEC_U32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_DEC_U64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_GWS_BARRIER(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_GWS_INIT(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_GWS_SEMA_BR(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_GWS_SEMA_P(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_GWS_SEMA_RELEASE_ALL(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_GWS_SEMA_V(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_INC_RTN_U32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_INC_RTN_U64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_INC_SRC2_U32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_INC_SRC2_U64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_INC_U32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_INC_U64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MAX_F32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MAX_F64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MAX_I32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MAX_I64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MAX_RTN_F32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MAX_RTN_F64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MAX_RTN_I32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MAX_RTN_I64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MAX_RTN_U32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MAX_RTN_U64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MAX_SRC2_F32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MAX_SRC2_F64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MAX_SRC2_I32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MAX_SRC2_I64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MAX_SRC2_U32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MAX_SRC2_U64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MAX_U32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MAX_U64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MIN_F32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MIN_F64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MIN_I32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MIN_I64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MIN_RTN_F32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MIN_RTN_F64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MIN_RTN_I32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MIN_RTN_I64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MIN_RTN_U32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MIN_RTN_U64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MIN_SRC2_F32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MIN_SRC2_F64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MIN_SRC2_I32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MIN_SRC2_I64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MIN_SRC2_U32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MIN_SRC2_U64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MIN_U32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MIN_U64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MSKOR_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MSKOR_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MSKOR_RTN_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_MSKOR_RTN_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_NOP(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_ORDERED_COUNT(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_OR_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_OR_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_OR_RTN_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_OR_RTN_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_OR_SRC2_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_OR_SRC2_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_PERMUTE_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_READ2ST64_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_READ2ST64_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_READ2_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_READ2_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_READ_B128(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_READ_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_READ_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_READ_B96(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_READ_I16(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_READ_I8(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_READ_U16(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_READ_U8(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_RSUB_RTN_U32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_RSUB_RTN_U64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_RSUB_SRC2_U32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_RSUB_SRC2_U64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_RSUB_U32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_RSUB_U64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_SUB_RTN_U32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_SUB_RTN_U64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_SUB_SRC2_U32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_SUB_SRC2_U64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_SUB_U32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_SUB_U64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_SWIZZLE_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_WRAP_RTN_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_WRITE2ST64_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_WRITE2ST64_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_WRITE2_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_WRITE2_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_WRITE_B128(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_WRITE_B16(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_WRITE_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_WRITE_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_WRITE_B8(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_WRITE_B96(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_WRITE_SRC2_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_WRITE_SRC2_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_WRXCHG2ST64_RTN_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_WRXCHG2ST64_RTN_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_WRXCHG2_RTN_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_WRXCHG2_RTN_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_WRXCHG_RTN_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_WRXCHG_RTN_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_XOR_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_XOR_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_XOR_RTN_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_XOR_RTN_B64(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_XOR_SRC2_B32(MachInst);
+ GPUStaticInst* decode_OP_DS__DS_XOR_SRC2_B64(MachInst);
+ GPUStaticInst* decode_OP_EXP(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_ADD(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_ADD_X2(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_AND(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_AND_X2(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP_X2(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_DEC(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_DEC_X2(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_INC(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_INC_X2(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_OR(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_OR_X2(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_SMAX(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_SMAX_X2(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_SMIN(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_SMIN_X2(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_SUB(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_SUB_X2(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_SWAP(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_SWAP_X2(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_UMAX(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_UMAX_X2(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_UMIN(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_UMIN_X2(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_XOR(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_ATOMIC_XOR_X2(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_LOAD_DWORD(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_LOAD_DWORDX2(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_LOAD_DWORDX3(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_LOAD_DWORDX4(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_LOAD_SBYTE(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_LOAD_SSHORT(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_LOAD_UBYTE(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_LOAD_USHORT(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_STORE_BYTE(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_STORE_DWORD(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_STORE_DWORDX2(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_STORE_DWORDX3(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_STORE_DWORDX4(MachInst);
+ GPUStaticInst* decode_OP_FLAT__FLAT_STORE_SHORT(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_ATOMIC_ADD(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_ATOMIC_AND(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_ATOMIC_DEC(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_ATOMIC_INC(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_ATOMIC_OR(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_ATOMIC_SMAX(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_ATOMIC_SMIN(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_ATOMIC_SUB(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_ATOMIC_SWAP(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_ATOMIC_UMAX(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_ATOMIC_UMIN(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_ATOMIC_XOR(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_B(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_B_CL(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_B_CL_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_B_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_C(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_CL(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_CL_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_C_B(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_C_B_CL(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_C_B_CL_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_C_B_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_C_CL(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_C_CL_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_C_L(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_C_LZ(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_C_LZ_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_C_L_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_C_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_L(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_LZ(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_LZ_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_L_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GET_LOD(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_GET_RESINFO(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_LOAD(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_LOAD_MIP(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_LOAD_MIP_PCK(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_LOAD_MIP_PCK_SGN(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_LOAD_PCK(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_LOAD_PCK_SGN(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_B(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_B_CL(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_B_CL_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_B_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_C(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_CD(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_CD_CL(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_CD_CL_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_CD_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_CL(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_CL_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_C_B(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_C_B_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_C_CD(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_C_CD_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_C_CL(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_C_CL_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_C_D(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_C_D_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_C_L(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_C_LZ(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_C_L_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_C_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_D(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_D_CL(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_D_CL_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_D_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_L(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_LZ(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_LZ_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_L_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_O(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_STORE(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_STORE_MIP(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_STORE_MIP_PCK(MachInst);
+ GPUStaticInst* decode_OP_MIMG__IMAGE_STORE_PCK(MachInst);
+ GPUStaticInst* decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_X(MachInst);
+ GPUStaticInst* decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY(MachInst);
+ GPUStaticInst* decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ(MachInst);
+ GPUStaticInst* decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW(MachInst);
+ GPUStaticInst* decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_X(MachInst);
+ GPUStaticInst* decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XY(MachInst);
+ GPUStaticInst* decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZ(MachInst);
+ GPUStaticInst* decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZW(MachInst);
+ GPUStaticInst* decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_X(MachInst);
+ GPUStaticInst* decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XY(MachInst);
+ GPUStaticInst* decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ(MachInst);
+ GPUStaticInst*
+ decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW(MachInst);
+ GPUStaticInst* decode_OP_MTBUF__TBUFFER_STORE_FORMAT_X(MachInst);
+ GPUStaticInst* decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XY(MachInst);
+ GPUStaticInst* decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZ(MachInst);
+ GPUStaticInst* decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZW(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_ADD(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_ADD_X2(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_AND(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_AND_X2(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_DEC(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_DEC_X2(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_INC(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_INC_X2(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_OR(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_OR_X2(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_SMAX(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_SMAX_X2(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_SMIN(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_SMIN_X2(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_SUB(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_SUB_X2(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_SWAP(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_SWAP_X2(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_UMAX(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_UMAX_X2(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_UMIN(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_UMIN_X2(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_XOR(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_ATOMIC_XOR_X2(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_DWORD(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_DWORDX2(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_DWORDX3(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_DWORDX4(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_X(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XY(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_FORMAT_X(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XY(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZ(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZW(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_SBYTE(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_SSHORT(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_UBYTE(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_USHORT(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_BYTE(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_DWORD(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_DWORDX2(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_DWORDX3(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_DWORDX4(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_X(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XY(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_FORMAT_X(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_FORMAT_XY(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZ(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZW(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_SHORT(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_WBINVL1(MachInst);
+ GPUStaticInst* decode_OP_MUBUF__BUFFER_WBINVL1_VOL(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_ATC_PROBE(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_ATC_PROBE_BUFFER(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_BUFFER_LOAD_DWORD(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_BUFFER_LOAD_DWORDX16(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_BUFFER_LOAD_DWORDX8(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_BUFFER_STORE_DWORD(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_BUFFER_STORE_DWORDX2(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_BUFFER_STORE_DWORDX4(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_DCACHE_INV(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_DCACHE_INV_VOL(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_DCACHE_WB(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_DCACHE_WB_VOL(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_LOAD_DWORD(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_LOAD_DWORDX16(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_LOAD_DWORDX2(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_LOAD_DWORDX4(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_LOAD_DWORDX8(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_MEMREALTIME(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_MEMTIME(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_STORE_DWORD(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_STORE_DWORDX2(MachInst);
+ GPUStaticInst* decode_OP_SMEM__S_STORE_DWORDX4(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_ABS_I32(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_ANDN2_SAVEEXEC_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_AND_SAVEEXEC_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_BCNT0_I32_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_BCNT0_I32_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_BCNT1_I32_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_BCNT1_I32_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_BITSET0_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_BITSET0_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_BITSET1_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_BITSET1_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_BREV_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_BREV_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_CBRANCH_JOIN(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_CMOV_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_CMOV_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_FF0_I32_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_FF0_I32_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_FF1_I32_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_FF1_I32_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_FLBIT_I32(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_FLBIT_I32_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_FLBIT_I32_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_FLBIT_I32_I64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_GETPC_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_MOVRELD_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_MOVRELD_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_MOVRELS_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_MOVRELS_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_MOV_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_MOV_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_MOV_FED_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_NAND_SAVEEXEC_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_NOR_SAVEEXEC_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_NOT_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_NOT_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_ORN2_SAVEEXEC_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_OR_SAVEEXEC_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_QUADMASK_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_QUADMASK_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_RFE_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_SETPC_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_SET_GPR_IDX_IDX(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_SEXT_I32_I16(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_SEXT_I32_I8(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_SWAPPC_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_WQM_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_WQM_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_XNOR_SAVEEXEC_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP1__S_XOR_SAVEEXEC_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_ABSDIFF_I32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_ADDC_U32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_ADD_I32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_ADD_U32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_ANDN2_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_ANDN2_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_AND_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_AND_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_ASHR_I32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_ASHR_I64(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_BFE_I32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_BFE_I64(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_BFE_U32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_BFE_U64(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_BFM_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_BFM_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_CBRANCH_G_FORK(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_CSELECT_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_CSELECT_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_LSHL_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_LSHL_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_LSHR_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_LSHR_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_MAX_I32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_MAX_U32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_MIN_I32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_MIN_U32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_MUL_I32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_NAND_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_NAND_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_NOR_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_NOR_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_ORN2_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_ORN2_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_OR_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_OR_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_RFE_RESTORE_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_SUBB_U32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_SUB_I32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_SUB_U32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_XNOR_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_XNOR_B64(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_XOR_B32(MachInst);
+ GPUStaticInst* decode_OP_SOP2__S_XOR_B64(MachInst);
+ GPUStaticInst* decode_OP_SOPC__S_BITCMP0_B32(MachInst);
+ GPUStaticInst* decode_OP_SOPC__S_BITCMP0_B64(MachInst);
+ GPUStaticInst* decode_OP_SOPC__S_BITCMP1_B32(MachInst);
+ GPUStaticInst* decode_OP_SOPC__S_BITCMP1_B64(MachInst);
+ GPUStaticInst* decode_OP_SOPC__S_CMP_EQ_I32(MachInst);
+ GPUStaticInst* decode_OP_SOPC__S_CMP_EQ_U32(MachInst);
+ GPUStaticInst* decode_OP_SOPC__S_CMP_EQ_U64(MachInst);
+ GPUStaticInst* decode_OP_SOPC__S_CMP_GE_I32(MachInst);
+ GPUStaticInst* decode_OP_SOPC__S_CMP_GE_U32(MachInst);
+ GPUStaticInst* decode_OP_SOPC__S_CMP_GT_I32(MachInst);
+ GPUStaticInst* decode_OP_SOPC__S_CMP_GT_U32(MachInst);
+ GPUStaticInst* decode_OP_SOPC__S_CMP_LE_I32(MachInst);
+ GPUStaticInst* decode_OP_SOPC__S_CMP_LE_U32(MachInst);
+ GPUStaticInst* decode_OP_SOPC__S_CMP_LG_I32(MachInst);
+ GPUStaticInst* decode_OP_SOPC__S_CMP_LG_U32(MachInst);
+ GPUStaticInst* decode_OP_SOPC__S_CMP_LG_U64(MachInst);
+ GPUStaticInst* decode_OP_SOPC__S_CMP_LT_I32(MachInst);
+ GPUStaticInst* decode_OP_SOPC__S_CMP_LT_U32(MachInst);
+ GPUStaticInst* decode_OP_SOPC__S_SETVSKIP(MachInst);
+ GPUStaticInst* decode_OP_SOPC__S_SET_GPR_IDX_ON(MachInst);
+ GPUStaticInst* decode_OP_SOPK__S_ADDK_I32(MachInst);
+ GPUStaticInst* decode_OP_SOPK__S_CBRANCH_I_FORK(MachInst);
+ GPUStaticInst* decode_OP_SOPK__S_CMOVK_I32(MachInst);
+ GPUStaticInst* decode_OP_SOPK__S_CMPK_EQ_I32(MachInst);
+ GPUStaticInst* decode_OP_SOPK__S_CMPK_EQ_U32(MachInst);
+ GPUStaticInst* decode_OP_SOPK__S_CMPK_GE_I32(MachInst);
+ GPUStaticInst* decode_OP_SOPK__S_CMPK_GE_U32(MachInst);
+ GPUStaticInst* decode_OP_SOPK__S_CMPK_GT_I32(MachInst);
+ GPUStaticInst* decode_OP_SOPK__S_CMPK_GT_U32(MachInst);
+ GPUStaticInst* decode_OP_SOPK__S_CMPK_LE_I32(MachInst);
+ GPUStaticInst* decode_OP_SOPK__S_CMPK_LE_U32(MachInst);
+ GPUStaticInst* decode_OP_SOPK__S_CMPK_LG_I32(MachInst);
+ GPUStaticInst* decode_OP_SOPK__S_CMPK_LG_U32(MachInst);
+ GPUStaticInst* decode_OP_SOPK__S_CMPK_LT_I32(MachInst);
+ GPUStaticInst* decode_OP_SOPK__S_CMPK_LT_U32(MachInst);
+ GPUStaticInst* decode_OP_SOPK__S_GETREG_B32(MachInst);
+ GPUStaticInst* decode_OP_SOPK__S_MOVK_I32(MachInst);
+ GPUStaticInst* decode_OP_SOPK__S_MULK_I32(MachInst);
+ GPUStaticInst* decode_OP_SOPK__S_SETREG_B32(MachInst);
+ GPUStaticInst* decode_OP_SOPK__S_SETREG_IMM32_B32(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_BARRIER(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_BRANCH(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_CBRANCH_CDBGSYS(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_CBRANCH_CDBGSYS_AND_USER(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_CBRANCH_CDBGSYS_OR_USER(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_CBRANCH_CDBGUSER(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_CBRANCH_EXECNZ(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_CBRANCH_EXECZ(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_CBRANCH_SCC0(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_CBRANCH_SCC1(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_CBRANCH_VCCNZ(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_CBRANCH_VCCZ(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_DECPERFLEVEL(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_ENDPGM(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_ENDPGM_SAVED(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_ICACHE_INV(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_INCPERFLEVEL(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_NOP(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_SENDMSG(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_SENDMSGHALT(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_SETHALT(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_SETKILL(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_SETPRIO(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_SET_GPR_IDX_MODE(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_SET_GPR_IDX_OFF(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_SLEEP(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_TRAP(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_TTRACEDATA(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_WAITCNT(MachInst);
+ GPUStaticInst* decode_OP_SOPP__S_WAKEUP(MachInst);
+ GPUStaticInst* decode_OP_VINTRP__V_INTERP_MOV_F32(MachInst);
+ GPUStaticInst* decode_OP_VINTRP__V_INTERP_P1_F32(MachInst);
+ GPUStaticInst* decode_OP_VINTRP__V_INTERP_P2_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_BFREV_B32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CEIL_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CEIL_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CEIL_F64(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CLREXCP(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_COS_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_COS_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_F16_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_F16_I16(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_F16_U16(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_F32_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_F32_F64(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_F32_I32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_F32_U32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_F32_UBYTE0(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_F32_UBYTE1(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_F32_UBYTE2(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_F32_UBYTE3(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_F64_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_F64_I32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_F64_U32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_FLR_I32_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_I16_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_I32_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_I32_F64(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_OFF_F32_I4(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_RPI_I32_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_U16_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_U32_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_CVT_U32_F64(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_EXP_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_EXP_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_EXP_LEGACY_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_FFBH_I32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_FFBH_U32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_FFBL_B32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_FLOOR_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_FLOOR_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_FLOOR_F64(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_FRACT_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_FRACT_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_FRACT_F64(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_FREXP_EXP_I16_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_FREXP_EXP_I32_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_FREXP_EXP_I32_F64(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_FREXP_MANT_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_FREXP_MANT_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_FREXP_MANT_F64(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_LOG_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_LOG_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_LOG_LEGACY_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_MOV_B32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_MOV_FED_B32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_NOP(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_NOT_B32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_RCP_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_RCP_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_RCP_F64(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_RCP_IFLAG_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_READFIRSTLANE_B32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_RNDNE_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_RNDNE_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_RNDNE_F64(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_RSQ_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_RSQ_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_RSQ_F64(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_SIN_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_SIN_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_SQRT_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_SQRT_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_SQRT_F64(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_TRUNC_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_TRUNC_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP1__V_TRUNC_F64(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_ADDC_U32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_ADD_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_ADD_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_ADD_U16(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_ADD_U32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_AND_B32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_ASHRREV_I16(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_ASHRREV_I32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_CNDMASK_B32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_LDEXP_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_LSHLREV_B16(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_LSHLREV_B32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_LSHRREV_B16(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_LSHRREV_B32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MAC_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MAC_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MADAK_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MADAK_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MADMK_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MADMK_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MAX_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MAX_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MAX_I16(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MAX_I32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MAX_U16(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MAX_U32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MIN_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MIN_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MIN_I16(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MIN_I32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MIN_U16(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MIN_U32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MUL_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MUL_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MUL_HI_I32_I24(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MUL_HI_U32_U24(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MUL_I32_I24(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MUL_LEGACY_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MUL_LO_U16(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_MUL_U32_U24(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_OR_B32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_SUBBREV_U32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_SUBB_U32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_SUBREV_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_SUBREV_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_SUBREV_U16(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_SUBREV_U32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_SUB_F16(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_SUB_F32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_SUB_U16(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_SUB_U32(MachInst);
+ GPUStaticInst* decode_OP_VOP2__V_XOR_B32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_CLASS_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_CLASS_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_CLASS_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_EQ_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_EQ_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_EQ_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_EQ_I16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_EQ_I32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_EQ_I64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_EQ_U16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_EQ_U32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_EQ_U64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_F_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_F_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_F_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_F_I16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_F_I32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_F_I64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_F_U16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_F_U32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_F_U64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_GE_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_GE_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_GE_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_GE_I16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_GE_I32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_GE_I64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_GE_U16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_GE_U32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_GE_U64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_GT_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_GT_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_GT_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_GT_I16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_GT_I32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_GT_I64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_GT_U16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_GT_U32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_GT_U64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_LE_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_LE_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_LE_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_LE_I16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_LE_I32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_LE_I64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_LE_U16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_LE_U32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_LE_U64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_LG_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_LG_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_LG_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_LT_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_LT_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_LT_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_LT_I16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_LT_I32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_LT_I64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_LT_U16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_LT_U32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_LT_U64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NEQ_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NEQ_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NEQ_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NE_I16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NE_I32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NE_I64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NE_U16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NE_U32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NE_U64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NGE_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NGE_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NGE_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NGT_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NGT_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NGT_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NLE_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NLE_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NLE_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NLG_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NLG_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NLG_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NLT_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NLT_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_NLT_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_O_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_O_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_O_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_TRU_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_TRU_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_TRU_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_T_I16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_T_I32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_T_I64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_T_U16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_T_U32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_T_U64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_U_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_U_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMPX_U_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_CLASS_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_CLASS_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_CLASS_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_EQ_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_EQ_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_EQ_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_EQ_I16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_EQ_I32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_EQ_I64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_EQ_U16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_EQ_U32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_EQ_U64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_F_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_F_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_F_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_F_I16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_F_I32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_F_I64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_F_U16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_F_U32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_F_U64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_GE_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_GE_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_GE_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_GE_I16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_GE_I32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_GE_I64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_GE_U16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_GE_U32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_GE_U64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_GT_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_GT_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_GT_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_GT_I16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_GT_I32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_GT_I64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_GT_U16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_GT_U32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_GT_U64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_LE_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_LE_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_LE_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_LE_I16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_LE_I32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_LE_I64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_LE_U16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_LE_U32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_LE_U64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_LG_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_LG_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_LG_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_LT_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_LT_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_LT_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_LT_I16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_LT_I32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_LT_I64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_LT_U16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_LT_U32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_LT_U64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NEQ_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NEQ_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NEQ_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NE_I16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NE_I32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NE_I64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NE_U16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NE_U32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NE_U64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NGE_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NGE_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NGE_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NGT_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NGT_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NGT_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NLE_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NLE_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NLE_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NLG_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NLG_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NLG_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NLT_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NLT_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_NLT_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_O_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_O_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_O_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_TRU_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_TRU_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_TRU_F64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_T_I16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_T_I32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_T_I64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_T_U16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_T_U32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_T_U64(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_U_F16(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_U_F32(MachInst);
+ GPUStaticInst* decode_OP_VOPC__V_CMP_U_F64(MachInst);
+ GPUStaticInst* subDecode_OPU_VOP3(MachInst);
+ GPUStaticInst* subDecode_OP_DS(MachInst);
+ GPUStaticInst* subDecode_OP_FLAT(MachInst);
+ GPUStaticInst* subDecode_OP_MIMG(MachInst);
+ GPUStaticInst* subDecode_OP_MTBUF(MachInst);
+ GPUStaticInst* subDecode_OP_MUBUF(MachInst);
+ GPUStaticInst* subDecode_OP_SMEM(MachInst);
+ GPUStaticInst* subDecode_OP_SOP1(MachInst);
+ GPUStaticInst* subDecode_OP_SOPC(MachInst);
+ GPUStaticInst* subDecode_OP_SOPP(MachInst);
+ GPUStaticInst* subDecode_OP_VINTRP(MachInst);
+ GPUStaticInst* subDecode_OP_VOP1(MachInst);
+ GPUStaticInst* subDecode_OP_VOPC(MachInst);
+ GPUStaticInst* decode_invalid(MachInst);
+ };
+
+ struct InFmt_DS {
+ unsigned int OFFSET0 : 8;
+ unsigned int OFFSET1 : 8;
+ unsigned int GDS : 1;
+ unsigned int OP : 8;
+ unsigned int pad_25 : 1;
+ unsigned int ENCODING : 6;
+ };
+
+ struct InFmt_DS_1 {
+ unsigned int ADDR : 8;
+ unsigned int DATA0 : 8;
+ unsigned int DATA1 : 8;
+ unsigned int VDST : 8;
+ };
+
+ struct InFmt_EXP {
+ unsigned int EN : 4;
+ unsigned int TGT : 6;
+ unsigned int COMPR : 1;
+ unsigned int DONE : 1;
+ unsigned int VM : 1;
+ unsigned int pad_13_25 : 13;
+ unsigned int ENCODING : 6;
+ };
+
+ struct InFmt_EXP_1 {
+ unsigned int VSRC0 : 8;
+ unsigned int VSRC1 : 8;
+ unsigned int VSRC2 : 8;
+ unsigned int VSRC3 : 8;
+ };
+
+ struct InFmt_FLAT {
+ unsigned int pad_0_15 : 16;
+ unsigned int GLC : 1;
+ unsigned int SLC : 1;
+ unsigned int OP : 7;
+ unsigned int pad_25 : 1;
+ unsigned int ENCODING : 6;
+ };
+
+ struct InFmt_FLAT_1 {
+ unsigned int ADDR : 8;
+ unsigned int DATA : 8;
+ unsigned int pad_16_22 : 7;
+ unsigned int TFE : 1;
+ unsigned int VDST : 8;
+ };
+
+ struct InFmt_INST {
+ unsigned int ENCODING : 32;
+ };
+
+ struct InFmt_MIMG {
+ unsigned int pad_0_7 : 8;
+ unsigned int DMASK : 4;
+ unsigned int UNORM : 1;
+ unsigned int GLC : 1;
+ unsigned int DA : 1;
+ unsigned int R128 : 1;
+ unsigned int TFE : 1;
+ unsigned int LWE : 1;
+ unsigned int OP : 7;
+ unsigned int SLC : 1;
+ unsigned int ENCODING : 6;
+ };
+
+ struct InFmt_MIMG_1 {
+ unsigned int VADDR : 8;
+ unsigned int VDATA : 8;
+ unsigned int SRSRC : 5;
+ unsigned int SSAMP : 5;
+ unsigned int pad_26_30 : 5;
+ unsigned int D16 : 1;
+ };
+
+ struct InFmt_MTBUF {
+ unsigned int OFFSET : 12;
+ unsigned int OFFEN : 1;
+ unsigned int IDXEN : 1;
+ unsigned int GLC : 1;
+ unsigned int OP : 4;
+ unsigned int DFMT : 4;
+ unsigned int NFMT : 3;
+ unsigned int ENCODING : 6;
+ };
+
+ struct InFmt_MTBUF_1 {
+ unsigned int VADDR : 8;
+ unsigned int VDATA : 8;
+ unsigned int SRSRC : 5;
+ unsigned int pad_21 : 1;
+ unsigned int SLC : 1;
+ unsigned int TFE : 1;
+ unsigned int SOFFSET : 8;
+ };
+
+ struct InFmt_MUBUF {
+ unsigned int OFFSET : 12;
+ unsigned int OFFEN : 1;
+ unsigned int IDXEN : 1;
+ unsigned int GLC : 1;
+ unsigned int pad_15 : 1;
+ unsigned int LDS : 1;
+ unsigned int SLC : 1;
+ unsigned int OP : 7;
+ unsigned int pad_25 : 1;
+ unsigned int ENCODING : 6;
+ };
+
+ struct InFmt_MUBUF_1 {
+ unsigned int VADDR : 8;
+ unsigned int VDATA : 8;
+ unsigned int SRSRC : 5;
+ unsigned int pad_21_22 : 2;
+ unsigned int TFE : 1;
+ unsigned int SOFFSET : 8;
+ };
+
+ struct InFmt_SMEM {
+ unsigned int SBASE : 6;
+ unsigned int SDATA : 7;
+ unsigned int pad_13_15 : 3;
+ unsigned int GLC : 1;
+ unsigned int IMM : 1;
+ unsigned int OP : 8;
+ unsigned int ENCODING : 6;
+ };
+
+ struct InFmt_SMEM_1 {
+ unsigned int OFFSET : 20;
+ };
+
+ struct InFmt_SOP1 {
+ unsigned int SSRC0 : 8;
+ unsigned int OP : 8;
+ unsigned int SDST : 7;
+ unsigned int ENCODING : 9;
+ };
+
+ struct InFmt_SOP2 {
+ unsigned int SSRC0 : 8;
+ unsigned int SSRC1 : 8;
+ unsigned int SDST : 7;
+ unsigned int OP : 7;
+ unsigned int ENCODING : 2;
+ };
+
+ struct InFmt_SOPC {
+ unsigned int SSRC0 : 8;
+ unsigned int SSRC1 : 8;
+ unsigned int OP : 7;
+ unsigned int ENCODING : 9;
+ };
+
+ struct InFmt_SOPK {
+ unsigned int SIMM16 : 16;
+ unsigned int SDST : 7;
+ unsigned int OP : 5;
+ unsigned int ENCODING : 4;
+ };
+
+ struct InFmt_SOPP {
+ unsigned int SIMM16 : 16;
+ unsigned int OP : 7;
+ unsigned int ENCODING : 9;
+ };
+
+ struct InFmt_VINTRP {
+ unsigned int VSRC : 8;
+ unsigned int ATTRCHAN : 2;
+ unsigned int ATTR : 6;
+ unsigned int OP : 2;
+ unsigned int VDST : 8;
+ unsigned int ENCODING : 6;
+ };
+
+ struct InFmt_VOP1 {
+ unsigned int SRC0 : 9;
+ unsigned int OP : 8;
+ unsigned int VDST : 8;
+ unsigned int ENCODING : 7;
+ };
+
+ struct InFmt_VOP2 {
+ unsigned int SRC0 : 9;
+ unsigned int VSRC1 : 8;
+ unsigned int VDST : 8;
+ unsigned int OP : 6;
+ unsigned int ENCODING : 1;
+ };
+
+ struct InFmt_VOP3 {
+ unsigned int VDST : 8;
+ unsigned int ABS : 3;
+ unsigned int pad_11_14 : 4;
+ unsigned int CLAMP : 1;
+ unsigned int OP : 10;
+ unsigned int ENCODING : 6;
+ };
+
+ struct InFmt_VOP3_1 {
+ unsigned int SRC0 : 9;
+ unsigned int SRC1 : 9;
+ unsigned int SRC2 : 9;
+ unsigned int OMOD : 2;
+ unsigned int NEG : 3;
+ };
+
+ struct InFmt_VOP3_SDST_ENC {
+ unsigned int VDST : 8;
+ unsigned int SDST : 7;
+ unsigned int CLAMP : 1;
+ unsigned int OP : 10;
+ unsigned int ENCODING : 6;
+ };
+
+ struct InFmt_VOPC {
+ unsigned int SRC0 : 9;
+ unsigned int VSRC1 : 8;
+ unsigned int OP : 8;
+ unsigned int ENCODING : 7;
+ };
+
+ struct InFmt_VOP_DPP {
+ unsigned int SRC0 : 8;
+ unsigned int DPP_CTRL : 9;
+ unsigned int pad_17_18 : 2;
+ unsigned int BOUND_CTRL : 1;
+ unsigned int SRC0_NEG : 1;
+ unsigned int SRC0_ABS : 1;
+ unsigned int SRC1_NEG : 1;
+ unsigned int SRC1_ABS : 1;
+ unsigned int BANK_MASK : 4;
+ unsigned int ROW_MASK : 4;
+ };
+
+ struct InFmt_VOP_SDWA {
+ unsigned int SRC0 : 8;
+ unsigned int DST_SEL : 3;
+ unsigned int DST_UNUSED : 2;
+ unsigned int CLAMP : 1;
+ unsigned int pad_14_15 : 2;
+ unsigned int SRC0_SEL : 3;
+ unsigned int SRC0_SEXT : 1;
+ unsigned int SRC0_NEG : 1;
+ unsigned int SRC0_ABS : 1;
+ unsigned int pad_22_23 : 2;
+ unsigned int SRC1_SEL : 3;
+ unsigned int SRC1_SEXT : 1;
+ unsigned int SRC1_NEG : 1;
+ unsigned int SRC1_ABS : 1;
+ };
+
+ union InstFormat {
+ InFmt_DS iFmt_DS;
+ InFmt_DS_1 iFmt_DS_1;
+ InFmt_EXP iFmt_EXP;
+ InFmt_EXP_1 iFmt_EXP_1;
+ InFmt_FLAT iFmt_FLAT;
+ InFmt_FLAT_1 iFmt_FLAT_1;
+ InFmt_INST iFmt_INST;
+ InFmt_MIMG iFmt_MIMG;
+ InFmt_MIMG_1 iFmt_MIMG_1;
+ InFmt_MTBUF iFmt_MTBUF;
+ InFmt_MTBUF_1 iFmt_MTBUF_1;
+ InFmt_MUBUF iFmt_MUBUF;
+ InFmt_MUBUF_1 iFmt_MUBUF_1;
+ InFmt_SMEM iFmt_SMEM;
+ InFmt_SMEM_1 iFmt_SMEM_1;
+ InFmt_SOP1 iFmt_SOP1;
+ InFmt_SOP2 iFmt_SOP2;
+ InFmt_SOPC iFmt_SOPC;
+ InFmt_SOPK iFmt_SOPK;
+ InFmt_SOPP iFmt_SOPP;
+ InFmt_VINTRP iFmt_VINTRP;
+ InFmt_VOP1 iFmt_VOP1;
+ InFmt_VOP2 iFmt_VOP2;
+ InFmt_VOP3 iFmt_VOP3;
+ InFmt_VOP3_1 iFmt_VOP3_1;
+ InFmt_VOP3_SDST_ENC iFmt_VOP3_SDST_ENC;
+ InFmt_VOPC iFmt_VOPC;
+ InFmt_VOP_DPP iFmt_VOP_DPP;
+ InFmt_VOP_SDWA iFmt_VOP_SDWA;
+ uint32_t imm_u32;
+ float imm_f32;
+ }; // union InstFormat
+} // namespace Gcn3ISA
+
+#endif // __ARCH_GCN3_DECODER_HH__
diff --git a/src/arch/gcn3/gpu_isa.hh b/src/arch/gcn3/gpu_isa.hh
new file mode 100644
index 0000000..26b79c7
--- /dev/null
+++ b/src/arch/gcn3/gpu_isa.hh
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2016-2018 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * For use for simulation and test purposes only
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Anthony Gutierrez
+ */
+
+#ifndef __ARCH_GCN3_GPU_ISA_HH__
+#define __ARCH_GCN3_GPU_ISA_HH__
+
+#include <array>
+
+#include "arch/gcn3/registers.hh"
+#include "gpu-compute/dispatcher.hh"
+#include "gpu-compute/hsa_queue_entry.hh"
+#include "gpu-compute/misc.hh"
+
+class Wavefront;
+
+namespace Gcn3ISA
+{
+ class GPUISA
+ {
+ public:
+ GPUISA(Wavefront &wf);
+
+ ScalarRegU32 readMiscReg(int opIdx) const;
+ void writeMiscReg(int opIdx, ScalarRegU32 operandVal);
+ bool hasScalarUnit() const { return true; }
+ void advancePC(GPUDynInstPtr gpuDynInst);
+
+ private:
+ ScalarRegU32 readPosConstReg(int opIdx) const
+ {
+ return posConstRegs[opIdx - REG_INT_CONST_POS_MIN];
+ }
+
+ ScalarRegU32 readNegConstReg(int opIdx) const
+ {
+ return *((ScalarRegU32*)
+ &negConstRegs[opIdx - REG_INT_CONST_NEG_MIN]);
+ }
+
+ static const std::array<const ScalarRegU32, NumPosConstRegs>
+ posConstRegs;
+ static const std::array<const ScalarRegI32, NumNegConstRegs>
+ negConstRegs;
+
+ // parent wavefront
+ Wavefront &wavefront;
+
+ // shader status bits
+ StatusReg statusReg;
+ // memory descriptor reg
+ ScalarRegU32 m0;
+ };
+} // namespace Gcn3ISA
+
+#endif // __ARCH_GCN3_GPU_ISA_HH__
diff --git a/src/arch/gcn3/gpu_types.hh b/src/arch/gcn3/gpu_types.hh
new file mode 100644
index 0000000..62d2aea
--- /dev/null
+++ b/src/arch/gcn3/gpu_types.hh
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * For use for simulation and test purposes only
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Anthony Gutierrez
+ */
+
+#ifndef __ARCH_GCN3_GPU_TYPES_HH__
+#define __ARCH_GCN3_GPU_TYPES_HH__
+
+#include <cstdint>
+
+namespace Gcn3ISA
+{
+ union InstFormat;
+
+ /**
+ * used to represnt a GPU inst in its raw format. GCN3
+ * instructions may be 32b or 64b, therefore we represent
+ * a raw inst with 64b to ensure that all of its inst data,
+ * including potential immediate values, may be represented
+ * in the worst case.
+ */
+ typedef uint64_t RawMachInst;
+
+ /**
+ * used to represent the encoding of a GCN3 inst. each portion
+ * of a GCN3 inst must be 1 DWORD (32b), so we use a pointer
+ * to InstFormat type (which is 32b). for the case in which we
+ * need multiple DWORDS to represnt a single inst, this pointer
+ * essentialy acts as an array of the DWORDs needed to represent
+ * the entire inst encoding.
+ */
+ typedef InstFormat *MachInst;
+
+} // namespace Gcn3ISA
+
+#endif // __ARCH_GCN3_GPU_TYPES_HH__
diff --git a/src/arch/gcn3/insts/gpu_static_inst.cc b/src/arch/gcn3/insts/gpu_static_inst.cc
new file mode 100644
index 0000000..588875f
--- /dev/null
+++ b/src/arch/gcn3/insts/gpu_static_inst.cc
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * For use for simulation and test purposes only
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Anthony Gutierrez
+ */
+
+#include "arch/gcn3/insts/gpu_static_inst.hh"
+
+#include "arch/gcn3/gpu_decoder.hh"
+#include "arch/gcn3/insts/instructions.hh"
+#include "debug/GPUExec.hh"
+#include "gpu-compute/shader.hh"
+
+namespace Gcn3ISA
+{
+ GCN3GPUStaticInst::GCN3GPUStaticInst(const std::string &opcode)
+ : GPUStaticInst(opcode), _srcLiteral(0)
+ {
+ }
+
+ GCN3GPUStaticInst::~GCN3GPUStaticInst()
+ {
+ }
+
+ void
+ GCN3GPUStaticInst::panicUnimplemented() const
+ {
+ fatal("Encountered unimplemented GCN3 instruction: %s\n", _opcode);
+ }
+} // namespace Gcn3ISA
diff --git a/src/arch/gcn3/insts/gpu_static_inst.hh b/src/arch/gcn3/insts/gpu_static_inst.hh
new file mode 100644
index 0000000..3e87893
--- /dev/null
+++ b/src/arch/gcn3/insts/gpu_static_inst.hh
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * For use for simulation and test purposes only
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Anthony Gutierrez
+ */
+
+#ifndef __ARCH_GCN3_INSTS_GPU_STATIC_INST_HH__
+#define __ARCH_GCN3_INSTS_GPU_STATIC_INST_HH__
+
+#include "arch/gcn3/operand.hh"
+#include "arch/gcn3/registers.hh"
+#include "gpu-compute/gpu_static_inst.hh"
+#include "gpu-compute/scalar_register_file.hh"
+#include "gpu-compute/vector_register_file.hh"
+#include "gpu-compute/wavefront.hh"
+
+namespace Gcn3ISA
+{
+ class GCN3GPUStaticInst : public GPUStaticInst
+ {
+ public:
+ GCN3GPUStaticInst(const std::string &opcode);
+ ~GCN3GPUStaticInst();
+
+ void generateDisassembly() override { disassembly = _opcode; }
+
+ bool
+ isFlatScratchRegister(int opIdx) override
+ {
+ return isFlatScratchReg(opIdx);
+ }
+
+ bool
+ isExecMaskRegister(int opIdx) override
+ {
+ return isExecMask(opIdx);
+ }
+
+ bool isScalarRegister(int opIdx) override { return false; }
+ bool isVectorRegister(int opIdx) override { return false; }
+ bool isSrcOperand(int opIdx) override { return false; }
+ bool isDstOperand(int opIdx) override { return false; }
+ int getOperandSize(int opIdx) override { return 0; }
+
+ int
+ getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override
+ {
+ return 0;
+ }
+
+ /**
+ * Return the number of tokens needed by the coalescer. In GCN3 there
+ * is generally one packet per memory request per lane generated. In
+ * HSAIL, the number of dest operands is used for loads and src
+ * operands for stores. This method should be overriden on a per-inst
+ * basis when this value differs.
+ */
+ int coalescerTokenCount() const override { return 1; }
+ ScalarRegU32 srcLiteral() const override { return _srcLiteral; }
+
+ protected:
+ void panicUnimplemented() const;
+
+ /**
+ * if the instruction has a src literal - an immediate
+ * value that is part of the instruction stream - we
+ * store that here
+ */
+ ScalarRegU32 _srcLiteral;
+ }; // class GCN3GPUStaticInst
+
+} // namespace Gcn3ISA
+#endif //__ARCH_GCN3_INSTS_GPU_STATIC_INST_HH__
diff --git a/src/arch/gcn3/insts/inst_util.hh b/src/arch/gcn3/insts/inst_util.hh
new file mode 100644
index 0000000..a3b2f4a
--- /dev/null
+++ b/src/arch/gcn3/insts/inst_util.hh
@@ -0,0 +1,888 @@
+/*
+ * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * For use for simulation and test purposes only
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Anthony Gutierrez
+ */
+
+#ifndef __ARCH_GCN3_INSTS_INST_UTIL_HH__
+#define __ARCH_GCN3_INSTS_INST_UTIL_HH__
+
+#include <cmath>
+
+#include "arch/gcn3/registers.hh"
+
+// values for SDWA select operations
+enum SDWASelVals : int
+{
+ SDWA_BYTE_0 = 0, /* select data[7:0] */
+ SDWA_BYTE_1 = 1, /* select data[15:8] */
+ SDWA_BYTE_2 = 2, /* select data[23:16] */
+ SDWA_BYTE_3 = 3, /* select data[31:24] */
+ SDWA_WORD_0 = 4, /* select data[15:0] */
+ SDWA_WORD_1 = 5, /* select data[31:16] */
+ SDWA_DWORD = 6 /* select data[31:0] */
+};
+
+// values for format of destination bits for SDWA operations
+enum SDWADstVals : int
+{
+ SDWA_UNUSED_PAD = 0, /* Pad all unused bits with 0 */
+ SDWA_UNUSED_SEXT = 1, /* Sign-extend upper bits; pad lower bits w/ 0 */
+ SDWA_UNUSED_PRESERVE = 2 /* select data[31:0] */
+};
+
+// values for DPP operations
+enum SqDPPVals : int
+{
+ SQ_DPP_QUAD_PERM_MAX = 0xFF,
+ SQ_DPP_RESERVED = 0x100,
+ SQ_DPP_ROW_SL1 = 0x101,
+ SQ_DPP_ROW_SL15 = 0x10F,
+ SQ_DPP_ROW_SR1 = 0x111,
+ SQ_DPP_ROW_SR15 = 0x11F,
+ SQ_DPP_ROW_RR1 = 0x121,
+ SQ_DPP_ROW_RR15 = 0x12F,
+ SQ_DPP_WF_SL1 = 0x130,
+ SQ_DPP_WF_RL1 = 0x134,
+ SQ_DPP_WF_SR1 = 0x138,
+ SQ_DPP_WF_RR1 = 0x13C,
+ SQ_DPP_ROW_MIRROR = 0x140,
+ SQ_DPP_ROW_HALF_MIRROR = 0x141,
+ SQ_DPP_ROW_BCAST15 = 0x142,
+ SQ_DPP_ROW_BCAST31 = 0x143
+};
+static const int ROW_SIZE = 16; /* 16 registers per row */
+static const int NUM_BANKS = 4; /* 64 registers, 16/bank */
+
+namespace Gcn3ISA
+{
+ template<typename T>
+ inline T
+ wholeQuadMode(T val)
+ {
+ T wqm = 0;
+ T mask = 0xF;
+
+ for (T bits = val; mask != 0; mask <<= 4)
+ if ((bits & mask) != 0)
+ wqm |= mask;
+
+ return wqm;
+ }
+
+ template<typename T>
+ inline T
+ quadMask(T val)
+ {
+ T qmsk = 0;
+ T mask = 0xF;
+ T qbit = 0x1;
+
+ for (T bits = val; mask != 0; mask <<= 4, qbit <<= 1) {
+ if (bits & mask) {
+ qmsk |= qbit;
+ }
+ }
+
+ return qmsk;
+ }
+
+ template<typename T>
+ inline ScalarRegI32
+ countZeroBits(T val)
+ {
+ ScalarRegI32 num_zeros
+ = std::numeric_limits<T>::digits - popCount(val);
+
+ return num_zeros;
+ }
+
+ template<typename T>
+ inline ScalarRegI32
+ findFirstZero(T val)
+ {
+ if (val == ~T(0)) {
+ return -1;
+ }
+
+ return findLsbSet(~val);
+ }
+
+ template<typename T>
+ inline ScalarRegI32
+ findFirstOne(T val)
+ {
+ if (!val) {
+ return -1;
+ }
+
+ return findLsbSet(val);
+ }
+
+ template<typename T>
+ inline ScalarRegI32
+ findFirstOneMsb(T val)
+ {
+ if (!val) {
+ return -1;
+ }
+
+ return findMsbSet(val);
+ }
+
+ template<typename T>
+ inline ScalarRegI32
+ countZeroBitsMsb(T val)
+ {
+ if (!val) {
+ return -1;
+ }
+
+ return std::numeric_limits<T>::digits - 1 - findMsbSet(val);
+ }
+
+ inline ScalarRegI32
+ firstOppositeSignBit(ScalarRegI32 val)
+ {
+ bool found(false);
+ bool sign_bit = (val & 0x80000000) != 0;
+ ScalarRegU32 tmp_val(0);
+ int count(0);
+
+ if (!val || val == -1) {
+ return -1;
+ }
+
+ for (int i = 0; i < std::numeric_limits<ScalarRegU32>::digits; ++i) {
+ tmp_val = val & (0x80000000 >> i);
+
+ if (!sign_bit) {
+ if (tmp_val) {
+ found = true;
+ break;
+ }
+ } else {
+ if (!tmp_val) {
+ found = true;
+ break;
+ }
+ }
+ ++count;
+ }
+
+ if (found) {
+ return count;
+ } else {
+ return -1;
+ }
+ }
+
+ inline ScalarRegI32
+ firstOppositeSignBit(ScalarRegI64 val)
+ {
+ bool found(false);
+ bool sign_bit = (val & 0x8000000000000000ULL) != 0;
+ ScalarRegU64 tmp_val(0);
+ int count(0);
+
+ if (!val || val == -1) {
+ return -1;
+ }
+
+ for (int i = 0; i < std::numeric_limits<ScalarRegU64>::digits; ++i) {
+ tmp_val = val & (0x8000000000000000ULL >> i);
+
+ if (!sign_bit) {
+ if (tmp_val) {
+ found = true;
+ break;
+ }
+ } else {
+ if (!tmp_val) {
+ found = true;
+ break;
+ }
+ }
+ ++count;
+ }
+
+ if (found) {
+ return count;
+ } else {
+ return -1;
+ }
+ }
+
+ template<typename T>
+ inline T
+ median(T val_0, T val_1, T val_2)
+ {
+ if (std::is_floating_point<T>::value) {
+ return std::fmax(std::fmin(val_0, val_1),
+ std::fmin(std::fmax(val_0, val_1), val_2));
+ } else {
+ return std::max(std::min(val_0, val_1),
+ std::min(std::max(val_0, val_1), val_2));
+ }
+ }
+
+ template <typename T>
+ inline T roundNearestEven(T val)
+ {
+ T nearest_round = std::round(val * 0.5) * 2.0;
+ return nearest_round;
+ }
+
+ inline VecElemU32
+ muladd(VecElemU64 &dst, VecElemU32 val_0, VecElemU32 val_1,
+ VecElemU64 val_2)
+ {
+ __uint128_t u0 = (__uint128_t)val_0;
+ __uint128_t u1 = (__uint128_t)val_1;
+ __uint128_t u2 = (__uint128_t)val_2;
+ __uint128_t result = u0 * u1 + u2;
+
+ dst = (VecElemU64)result;
+
+ return (VecElemU32)(result >> 64) ? 1 : 0;
+ }
+
+ inline VecElemU32
+ muladd(VecElemI64 &dst, VecElemI32 val_0, VecElemI32 val_1,
+ VecElemI64 val_2)
+ {
+ __int128_t u0 = (__int128_t)val_0;
+ __int128_t u1 = (__int128_t)val_1;
+ __int128_t u2 = (__int128_t)val_2;
+ __int128_t result = u0 * u1 + u2;
+
+ dst = (VecElemI64)result;
+
+ return (VecElemU32)(result >> 64) ? 1 : 0;
+ }
+
+ /**
+ * dppInstImpl is a helper function that performs the inputted operation
+ * on the inputted vector register lane. The returned output lane
+ * represents the input lane given the destination lane and DPP_CTRL word.
+ *
+ * Currently the values are:
+ * 0x0 - 0xFF: full permute of four threads
+ * 0x100: reserved
+ * 0x101 - 0x10F: row shift right by 1-15 threads
+ * 0x111 - 0x11F: row shift right by 1-15 threads
+ * 0x121 - 0x12F: row shift right by 1-15 threads
+ * 0x130: wavefront left shift by 1 thread
+ * 0x134: wavefront left rotate by 1 thread
+ * 0x138: wavefront right shift by 1 thread
+ * 0x13C: wavefront right rotate by 1 thread
+ * 0x140: mirror threads within row
+ * 0x141: mirror threads within 1/2 row (8 threads)
+ * 0x142: broadcast 15th thread of each row to next row
+ * 0x143: broadcast thread 31 to rows 2 and 3
+ */
+ int dppInstImpl(SqDPPVals dppCtrl, int currLane, int rowNum,
+ int rowOffset, bool & outOfBounds)
+ {
+ // local variables
+ // newLane will be the same as the input lane unless swizzling happens
+ int newLane = currLane;
+ // for shift/rotate permutations; positive values are LEFT rotates
+ int count = 1;
+ int localRowOffset = rowOffset;
+ int localRowNum = rowNum;
+
+ if (dppCtrl <= SQ_DPP_QUAD_PERM_MAX) { // DPP_QUAD_PERM{00:FF}
+ int quadBase = (currLane & ~(3));
+ int quadPix = (currLane & 3);
+ quadPix = ((dppCtrl >> (2 * quadPix)) & 3);
+ newLane = (quadBase | quadPix);
+ } else if (dppCtrl == SQ_DPP_RESERVED) {
+ panic("ERROR: instruction using reserved DPP_CTRL value\n");
+ } else if ((dppCtrl >= SQ_DPP_ROW_SL1) &&
+ (dppCtrl <= SQ_DPP_ROW_SL15)) { // DPP_ROW_SL{1:15}
+ count -= (dppCtrl - SQ_DPP_ROW_SL1 + 1);
+ if ((localRowOffset + count >= 0) &&
+ (localRowOffset + count < ROW_SIZE)) {
+ localRowOffset += count;
+ newLane = (rowNum | localRowOffset);
+ } else {
+ outOfBounds = true;
+ }
+ } else if ((dppCtrl >= SQ_DPP_ROW_SR1) &&
+ (dppCtrl <= SQ_DPP_ROW_SR15)) { // DPP_ROW_SR{1:15}
+ count -= (dppCtrl - SQ_DPP_ROW_SR1 + 1);
+ if ((localRowOffset + count >= 0) &&
+ (localRowOffset + count < ROW_SIZE)) {
+ localRowOffset += count;
+ newLane = (rowNum | localRowOffset);
+ } else {
+ outOfBounds = true;
+ }
+ } else if ((dppCtrl >= SQ_DPP_ROW_RR1) &&
+ (dppCtrl <= SQ_DPP_ROW_RR15)) { // DPP_ROW_RR{1:15}
+ count -= (dppCtrl - SQ_DPP_ROW_RR1 + 1);
+ localRowOffset = (localRowOffset + count + ROW_SIZE) % ROW_SIZE;
+ newLane = (rowNum | localRowOffset);
+ } else if (dppCtrl == SQ_DPP_WF_SL1) { // DPP_WF_SL1
+ count = 1;
+ if ((currLane >= 0) && (currLane < NumVecElemPerVecReg)) {
+ newLane += count;
+ } else {
+ outOfBounds = true;
+ }
+ } else if (dppCtrl == SQ_DPP_WF_RL1) { // DPP_WF_RL1
+ count = 1;
+ newLane = (currLane + count + NumVecElemPerVecReg) %
+ NumVecElemPerVecReg;
+ } else if (dppCtrl == SQ_DPP_WF_SR1) { // DPP_WF_SR1
+ count = -1;
+ int currVal = (currLane + count);
+ if ((currVal >= 0) && (currVal < NumVecElemPerVecReg)) {
+ newLane += count;
+ } else {
+ outOfBounds = true;
+ }
+ } else if (dppCtrl == SQ_DPP_WF_RR1) { // DPP_WF_RR1
+ count = -1;
+ newLane = (currLane + count + NumVecElemPerVecReg) %
+ NumVecElemPerVecReg;
+ } else if (dppCtrl == SQ_DPP_ROW_MIRROR) { // DPP_ROW_MIRROR
+ localRowOffset = (15 - localRowOffset);
+ newLane = (rowNum | localRowOffset);
+ } else if (dppCtrl == SQ_DPP_ROW_HALF_MIRROR) { // DPP_ROW_HALF_MIRROR
+ localRowNum = (currLane & -0x7);
+ localRowOffset = (currLane & 0x7);
+ localRowOffset = (7 - localRowNum);
+ newLane = (localRowNum | localRowOffset);
+ } else if (dppCtrl == SQ_DPP_ROW_BCAST15) { // DPP_ROW_BCAST15
+ count = 15;
+ if (currLane > count) {
+ newLane = (currLane & ~count) - 1;
+ }
+ } else if (dppCtrl == SQ_DPP_ROW_BCAST31) { // DPP_ROW_BCAST31
+ count = 31;
+ if (currLane > count) {
+ newLane = (currLane & ~count) - 1;
+ }
+ } else {
+ panic("Unimplemented DPP control operation: %d\n", dppCtrl);
+ }
+
+ return newLane;
+ }
+
+ /**
+ * processDPP is a helper function for implementing Data Parallel Primitive
+ * instructions. This function may be called by many different VOP1
+ * instructions to do operations within a register.
+ */
+ template<typename T>
+ void processDPP(GPUDynInstPtr gpuDynInst, InFmt_VOP_DPP dppInst,
+ T & src0)
+ {
+ // local variables
+ SqDPPVals dppCtrl = (SqDPPVals)dppInst.DPP_CTRL;
+ int boundCtrl = dppInst.BOUND_CTRL;
+ int bankMask = dppInst.BANK_MASK;
+ int rowMask = dppInst.ROW_MASK;
+ // row, bank info to be calculated per lane
+ int rowNum = 0, bankNum = 0, rowOffset = 0;
+ // outLane will be the same as the input lane unless swizzling happens
+ int outLane = 0;
+ bool laneDisabled = false;
+ // flags used for determining if a lane should be written to/reset/etc.
+ bool outOfBounds = false, zeroSrc = false;
+ long long threadValid = 0;
+
+ /**
+ * STEP 1a: check if the absolute value (ABS) or negation (NEG) tags
+ * are set. If so, do the appropriate action(s) on src0 and/or src1.
+ *
+ * NOTE: ABS takes priority over NEG.
+ */
+ if (dppInst.SRC0_NEG) {
+ src0.negModifier();
+ }
+
+ if (dppInst.SRC0_ABS) {
+ src0.absModifier();
+ }
+
+ // iterate over all register lanes, performing steps 2-4
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ threadValid = (0x1LL << lane);
+ /**
+ * STEP 2: check the row and bank mask values. These determine
+ * which threads are enabled for the subsequent DPP_CTRL
+ * operations.
+ */
+ rowNum = (lane / ROW_SIZE);
+ rowOffset = (lane % ROW_SIZE);
+ bankNum = (rowOffset / NUM_BANKS);
+
+ if (((rowMask & (0x1 << rowNum)) == 0) /* row mask */ ||
+ ((bankMask & (0x1 << bankNum)) == 0) /* bank mask */) {
+ laneDisabled = true;
+ continue;
+ }
+
+ /**
+ * STEP 4: Handle the potential values of DPP_CTRL:
+ * 0x0 - 0xFF: full permute of four threads
+ * 0x100: reserved
+ * 0x101 - 0x10F: row shift right by 1-15 threads
+ * 0x111 - 0x11F: row shift right by 1-15 threads
+ * 0x121 - 0x12F: row shift right by 1-15 threads
+ * 0x130: wavefront left shift by 1 thread
+ * 0x134: wavefront left rotate by 1 thread
+ * 0x138: wavefront right shift by 1 thread
+ * 0x13C: wavefront right rotate by 1 thread
+ * 0x140: mirror threads within row
+ * 0x141: mirror threads within 1/2 row (8 threads)
+ * 0x142: broadcast 15th thread of each row to next row
+ * 0x143: broadcast thread 31 to rows 2 and 3
+ */
+ if (!laneDisabled) {
+ outLane = dppInstImpl(dppCtrl, lane, rowNum, rowOffset,
+ outOfBounds);
+ }
+
+ /**
+ * STEP 4: Implement bound control for disabled threads. If thread
+ * is disabled but boundCtrl is set, then we need to set the source
+ * data to 0 (i.e., set this lane to 0).
+ */
+ if (laneDisabled) {
+ threadValid = 0;
+ } else if (outOfBounds) {
+ if (boundCtrl == 1) {
+ zeroSrc = true;
+ } else {
+ threadValid = 0;
+ }
+ } else if (!gpuDynInst->exec_mask[lane]) {
+ if (boundCtrl == 1) {
+ zeroSrc = true;
+ } else {
+ threadValid = 0;
+ }
+ }
+
+ if (threadValid != 0 && !outOfBounds && !zeroSrc) {
+ assert(!laneDisabled);
+ src0[outLane] = src0[lane];
+ } else if (zeroSrc) {
+ src0[lane] = 0;
+ }
+
+ src0.write();
+ // reset for next iteration
+ laneDisabled = false;
+ }
+ }
+
+ /**
+ * processDPP is a helper function for implementing Data Parallel Primitive
+ * instructions. This function may be called by many different
+ * VOP2/VOPC instructions to do operations within a register.
+ */
+ template<typename T>
+ void processDPP(GPUDynInstPtr gpuDynInst, InFmt_VOP_DPP dppInst,
+ T & src0, T & src1)
+ {
+ /**
+ * STEP 1b: check if the absolute value (ABS) or negation (NEG) tags
+ * are set. If so, do the appropriate action(s) on src0 and/or src1.
+ *
+ * NOTE: ABS takes priority over NEG.
+ */
+ if (dppInst.SRC1_NEG) {
+ src1.negModifier();
+ }
+
+ if (dppInst.SRC1_ABS) {
+ src1.absModifier();
+ }
+
+ // Since only difference for VOP1 and VOP2/VOPC instructions is SRC1,
+ // which is only used for negation/absolute value, call other version
+ // to do everything else.
+ processDPP(gpuDynInst, dppInst, src0);
+ }
+
+ /**
+ * sdwaInstSrcImpl_helper contains the per-lane code for selecting the
+ * appropriate bytes/words of the lane and doing the appropriate
+ * masking/padding/sign extending. It returns the value after these
+ * operations are done on it.
+ */
+ template<typename T>
+ T sdwaInstSrcImpl_helper(T currOperVal, T origOperVal, SDWASelVals sel,
+ bool signExt)
+ {
+ // local variables
+ int first_bit = 0, last_bit = 0;
+ bool signExt_local = signExt;
+ T retVal = 0;
+
+ // if we're preserving all of the bits, then we can immediately return
+ if (sel == SDWA_DWORD) {
+ return currOperVal;
+ }
+
+ if (sel < SDWA_WORD_0) { // we are selecting 1 byte
+ /*
+ Process byte 0 first. This code eiter selects the original bits
+ of byte 0, or makes the bits of the selected byte be byte 0 (and
+ next either sign extends or zero's out upper bits).
+ */
+ first_bit = (sel * Gcn3ISA::BITS_PER_BYTE);
+ last_bit = first_bit + Gcn3ISA::MSB_PER_BYTE;
+ retVal = bits(currOperVal, first_bit, last_bit);
+
+ // make sure update propagated, since used next
+ assert(bits(retVal, Gcn3ISA::MSB_PER_BYTE) ==
+ bits(origOperVal, (sel * Gcn3ISA::BITS_PER_BYTE) +
+ Gcn3ISA::MSB_PER_BYTE));
+ // sign extended value depends on upper-most bit of the new byte 0
+ signExt_local = (signExt &&
+ (bits(retVal, 0, Gcn3ISA::MSB_PER_BYTE) & 0x80));
+
+ // process all other bytes -- if sign extending, make them 1, else
+ // all 0's so leave as is
+ if (signExt_local) {
+ retVal = (uint32_t)sext<Gcn3ISA::MSB_PER_BYTE>(retVal);
+ }
+ } else if (sel < SDWA_DWORD) { // we are selecting 1 word
+ /*
+ Process word 0 first. This code eiter selects the original bits
+ of word 0, or makes the bits of the selected word be word 0 (and
+ next either sign extends or zero's out upper bits).
+ */
+ first_bit = (sel & 1) * Gcn3ISA::BITS_PER_WORD;
+ last_bit = first_bit + Gcn3ISA::MSB_PER_WORD;
+ retVal = bits(currOperVal, first_bit, last_bit);
+
+ // make sure update propagated, since used next
+ assert(bits(retVal, Gcn3ISA::MSB_PER_WORD) ==
+ bits(origOperVal, ((sel & 1) * Gcn3ISA::BITS_PER_WORD) +
+ Gcn3ISA::MSB_PER_WORD));
+ // sign extended value depends on upper-most bit of the new word 0
+ signExt_local = (signExt &&
+ (bits(retVal, 0, Gcn3ISA::MSB_PER_WORD) &
+ 0x8000));
+
+ // process other word -- if sign extending, make them 1, else all
+ // 0's so leave as is
+ if (signExt_local) {
+ retVal = (uint32_t)sext<Gcn3ISA::MSB_PER_WORD>(retVal);
+ }
+ } else {
+ assert(sel != SDWA_DWORD); // should have returned earlier
+ panic("Unimplemented SDWA select operation: %d\n", sel);
+ }
+
+ return retVal;
+ }
+
+
+ /**
+ * sdwaInstSrcImpl is a helper function that selects the appropriate
+ * bits/bytes for each lane of the inputted source operand of an SDWA
+ * instruction, does the appropriate masking/padding/sign extending for the
+ * non-selected bits/bytes, and updates the operands values with the
+ * resultant value.
+ *
+ * The desired behavior is:
+ * 1. Select the appropriate bits/bytes based on sel:
+ * 0 (SDWA_BYTE_0): select data[7:0]
+ * 1 (SDWA_BYTE_1): select data[15:8]
+ * 2 (SDWA_BYTE_2): select data[23:16]
+ * 3 (SDWA_BYTE_3): select data[31:24]
+ * 4 (SDWA_WORD_0): select data[15:0]
+ * 5 (SDWA_WORD_1): select data[31:16]
+ * 6 (SDWA_DWORD): select data[31:0]
+ * 2. if sign extend is set, then sign extend the value
+ */
+ template<typename T>
+ void sdwaInstSrcImpl(T & currOper, T & origCurrOper, SDWASelVals sel,
+ bool signExt)
+ {
+ // iterate over all lanes, setting appropriate, selected value
+ currOper.read();
+ origCurrOper.read();
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ currOper[lane] = sdwaInstSrcImpl_helper(currOper[lane],
+ origCurrOper[lane], sel,
+ signExt);
+ }
+ }
+
+
+ /**
+ * sdwaInstDstImpl_helper contains the per-lane code for selecting the
+ * appropriate bytes/words of the lane and doing the appropriate
+ * masking/padding/sign extending. It returns the value after these
+ * operations are done on it.
+ */
+ template<typename T>
+ T sdwaInstDstImpl_helper(T currDstVal, T origDstVal, bool clamp,
+ SDWASelVals sel, SDWADstVals unusedBits_format)
+ {
+ // local variables
+ int first_bit = 0, last_bit = 0;
+ bool signExt = (unusedBits_format == SDWA_UNUSED_SEXT);
+ //bool pad = (unusedBits_format == SDWA_UNUSED_PAD);
+ bool preserve = (unusedBits_format == SDWA_UNUSED_PRESERVE);
+ T retVal = 0, origBits_thisByte = 0, currBits_thisByte = 0,
+ origBits_thisWord = 0, currBits_thisWord = 0, newBits = 0;
+
+ // if we're preserving all of the bits, then we can immediately return
+ if (unusedBits_format == SDWA_UNUSED_PRESERVE) {
+ assert(sel == SDWA_DWORD);
+ return currDstVal;
+ } else if (sel == SDWA_DWORD) {
+ // NOTE: users may set the unused bits variable to anything in this
+ // scenario, because it will be ignored
+ return currDstVal;
+ }
+
+ if (sel < SDWA_WORD_0) { // we are selecting 1 byte
+ // if we sign extended depends on upper-most bit of byte 0
+ signExt = (signExt &&
+ (bits(currDstVal, 0, Gcn3ISA::MSB_PER_WORD) & 0x80));
+
+ for (int byte = 0; byte < 4; ++byte) {
+ first_bit = byte * Gcn3ISA::BITS_PER_BYTE;
+ last_bit = first_bit + Gcn3ISA::MSB_PER_BYTE;
+ /*
+ Options:
+ 1. byte == sel: we are keeping all bits in this byte
+ 2. preserve is set: keep this byte as is because the
+ output preserve flag is set
+ 3. byte > sel && signExt: we're sign extending and
+ this byte is one of the bytes we need to sign extend
+ */
+ origBits_thisByte = bits(origDstVal, first_bit, last_bit);
+ currBits_thisByte = bits(currDstVal, first_bit, last_bit);
+ newBits = ((byte == sel) ? origBits_thisByte :
+ ((preserve) ? currBits_thisByte :
+ (((byte > sel) && signExt) ? 0xff : 0)));
+ retVal = insertBits(retVal, first_bit, last_bit, newBits);
+ }
+ } else if (sel < SDWA_DWORD) { // we are selecting 1 word
+ first_bit = 0;
+ last_bit = first_bit + Gcn3ISA::MSB_PER_WORD;
+ // if we sign extended depends on upper-most bit of word 0
+ signExt = (signExt &&
+ (bits(currDstVal, first_bit, last_bit) & 0x8000));
+
+ for (int word = 0; word < 2; ++word) {
+ first_bit = word * Gcn3ISA::BITS_PER_WORD;
+ last_bit = first_bit + Gcn3ISA::MSB_PER_WORD;
+ /*
+ Options:
+ 1. word == sel & 1: we are keeping all bits in this word
+ 2. preserve is set: keep this word as is because the
+ output preserve flag is set
+ 3. word > (sel & 1) && signExt: we're sign extending and
+ this word is one of the words we need to sign extend
+ */
+ origBits_thisWord = bits(origDstVal, first_bit, last_bit);
+ currBits_thisWord = bits(currDstVal, first_bit, last_bit);
+ newBits = ((word == (sel & 0x1)) ? origBits_thisWord :
+ ((preserve) ? currBits_thisWord :
+ (((word > (sel & 0x1)) && signExt) ? 0xffff : 0)));
+ retVal = insertBits(retVal, first_bit, last_bit, newBits);
+ }
+ } else {
+ assert(sel != SDWA_DWORD); // should have returned earlier
+ panic("Unimplemented SDWA select operation: %d\n", sel);
+ }
+
+ return retVal;
+ }
+
+
+ /**
+ * sdwaInstDestImpl is a helper function that selects the appropriate
+ * bits/bytes for the inputted dest operand of an SDWA instruction, does
+ * the appropriate masking/padding/sign extending for the non-selected
+ * bits/bytes, and updates the operands values with the resultant value.
+ *
+ * The desired behavior is:
+ * 1. Select the appropriate bits/bytes based on sel:
+ * 0 (SDWA_BYTE_0): select data[7:0]
+ * 1 (SDWA_BYTE_1): select data[15:8]
+ * 2 (SDWA_BYTE_2): select data[23:16]
+ * 3 (SDWA_BYTE_3): select data[31:24]
+ * 4 (SDWA_WORD_0): select data[15:0]
+ * 5 (SDWA_WORD_1): select data[31:16]
+ * 6 (SDWA_DWORD): select data[31:0]
+ * 2. either pad, sign extend, or select all bits based on the value of
+ * unusedBits_format:
+ * 0 (SDWA_UNUSED_PAD): pad all unused bits with 0
+ * 1 (SDWA_UNUSED_SEXT): sign-extend upper bits; pad lower bits w/ 0
+ * 2 (SDWA_UNUSED_PRESERVE): select data[31:0]
+ */
+ template<typename T>
+ void sdwaInstDstImpl(T & dstOper, T & origDstOper, bool clamp,
+ SDWASelVals sel, SDWADstVals unusedBits_format)
+ {
+ // iterate over all lanes, setting appropriate, selected value
+ dstOper.read();
+ origDstOper.read();
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ dstOper[lane] = sdwaInstDstImpl_helper(dstOper[lane],
+ origDstOper[lane], clamp,
+ sel, unusedBits_format);
+ }
+ }
+
+
+ /**
+ * processSDWA_srcHelper is a helper function for implementing sub d-word
+ * addressing instructions for the src operands. This function may be
+ * called by many different VOP1/VOP2/VOPC instructions to do operations
+ * within a register. This function is also agnostic of which operand it
+ * is operating on, so that it can be called for any src operand.
+ */
+ template<typename T>
+ void processSDWA_src_helper(T & currSrc, T & origCurrSrc,
+ SDWASelVals src_sel, bool src_signExt,
+ bool src_abs, bool src_neg)
+ {
+ /**
+ * STEP 1: check if the absolute value (ABS) or negation (NEG) tags
+ * are set. If so, do the appropriate action(s) on the src operand.
+ *
+ * NOTE: According to the CSim implementation, ABS takes priority over
+ * NEG.
+ */
+ if (src_neg) {
+ currSrc.negModifier();
+ }
+
+ if (src_abs) {
+ currSrc.absModifier();
+ }
+
+ /**
+ * STEP 2: select the appropriate bits for each lane of source operand.
+ */
+ sdwaInstSrcImpl(currSrc, origCurrSrc, src_sel, src_signExt);
+ }
+
+
+ /**
+ * processSDWA_src is a helper function for implementing sub d-word
+ * addressing instructions for the src operands. This function may be
+ * called by many different VOP1 instructions to do operations within a
+ * register. processSDWA_dst is called after the math, while
+ * processSDWA_src is called before the math.
+ */
+ template<typename T>
+ void processSDWA_src(GPUDynInstPtr gpuDynInst, InFmt_VOP_SDWA sdwaInst,
+ T & src0, T & origSrc0)
+ {
+ // local variables
+ SDWASelVals src0_sel = (SDWASelVals)sdwaInst.SRC0_SEL;
+ bool src0_signExt = sdwaInst.SRC0_SEXT;
+ bool src0_neg = sdwaInst.SRC0_NEG;
+ bool src0_abs = sdwaInst.SRC0_ABS;
+
+ // NOTE: difference between VOP1 and VOP2/VOPC is that there is no src1
+ // operand. So ensure that SRC1 fields are not set, then call helper
+ // function only on src0.
+ assert(!sdwaInst.SRC1_SEXT);
+ assert(!sdwaInst.SRC1_NEG);
+ assert(!sdwaInst.SRC1_ABS);
+
+ processSDWA_src_helper(src0, origSrc0, src0_sel, src0_signExt,
+ src0_abs, src0_neg);
+ }
+
+
+ /**
+ * processSDWA_src is a helper function for implementing sub d-word
+ * addressing instructions. This function may be called by many different
+ * VOP2/VOPC instructions to do operations within a register.
+ * processSDWA_dst is called after the math, while processSDWA_src is
+ * called before the math.
+ */
+ template<typename T>
+ void processSDWA_src(GPUDynInstPtr gpuDynInst, InFmt_VOP_SDWA sdwaInst,
+ T & src0, T & origSrc0, T & src1, T & origSrc1)
+ {
+ // local variables
+ SDWASelVals src0_sel = (SDWASelVals)sdwaInst.SRC0_SEL;
+ bool src0_signExt = sdwaInst.SRC0_SEXT;
+ bool src0_neg = sdwaInst.SRC0_NEG;
+ bool src0_abs = sdwaInst.SRC0_ABS;
+ SDWASelVals src1_sel = (SDWASelVals)sdwaInst.SRC1_SEL;
+ bool src1_signExt = sdwaInst.SRC1_SEXT;
+ bool src1_neg = sdwaInst.SRC1_NEG;
+ bool src1_abs = sdwaInst.SRC1_ABS;
+
+ processSDWA_src_helper(src0, origSrc0, src0_sel, src0_signExt,
+ src0_abs, src0_neg);
+ processSDWA_src_helper(src1, origSrc1, src1_sel, src1_signExt,
+ src1_abs, src1_neg);
+ }
+
+
+ /**
+ * processSDWA_dst is a helper function for implementing sub d-word
+ * addressing instructions for the dst operand. This function may be
+ * called by many different VOP1/VOP2/VOPC instructions to do operations
+ * within a register. processSDWA_dst is called after the math, while
+ * processSDWA_src is called before the math.
+ */
+ template<typename T>
+ void processSDWA_dst(GPUDynInstPtr gpuDynInst, InFmt_VOP_SDWA sdwaInst,
+ T & dst, T & origDst)
+ {
+ // local variables
+ SDWADstVals dst_unusedBits_format = (SDWADstVals)sdwaInst.DST_UNUSED;
+ SDWASelVals dst_sel = (SDWASelVals)sdwaInst.DST_SEL;
+ bool clamp = sdwaInst.CLAMP;
+
+ /**
+ * STEP 1: select the appropriate bits for dst and pad/sign-extend as
+ * appropriate.
+ */
+ sdwaInstDstImpl(dst, origDst, clamp, dst_sel, dst_unusedBits_format);
+ }
+} // namespace Gcn3ISA
+
+#endif // __ARCH_GCN3_INSTS_INST_UTIL_HH__
diff --git a/src/arch/gcn3/insts/instructions.cc b/src/arch/gcn3/insts/instructions.cc
new file mode 100644
index 0000000..88095e7
--- /dev/null
+++ b/src/arch/gcn3/insts/instructions.cc
@@ -0,0 +1,39996 @@
+/*
+ * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * For use for simulation and test purposes only
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Anthony Gutierrez
+ */
+
+#include "arch/gcn3/insts/instructions.hh"
+
+#include <cmath>
+
+#include "arch/gcn3/insts/inst_util.hh"
+#include "debug/GCN3.hh"
+#include "gpu-compute/shader.hh"
+
+namespace Gcn3ISA
+{
+
+ Inst_SOP2__S_ADD_U32::Inst_SOP2__S_ADD_U32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_add_u32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_ADD_U32
+
+ Inst_SOP2__S_ADD_U32::~Inst_SOP2__S_ADD_U32()
+ {
+ } // ~Inst_SOP2__S_ADD_U32
+
+ // D.u = S0.u + S1.u;
+ // SCC = (S0.u + S1.u >= 0x100000000ULL ? 1 : 0) is an unsigned
+ // overflow/carry-out.
+ void
+ Inst_SOP2__S_ADD_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = src0.rawData() + src1.rawData();
+ scc = ((ScalarRegU64)src0.rawData() + (ScalarRegU64)src1.rawData())
+ >= 0x100000000ULL ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_SUB_U32::Inst_SOP2__S_SUB_U32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_sub_u32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_SUB_U32
+
+ Inst_SOP2__S_SUB_U32::~Inst_SOP2__S_SUB_U32()
+ {
+ } // ~Inst_SOP2__S_SUB_U32
+
+ // D.u = S0.u - S1.u;
+ // SCC = (S1.u > S0.u ? 1 : 0) is an unsigned overflow or carry-out.
+ void
+ Inst_SOP2__S_SUB_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = src0.rawData() - src1.rawData();
+ scc = (src1.rawData() > src0.rawData()) ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_ADD_I32::Inst_SOP2__S_ADD_I32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_add_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_ADD_I32
+
+ Inst_SOP2__S_ADD_I32::~Inst_SOP2__S_ADD_I32()
+ {
+ } // ~Inst_SOP2__S_ADD_I32
+
+ // D.i = S0.i + S1.i;
+ // SCC = (S0.u[31] == S1.u[31] && S0.u[31] != D.u[31]) is a signed
+ // overflow.
+ void
+ Inst_SOP2__S_ADD_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandI32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = src0.rawData() + src1.rawData();
+ scc = (bits(src0.rawData(), 31) == bits(src1.rawData(), 31)
+ && bits(src0.rawData(), 31) != bits(sdst.rawData(), 31))
+ ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_SUB_I32::Inst_SOP2__S_SUB_I32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_sub_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_SUB_I32
+
+ Inst_SOP2__S_SUB_I32::~Inst_SOP2__S_SUB_I32()
+ {
+ } // ~Inst_SOP2__S_SUB_I32
+
+ // D.i = S0.i - S1.i;
+ // SCC = (S0.u[31] != S1.u[31] && S0.u[31] != D.u[31]) is a signed
+ // overflow.
+ void
+ Inst_SOP2__S_SUB_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandI32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = src0.rawData() - src1.rawData();
+ scc = (bits(src0.rawData(), 31) != bits(src1.rawData(), 31)
+ && bits(src0.rawData(), 31) != bits(sdst.rawData(), 31)) ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_ADDC_U32::Inst_SOP2__S_ADDC_U32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_addc_u32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_ADDC_U32
+
+ Inst_SOP2__S_ADDC_U32::~Inst_SOP2__S_ADDC_U32()
+ {
+ } // ~Inst_SOP2__S_ADDC_U32
+
+ // D.u = S0.u + S1.u + SCC;
+ // SCC = (S0.u + S1.u + SCC >= 0x100000000ULL ? 1 : 0) is an unsigned
+ // overflow.
+ void
+ Inst_SOP2__S_ADDC_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+ scc.read();
+
+ sdst = src0.rawData() + src1.rawData() + scc.rawData();
+ scc = ((ScalarRegU64)src0.rawData() + (ScalarRegU64)src1.rawData()
+ + (ScalarRegU64)scc.rawData()) >= 0x100000000ULL ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_SUBB_U32::Inst_SOP2__S_SUBB_U32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_subb_u32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_SUBB_U32
+
+ Inst_SOP2__S_SUBB_U32::~Inst_SOP2__S_SUBB_U32()
+ {
+ } // ~Inst_SOP2__S_SUBB_U32
+
+ // D.u = S0.u - S1.u - SCC;
+ // SCC = (S1.u + SCC > S0.u ? 1 : 0) is an unsigned overflow.
+ void
+ Inst_SOP2__S_SUBB_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+ scc.read();
+
+ sdst = src0.rawData() - src1.rawData() - scc.rawData();
+ scc = (src1.rawData() + scc.rawData()) > src0.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_MIN_I32::Inst_SOP2__S_MIN_I32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_min_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_MIN_I32
+
+ Inst_SOP2__S_MIN_I32::~Inst_SOP2__S_MIN_I32()
+ {
+ } // ~Inst_SOP2__S_MIN_I32
+
+ // D.i = (S0.i < S1.i) ? S0.i : S1.i;
+ // SCC = 1 if S0 is chosen as the minimum value.
+ void
+ Inst_SOP2__S_MIN_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandI32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = std::min(src0.rawData(), src1.rawData());
+ scc = (src0.rawData() < src1.rawData()) ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_MIN_U32::Inst_SOP2__S_MIN_U32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_min_u32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_MIN_U32
+
+ Inst_SOP2__S_MIN_U32::~Inst_SOP2__S_MIN_U32()
+ {
+ } // ~Inst_SOP2__S_MIN_U32
+
+ // D.u = (S0.u < S1.u) ? S0.u : S1.u;
+ // SCC = 1 if S0 is chosen as the minimum value.
+ void
+ Inst_SOP2__S_MIN_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = std::min(src0.rawData(), src1.rawData());
+ scc = (src0.rawData() < src1.rawData()) ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_MAX_I32::Inst_SOP2__S_MAX_I32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_max_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_MAX_I32
+
+ Inst_SOP2__S_MAX_I32::~Inst_SOP2__S_MAX_I32()
+ {
+ } // ~Inst_SOP2__S_MAX_I32
+
+ // D.i = (S0.i > S1.i) ? S0.i : S1.i;
+ // SCC = 1 if S0 is chosen as the maximum value.
+ void
+ Inst_SOP2__S_MAX_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandI32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = std::max(src0.rawData(), src1.rawData());
+ scc = (src0.rawData() > src1.rawData()) ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_MAX_U32::Inst_SOP2__S_MAX_U32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_max_u32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_MAX_U32
+
+ Inst_SOP2__S_MAX_U32::~Inst_SOP2__S_MAX_U32()
+ {
+ } // ~Inst_SOP2__S_MAX_U32
+
+ // D.u = (S0.u > S1.u) ? S0.u : S1.u;
+ // SCC = 1 if S0 is chosen as the maximum value.
+ void
+ Inst_SOP2__S_MAX_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = std::max(src0.rawData(), src1.rawData());
+ scc = (src0.rawData() > src1.rawData()) ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_CSELECT_B32::Inst_SOP2__S_CSELECT_B32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_cselect_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_CSELECT_B32
+
+ Inst_SOP2__S_CSELECT_B32::~Inst_SOP2__S_CSELECT_B32()
+ {
+ } // ~Inst_SOP2__S_CSELECT_B32
+
+ // D.u = SCC ? S0.u : S1.u (conditional select).
+ void
+ Inst_SOP2__S_CSELECT_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+ ConstScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+ scc.read();
+
+ sdst = scc.rawData() ? src0.rawData() : src1.rawData();
+
+ sdst.write();
+ }
+
+ Inst_SOP2__S_CSELECT_B64::Inst_SOP2__S_CSELECT_B64(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_cselect_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_CSELECT_B64
+
+ Inst_SOP2__S_CSELECT_B64::~Inst_SOP2__S_CSELECT_B64()
+ {
+ } // ~Inst_SOP2__S_CSELECT_B64
+
+ // D.u64 = SCC ? S0.u64 : S1.u64 (conditional select).
+ void
+ Inst_SOP2__S_CSELECT_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU64 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ConstScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+ scc.read();
+
+ sdst = scc.rawData() ? src0.rawData() : src1.rawData();
+
+ sdst.write();
+ }
+
+ Inst_SOP2__S_AND_B32::Inst_SOP2__S_AND_B32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_and_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_AND_B32
+
+ Inst_SOP2__S_AND_B32::~Inst_SOP2__S_AND_B32()
+ {
+ } // ~Inst_SOP2__S_AND_B32
+
+ // D.u = S0.u & S1.u;
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP2__S_AND_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = src0.rawData() & src1.rawData();
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_AND_B64::Inst_SOP2__S_AND_B64(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_and_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_AND_B64
+
+ Inst_SOP2__S_AND_B64::~Inst_SOP2__S_AND_B64()
+ {
+ } // ~Inst_SOP2__S_AND_B64
+
+ // D.u64 = S0.u64 & S1.u64;
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP2__S_AND_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU64 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = src0.rawData() & src1.rawData();
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_OR_B32::Inst_SOP2__S_OR_B32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_or_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_OR_B32
+
+ Inst_SOP2__S_OR_B32::~Inst_SOP2__S_OR_B32()
+ {
+ } // ~Inst_SOP2__S_OR_B32
+
+ // D.u = S0.u | S1.u;
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP2__S_OR_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = src0.rawData() | src1.rawData();
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_OR_B64::Inst_SOP2__S_OR_B64(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_or_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_OR_B64
+
+ Inst_SOP2__S_OR_B64::~Inst_SOP2__S_OR_B64()
+ {
+ } // ~Inst_SOP2__S_OR_B64
+
+ // D.u64 = S0.u64 | S1.u64;
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP2__S_OR_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU64 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = src0.rawData() | src1.rawData();
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_XOR_B32::Inst_SOP2__S_XOR_B32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_xor_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_XOR_B32
+
+ Inst_SOP2__S_XOR_B32::~Inst_SOP2__S_XOR_B32()
+ {
+ } // ~Inst_SOP2__S_XOR_B32
+
+ // D.u = S0.u ^ S1.u;
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP2__S_XOR_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = src0.rawData() ^ src1.rawData();
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_XOR_B64::Inst_SOP2__S_XOR_B64(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_xor_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_XOR_B64
+
+ Inst_SOP2__S_XOR_B64::~Inst_SOP2__S_XOR_B64()
+ {
+ } // ~Inst_SOP2__S_XOR_B64
+
+ // D.u64 = S0.u64 ^ S1.u64;
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP2__S_XOR_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU64 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = src0.rawData() ^ src1.rawData();
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_ANDN2_B32::Inst_SOP2__S_ANDN2_B32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_andn2_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_ANDN2_B32
+
+ Inst_SOP2__S_ANDN2_B32::~Inst_SOP2__S_ANDN2_B32()
+ {
+ } // ~Inst_SOP2__S_ANDN2_B32
+
+ // D.u = S0.u & ~S1.u;
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP2__S_ANDN2_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = src0.rawData() &~ src1.rawData();
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_ANDN2_B64::Inst_SOP2__S_ANDN2_B64(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_andn2_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_ANDN2_B64
+
+ Inst_SOP2__S_ANDN2_B64::~Inst_SOP2__S_ANDN2_B64()
+ {
+ } // ~Inst_SOP2__S_ANDN2_B64
+
+ // D.u64 = S0.u64 & ~S1.u64;
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP2__S_ANDN2_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU64 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = src0.rawData() &~ src1.rawData();
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_ORN2_B32::Inst_SOP2__S_ORN2_B32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_orn2_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_ORN2_B32
+
+ Inst_SOP2__S_ORN2_B32::~Inst_SOP2__S_ORN2_B32()
+ {
+ } // ~Inst_SOP2__S_ORN2_B32
+
+ // D.u = S0.u | ~S1.u;
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP2__S_ORN2_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = src0.rawData() |~ src1.rawData();
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_ORN2_B64::Inst_SOP2__S_ORN2_B64(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_orn2_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_ORN2_B64
+
+ Inst_SOP2__S_ORN2_B64::~Inst_SOP2__S_ORN2_B64()
+ {
+ } // ~Inst_SOP2__S_ORN2_B64
+
+ // D.u64 = S0.u64 | ~S1.u64;
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP2__S_ORN2_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU64 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = src0.rawData() |~ src1.rawData();
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_NAND_B32::Inst_SOP2__S_NAND_B32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_nand_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_NAND_B32
+
+ Inst_SOP2__S_NAND_B32::~Inst_SOP2__S_NAND_B32()
+ {
+ } // ~Inst_SOP2__S_NAND_B32
+
+ // D.u = ~(S0.u & S1.u);
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP2__S_NAND_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = ~(src0.rawData() & src1.rawData());
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_NAND_B64::Inst_SOP2__S_NAND_B64(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_nand_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_NAND_B64
+
+ Inst_SOP2__S_NAND_B64::~Inst_SOP2__S_NAND_B64()
+ {
+ } // ~Inst_SOP2__S_NAND_B64
+
+ // D.u64 = ~(S0.u64 & S1.u64);
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP2__S_NAND_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU64 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = ~(src0.rawData() & src1.rawData());
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_NOR_B32::Inst_SOP2__S_NOR_B32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_nor_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_NOR_B32
+
+ Inst_SOP2__S_NOR_B32::~Inst_SOP2__S_NOR_B32()
+ {
+ } // ~Inst_SOP2__S_NOR_B32
+
+ // D.u = ~(S0.u | S1.u);
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP2__S_NOR_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = ~(src0.rawData() | src1.rawData());
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_NOR_B64::Inst_SOP2__S_NOR_B64(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_nor_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_NOR_B64
+
+ Inst_SOP2__S_NOR_B64::~Inst_SOP2__S_NOR_B64()
+ {
+ } // ~Inst_SOP2__S_NOR_B64
+
+ // D.u64 = ~(S0.u64 | S1.u64);
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP2__S_NOR_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU64 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = ~(src0.rawData() | src1.rawData());
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_XNOR_B32::Inst_SOP2__S_XNOR_B32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_xnor_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_XNOR_B32
+
+ Inst_SOP2__S_XNOR_B32::~Inst_SOP2__S_XNOR_B32()
+ {
+ } // ~Inst_SOP2__S_XNOR_B32
+
+ // D.u = ~(S0.u ^ S1.u);
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP2__S_XNOR_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = ~(src0.rawData() ^ src1.rawData());
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_XNOR_B64::Inst_SOP2__S_XNOR_B64(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_xnor_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_XNOR_B64
+
+ Inst_SOP2__S_XNOR_B64::~Inst_SOP2__S_XNOR_B64()
+ {
+ } // ~Inst_SOP2__S_XNOR_B64
+
+ // D.u64 = ~(S0.u64 ^ S1.u64);
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP2__S_XNOR_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU64 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = ~(src0.rawData() ^ src1.rawData());
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_LSHL_B32::Inst_SOP2__S_LSHL_B32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_lshl_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_LSHL_B32
+
+ Inst_SOP2__S_LSHL_B32::~Inst_SOP2__S_LSHL_B32()
+ {
+ } // ~Inst_SOP2__S_LSHL_B32
+
+ // D.u = S0.u << S1.u[4:0];
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP2__S_LSHL_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = (src0.rawData() << bits(src1.rawData(), 4, 0));
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_LSHL_B64::Inst_SOP2__S_LSHL_B64(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_lshl_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_LSHL_B64
+
+ Inst_SOP2__S_LSHL_B64::~Inst_SOP2__S_LSHL_B64()
+ {
+ } // ~Inst_SOP2__S_LSHL_B64
+
+ // D.u64 = S0.u64 << S1.u[5:0];
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP2__S_LSHL_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = (src0.rawData() << bits(src1.rawData(), 5, 0));
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_LSHR_B32::Inst_SOP2__S_LSHR_B32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_lshr_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_LSHR_B32
+
+ Inst_SOP2__S_LSHR_B32::~Inst_SOP2__S_LSHR_B32()
+ {
+ } // ~Inst_SOP2__S_LSHR_B32
+
+ // D.u = S0.u >> S1.u[4:0];
+ // SCC = 1 if result is non-zero.
+ // The vacated bits are set to zero.
+ void
+ Inst_SOP2__S_LSHR_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = (src0.rawData() >> bits(src1.rawData(), 4, 0));
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_LSHR_B64::Inst_SOP2__S_LSHR_B64(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_lshr_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_LSHR_B64
+
+ Inst_SOP2__S_LSHR_B64::~Inst_SOP2__S_LSHR_B64()
+ {
+ } // ~Inst_SOP2__S_LSHR_B64
+
+ // D.u64 = S0.u64 >> S1.u[5:0];
+ // SCC = 1 if result is non-zero.
+ // The vacated bits are set to zero.
+ void
+ Inst_SOP2__S_LSHR_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = (src0.rawData() >> bits(src1.rawData(), 5, 0));
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_ASHR_I32::Inst_SOP2__S_ASHR_I32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_ashr_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_ASHR_I32
+
+ Inst_SOP2__S_ASHR_I32::~Inst_SOP2__S_ASHR_I32()
+ {
+ } // ~Inst_SOP2__S_ASHR_I32
+
+ // D.i = signext(S0.i) >> S1.u[4:0];
+ // SCC = 1 if result is non-zero.
+ // The vacated bits are set to the sign bit of the input value.
+ void
+ Inst_SOP2__S_ASHR_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = (src0.rawData() >> bits(src1.rawData(), 4, 0));
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_ASHR_I64::Inst_SOP2__S_ASHR_I64(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_ashr_i64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_ASHR_I64
+
+ Inst_SOP2__S_ASHR_I64::~Inst_SOP2__S_ASHR_I64()
+ {
+ } // ~Inst_SOP2__S_ASHR_I64
+
+ // D.i64 = signext(S0.i64) >> S1.u[5:0];
+ // SCC = 1 if result is non-zero.
+ // The vacated bits are set to the sign bit of the input value.
+ void
+ Inst_SOP2__S_ASHR_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI64 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandI64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = (src0.rawData() >> bits(src1.rawData(), 5, 0));
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_BFM_B32::Inst_SOP2__S_BFM_B32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_bfm_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_BFM_B32
+
+ Inst_SOP2__S_BFM_B32::~Inst_SOP2__S_BFM_B32()
+ {
+ } // ~Inst_SOP2__S_BFM_B32
+
+ // D.u = ((1 << S0.u[4:0]) - 1) << S1.u[4:0] (bitfield mask).
+ void
+ Inst_SOP2__S_BFM_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+
+ src0.read();
+ src1.read();
+
+ sdst = ((1 << bits(src0.rawData(), 4, 0)) - 1)
+ << bits(src1.rawData(), 4, 0);
+
+ sdst.write();
+ }
+
+ Inst_SOP2__S_BFM_B64::Inst_SOP2__S_BFM_B64(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_bfm_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_BFM_B64
+
+ Inst_SOP2__S_BFM_B64::~Inst_SOP2__S_BFM_B64()
+ {
+ } // ~Inst_SOP2__S_BFM_B64
+
+ // D.u64 = ((1ULL << S0.u[5:0]) - 1) << S1.u[5:0] (bitfield mask).
+ void
+ Inst_SOP2__S_BFM_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+
+ src0.read();
+ src1.read();
+
+ sdst = ((1ULL << bits(src0.rawData(), 5, 0)) - 1)
+ << bits(src1.rawData(), 5, 0);
+
+ sdst.write();
+ }
+
+ Inst_SOP2__S_MUL_I32::Inst_SOP2__S_MUL_I32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_mul_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_MUL_I32
+
+ Inst_SOP2__S_MUL_I32::~Inst_SOP2__S_MUL_I32()
+ {
+ } // ~Inst_SOP2__S_MUL_I32
+
+ // D.i = S0.i * S1.i.
+ void
+ Inst_SOP2__S_MUL_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandI32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+
+ src0.read();
+ src1.read();
+
+ sdst = src0.rawData() * src1.rawData();
+
+ sdst.write();
+ }
+
+ Inst_SOP2__S_BFE_U32::Inst_SOP2__S_BFE_U32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_bfe_u32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_BFE_U32
+
+ Inst_SOP2__S_BFE_U32::~Inst_SOP2__S_BFE_U32()
+ {
+ } // ~Inst_SOP2__S_BFE_U32
+
+ // Bit field extract. S0 is Data, S1[4:0] is field offset, S1[22:16] is
+ // field width.
+ // D.u = (S0.u >> S1.u[4:0]) & ((1 << S1.u[22:16]) - 1);
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP2__S_BFE_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = (src0.rawData() >> bits(src1.rawData(), 4, 0))
+ & ((1 << bits(src1.rawData(), 22, 16)) - 1);
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_BFE_I32::Inst_SOP2__S_BFE_I32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_bfe_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_BFE_I32
+
+ Inst_SOP2__S_BFE_I32::~Inst_SOP2__S_BFE_I32()
+ {
+ } // ~Inst_SOP2__S_BFE_I32
+
+ // Bit field extract. S0 is Data, S1[4:0] is field offset, S1[22:16] is
+ // field width.
+ // D.i = (S0.i >> S1.u[4:0]) & ((1 << S1.u[22:16]) - 1);
+ // Sign-extend the result;
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP2__S_BFE_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = (src0.rawData() >> bits(src1.rawData(), 4, 0))
+ & ((1 << bits(src1.rawData(), 22, 16)) - 1);
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_BFE_U64::Inst_SOP2__S_BFE_U64(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_bfe_u64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_BFE_U64
+
+ Inst_SOP2__S_BFE_U64::~Inst_SOP2__S_BFE_U64()
+ {
+ } // ~Inst_SOP2__S_BFE_U64
+
+ // Bit field extract. S0 is Data, S1[5:0] is field offset, S1[22:16] is
+ // field width.
+ // D.u64 = (S0.u64 >> S1.u[5:0]) & ((1 << S1.u[22:16]) - 1);
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP2__S_BFE_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = (src0.rawData() >> bits(src1.rawData(), 5, 0))
+ & ((1 << bits(src1.rawData(), 22, 16)) - 1);
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_BFE_I64::Inst_SOP2__S_BFE_I64(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_bfe_i64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_BFE_I64
+
+ Inst_SOP2__S_BFE_I64::~Inst_SOP2__S_BFE_I64()
+ {
+ } // ~Inst_SOP2__S_BFE_I64
+
+ // Bit field extract. S0 is Data, S1[5:0] is field offset, S1[22:16] is
+ // field width.
+ // D.i64 = (S0.i64 >> S1.u[5:0]) & ((1 << S1.u[22:16]) - 1);
+ // Sign-extend result;
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP2__S_BFE_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI64 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandI64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ sdst = (src0.rawData() >> bits(src1.rawData(), 5, 0))
+ & ((1 << bits(src1.rawData(), 22, 16)) - 1);
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_CBRANCH_G_FORK::Inst_SOP2__S_CBRANCH_G_FORK(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_cbranch_g_fork")
+ {
+ setFlag(Branch);
+ } // Inst_SOP2__S_CBRANCH_G_FORK
+
+ Inst_SOP2__S_CBRANCH_G_FORK::~Inst_SOP2__S_CBRANCH_G_FORK()
+ {
+ } // ~Inst_SOP2__S_CBRANCH_G_FORK
+
+ // Conditional branch using branch-stack.
+ // S0 = compare mask(vcc or any sgpr) and
+ // S1 = 64-bit byte address of target instruction.
+ void
+ Inst_SOP2__S_CBRANCH_G_FORK::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOP2__S_ABSDIFF_I32::Inst_SOP2__S_ABSDIFF_I32(InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_absdiff_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP2__S_ABSDIFF_I32
+
+ Inst_SOP2__S_ABSDIFF_I32::~Inst_SOP2__S_ABSDIFF_I32()
+ {
+ } // ~Inst_SOP2__S_ABSDIFF_I32
+
+ // D.i = S0.i - S1.i;
+ // if (D.i < 0) then D.i = -D.i;
+ // SCC = 1 if result is non-zero.
+ // Compute the absolute value of difference between two values.
+ void
+ Inst_SOP2__S_ABSDIFF_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandI32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ sdst = std::abs(src0.rawData() - src1.rawData());
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP2__S_RFE_RESTORE_B64::Inst_SOP2__S_RFE_RESTORE_B64(
+ InFmt_SOP2 *iFmt)
+ : Inst_SOP2(iFmt, "s_rfe_restore_b64")
+ {
+ } // Inst_SOP2__S_RFE_RESTORE_B64
+
+ Inst_SOP2__S_RFE_RESTORE_B64::~Inst_SOP2__S_RFE_RESTORE_B64()
+ {
+ } // ~Inst_SOP2__S_RFE_RESTORE_B64
+
+ // Return from exception handler and continue.
+ void
+ Inst_SOP2__S_RFE_RESTORE_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPK__S_MOVK_I32::Inst_SOPK__S_MOVK_I32(InFmt_SOPK *iFmt)
+ : Inst_SOPK(iFmt, "s_movk_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPK__S_MOVK_I32
+
+ Inst_SOPK__S_MOVK_I32::~Inst_SOPK__S_MOVK_I32()
+ {
+ } // ~Inst_SOPK__S_MOVK_I32
+
+ // D.i = signext(SIMM16) (sign extension).
+ void
+ Inst_SOPK__S_MOVK_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16;
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+
+ sdst = simm16;
+
+ sdst.write();
+ }
+
+ Inst_SOPK__S_CMOVK_I32::Inst_SOPK__S_CMOVK_I32(InFmt_SOPK *iFmt)
+ : Inst_SOPK(iFmt, "s_cmovk_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPK__S_CMOVK_I32
+
+ Inst_SOPK__S_CMOVK_I32::~Inst_SOPK__S_CMOVK_I32()
+ {
+ } // ~Inst_SOPK__S_CMOVK_I32
+
+ // if (SCC) then D.i = signext(SIMM16);
+ // else NOP.
+ // Conditional move with sign extension.
+ void
+ Inst_SOPK__S_CMOVK_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16;
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+ ConstScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ scc.read();
+
+ if (scc.rawData()) {
+ sdst = simm16;
+ sdst.write();
+ }
+ }
+
+ Inst_SOPK__S_CMPK_EQ_I32::Inst_SOPK__S_CMPK_EQ_I32(InFmt_SOPK *iFmt)
+ : Inst_SOPK(iFmt, "s_cmpk_eq_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPK__S_CMPK_EQ_I32
+
+ Inst_SOPK__S_CMPK_EQ_I32::~Inst_SOPK__S_CMPK_EQ_I32()
+ {
+ } // ~Inst_SOPK__S_CMPK_EQ_I32
+
+ // SCC = (S0.i == signext(SIMM16)).
+ void
+ Inst_SOPK__S_CMPK_EQ_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16;
+ ConstScalarOperandI32 src(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ scc = (src.rawData() == simm16) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPK__S_CMPK_LG_I32::Inst_SOPK__S_CMPK_LG_I32(InFmt_SOPK *iFmt)
+ : Inst_SOPK(iFmt, "s_cmpk_lg_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPK__S_CMPK_LG_I32
+
+ Inst_SOPK__S_CMPK_LG_I32::~Inst_SOPK__S_CMPK_LG_I32()
+ {
+ } // ~Inst_SOPK__S_CMPK_LG_I32
+
+ // SCC = (S0.i != signext(SIMM16)).
+ void
+ Inst_SOPK__S_CMPK_LG_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16;
+ ConstScalarOperandI32 src(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ scc = (src.rawData() != simm16) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPK__S_CMPK_GT_I32::Inst_SOPK__S_CMPK_GT_I32(InFmt_SOPK *iFmt)
+ : Inst_SOPK(iFmt, "s_cmpk_gt_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPK__S_CMPK_GT_I32
+
+ Inst_SOPK__S_CMPK_GT_I32::~Inst_SOPK__S_CMPK_GT_I32()
+ {
+ } // ~Inst_SOPK__S_CMPK_GT_I32
+
+ // SCC = (S0.i > signext(SIMM16)).
+ void
+ Inst_SOPK__S_CMPK_GT_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16;
+ ConstScalarOperandI32 src(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ scc = (src.rawData() > simm16) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPK__S_CMPK_GE_I32::Inst_SOPK__S_CMPK_GE_I32(InFmt_SOPK *iFmt)
+ : Inst_SOPK(iFmt, "s_cmpk_ge_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPK__S_CMPK_GE_I32
+
+ Inst_SOPK__S_CMPK_GE_I32::~Inst_SOPK__S_CMPK_GE_I32()
+ {
+ } // ~Inst_SOPK__S_CMPK_GE_I32
+
+ // SCC = (S0.i >= signext(SIMM16)).
+ void
+ Inst_SOPK__S_CMPK_GE_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16;
+ ConstScalarOperandI32 src(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ scc = (src.rawData() >= simm16) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPK__S_CMPK_LT_I32::Inst_SOPK__S_CMPK_LT_I32(InFmt_SOPK *iFmt)
+ : Inst_SOPK(iFmt, "s_cmpk_lt_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPK__S_CMPK_LT_I32
+
+ Inst_SOPK__S_CMPK_LT_I32::~Inst_SOPK__S_CMPK_LT_I32()
+ {
+ } // ~Inst_SOPK__S_CMPK_LT_I32
+
+ // SCC = (S0.i < signext(SIMM16)).
+ void
+ Inst_SOPK__S_CMPK_LT_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16;
+ ConstScalarOperandI32 src(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ scc = (src.rawData() < simm16) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPK__S_CMPK_LE_I32::Inst_SOPK__S_CMPK_LE_I32(InFmt_SOPK *iFmt)
+ : Inst_SOPK(iFmt, "s_cmpk_le_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPK__S_CMPK_LE_I32
+
+ Inst_SOPK__S_CMPK_LE_I32::~Inst_SOPK__S_CMPK_LE_I32()
+ {
+ } // ~Inst_SOPK__S_CMPK_LE_I32
+
+ // SCC = (S0.i <= signext(SIMM16)).
+ void
+ Inst_SOPK__S_CMPK_LE_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16;
+ ConstScalarOperandI32 src(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ scc = (src.rawData() <= simm16) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPK__S_CMPK_EQ_U32::Inst_SOPK__S_CMPK_EQ_U32(InFmt_SOPK *iFmt)
+ : Inst_SOPK(iFmt, "s_cmpk_eq_u32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPK__S_CMPK_EQ_U32
+
+ Inst_SOPK__S_CMPK_EQ_U32::~Inst_SOPK__S_CMPK_EQ_U32()
+ {
+ } // ~Inst_SOPK__S_CMPK_EQ_U32
+
+ // SCC = (S0.u == SIMM16).
+ void
+ Inst_SOPK__S_CMPK_EQ_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ScalarRegU32 simm16 = (ScalarRegU32)instData.SIMM16;
+ ConstScalarOperandU32 src(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ scc = (src.rawData() == simm16) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPK__S_CMPK_LG_U32::Inst_SOPK__S_CMPK_LG_U32(InFmt_SOPK *iFmt)
+ : Inst_SOPK(iFmt, "s_cmpk_lg_u32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPK__S_CMPK_LG_U32
+
+ Inst_SOPK__S_CMPK_LG_U32::~Inst_SOPK__S_CMPK_LG_U32()
+ {
+ } // ~Inst_SOPK__S_CMPK_LG_U32
+
+ // SCC = (S0.u != SIMM16).
+ void
+ Inst_SOPK__S_CMPK_LG_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ScalarRegU32 simm16 = (ScalarRegU32)instData.SIMM16;
+ ConstScalarOperandU32 src(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ scc = (src.rawData() != simm16) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPK__S_CMPK_GT_U32::Inst_SOPK__S_CMPK_GT_U32(InFmt_SOPK *iFmt)
+ : Inst_SOPK(iFmt, "s_cmpk_gt_u32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPK__S_CMPK_GT_U32
+
+ Inst_SOPK__S_CMPK_GT_U32::~Inst_SOPK__S_CMPK_GT_U32()
+ {
+ } // ~Inst_SOPK__S_CMPK_GT_U32
+
+ // SCC = (S0.u > SIMM16).
+ void
+ Inst_SOPK__S_CMPK_GT_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ScalarRegU32 simm16 = (ScalarRegU32)instData.SIMM16;
+ ConstScalarOperandU32 src(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ scc = (src.rawData() > simm16) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPK__S_CMPK_GE_U32::Inst_SOPK__S_CMPK_GE_U32(InFmt_SOPK *iFmt)
+ : Inst_SOPK(iFmt, "s_cmpk_ge_u32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPK__S_CMPK_GE_U32
+
+ Inst_SOPK__S_CMPK_GE_U32::~Inst_SOPK__S_CMPK_GE_U32()
+ {
+ } // ~Inst_SOPK__S_CMPK_GE_U32
+
+ // SCC = (S0.u >= SIMM16).
+ void
+ Inst_SOPK__S_CMPK_GE_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ScalarRegU32 simm16 = (ScalarRegU32)instData.SIMM16;
+ ConstScalarOperandU32 src(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ scc = (src.rawData() >= simm16) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPK__S_CMPK_LT_U32::Inst_SOPK__S_CMPK_LT_U32(InFmt_SOPK *iFmt)
+ : Inst_SOPK(iFmt, "s_cmpk_lt_u32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPK__S_CMPK_LT_U32
+
+ Inst_SOPK__S_CMPK_LT_U32::~Inst_SOPK__S_CMPK_LT_U32()
+ {
+ } // ~Inst_SOPK__S_CMPK_LT_U32
+
+ // SCC = (S0.u < SIMM16).
+ void
+ Inst_SOPK__S_CMPK_LT_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ScalarRegU32 simm16 = (ScalarRegU32)instData.SIMM16;
+ ConstScalarOperandU32 src(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ scc = (src.rawData() < simm16) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPK__S_CMPK_LE_U32::Inst_SOPK__S_CMPK_LE_U32(InFmt_SOPK *iFmt)
+ : Inst_SOPK(iFmt, "s_cmpk_le_u32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPK__S_CMPK_LE_U32
+
+ Inst_SOPK__S_CMPK_LE_U32::~Inst_SOPK__S_CMPK_LE_U32()
+ {
+ } // ~Inst_SOPK__S_CMPK_LE_U32
+
+ // SCC = (S0.u <= SIMM16).
+ void
+ Inst_SOPK__S_CMPK_LE_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ScalarRegU32 simm16 = (ScalarRegU32)instData.SIMM16;
+ ConstScalarOperandU32 src(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ scc = (src.rawData() <= simm16) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPK__S_ADDK_I32::Inst_SOPK__S_ADDK_I32(InFmt_SOPK *iFmt)
+ : Inst_SOPK(iFmt, "s_addk_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPK__S_ADDK_I32
+
+ Inst_SOPK__S_ADDK_I32::~Inst_SOPK__S_ADDK_I32()
+ {
+ } // ~Inst_SOPK__S_ADDK_I32
+
+ // D.i = D.i + signext(SIMM16);
+ // SCC = overflow.
+ void
+ Inst_SOPK__S_ADDK_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ScalarRegI16 simm16 = instData.SIMM16;
+ ConstScalarOperandI32 src(gpuDynInst, instData.SDST);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ sdst = src.rawData() + (ScalarRegI32)simm16;
+ scc = (bits(src.rawData(), 31) == bits(simm16, 15)
+ && bits(src.rawData(), 31) != bits(sdst.rawData(), 31)) ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOPK__S_MULK_I32::Inst_SOPK__S_MULK_I32(InFmt_SOPK *iFmt)
+ : Inst_SOPK(iFmt, "s_mulk_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPK__S_MULK_I32
+
+ Inst_SOPK__S_MULK_I32::~Inst_SOPK__S_MULK_I32()
+ {
+ } // ~Inst_SOPK__S_MULK_I32
+
+ // D.i = D.i * signext(SIMM16).
+ void
+ Inst_SOPK__S_MULK_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ScalarRegI16 simm16 = instData.SIMM16;
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+
+ sdst.read();
+
+ sdst = sdst.rawData() * (ScalarRegI32)simm16;
+
+ sdst.write();
+ }
+
+ Inst_SOPK__S_CBRANCH_I_FORK::Inst_SOPK__S_CBRANCH_I_FORK(InFmt_SOPK *iFmt)
+ : Inst_SOPK(iFmt, "s_cbranch_i_fork")
+ {
+ setFlag(Branch);
+ } // Inst_SOPK__S_CBRANCH_I_FORK
+
+ Inst_SOPK__S_CBRANCH_I_FORK::~Inst_SOPK__S_CBRANCH_I_FORK()
+ {
+ } // ~Inst_SOPK__S_CBRANCH_I_FORK
+
+ // Conditional branch using branch-stack.
+ // S0 = compare mask(vcc or any sgpr), and
+ // SIMM16 = signed DWORD branch offset relative to next instruction.
+ void
+ Inst_SOPK__S_CBRANCH_I_FORK::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPK__S_GETREG_B32::Inst_SOPK__S_GETREG_B32(InFmt_SOPK *iFmt)
+ : Inst_SOPK(iFmt, "s_getreg_b32")
+ {
+ } // Inst_SOPK__S_GETREG_B32
+
+ Inst_SOPK__S_GETREG_B32::~Inst_SOPK__S_GETREG_B32()
+ {
+ } // ~Inst_SOPK__S_GETREG_B32
+
+ // D.u = hardware-reg. Read some or all of a hardware register into the
+ // LSBs of D.
+ // SIMM16 = {size[4:0], offset[4:0], hwRegId[5:0]}; offset is 0..31, size
+ // is 1..32.
+ void
+ Inst_SOPK__S_GETREG_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPK__S_SETREG_B32::Inst_SOPK__S_SETREG_B32(InFmt_SOPK *iFmt)
+ : Inst_SOPK(iFmt, "s_setreg_b32")
+ {
+ } // Inst_SOPK__S_SETREG_B32
+
+ Inst_SOPK__S_SETREG_B32::~Inst_SOPK__S_SETREG_B32()
+ {
+ } // ~Inst_SOPK__S_SETREG_B32
+
+ // hardware-reg = S0.u. Write some or all of the LSBs of D into a hardware
+ // register.
+ // SIMM16 = {size[4:0], offset[4:0], hwRegId[5:0]}; offset is 0..31, size
+ // is 1..32.
+ void
+ Inst_SOPK__S_SETREG_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPK__S_SETREG_IMM32_B32::Inst_SOPK__S_SETREG_IMM32_B32(
+ InFmt_SOPK *iFmt)
+ : Inst_SOPK(iFmt, "s_setreg_imm32_b32")
+ {
+ } // Inst_SOPK__S_SETREG_IMM32_B32
+
+ Inst_SOPK__S_SETREG_IMM32_B32::~Inst_SOPK__S_SETREG_IMM32_B32()
+ {
+ } // ~Inst_SOPK__S_SETREG_IMM32_B32
+
+ // Write some or all of the LSBs of IMM32 into a hardware register; this
+ // instruction requires a 32-bit literal constant.
+ // SIMM16 = {size[4:0], offset[4:0], hwRegId[5:0]}; offset is 0..31, size
+ // is 1..32.
+ void
+ Inst_SOPK__S_SETREG_IMM32_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOP1__S_MOV_B32::Inst_SOP1__S_MOV_B32(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_mov_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_MOV_B32
+
+ Inst_SOP1__S_MOV_B32::~Inst_SOP1__S_MOV_B32()
+ {
+ } // ~Inst_SOP1__S_MOV_B32
+
+ // D.u = S0.u.
+ void
+ Inst_SOP1__S_MOV_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+
+ src.read();
+
+ sdst = src.rawData();
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_MOV_B64::Inst_SOP1__S_MOV_B64(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_mov_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_MOV_B64
+
+ Inst_SOP1__S_MOV_B64::~Inst_SOP1__S_MOV_B64()
+ {
+ } // ~Inst_SOP1__S_MOV_B64
+
+ // D.u64 = S0.u64.
+ void
+ Inst_SOP1__S_MOV_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+
+ src.read();
+
+ sdst = src.rawData();
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_CMOV_B32::Inst_SOP1__S_CMOV_B32(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_cmov_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_CMOV_B32
+
+ Inst_SOP1__S_CMOV_B32::~Inst_SOP1__S_CMOV_B32()
+ {
+ } // ~Inst_SOP1__S_CMOV_B32
+
+ // if (SCC) then D.u = S0.u;
+ // else NOP.
+ // Conditional move.
+ void
+ Inst_SOP1__S_CMOV_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+ scc.read();
+
+ if (scc.rawData()) {
+ sdst = src.rawData();
+ sdst.write();
+ }
+ }
+
+ Inst_SOP1__S_CMOV_B64::Inst_SOP1__S_CMOV_B64(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_cmov_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_CMOV_B64
+
+ Inst_SOP1__S_CMOV_B64::~Inst_SOP1__S_CMOV_B64()
+ {
+ } // ~Inst_SOP1__S_CMOV_B64
+
+ // if (SCC) then D.u64 = S0.u64;
+ // else NOP.
+ // Conditional move.
+ void
+ Inst_SOP1__S_CMOV_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+ scc.read();
+
+ if (scc.rawData()) {
+ sdst = src.rawData();
+ sdst.write();
+ }
+ }
+
+ Inst_SOP1__S_NOT_B32::Inst_SOP1__S_NOT_B32(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_not_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_NOT_B32
+
+ Inst_SOP1__S_NOT_B32::~Inst_SOP1__S_NOT_B32()
+ {
+ } // ~Inst_SOP1__S_NOT_B32
+
+ // D.u = ~S0.u;
+ // SCC = 1 if result is non-zero.
+ // Bitwise negation.
+ void
+ Inst_SOP1__S_NOT_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ sdst = ~src.rawData();
+
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP1__S_NOT_B64::Inst_SOP1__S_NOT_B64(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_not_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_NOT_B64
+
+ Inst_SOP1__S_NOT_B64::~Inst_SOP1__S_NOT_B64()
+ {
+ } // ~Inst_SOP1__S_NOT_B64
+
+ // D.u64 = ~S0.u64;
+ // SCC = 1 if result is non-zero.
+ // Bitwise negation.
+ void
+ Inst_SOP1__S_NOT_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ sdst = ~src.rawData();
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP1__S_WQM_B32::Inst_SOP1__S_WQM_B32(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_wqm_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_WQM_B32
+
+ Inst_SOP1__S_WQM_B32::~Inst_SOP1__S_WQM_B32()
+ {
+ } // ~Inst_SOP1__S_WQM_B32
+
+ // Computes whole quad mode for an active/valid mask.
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP1__S_WQM_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ sdst = wholeQuadMode(src.rawData());
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP1__S_WQM_B64::Inst_SOP1__S_WQM_B64(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_wqm_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_WQM_B64
+
+ Inst_SOP1__S_WQM_B64::~Inst_SOP1__S_WQM_B64()
+ {
+ } // ~Inst_SOP1__S_WQM_B64
+
+ // Computes whole quad mode for an active/valid mask.
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP1__S_WQM_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ sdst = wholeQuadMode(src.rawData());
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP1__S_BREV_B32::Inst_SOP1__S_BREV_B32(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_brev_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_BREV_B32
+
+ Inst_SOP1__S_BREV_B32::~Inst_SOP1__S_BREV_B32()
+ {
+ } // ~Inst_SOP1__S_BREV_B32
+
+ // D.u[31:0] = S0.u[0:31] (reverse bits).
+ void
+ Inst_SOP1__S_BREV_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+
+ src.read();
+
+ sdst = reverseBits(src.rawData());
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_BREV_B64::Inst_SOP1__S_BREV_B64(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_brev_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_BREV_B64
+
+ Inst_SOP1__S_BREV_B64::~Inst_SOP1__S_BREV_B64()
+ {
+ } // ~Inst_SOP1__S_BREV_B64
+
+ // D.u64[63:0] = S0.u64[0:63] (reverse bits).
+ void
+ Inst_SOP1__S_BREV_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+
+ src.read();
+
+ sdst = reverseBits(src.rawData());
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_BCNT0_I32_B32::Inst_SOP1__S_BCNT0_I32_B32(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_bcnt0_i32_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_BCNT0_I32_B32
+
+ Inst_SOP1__S_BCNT0_I32_B32::~Inst_SOP1__S_BCNT0_I32_B32()
+ {
+ } // ~Inst_SOP1__S_BCNT0_I32_B32
+
+ // D.i = CountZeroBits(S0.u);
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP1__S_BCNT0_I32_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ sdst = countZeroBits(src.rawData());
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP1__S_BCNT0_I32_B64::Inst_SOP1__S_BCNT0_I32_B64(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_bcnt0_i32_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_BCNT0_I32_B64
+
+ Inst_SOP1__S_BCNT0_I32_B64::~Inst_SOP1__S_BCNT0_I32_B64()
+ {
+ } // ~Inst_SOP1__S_BCNT0_I32_B64
+
+ // D.i = CountZeroBits(S0.u64);
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP1__S_BCNT0_I32_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ sdst = countZeroBits(src.rawData());
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP1__S_BCNT1_I32_B32::Inst_SOP1__S_BCNT1_I32_B32(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_bcnt1_i32_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_BCNT1_I32_B32
+
+ Inst_SOP1__S_BCNT1_I32_B32::~Inst_SOP1__S_BCNT1_I32_B32()
+ {
+ } // ~Inst_SOP1__S_BCNT1_I32_B32
+
+ // D.i = CountOneBits(S0.u);
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP1__S_BCNT1_I32_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ sdst = popCount(src.rawData());
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP1__S_BCNT1_I32_B64::Inst_SOP1__S_BCNT1_I32_B64(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_bcnt1_i32_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_BCNT1_I32_B64
+
+ Inst_SOP1__S_BCNT1_I32_B64::~Inst_SOP1__S_BCNT1_I32_B64()
+ {
+ } // ~Inst_SOP1__S_BCNT1_I32_B64
+
+ // D.i = CountOneBits(S0.u64);
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP1__S_BCNT1_I32_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ sdst = popCount(src.rawData());
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP1__S_FF0_I32_B32::Inst_SOP1__S_FF0_I32_B32(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_ff0_i32_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_FF0_I32_B32
+
+ Inst_SOP1__S_FF0_I32_B32::~Inst_SOP1__S_FF0_I32_B32()
+ {
+ } // ~Inst_SOP1__S_FF0_I32_B32
+
+ // D.i = FindFirstZero(S0.u);
+ // If no zeros are found, return -1.
+ // Returns the bit position of the first zero from the LSB.
+ void
+ Inst_SOP1__S_FF0_I32_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+
+ src.read();
+
+ sdst = findFirstZero(src.rawData());
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_FF0_I32_B64::Inst_SOP1__S_FF0_I32_B64(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_ff0_i32_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_FF0_I32_B64
+
+ Inst_SOP1__S_FF0_I32_B64::~Inst_SOP1__S_FF0_I32_B64()
+ {
+ } // ~Inst_SOP1__S_FF0_I32_B64
+
+ // D.i = FindFirstZero(S0.u64);
+ // If no zeros are found, return -1.
+ // Returns the bit position of the first zero from the LSB.
+ void
+ Inst_SOP1__S_FF0_I32_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+
+ src.read();
+
+ sdst = findFirstZero(src.rawData());
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_FF1_I32_B32::Inst_SOP1__S_FF1_I32_B32(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_ff1_i32_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_FF1_I32_B32
+
+ Inst_SOP1__S_FF1_I32_B32::~Inst_SOP1__S_FF1_I32_B32()
+ {
+ } // ~Inst_SOP1__S_FF1_I32_B32
+
+ // D.i = FindFirstOne(S0.u);
+ // If no ones are found, return -1.
+ // Returns the bit position of the first one from the LSB.
+ void
+ Inst_SOP1__S_FF1_I32_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+
+ src.read();
+
+ sdst = findFirstOne(src.rawData());
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_FF1_I32_B64::Inst_SOP1__S_FF1_I32_B64(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_ff1_i32_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_FF1_I32_B64
+
+ Inst_SOP1__S_FF1_I32_B64::~Inst_SOP1__S_FF1_I32_B64()
+ {
+ } // ~Inst_SOP1__S_FF1_I32_B64
+
+ // D.i = FindFirstOne(S0.u64);
+ // If no ones are found, return -1.
+ // Returns the bit position of the first one from the LSB.
+ void
+ Inst_SOP1__S_FF1_I32_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+
+ src.read();
+
+ sdst = findFirstOne(src.rawData());
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_FLBIT_I32_B32::Inst_SOP1__S_FLBIT_I32_B32(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_flbit_i32_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_FLBIT_I32_B32
+
+ Inst_SOP1__S_FLBIT_I32_B32::~Inst_SOP1__S_FLBIT_I32_B32()
+ {
+ } // ~Inst_SOP1__S_FLBIT_I32_B32
+
+ // D.i = FindFirstOne(S0.u);
+ // If no ones are found, return -1.
+ // Counts how many zeros before the first one starting from the MSB.
+ void
+ Inst_SOP1__S_FLBIT_I32_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+
+ src.read();
+
+ sdst = countZeroBitsMsb(src.rawData());
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_FLBIT_I32_B64::Inst_SOP1__S_FLBIT_I32_B64(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_flbit_i32_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_FLBIT_I32_B64
+
+ Inst_SOP1__S_FLBIT_I32_B64::~Inst_SOP1__S_FLBIT_I32_B64()
+ {
+ } // ~Inst_SOP1__S_FLBIT_I32_B64
+
+ // D.i = FindFirstOne(S0.u64);
+ // If no ones are found, return -1.
+ // Counts how many zeros before the first one starting from the MSB.
+ void
+ Inst_SOP1__S_FLBIT_I32_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+
+ src.read();
+
+ sdst = countZeroBitsMsb(src.rawData());
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_FLBIT_I32::Inst_SOP1__S_FLBIT_I32(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_flbit_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_FLBIT_I32
+
+ Inst_SOP1__S_FLBIT_I32::~Inst_SOP1__S_FLBIT_I32()
+ {
+ } // ~Inst_SOP1__S_FLBIT_I32
+
+ // D.i = FirstOppositeSignBit(S0.i);
+ // If S0.i == 0 or S0.i == -1 (all bits are the same), return -1.
+ // Counts how many bits in a row (from MSB to LSB) are the same as the
+ // sign bit.
+ void
+ Inst_SOP1__S_FLBIT_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI32 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+
+ src.read();
+
+ sdst = firstOppositeSignBit(src.rawData());
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_FLBIT_I32_I64::Inst_SOP1__S_FLBIT_I32_I64(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_flbit_i32_i64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_FLBIT_I32_I64
+
+ Inst_SOP1__S_FLBIT_I32_I64::~Inst_SOP1__S_FLBIT_I32_I64()
+ {
+ } // ~Inst_SOP1__S_FLBIT_I32_I64
+
+ // D.i = FirstOppositeSignBit(S0.i64);
+ // If S0.i == 0 or S0.i == -1 (all bits are the same), return -1.
+ // Counts how many bits in a row (from MSB to LSB) are the same as the
+ // sign bit.
+ void
+ Inst_SOP1__S_FLBIT_I32_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI64 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+
+ src.read();
+
+ sdst = firstOppositeSignBit(src.rawData());
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_SEXT_I32_I8::Inst_SOP1__S_SEXT_I32_I8(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_sext_i32_i8")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_SEXT_I32_I8
+
+ Inst_SOP1__S_SEXT_I32_I8::~Inst_SOP1__S_SEXT_I32_I8()
+ {
+ } // ~Inst_SOP1__S_SEXT_I32_I8
+
+ // D.i = signext(S0.i[7:0]) (sign extension).
+ void
+ Inst_SOP1__S_SEXT_I32_I8::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI32 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+
+ src.read();
+
+ sdst = sext<std::numeric_limits<ScalarRegI8>::digits>(
+ bits(src.rawData(), 7, 0));
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_SEXT_I32_I16::Inst_SOP1__S_SEXT_I32_I16(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_sext_i32_i16")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_SEXT_I32_I16
+
+ Inst_SOP1__S_SEXT_I32_I16::~Inst_SOP1__S_SEXT_I32_I16()
+ {
+ } // ~Inst_SOP1__S_SEXT_I32_I16
+
+ // D.i = signext(S0.i[15:0]) (sign extension).
+ void
+ Inst_SOP1__S_SEXT_I32_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI32 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+
+ src.read();
+
+ sdst = sext<std::numeric_limits<ScalarRegI16>::digits>(
+ bits(src.rawData(), 15, 0));
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_BITSET0_B32::Inst_SOP1__S_BITSET0_B32(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_bitset0_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_BITSET0_B32
+
+ Inst_SOP1__S_BITSET0_B32::~Inst_SOP1__S_BITSET0_B32()
+ {
+ } // ~Inst_SOP1__S_BITSET0_B32
+
+ // D.u[S0.u[4:0]] = 0.
+ void
+ Inst_SOP1__S_BITSET0_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+
+ src.read();
+
+ sdst.setBit(bits(src.rawData(), 4, 0), 0);
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_BITSET0_B64::Inst_SOP1__S_BITSET0_B64(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_bitset0_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_BITSET0_B64
+
+ Inst_SOP1__S_BITSET0_B64::~Inst_SOP1__S_BITSET0_B64()
+ {
+ } // ~Inst_SOP1__S_BITSET0_B64
+
+ // D.u64[S0.u[5:0]] = 0.
+ void
+ Inst_SOP1__S_BITSET0_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+
+ src.read();
+
+ sdst.setBit(bits(src.rawData(), 5, 0), 0);
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_BITSET1_B32::Inst_SOP1__S_BITSET1_B32(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_bitset1_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_BITSET1_B32
+
+ Inst_SOP1__S_BITSET1_B32::~Inst_SOP1__S_BITSET1_B32()
+ {
+ } // ~Inst_SOP1__S_BITSET1_B32
+
+ // D.u[S0.u[4:0]] = 1.
+ void
+ Inst_SOP1__S_BITSET1_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+
+ src.read();
+
+ sdst.setBit(bits(src.rawData(), 4, 0), 1);
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_BITSET1_B64::Inst_SOP1__S_BITSET1_B64(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_bitset1_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_BITSET1_B64
+
+ Inst_SOP1__S_BITSET1_B64::~Inst_SOP1__S_BITSET1_B64()
+ {
+ } // ~Inst_SOP1__S_BITSET1_B64
+
+ // D.u64[S0.u[5:0]] = 1.
+ void
+ Inst_SOP1__S_BITSET1_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+
+ src.read();
+
+ sdst.setBit(bits(src.rawData(), 5, 0), 1);
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_GETPC_B64::Inst_SOP1__S_GETPC_B64(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_getpc_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_GETPC_B64
+
+ Inst_SOP1__S_GETPC_B64::~Inst_SOP1__S_GETPC_B64()
+ {
+ } // ~Inst_SOP1__S_GETPC_B64
+
+ // D.u64 = PC + 4.
+ // Destination receives the byte address of the next instruction.
+ void
+ Inst_SOP1__S_GETPC_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ Addr pc = wf->pc();
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+
+ sdst = pc + 4;
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_SETPC_B64::Inst_SOP1__S_SETPC_B64(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_setpc_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_SETPC_B64
+
+ Inst_SOP1__S_SETPC_B64::~Inst_SOP1__S_SETPC_B64()
+ {
+ } // ~Inst_SOP1__S_SETPC_B64
+
+ // PC = S0.u64.
+ // S0.u64 is a byte address of the instruction to jump to.
+ void
+ Inst_SOP1__S_SETPC_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
+
+ src.read();
+
+ wf->pc(src.rawData());
+ }
+
+ Inst_SOP1__S_SWAPPC_B64::Inst_SOP1__S_SWAPPC_B64(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_swappc_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_SWAPPC_B64
+
+ Inst_SOP1__S_SWAPPC_B64::~Inst_SOP1__S_SWAPPC_B64()
+ {
+ } // ~Inst_SOP1__S_SWAPPC_B64
+
+ // D.u64 = PC + 4; PC = S0.u64.
+ // S0.u64 is a byte address of the instruction to jump to.
+ void
+ Inst_SOP1__S_SWAPPC_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ Addr pc = wf->pc();
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+
+ src.read();
+
+ sdst = pc + 4;
+
+ wf->pc(src.rawData());
+ sdst.write();
+ }
+
+ Inst_SOP1__S_RFE_B64::Inst_SOP1__S_RFE_B64(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_rfe_b64")
+ {
+ } // Inst_SOP1__S_RFE_B64
+
+ Inst_SOP1__S_RFE_B64::~Inst_SOP1__S_RFE_B64()
+ {
+ } // ~Inst_SOP1__S_RFE_B64
+
+ // Return from exception handler and continue.
+ void
+ Inst_SOP1__S_RFE_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOP1__S_AND_SAVEEXEC_B64::Inst_SOP1__S_AND_SAVEEXEC_B64(
+ InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_and_saveexec_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_AND_SAVEEXEC_B64
+
+ Inst_SOP1__S_AND_SAVEEXEC_B64::~Inst_SOP1__S_AND_SAVEEXEC_B64()
+ {
+ } // ~Inst_SOP1__S_AND_SAVEEXEC_B64
+
+ // D.u64 = EXEC;
+ // EXEC = S0.u64 & EXEC;
+ // SCC = 1 if the new value of EXEC is non-zero.
+ void
+ Inst_SOP1__S_AND_SAVEEXEC_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ sdst = wf->execMask().to_ullong();
+ wf->execMask() = src.rawData() & wf->execMask().to_ullong();
+ scc = wf->execMask().any() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP1__S_OR_SAVEEXEC_B64::Inst_SOP1__S_OR_SAVEEXEC_B64(
+ InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_or_saveexec_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_OR_SAVEEXEC_B64
+
+ Inst_SOP1__S_OR_SAVEEXEC_B64::~Inst_SOP1__S_OR_SAVEEXEC_B64()
+ {
+ } // ~Inst_SOP1__S_OR_SAVEEXEC_B64
+
+ // D.u64 = EXEC;
+ // EXEC = S0.u64 | EXEC;
+ // SCC = 1 if the new value of EXEC is non-zero.
+ void
+ Inst_SOP1__S_OR_SAVEEXEC_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ sdst = wf->execMask().to_ullong();
+ wf->execMask() = src.rawData() | wf->execMask().to_ullong();
+ scc = wf->execMask().any() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP1__S_XOR_SAVEEXEC_B64::Inst_SOP1__S_XOR_SAVEEXEC_B64(
+ InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_xor_saveexec_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_XOR_SAVEEXEC_B64
+
+ Inst_SOP1__S_XOR_SAVEEXEC_B64::~Inst_SOP1__S_XOR_SAVEEXEC_B64()
+ {
+ } // ~Inst_SOP1__S_XOR_SAVEEXEC_B64
+
+ // D.u64 = EXEC;
+ // EXEC = S0.u64 ^ EXEC;
+ // SCC = 1 if the new value of EXEC is non-zero.
+ void
+ Inst_SOP1__S_XOR_SAVEEXEC_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ sdst = wf->execMask().to_ullong();
+ wf->execMask() = src.rawData() ^ wf->execMask().to_ullong();
+ scc = wf->execMask().any() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP1__S_ANDN2_SAVEEXEC_B64::Inst_SOP1__S_ANDN2_SAVEEXEC_B64(
+ InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_andn2_saveexec_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_ANDN2_SAVEEXEC_B64
+
+ Inst_SOP1__S_ANDN2_SAVEEXEC_B64::~Inst_SOP1__S_ANDN2_SAVEEXEC_B64()
+ {
+ } // ~Inst_SOP1__S_ANDN2_SAVEEXEC_B64
+
+ // D.u64 = EXEC;
+ // EXEC = S0.u64 & ~EXEC;
+ // SCC = 1 if the new value of EXEC is non-zero.
+ void
+ Inst_SOP1__S_ANDN2_SAVEEXEC_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ sdst = wf->execMask().to_ullong();
+ wf->execMask() = src.rawData() &~ wf->execMask().to_ullong();
+ scc = wf->execMask().any() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP1__S_ORN2_SAVEEXEC_B64::Inst_SOP1__S_ORN2_SAVEEXEC_B64(
+ InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_orn2_saveexec_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_ORN2_SAVEEXEC_B64
+
+ Inst_SOP1__S_ORN2_SAVEEXEC_B64::~Inst_SOP1__S_ORN2_SAVEEXEC_B64()
+ {
+ } // ~Inst_SOP1__S_ORN2_SAVEEXEC_B64
+
+ // D.u64 = EXEC;
+ // EXEC = S0.u64 | ~EXEC;
+ // SCC = 1 if the new value of EXEC is non-zero.
+ void
+ Inst_SOP1__S_ORN2_SAVEEXEC_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ sdst = wf->execMask().to_ullong();
+ wf->execMask() = src.rawData() |~ wf->execMask().to_ullong();
+ scc = wf->execMask().any() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP1__S_NAND_SAVEEXEC_B64::Inst_SOP1__S_NAND_SAVEEXEC_B64(
+ InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_nand_saveexec_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_NAND_SAVEEXEC_B64
+
+ Inst_SOP1__S_NAND_SAVEEXEC_B64::~Inst_SOP1__S_NAND_SAVEEXEC_B64()
+ {
+ } // ~Inst_SOP1__S_NAND_SAVEEXEC_B64
+
+ // D.u64 = EXEC;
+ // EXEC = ~(S0.u64 & EXEC);
+ // SCC = 1 if the new value of EXEC is non-zero.
+ void
+ Inst_SOP1__S_NAND_SAVEEXEC_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ sdst = wf->execMask().to_ullong();
+ wf->execMask() = ~(src.rawData() & wf->execMask().to_ullong());
+ scc = wf->execMask().any() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP1__S_NOR_SAVEEXEC_B64::Inst_SOP1__S_NOR_SAVEEXEC_B64(
+ InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_nor_saveexec_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_NOR_SAVEEXEC_B64
+
+ Inst_SOP1__S_NOR_SAVEEXEC_B64::~Inst_SOP1__S_NOR_SAVEEXEC_B64()
+ {
+ } // ~Inst_SOP1__S_NOR_SAVEEXEC_B64
+
+ // D.u64 = EXEC;
+ // EXEC = ~(S0.u64 | EXEC);
+ // SCC = 1 if the new value of EXEC is non-zero.
+ void
+ Inst_SOP1__S_NOR_SAVEEXEC_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ sdst = wf->execMask().to_ullong();
+ wf->execMask() = ~(src.rawData() | wf->execMask().to_ullong());
+ scc = wf->execMask().any() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP1__S_XNOR_SAVEEXEC_B64::Inst_SOP1__S_XNOR_SAVEEXEC_B64(
+ InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_xnor_saveexec_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_XNOR_SAVEEXEC_B64
+
+ Inst_SOP1__S_XNOR_SAVEEXEC_B64::~Inst_SOP1__S_XNOR_SAVEEXEC_B64()
+ {
+ } // ~Inst_SOP1__S_XNOR_SAVEEXEC_B64
+
+ // D.u64 = EXEC;
+ // EXEC = ~(S0.u64 ^ EXEC);
+ // SCC = 1 if the new value of EXEC is non-zero.
+ void
+ Inst_SOP1__S_XNOR_SAVEEXEC_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ sdst = wf->execMask().to_ullong();
+ wf->execMask() = ~(src.rawData() ^ wf->execMask().to_ullong());
+ scc = wf->execMask().any() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP1__S_QUADMASK_B32::Inst_SOP1__S_QUADMASK_B32(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_quadmask_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_QUADMASK_B32
+
+ Inst_SOP1__S_QUADMASK_B32::~Inst_SOP1__S_QUADMASK_B32()
+ {
+ } // ~Inst_SOP1__S_QUADMASK_B32
+
+ // D.u = QuadMask(S0.u):
+ // D[0] = OR(S0[3:0]), D[1] = OR(S0[7:4]) ... D[31:8] = 0;
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP1__S_QUADMASK_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ sdst = quadMask(src.rawData());
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP1__S_QUADMASK_B64::Inst_SOP1__S_QUADMASK_B64(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_quadmask_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_QUADMASK_B64
+
+ Inst_SOP1__S_QUADMASK_B64::~Inst_SOP1__S_QUADMASK_B64()
+ {
+ } // ~Inst_SOP1__S_QUADMASK_B64
+
+ // D.u64 = QuadMask(S0.u64):
+ // D[0] = OR(S0[3:0]), D[1] = OR(S0[7:4]) ... D[63:16] = 0;
+ // SCC = 1 if result is non-zero.
+ void
+ Inst_SOP1__S_QUADMASK_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ sdst = quadMask(src.rawData());
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP1__S_MOVRELS_B32::Inst_SOP1__S_MOVRELS_B32(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_movrels_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_MOVRELS_B32
+
+ Inst_SOP1__S_MOVRELS_B32::~Inst_SOP1__S_MOVRELS_B32()
+ {
+ } // ~Inst_SOP1__S_MOVRELS_B32
+
+ // D.u = SGPR[S0.u + M0.u].u (move from relative source).
+ void
+ Inst_SOP1__S_MOVRELS_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 m0(gpuDynInst, REG_M0);
+ m0.read();
+ ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0 + m0.rawData());
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+
+ src.read();
+
+ sdst = src.rawData();
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_MOVRELS_B64::Inst_SOP1__S_MOVRELS_B64(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_movrels_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_MOVRELS_B64
+
+ Inst_SOP1__S_MOVRELS_B64::~Inst_SOP1__S_MOVRELS_B64()
+ {
+ } // ~Inst_SOP1__S_MOVRELS_B64
+
+ // D.u64 = SGPR[S0.u + M0.u].u64 (move from relative source).
+ // The index in M0.u must be even for this operation.
+ void
+ Inst_SOP1__S_MOVRELS_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 m0(gpuDynInst, REG_M0);
+ m0.read();
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0 + m0.rawData());
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+
+ src.read();
+
+ sdst = src.rawData();
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_MOVRELD_B32::Inst_SOP1__S_MOVRELD_B32(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_movreld_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_MOVRELD_B32
+
+ Inst_SOP1__S_MOVRELD_B32::~Inst_SOP1__S_MOVRELD_B32()
+ {
+ } // ~Inst_SOP1__S_MOVRELD_B32
+
+ // SGPR[D.u + M0.u].u = S0.u (move to relative destination).
+ void
+ Inst_SOP1__S_MOVRELD_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 m0(gpuDynInst, REG_M0);
+ m0.read();
+ ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDST + m0.rawData());
+
+ src.read();
+
+ sdst = src.rawData();
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_MOVRELD_B64::Inst_SOP1__S_MOVRELD_B64(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_movreld_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_MOVRELD_B64
+
+ Inst_SOP1__S_MOVRELD_B64::~Inst_SOP1__S_MOVRELD_B64()
+ {
+ } // ~Inst_SOP1__S_MOVRELD_B64
+
+ // SGPR[D.u + M0.u].u64 = S0.u64 (move to relative destination).
+ // The index in M0.u must be even for this operation.
+ void
+ Inst_SOP1__S_MOVRELD_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 m0(gpuDynInst, REG_M0);
+ m0.read();
+ ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST + m0.rawData());
+
+ src.read();
+
+ sdst = src.rawData();
+
+ sdst.write();
+ }
+
+ Inst_SOP1__S_CBRANCH_JOIN::Inst_SOP1__S_CBRANCH_JOIN(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_cbranch_join")
+ {
+ setFlag(Branch);
+ } // Inst_SOP1__S_CBRANCH_JOIN
+
+ Inst_SOP1__S_CBRANCH_JOIN::~Inst_SOP1__S_CBRANCH_JOIN()
+ {
+ } // ~Inst_SOP1__S_CBRANCH_JOIN
+
+ // Conditional branch join point (end of conditional branch block).
+ void
+ Inst_SOP1__S_CBRANCH_JOIN::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOP1__S_ABS_I32::Inst_SOP1__S_ABS_I32(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_abs_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_ABS_I32
+
+ Inst_SOP1__S_ABS_I32::~Inst_SOP1__S_ABS_I32()
+ {
+ } // ~Inst_SOP1__S_ABS_I32
+
+ // if (S.i < 0) then D.i = -S.i;
+ // else D.i = S.i;
+ // SCC = 1 if result is non-zero.
+ // Integer absolute value.
+ void
+ Inst_SOP1__S_ABS_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI32 src(gpuDynInst, instData.SSRC0);
+ ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src.read();
+
+ sdst = std::abs(src.rawData());
+
+ scc = sdst.rawData() ? 1 : 0;
+
+ sdst.write();
+ scc.write();
+ }
+
+ Inst_SOP1__S_MOV_FED_B32::Inst_SOP1__S_MOV_FED_B32(InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_mov_fed_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOP1__S_MOV_FED_B32
+
+ Inst_SOP1__S_MOV_FED_B32::~Inst_SOP1__S_MOV_FED_B32()
+ {
+ } // ~Inst_SOP1__S_MOV_FED_B32
+
+ // D.u = S0.u.
+ void
+ Inst_SOP1__S_MOV_FED_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOP1__S_SET_GPR_IDX_IDX::Inst_SOP1__S_SET_GPR_IDX_IDX(
+ InFmt_SOP1 *iFmt)
+ : Inst_SOP1(iFmt, "s_set_gpr_idx_idx")
+ {
+ } // Inst_SOP1__S_SET_GPR_IDX_IDX
+
+ Inst_SOP1__S_SET_GPR_IDX_IDX::~Inst_SOP1__S_SET_GPR_IDX_IDX()
+ {
+ } // ~Inst_SOP1__S_SET_GPR_IDX_IDX
+
+ // M0[7:0] = S0.u[7:0].
+ // Modify the index used in vector GPR indexing.
+ void
+ Inst_SOP1__S_SET_GPR_IDX_IDX::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPC__S_CMP_EQ_I32::Inst_SOPC__S_CMP_EQ_I32(InFmt_SOPC *iFmt)
+ : Inst_SOPC(iFmt, "s_cmp_eq_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPC__S_CMP_EQ_I32
+
+ Inst_SOPC__S_CMP_EQ_I32::~Inst_SOPC__S_CMP_EQ_I32()
+ {
+ } // ~Inst_SOPC__S_CMP_EQ_I32
+
+ // SCC = (S0.i == S1.i).
+ void
+ Inst_SOPC__S_CMP_EQ_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandI32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ scc = (src0.rawData() == src1.rawData()) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPC__S_CMP_LG_I32::Inst_SOPC__S_CMP_LG_I32(InFmt_SOPC *iFmt)
+ : Inst_SOPC(iFmt, "s_cmp_lg_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPC__S_CMP_LG_I32
+
+ Inst_SOPC__S_CMP_LG_I32::~Inst_SOPC__S_CMP_LG_I32()
+ {
+ } // ~Inst_SOPC__S_CMP_LG_I32
+
+ // SCC = (S0.i != S1.i).
+ void
+ Inst_SOPC__S_CMP_LG_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandI32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ scc = (src0.rawData() != src1.rawData()) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPC__S_CMP_GT_I32::Inst_SOPC__S_CMP_GT_I32(InFmt_SOPC *iFmt)
+ : Inst_SOPC(iFmt, "s_cmp_gt_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPC__S_CMP_GT_I32
+
+ Inst_SOPC__S_CMP_GT_I32::~Inst_SOPC__S_CMP_GT_I32()
+ {
+ } // ~Inst_SOPC__S_CMP_GT_I32
+
+ // SCC = (S0.i > S1.i).
+ void
+ Inst_SOPC__S_CMP_GT_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandI32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ scc = (src0.rawData() > src1.rawData()) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPC__S_CMP_GE_I32::Inst_SOPC__S_CMP_GE_I32(InFmt_SOPC *iFmt)
+ : Inst_SOPC(iFmt, "s_cmp_ge_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPC__S_CMP_GE_I32
+
+ Inst_SOPC__S_CMP_GE_I32::~Inst_SOPC__S_CMP_GE_I32()
+ {
+ } // ~Inst_SOPC__S_CMP_GE_I32
+
+ // SCC = (S0.i >= S1.i).
+ void
+ Inst_SOPC__S_CMP_GE_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandI32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ scc = (src0.rawData() >= src1.rawData()) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPC__S_CMP_LT_I32::Inst_SOPC__S_CMP_LT_I32(InFmt_SOPC *iFmt)
+ : Inst_SOPC(iFmt, "s_cmp_lt_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPC__S_CMP_LT_I32
+
+ Inst_SOPC__S_CMP_LT_I32::~Inst_SOPC__S_CMP_LT_I32()
+ {
+ } // ~Inst_SOPC__S_CMP_LT_I32
+
+ // SCC = (S0.i < S1.i).
+ void
+ Inst_SOPC__S_CMP_LT_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandI32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ scc = (src0.rawData() < src1.rawData()) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPC__S_CMP_LE_I32::Inst_SOPC__S_CMP_LE_I32(InFmt_SOPC *iFmt)
+ : Inst_SOPC(iFmt, "s_cmp_le_i32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPC__S_CMP_LE_I32
+
+ Inst_SOPC__S_CMP_LE_I32::~Inst_SOPC__S_CMP_LE_I32()
+ {
+ } // ~Inst_SOPC__S_CMP_LE_I32
+
+ // SCC = (S0.i <= S1.i).
+ void
+ Inst_SOPC__S_CMP_LE_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandI32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ scc = (src0.rawData() <= src1.rawData()) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPC__S_CMP_EQ_U32::Inst_SOPC__S_CMP_EQ_U32(InFmt_SOPC *iFmt)
+ : Inst_SOPC(iFmt, "s_cmp_eq_u32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPC__S_CMP_EQ_U32
+
+ Inst_SOPC__S_CMP_EQ_U32::~Inst_SOPC__S_CMP_EQ_U32()
+ {
+ } // ~Inst_SOPC__S_CMP_EQ_U32
+
+ // SCC = (S0.u == S1.u).
+ void
+ Inst_SOPC__S_CMP_EQ_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ scc = (src0.rawData() == src1.rawData()) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPC__S_CMP_LG_U32::Inst_SOPC__S_CMP_LG_U32(InFmt_SOPC *iFmt)
+ : Inst_SOPC(iFmt, "s_cmp_lg_u32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPC__S_CMP_LG_U32
+
+ Inst_SOPC__S_CMP_LG_U32::~Inst_SOPC__S_CMP_LG_U32()
+ {
+ } // ~Inst_SOPC__S_CMP_LG_U32
+
+ // SCC = (S0.u != S1.u).
+ void
+ Inst_SOPC__S_CMP_LG_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ scc = (src0.rawData() != src1.rawData()) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPC__S_CMP_GT_U32::Inst_SOPC__S_CMP_GT_U32(InFmt_SOPC *iFmt)
+ : Inst_SOPC(iFmt, "s_cmp_gt_u32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPC__S_CMP_GT_U32
+
+ Inst_SOPC__S_CMP_GT_U32::~Inst_SOPC__S_CMP_GT_U32()
+ {
+ } // ~Inst_SOPC__S_CMP_GT_U32
+
+ // SCC = (S0.u > S1.u).
+ void
+ Inst_SOPC__S_CMP_GT_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ scc = (src0.rawData() > src1.rawData()) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPC__S_CMP_GE_U32::Inst_SOPC__S_CMP_GE_U32(InFmt_SOPC *iFmt)
+ : Inst_SOPC(iFmt, "s_cmp_ge_u32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPC__S_CMP_GE_U32
+
+ Inst_SOPC__S_CMP_GE_U32::~Inst_SOPC__S_CMP_GE_U32()
+ {
+ } // ~Inst_SOPC__S_CMP_GE_U32
+
+ // SCC = (S0.u >= S1.u).
+ void
+ Inst_SOPC__S_CMP_GE_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ scc = (src0.rawData() >= src1.rawData()) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPC__S_CMP_LT_U32::Inst_SOPC__S_CMP_LT_U32(InFmt_SOPC *iFmt)
+ : Inst_SOPC(iFmt, "s_cmp_lt_u32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPC__S_CMP_LT_U32
+
+ Inst_SOPC__S_CMP_LT_U32::~Inst_SOPC__S_CMP_LT_U32()
+ {
+ } // ~Inst_SOPC__S_CMP_LT_U32
+
+ // SCC = (S0.u < S1.u).
+ void
+ Inst_SOPC__S_CMP_LT_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ scc = (src0.rawData() <= src1.rawData()) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPC__S_CMP_LE_U32::Inst_SOPC__S_CMP_LE_U32(InFmt_SOPC *iFmt)
+ : Inst_SOPC(iFmt, "s_cmp_le_u32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPC__S_CMP_LE_U32
+
+ Inst_SOPC__S_CMP_LE_U32::~Inst_SOPC__S_CMP_LE_U32()
+ {
+ } // ~Inst_SOPC__S_CMP_LE_U32
+
+ // SCC = (S0.u <= S1.u).
+ void
+ Inst_SOPC__S_CMP_LE_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ scc = (src0.rawData() <= src1.rawData()) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPC__S_BITCMP0_B32::Inst_SOPC__S_BITCMP0_B32(InFmt_SOPC *iFmt)
+ : Inst_SOPC(iFmt, "s_bitcmp0_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPC__S_BITCMP0_B32
+
+ Inst_SOPC__S_BITCMP0_B32::~Inst_SOPC__S_BITCMP0_B32()
+ {
+ } // ~Inst_SOPC__S_BITCMP0_B32
+
+ // SCC = (S0.u[S1.u[4:0]] == 0).
+ void
+ Inst_SOPC__S_BITCMP0_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ scc = !bits(src0.rawData(), bits(src1.rawData(), 4, 0)) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPC__S_BITCMP1_B32::Inst_SOPC__S_BITCMP1_B32(InFmt_SOPC *iFmt)
+ : Inst_SOPC(iFmt, "s_bitcmp1_b32")
+ {
+ setFlag(ALU);
+ } // Inst_SOPC__S_BITCMP1_B32
+
+ Inst_SOPC__S_BITCMP1_B32::~Inst_SOPC__S_BITCMP1_B32()
+ {
+ } // ~Inst_SOPC__S_BITCMP1_B32
+
+ // SCC = (S0.u[S1.u[4:0]] == 1).
+ void
+ Inst_SOPC__S_BITCMP1_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ scc = bits(src0.rawData(), bits(src1.rawData(), 4, 0)) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPC__S_BITCMP0_B64::Inst_SOPC__S_BITCMP0_B64(InFmt_SOPC *iFmt)
+ : Inst_SOPC(iFmt, "s_bitcmp0_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOPC__S_BITCMP0_B64
+
+ Inst_SOPC__S_BITCMP0_B64::~Inst_SOPC__S_BITCMP0_B64()
+ {
+ } // ~Inst_SOPC__S_BITCMP0_B64
+
+ // SCC = (S0.u64[S1.u[5:0]] == 0).
+ void
+ Inst_SOPC__S_BITCMP0_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ scc = !bits(src0.rawData(), bits(src1.rawData(), 5, 0)) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPC__S_BITCMP1_B64::Inst_SOPC__S_BITCMP1_B64(InFmt_SOPC *iFmt)
+ : Inst_SOPC(iFmt, "s_bitcmp1_b64")
+ {
+ setFlag(ALU);
+ } // Inst_SOPC__S_BITCMP1_B64
+
+ Inst_SOPC__S_BITCMP1_B64::~Inst_SOPC__S_BITCMP1_B64()
+ {
+ } // ~Inst_SOPC__S_BITCMP1_B64
+
+ // SCC = (S0.u64[S1.u[5:0]] == 1).
+ void
+ Inst_SOPC__S_BITCMP1_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ scc = bits(src0.rawData(), bits(src1.rawData(), 5, 0)) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPC__S_SETVSKIP::Inst_SOPC__S_SETVSKIP(InFmt_SOPC *iFmt)
+ : Inst_SOPC(iFmt, "s_setvskip")
+ {
+ setFlag(UnconditionalJump);
+ } // Inst_SOPC__S_SETVSKIP
+
+ Inst_SOPC__S_SETVSKIP::~Inst_SOPC__S_SETVSKIP()
+ {
+ } // ~Inst_SOPC__S_SETVSKIP
+
+ // VSKIP = S0.u[S1.u[4:0]].
+ // Enables and disables VSKIP mode.
+ // When VSKIP is enabled, no VOP*/M*BUF/MIMG/DS/FLAT/EXP instuctions are
+ // issued.
+ void
+ Inst_SOPC__S_SETVSKIP::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPC__S_SET_GPR_IDX_ON::Inst_SOPC__S_SET_GPR_IDX_ON(InFmt_SOPC *iFmt)
+ : Inst_SOPC(iFmt, "s_set_gpr_idx_on")
+ {
+ } // Inst_SOPC__S_SET_GPR_IDX_ON
+
+ Inst_SOPC__S_SET_GPR_IDX_ON::~Inst_SOPC__S_SET_GPR_IDX_ON()
+ {
+ } // ~Inst_SOPC__S_SET_GPR_IDX_ON
+
+ // MODE.gpr_idx_en = 1;
+ // M0[7:0] = S0.u[7:0];
+ // M0[15:12] = SIMM4 (direct contents of S1 field);
+ // Remaining bits of M0 are unmodified.
+ // Enable GPR indexing mode. Vector operations after this will perform
+ // relative GPR addressing based on the contents of M0.
+ // The raw contents of the S1 field are read and used to set the enable
+ // bits. S1[0] = VSRC0_REL, S1[1] = VSRC1_REL, S1[2] = VSRC2_REL and
+ // S1[3] = VDST_REL.
+ void
+ Inst_SOPC__S_SET_GPR_IDX_ON::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPC__S_CMP_EQ_U64::Inst_SOPC__S_CMP_EQ_U64(InFmt_SOPC *iFmt)
+ : Inst_SOPC(iFmt, "s_cmp_eq_u64")
+ {
+ setFlag(ALU);
+ } // Inst_SOPC__S_CMP_EQ_U64
+
+ Inst_SOPC__S_CMP_EQ_U64::~Inst_SOPC__S_CMP_EQ_U64()
+ {
+ } // ~Inst_SOPC__S_CMP_EQ_U64
+
+ // SCC = (S0.i64 == S1.i64).
+ void
+ Inst_SOPC__S_CMP_EQ_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI64 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandI64 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ scc = (src0.rawData() == src1.rawData()) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPC__S_CMP_LG_U64::Inst_SOPC__S_CMP_LG_U64(InFmt_SOPC *iFmt)
+ : Inst_SOPC(iFmt, "s_cmp_lg_u64")
+ {
+ setFlag(ALU);
+ } // Inst_SOPC__S_CMP_LG_U64
+
+ Inst_SOPC__S_CMP_LG_U64::~Inst_SOPC__S_CMP_LG_U64()
+ {
+ } // ~Inst_SOPC__S_CMP_LG_U64
+
+ // SCC = (S0.i64 != S1.i64).
+ void
+ Inst_SOPC__S_CMP_LG_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandI64 src0(gpuDynInst, instData.SSRC0);
+ ConstScalarOperandI64 src1(gpuDynInst, instData.SSRC1);
+ ScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ src0.read();
+ src1.read();
+
+ scc = (src0.rawData() != src1.rawData()) ? 1 : 0;
+
+ scc.write();
+ }
+
+ Inst_SOPP__S_NOP::Inst_SOPP__S_NOP(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_nop")
+ {
+ setFlag(Nop);
+ } // Inst_SOPP__S_NOP
+
+ Inst_SOPP__S_NOP::~Inst_SOPP__S_NOP()
+ {
+ } // ~Inst_SOPP__S_NOP
+
+ // Do nothing.
+ void
+ Inst_SOPP__S_NOP::execute(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_SOPP__S_ENDPGM::Inst_SOPP__S_ENDPGM(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_endpgm")
+ {
+ setFlag(EndOfKernel);
+ } // Inst_SOPP__S_ENDPGM
+
+ Inst_SOPP__S_ENDPGM::~Inst_SOPP__S_ENDPGM()
+ {
+ } // ~Inst_SOPP__S_ENDPGM
+
+ // End of program; terminate wavefront.
+ void
+ Inst_SOPP__S_ENDPGM::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ // delete extra instructions fetched for completed work-items
+ wf->instructionBuffer.erase(wf->instructionBuffer.begin() + 1,
+ wf->instructionBuffer.end());
+
+ if (wf->pendingFetch) {
+ wf->dropFetch = true;
+ }
+
+ wf->computeUnit->fetchStage.fetchUnit(wf->simdId)
+ .flushBuf(wf->wfSlotId);
+ wf->setStatus(Wavefront::S_STOPPED);
+
+ int refCount = wf->computeUnit->getLds()
+ .decreaseRefCounter(wf->dispatchId, wf->wgId);
+
+ DPRINTF(GPUExec, "CU%d: decrease ref ctr WG[%d] to [%d]\n",
+ wf->computeUnit->cu_id, wf->wgId, refCount);
+
+ wf->computeUnit->registerManager.freeRegisters(wf);
+ wf->computeUnit->completedWfs++;
+ wf->computeUnit->activeWaves--;
+
+ panic_if(wf->computeUnit->activeWaves < 0, "CU[%d] Active waves less "
+ "than zero\n", wf->computeUnit->cu_id);
+
+ DPRINTF(GPUExec, "Doing return for CU%d: WF[%d][%d][%d]\n",
+ wf->computeUnit->cu_id, wf->simdId, wf->wfSlotId, wf->wfDynId);
+
+ for (int i = 0; i < wf->vecReads.size(); i++) {
+ if (wf->rawDist.find(i) != wf->rawDist.end()) {
+ wf->readsPerWrite.sample(wf->vecReads.at(i));
+ }
+ }
+ wf->vecReads.clear();
+ wf->rawDist.clear();
+ wf->lastInstExec = 0;
+
+ if (!refCount) {
+ /**
+ * Last wavefront of the workgroup has executed return. If the
+ * workgroup is not the final one in the kernel, then simply
+ * retire it; however, if it is the final one (i.e., indicating
+ * the kernel end) then release operation is needed.
+ */
+
+ // check whether the workgroup is indicating the kernel end (i.e.,
+ // the last workgroup in the kernel).
+ bool kernelEnd =
+ wf->computeUnit->shader->dispatcher().isReachingKernelEnd(wf);
+
+ // if it is not a kernel end, then retire the workgroup directly
+ if (!kernelEnd) {
+ wf->computeUnit->shader->dispatcher().notifyWgCompl(wf);
+ wf->setStatus(Wavefront::S_STOPPED);
+ wf->computeUnit->completedWGs++;
+
+ return;
+ }
+
+ /**
+ * If it is a kernel end, inject a memory sync and retire the
+ * workgroup after receving response.
+ */
+ setFlag(MemSync);
+ setFlag(GlobalSegment);
+ // Notify Memory System of Kernel Completion
+ wf->setStatus(Wavefront::S_RETURNING);
+ gpuDynInst->simdId = wf->simdId;
+ gpuDynInst->wfSlotId = wf->wfSlotId;
+ gpuDynInst->wfDynId = wf->wfDynId;
+
+ DPRINTF(GPUExec, "inject global memory fence for CU%d: "
+ "WF[%d][%d][%d]\n", wf->computeUnit->cu_id,
+ wf->simdId, wf->wfSlotId, wf->wfDynId);
+
+ // call shader to prepare the flush operations
+ wf->computeUnit->shader->prepareFlush(gpuDynInst);
+
+ wf->computeUnit->completedWGs++;
+ } else {
+ wf->computeUnit->shader->dispatcher().scheduleDispatch();
+ }
+ }
+
+
+ Inst_SOPP__S_BRANCH::Inst_SOPP__S_BRANCH(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_branch")
+ {
+ setFlag(Branch);
+ } // Inst_SOPP__S_BRANCH
+
+ Inst_SOPP__S_BRANCH::~Inst_SOPP__S_BRANCH()
+ {
+ } // ~Inst_SOPP__S_BRANCH
+
+ // PC = PC + signext(SIMM16 * 4) + 4 (short jump).
+ void
+ Inst_SOPP__S_BRANCH::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ Addr pc = wf->pc();
+ ScalarRegI16 simm16 = instData.SIMM16;
+
+ pc = pc + ((ScalarRegI64)simm16 * 4LL) + 4LL;
+
+ wf->pc(pc);
+ }
+
+ Inst_SOPP__S_WAKEUP::Inst_SOPP__S_WAKEUP(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_wakeup")
+ {
+ } // Inst_SOPP__S_WAKEUP
+
+ Inst_SOPP__S_WAKEUP::~Inst_SOPP__S_WAKEUP()
+ {
+ } // ~Inst_SOPP__S_WAKEUP
+
+ // Allow a wave to wakeup all the other waves in its workgroup to force
+ // them to wake up immediately from an S_SLEEP instruction. The wakeup is
+ // ignored if the waves are not sleeping.
+ void
+ Inst_SOPP__S_WAKEUP::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPP__S_CBRANCH_SCC0::Inst_SOPP__S_CBRANCH_SCC0(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_cbranch_scc0")
+ {
+ setFlag(Branch);
+ } // Inst_SOPP__S_CBRANCH_SCC0
+
+ Inst_SOPP__S_CBRANCH_SCC0::~Inst_SOPP__S_CBRANCH_SCC0()
+ {
+ } // ~Inst_SOPP__S_CBRANCH_SCC0
+
+ // if (SCC == 0) then PC = PC + signext(SIMM16 * 4) + 4;
+ // else NOP.
+ void
+ Inst_SOPP__S_CBRANCH_SCC0::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ Addr pc = wf->pc();
+ ScalarRegI16 simm16 = instData.SIMM16;
+ ConstScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ scc.read();
+
+ if (!scc.rawData()) {
+ pc = pc + ((ScalarRegI64)simm16 * 4LL) + 4LL;
+ }
+
+ wf->pc(pc);
+ }
+
+ Inst_SOPP__S_CBRANCH_SCC1::Inst_SOPP__S_CBRANCH_SCC1(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_cbranch_scc1")
+ {
+ setFlag(Branch);
+ } // Inst_SOPP__S_CBRANCH_SCC1
+
+ Inst_SOPP__S_CBRANCH_SCC1::~Inst_SOPP__S_CBRANCH_SCC1()
+ {
+ } // ~Inst_SOPP__S_CBRANCH_SCC1
+
+ // if (SCC == 1) then PC = PC + signext(SIMM16 * 4) + 4;
+ // else NOP.
+ void
+ Inst_SOPP__S_CBRANCH_SCC1::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ Addr pc = wf->pc();
+ ScalarRegI16 simm16 = instData.SIMM16;
+ ConstScalarOperandU32 scc(gpuDynInst, REG_SCC);
+
+ scc.read();
+
+ if (scc.rawData()) {
+ pc = pc + ((ScalarRegI64)simm16 * 4LL) + 4LL;
+ }
+
+ wf->pc(pc);
+ }
+
+ Inst_SOPP__S_CBRANCH_VCCZ::Inst_SOPP__S_CBRANCH_VCCZ(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_cbranch_vccz")
+ {
+ setFlag(Branch);
+ setFlag(ReadsVCC);
+ } // Inst_SOPP__S_CBRANCH_VCCZ
+
+ Inst_SOPP__S_CBRANCH_VCCZ::~Inst_SOPP__S_CBRANCH_VCCZ()
+ {
+ } // ~Inst_SOPP__S_CBRANCH_VCCZ
+
+ // if (VCC == 0) then PC = PC + signext(SIMM16 * 4) + 4;
+ // else NOP.
+ void
+ Inst_SOPP__S_CBRANCH_VCCZ::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+ Addr pc = wf->pc();
+ ScalarRegI16 simm16 = instData.SIMM16;
+
+ vcc.read();
+
+ if (!vcc.rawData()) {
+ pc = pc + ((ScalarRegI64)simm16 * 4LL) + 4LL;
+ }
+
+ wf->pc(pc);
+ }
+
+ Inst_SOPP__S_CBRANCH_VCCNZ::Inst_SOPP__S_CBRANCH_VCCNZ(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_cbranch_vccnz")
+ {
+ setFlag(Branch);
+ setFlag(ReadsVCC);
+ } // Inst_SOPP__S_CBRANCH_VCCNZ
+
+ Inst_SOPP__S_CBRANCH_VCCNZ::~Inst_SOPP__S_CBRANCH_VCCNZ()
+ {
+ } // ~Inst_SOPP__S_CBRANCH_VCCNZ
+
+ // if (VCC != 0) then PC = PC + signext(SIMM16 * 4) + 4;
+ // else NOP.
+ void
+ Inst_SOPP__S_CBRANCH_VCCNZ::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ vcc.read();
+
+ if (vcc.rawData()) {
+ Addr pc = wf->pc();
+ ScalarRegI16 simm16 = instData.SIMM16;
+ pc = pc + ((ScalarRegI64)simm16 * 4LL) + 4LL;
+ wf->pc(pc);
+ }
+ }
+
+ Inst_SOPP__S_CBRANCH_EXECZ::Inst_SOPP__S_CBRANCH_EXECZ(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_cbranch_execz")
+ {
+ setFlag(Branch);
+ } // Inst_SOPP__S_CBRANCH_EXECZ
+
+ Inst_SOPP__S_CBRANCH_EXECZ::~Inst_SOPP__S_CBRANCH_EXECZ()
+ {
+ } // ~Inst_SOPP__S_CBRANCH_EXECZ
+
+ // if (EXEC == 0) then PC = PC + signext(SIMM16 * 4) + 4;
+ // else NOP.
+ void
+ Inst_SOPP__S_CBRANCH_EXECZ::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ if (wf->execMask().none()) {
+ Addr pc = wf->pc();
+ ScalarRegI16 simm16 = instData.SIMM16;
+ pc = pc + ((ScalarRegI64)simm16 * 4LL) + 4LL;
+ wf->pc(pc);
+ }
+ }
+
+ Inst_SOPP__S_CBRANCH_EXECNZ::Inst_SOPP__S_CBRANCH_EXECNZ(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_cbranch_execnz")
+ {
+ setFlag(Branch);
+ } // Inst_SOPP__S_CBRANCH_EXECNZ
+
+ Inst_SOPP__S_CBRANCH_EXECNZ::~Inst_SOPP__S_CBRANCH_EXECNZ()
+ {
+ } // ~Inst_SOPP__S_CBRANCH_EXECNZ
+
+ // if (EXEC != 0) then PC = PC + signext(SIMM16 * 4) + 4;
+ // else NOP.
+ void
+ Inst_SOPP__S_CBRANCH_EXECNZ::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ if (wf->execMask().any()) {
+ Addr pc = wf->pc();
+ ScalarRegI16 simm16 = instData.SIMM16;
+ pc = pc + ((ScalarRegI64)simm16 * 4LL) + 4LL;
+ wf->pc(pc);
+ }
+ }
+
+ Inst_SOPP__S_BARRIER::Inst_SOPP__S_BARRIER(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_barrier")
+ {
+ setFlag(MemBarrier);
+ } // Inst_SOPP__S_BARRIER
+
+ Inst_SOPP__S_BARRIER::~Inst_SOPP__S_BARRIER()
+ {
+ } // ~Inst_SOPP__S_BARRIER
+
+ /**
+ * Synchronize waves within a workgroup. If not all waves of the workgroup
+ * have been created yet, wait for entire group before proceeding. If some
+ * waves in the wokgroup have already terminated, this waits on only the
+ * surviving waves.
+ */
+ void
+ Inst_SOPP__S_BARRIER::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ assert(wf->barrierCnt == wf->oldBarrierCnt);
+
+ wf->barrierCnt = wf->oldBarrierCnt + 1;
+ wf->stalledAtBarrier = true;
+ }
+
+ Inst_SOPP__S_SETKILL::Inst_SOPP__S_SETKILL(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_setkill")
+ {
+ } // Inst_SOPP__S_SETKILL
+
+ Inst_SOPP__S_SETKILL::~Inst_SOPP__S_SETKILL()
+ {
+ } // ~Inst_SOPP__S_SETKILL
+
+ void
+ Inst_SOPP__S_SETKILL::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPP__S_WAITCNT::Inst_SOPP__S_WAITCNT(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_waitcnt")
+ {
+ setFlag(ALU);
+ setFlag(Waitcnt);
+ } // Inst_SOPP__S_WAITCNT
+
+ Inst_SOPP__S_WAITCNT::~Inst_SOPP__S_WAITCNT()
+ {
+ } // ~Inst_SOPP__S_WAITCNT
+
+ // Wait for the counts of outstanding lds, vector-memory and
+ // export/vmem-write-data to be at or below the specified levels.
+ // SIMM16[3:0] = vmcount (vector memory operations),
+ // SIMM16[6:4] = export/mem-write-data count,
+ // SIMM16[12:8] = LGKM_cnt (scalar-mem/GDS/LDS count).
+ void
+ Inst_SOPP__S_WAITCNT::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ScalarRegI32 vm_cnt = 0;
+ ScalarRegI32 exp_cnt = 0;
+ ScalarRegI32 lgkm_cnt = 0;
+ vm_cnt = bits<ScalarRegI16>(instData.SIMM16, 3, 0);
+ exp_cnt = bits<ScalarRegI16>(instData.SIMM16, 6, 4);
+ lgkm_cnt = bits<ScalarRegI16>(instData.SIMM16, 12, 8);
+ gpuDynInst->wavefront()->setWaitCnts(vm_cnt, exp_cnt, lgkm_cnt);
+ }
+
+ Inst_SOPP__S_SETHALT::Inst_SOPP__S_SETHALT(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_sethalt")
+ {
+ } // Inst_SOPP__S_SETHALT
+
+ Inst_SOPP__S_SETHALT::~Inst_SOPP__S_SETHALT()
+ {
+ } // ~Inst_SOPP__S_SETHALT
+
+ void
+ Inst_SOPP__S_SETHALT::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPP__S_SLEEP::Inst_SOPP__S_SLEEP(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_sleep")
+ {
+ } // Inst_SOPP__S_SLEEP
+
+ Inst_SOPP__S_SLEEP::~Inst_SOPP__S_SLEEP()
+ {
+ } // ~Inst_SOPP__S_SLEEP
+
+ // Cause a wave to sleep for (64 * SIMM16[2:0] + 1..64) clocks.
+ void
+ Inst_SOPP__S_SLEEP::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPP__S_SETPRIO::Inst_SOPP__S_SETPRIO(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_setprio")
+ {
+ } // Inst_SOPP__S_SETPRIO
+
+ Inst_SOPP__S_SETPRIO::~Inst_SOPP__S_SETPRIO()
+ {
+ } // ~Inst_SOPP__S_SETPRIO
+
+ // User settable wave priority is set to SIMM16[1:0]. 0 = lowest,
+ // 3 = highest.
+ void
+ Inst_SOPP__S_SETPRIO::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPP__S_SENDMSG::Inst_SOPP__S_SENDMSG(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_sendmsg")
+ {
+ } // Inst_SOPP__S_SENDMSG
+
+ Inst_SOPP__S_SENDMSG::~Inst_SOPP__S_SENDMSG()
+ {
+ } // ~Inst_SOPP__S_SENDMSG
+
+ void
+ Inst_SOPP__S_SENDMSG::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPP__S_SENDMSGHALT::Inst_SOPP__S_SENDMSGHALT(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_sendmsghalt")
+ {
+ } // Inst_SOPP__S_SENDMSGHALT
+
+ Inst_SOPP__S_SENDMSGHALT::~Inst_SOPP__S_SENDMSGHALT()
+ {
+ } // ~Inst_SOPP__S_SENDMSGHALT
+
+ void
+ Inst_SOPP__S_SENDMSGHALT::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPP__S_TRAP::Inst_SOPP__S_TRAP(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_trap")
+ {
+ } // Inst_SOPP__S_TRAP
+
+ Inst_SOPP__S_TRAP::~Inst_SOPP__S_TRAP()
+ {
+ } // ~Inst_SOPP__S_TRAP
+
+ // Enter the trap handler.
+ void
+ Inst_SOPP__S_TRAP::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPP__S_ICACHE_INV::Inst_SOPP__S_ICACHE_INV(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_icache_inv")
+ {
+ } // Inst_SOPP__S_ICACHE_INV
+
+ Inst_SOPP__S_ICACHE_INV::~Inst_SOPP__S_ICACHE_INV()
+ {
+ } // ~Inst_SOPP__S_ICACHE_INV
+
+ // Invalidate entire L1 instruction cache.
+ void
+ Inst_SOPP__S_ICACHE_INV::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPP__S_INCPERFLEVEL::Inst_SOPP__S_INCPERFLEVEL(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_incperflevel")
+ {
+ } // Inst_SOPP__S_INCPERFLEVEL
+
+ Inst_SOPP__S_INCPERFLEVEL::~Inst_SOPP__S_INCPERFLEVEL()
+ {
+ } // ~Inst_SOPP__S_INCPERFLEVEL
+
+ void
+ Inst_SOPP__S_INCPERFLEVEL::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPP__S_DECPERFLEVEL::Inst_SOPP__S_DECPERFLEVEL(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_decperflevel")
+ {
+ } // Inst_SOPP__S_DECPERFLEVEL
+
+ Inst_SOPP__S_DECPERFLEVEL::~Inst_SOPP__S_DECPERFLEVEL()
+ {
+ } // ~Inst_SOPP__S_DECPERFLEVEL
+
+ void
+ Inst_SOPP__S_DECPERFLEVEL::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPP__S_TTRACEDATA::Inst_SOPP__S_TTRACEDATA(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_ttracedata")
+ {
+ } // Inst_SOPP__S_TTRACEDATA
+
+ Inst_SOPP__S_TTRACEDATA::~Inst_SOPP__S_TTRACEDATA()
+ {
+ } // ~Inst_SOPP__S_TTRACEDATA
+
+ void
+ Inst_SOPP__S_TTRACEDATA::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPP__S_CBRANCH_CDBGSYS::Inst_SOPP__S_CBRANCH_CDBGSYS(
+ InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_cbranch_cdbgsys")
+ {
+ setFlag(Branch);
+ } // Inst_SOPP__S_CBRANCH_CDBGSYS
+
+ Inst_SOPP__S_CBRANCH_CDBGSYS::~Inst_SOPP__S_CBRANCH_CDBGSYS()
+ {
+ } // ~Inst_SOPP__S_CBRANCH_CDBGSYS
+
+ void
+ Inst_SOPP__S_CBRANCH_CDBGSYS::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPP__S_CBRANCH_CDBGUSER::Inst_SOPP__S_CBRANCH_CDBGUSER(
+ InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_cbranch_cdbguser")
+ {
+ setFlag(Branch);
+ } // Inst_SOPP__S_CBRANCH_CDBGUSER
+
+ Inst_SOPP__S_CBRANCH_CDBGUSER::~Inst_SOPP__S_CBRANCH_CDBGUSER()
+ {
+ } // ~Inst_SOPP__S_CBRANCH_CDBGUSER
+
+ void
+ Inst_SOPP__S_CBRANCH_CDBGUSER::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPP__S_CBRANCH_CDBGSYS_OR_USER::Inst_SOPP__S_CBRANCH_CDBGSYS_OR_USER(
+ InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_cbranch_cdbgsys_or_user")
+ {
+ setFlag(Branch);
+ } // Inst_SOPP__S_CBRANCH_CDBGSYS_OR_USER
+
+ Inst_SOPP__S_CBRANCH_CDBGSYS_OR_USER::
+ ~Inst_SOPP__S_CBRANCH_CDBGSYS_OR_USER()
+ {
+ } // ~Inst_SOPP__S_CBRANCH_CDBGSYS_OR_USER
+
+ void
+ Inst_SOPP__S_CBRANCH_CDBGSYS_OR_USER::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPP__S_CBRANCH_CDBGSYS_AND_USER::
+ Inst_SOPP__S_CBRANCH_CDBGSYS_AND_USER(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_cbranch_cdbgsys_and_user")
+ {
+ setFlag(Branch);
+ } // Inst_SOPP__S_CBRANCH_CDBGSYS_AND_USER
+
+ Inst_SOPP__S_CBRANCH_CDBGSYS_AND_USER::
+ ~Inst_SOPP__S_CBRANCH_CDBGSYS_AND_USER()
+ {
+ } // ~Inst_SOPP__S_CBRANCH_CDBGSYS_AND_USER
+
+ void
+ Inst_SOPP__S_CBRANCH_CDBGSYS_AND_USER::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPP__S_ENDPGM_SAVED::Inst_SOPP__S_ENDPGM_SAVED(InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_endpgm_saved")
+ {
+ } // Inst_SOPP__S_ENDPGM_SAVED
+
+ Inst_SOPP__S_ENDPGM_SAVED::~Inst_SOPP__S_ENDPGM_SAVED()
+ {
+ } // ~Inst_SOPP__S_ENDPGM_SAVED
+
+ // End of program.
+ void
+ Inst_SOPP__S_ENDPGM_SAVED::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPP__S_SET_GPR_IDX_OFF::Inst_SOPP__S_SET_GPR_IDX_OFF(
+ InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_set_gpr_idx_off")
+ {
+ } // Inst_SOPP__S_SET_GPR_IDX_OFF
+
+ Inst_SOPP__S_SET_GPR_IDX_OFF::~Inst_SOPP__S_SET_GPR_IDX_OFF()
+ {
+ } // ~Inst_SOPP__S_SET_GPR_IDX_OFF
+
+ // MODE.gpr_idx_en = 0.
+ // Clear GPR indexing mode. Vector operations after this will not perform
+ // relative GPR addressing regardless of the contents of M0.
+ void
+ Inst_SOPP__S_SET_GPR_IDX_OFF::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SOPP__S_SET_GPR_IDX_MODE::Inst_SOPP__S_SET_GPR_IDX_MODE(
+ InFmt_SOPP *iFmt)
+ : Inst_SOPP(iFmt, "s_set_gpr_idx_mode")
+ {
+ } // Inst_SOPP__S_SET_GPR_IDX_MODE
+
+ Inst_SOPP__S_SET_GPR_IDX_MODE::~Inst_SOPP__S_SET_GPR_IDX_MODE()
+ {
+ } // ~Inst_SOPP__S_SET_GPR_IDX_MODE
+
+ // M0[15:12] = SIMM4.
+ // Modify the mode used for vector GPR indexing.
+ // The raw contents of the source field are read and used to set the enable
+ // bits. SIMM4[0] = VSRC0_REL, SIMM4[1] = VSRC1_REL, SIMM4[2] = VSRC2_REL
+ // and SIMM4[3] = VDST_REL.
+ void
+ Inst_SOPP__S_SET_GPR_IDX_MODE::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SMEM__S_LOAD_DWORD::Inst_SMEM__S_LOAD_DWORD(InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_load_dword")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_SMEM__S_LOAD_DWORD
+
+ Inst_SMEM__S_LOAD_DWORD::~Inst_SMEM__S_LOAD_DWORD()
+ {
+ } // ~Inst_SMEM__S_LOAD_DWORD
+
+ /**
+ * Read 1 dword from scalar data cache. If the offset is specified as an
+ * sgpr, the sgpr contains an unsigned byte offset (the 2 LSBs are
+ * ignored). If the offset is specified as an immediate 20-bit constant,
+ * the constant is an unsigned byte offset.
+ */
+ void
+ Inst_SMEM__S_LOAD_DWORD::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+ ScalarRegU32 offset(0);
+ ConstScalarOperandU64 addr(gpuDynInst, instData.SBASE << 1);
+
+ addr.read();
+
+ if (instData.IMM) {
+ offset = extData.OFFSET;
+ } else {
+ ConstScalarOperandU32 off_sgpr(gpuDynInst, extData.OFFSET);
+ off_sgpr.read();
+ offset = off_sgpr.rawData();
+ }
+
+ calcAddr(gpuDynInst, addr, offset);
+
+ gpuDynInst->computeUnit()->scalarMemoryPipe
+ .getGMReqFIFO().push(gpuDynInst);
+
+ wf->scalarRdGmReqsInPipe--;
+ wf->scalarOutstandingReqsRdGm++;
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ }
+
+ void
+ Inst_SMEM__S_LOAD_DWORD::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ initMemRead<1>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_SMEM__S_LOAD_DWORD::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ ScalarOperandU32 sdst(gpuDynInst, instData.SDATA);
+ sdst.write();
+ } // completeAcc
+
+ Inst_SMEM__S_LOAD_DWORDX2::Inst_SMEM__S_LOAD_DWORDX2(InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_load_dwordx2")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_SMEM__S_LOAD_DWORDX2
+
+ Inst_SMEM__S_LOAD_DWORDX2::~Inst_SMEM__S_LOAD_DWORDX2()
+ {
+ } // ~Inst_SMEM__S_LOAD_DWORDX2
+
+ /**
+ * Read 2 dwords from scalar data cache. See s_load_dword for details on
+ * the offset input.
+ */
+ void
+ Inst_SMEM__S_LOAD_DWORDX2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+ ScalarRegU32 offset(0);
+ ConstScalarOperandU64 addr(gpuDynInst, instData.SBASE << 1);
+
+ addr.read();
+
+ if (instData.IMM) {
+ offset = extData.OFFSET;
+ } else {
+ ConstScalarOperandU32 off_sgpr(gpuDynInst, extData.OFFSET);
+ off_sgpr.read();
+ offset = off_sgpr.rawData();
+ }
+
+ calcAddr(gpuDynInst, addr, offset);
+
+ gpuDynInst->computeUnit()->scalarMemoryPipe.
+ getGMReqFIFO().push(gpuDynInst);
+
+ wf->scalarRdGmReqsInPipe--;
+ wf->scalarOutstandingReqsRdGm++;
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ }
+
+ void
+ Inst_SMEM__S_LOAD_DWORDX2::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ initMemRead<2>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_SMEM__S_LOAD_DWORDX2::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDATA);
+ sdst.write();
+ } // completeAcc
+
+ Inst_SMEM__S_LOAD_DWORDX4::Inst_SMEM__S_LOAD_DWORDX4(InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_load_dwordx4")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_SMEM__S_LOAD_DWORDX4
+
+ Inst_SMEM__S_LOAD_DWORDX4::~Inst_SMEM__S_LOAD_DWORDX4()
+ {
+ } // ~Inst_SMEM__S_LOAD_DWORDX4
+
+ // Read 4 dwords from scalar data cache. See S_LOAD_DWORD for details on
+ // the offset input.
+ void
+ Inst_SMEM__S_LOAD_DWORDX4::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+ ScalarRegU32 offset(0);
+ ConstScalarOperandU64 addr(gpuDynInst, instData.SBASE << 1);
+
+ addr.read();
+
+ if (instData.IMM) {
+ offset = extData.OFFSET;
+ } else {
+ ConstScalarOperandU32 off_sgpr(gpuDynInst, extData.OFFSET);
+ off_sgpr.read();
+ offset = off_sgpr.rawData();
+ }
+
+ calcAddr(gpuDynInst, addr, offset);
+
+ gpuDynInst->computeUnit()->scalarMemoryPipe.
+ getGMReqFIFO().push(gpuDynInst);
+
+ wf->scalarRdGmReqsInPipe--;
+ wf->scalarOutstandingReqsRdGm++;
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ }
+
+ void
+ Inst_SMEM__S_LOAD_DWORDX4::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ initMemRead<4>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_SMEM__S_LOAD_DWORDX4::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ ScalarOperandU128 sdst(gpuDynInst, instData.SDATA);
+ sdst.write();
+ } // completeAcc
+
+ Inst_SMEM__S_LOAD_DWORDX8::Inst_SMEM__S_LOAD_DWORDX8(InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_load_dwordx8")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_SMEM__S_LOAD_DWORDX8
+
+ Inst_SMEM__S_LOAD_DWORDX8::~Inst_SMEM__S_LOAD_DWORDX8()
+ {
+ } // ~Inst_SMEM__S_LOAD_DWORDX8
+
+ // Read 8 dwords from scalar data cache. See S_LOAD_DWORD for details on
+ // the offset input.
+ void
+ Inst_SMEM__S_LOAD_DWORDX8::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+ ScalarRegU32 offset(0);
+ ConstScalarOperandU64 addr(gpuDynInst, instData.SBASE << 1);
+
+ addr.read();
+
+ if (instData.IMM) {
+ offset = extData.OFFSET;
+ } else {
+ ConstScalarOperandU32 off_sgpr(gpuDynInst, extData.OFFSET);
+ off_sgpr.read();
+ offset = off_sgpr.rawData();
+ }
+
+ calcAddr(gpuDynInst, addr, offset);
+
+ gpuDynInst->computeUnit()->scalarMemoryPipe.
+ getGMReqFIFO().push(gpuDynInst);
+
+ wf->scalarRdGmReqsInPipe--;
+ wf->scalarOutstandingReqsRdGm++;
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ }
+
+ void
+ Inst_SMEM__S_LOAD_DWORDX8::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ initMemRead<8>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_SMEM__S_LOAD_DWORDX8::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ ScalarOperandU256 sdst(gpuDynInst, instData.SDATA);
+ sdst.write();
+ } // completeAcc
+
+ Inst_SMEM__S_LOAD_DWORDX16::Inst_SMEM__S_LOAD_DWORDX16(InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_load_dwordx16")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_SMEM__S_LOAD_DWORDX16
+
+ Inst_SMEM__S_LOAD_DWORDX16::~Inst_SMEM__S_LOAD_DWORDX16()
+ {
+ } // ~Inst_SMEM__S_LOAD_DWORDX16
+
+ // Read 16 dwords from scalar data cache. See S_LOAD_DWORD for details on
+ // the offset input.
+ void
+ Inst_SMEM__S_LOAD_DWORDX16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+ ScalarRegU32 offset(0);
+ ConstScalarOperandU64 addr(gpuDynInst, instData.SBASE << 1);
+
+ addr.read();
+
+ if (instData.IMM) {
+ offset = extData.OFFSET;
+ } else {
+ ConstScalarOperandU32 off_sgpr(gpuDynInst, extData.OFFSET);
+ off_sgpr.read();
+ offset = off_sgpr.rawData();
+ }
+
+ calcAddr(gpuDynInst, addr, offset);
+
+ gpuDynInst->computeUnit()->scalarMemoryPipe.
+ getGMReqFIFO().push(gpuDynInst);
+
+ wf->scalarRdGmReqsInPipe--;
+ wf->scalarOutstandingReqsRdGm++;
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ }
+
+ void
+ Inst_SMEM__S_LOAD_DWORDX16::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ initMemRead<16>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_SMEM__S_LOAD_DWORDX16::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ ScalarOperandU512 sdst(gpuDynInst, instData.SDATA);
+ sdst.write();
+ } // completeAcc
+
+ Inst_SMEM__S_BUFFER_LOAD_DWORD::Inst_SMEM__S_BUFFER_LOAD_DWORD(
+ InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_buffer_load_dword")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_SMEM__S_BUFFER_LOAD_DWORD
+
+ Inst_SMEM__S_BUFFER_LOAD_DWORD::~Inst_SMEM__S_BUFFER_LOAD_DWORD()
+ {
+ } // ~Inst_SMEM__S_BUFFER_LOAD_DWORD
+
+ // Read 1 dword from scalar data cache. See S_LOAD_DWORD for details on the
+ // offset input.
+ void
+ Inst_SMEM__S_BUFFER_LOAD_DWORD::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_SMEM__S_BUFFER_LOAD_DWORD::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_SMEM__S_BUFFER_LOAD_DWORD::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX2::Inst_SMEM__S_BUFFER_LOAD_DWORDX2(
+ InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_buffer_load_dwordx2")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_SMEM__S_BUFFER_LOAD_DWORDX2
+
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX2::~Inst_SMEM__S_BUFFER_LOAD_DWORDX2()
+ {
+ } // ~Inst_SMEM__S_BUFFER_LOAD_DWORDX2
+
+ // Read 2 dwords from scalar data cache. See S_LOAD_DWORD for details on
+ // the offset input.
+ void
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX2::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX2::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX4::Inst_SMEM__S_BUFFER_LOAD_DWORDX4(
+ InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_buffer_load_dwordx4")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_SMEM__S_BUFFER_LOAD_DWORDX4
+
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX4::~Inst_SMEM__S_BUFFER_LOAD_DWORDX4()
+ {
+ } // ~Inst_SMEM__S_BUFFER_LOAD_DWORDX4
+
+ // Read 4 dwords from scalar data cache. See S_LOAD_DWORD for details on
+ // the offset input.
+ void
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX4::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX4::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX4::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX8::Inst_SMEM__S_BUFFER_LOAD_DWORDX8(
+ InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_buffer_load_dwordx8")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_SMEM__S_BUFFER_LOAD_DWORDX8
+
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX8::~Inst_SMEM__S_BUFFER_LOAD_DWORDX8()
+ {
+ } // ~Inst_SMEM__S_BUFFER_LOAD_DWORDX8
+
+ // Read 8 dwords from scalar data cache. See S_LOAD_DWORD for details on
+ // the offset input.
+ void
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX8::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX8::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX8::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX16::Inst_SMEM__S_BUFFER_LOAD_DWORDX16(
+ InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_buffer_load_dwordx16")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_SMEM__S_BUFFER_LOAD_DWORDX16
+
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX16::~Inst_SMEM__S_BUFFER_LOAD_DWORDX16()
+ {
+ } // ~Inst_SMEM__S_BUFFER_LOAD_DWORDX16
+
+ // Read 16 dwords from scalar data cache. See S_LOAD_DWORD for details on
+ // the offset input.
+ void
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX16::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX16::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_SMEM__S_STORE_DWORD::Inst_SMEM__S_STORE_DWORD(InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_store_dword")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_SMEM__S_STORE_DWORD
+
+ Inst_SMEM__S_STORE_DWORD::~Inst_SMEM__S_STORE_DWORD()
+ {
+ } // ~Inst_SMEM__S_STORE_DWORD
+
+ // Write 1 dword to scalar data cache.
+ // If the offset is specified as an SGPR, the SGPR contains an unsigned
+ // BYTE offset (the 2 LSBs are ignored).
+ // If the offset is specified as an immediate 20-bit constant, the
+ // constant is an unsigned BYTE offset.
+ void
+ Inst_SMEM__S_STORE_DWORD::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+ ScalarRegU32 offset(0);
+ ConstScalarOperandU64 addr(gpuDynInst, instData.SBASE << 1);
+
+ addr.read();
+
+ if (instData.IMM) {
+ offset = extData.OFFSET;
+ } else {
+ ConstScalarOperandU32 off_sgpr(gpuDynInst, extData.OFFSET);
+ off_sgpr.read();
+ offset = off_sgpr.rawData();
+ }
+
+ calcAddr(gpuDynInst, addr, offset);
+
+ gpuDynInst->computeUnit()->scalarMemoryPipe.
+ getGMReqFIFO().push(gpuDynInst);
+
+ wf->scalarWrGmReqsInPipe--;
+ wf->scalarOutstandingReqsWrGm++;
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ }
+
+ void
+ Inst_SMEM__S_STORE_DWORD::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 sdata(gpuDynInst, instData.SDATA);
+ sdata.read();
+ std::memcpy((void*)gpuDynInst->scalar_data, sdata.rawDataPtr(),
+ sizeof(ScalarRegU32));
+ initMemWrite<1>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_SMEM__S_STORE_DWORD::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_SMEM__S_STORE_DWORDX2::Inst_SMEM__S_STORE_DWORDX2(InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_store_dwordx2")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_SMEM__S_STORE_DWORDX2
+
+ Inst_SMEM__S_STORE_DWORDX2::~Inst_SMEM__S_STORE_DWORDX2()
+ {
+ } // ~Inst_SMEM__S_STORE_DWORDX2
+
+ // Write 2 dwords to scalar data cache. See S_STORE_DWORD for details on
+ // the offset input.
+ void
+ Inst_SMEM__S_STORE_DWORDX2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+ ScalarRegU32 offset(0);
+ ConstScalarOperandU64 addr(gpuDynInst, instData.SBASE << 1);
+
+ addr.read();
+
+ if (instData.IMM) {
+ offset = extData.OFFSET;
+ } else {
+ ConstScalarOperandU32 off_sgpr(gpuDynInst, extData.OFFSET);
+ off_sgpr.read();
+ offset = off_sgpr.rawData();
+ }
+
+ calcAddr(gpuDynInst, addr, offset);
+
+ gpuDynInst->computeUnit()->scalarMemoryPipe.
+ getGMReqFIFO().push(gpuDynInst);
+
+ wf->scalarWrGmReqsInPipe--;
+ wf->scalarOutstandingReqsWrGm++;
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ }
+
+ void
+ Inst_SMEM__S_STORE_DWORDX2::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 sdata(gpuDynInst, instData.SDATA);
+ sdata.read();
+ std::memcpy((void*)gpuDynInst->scalar_data, sdata.rawDataPtr(),
+ sizeof(ScalarRegU64));
+ initMemWrite<2>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_SMEM__S_STORE_DWORDX2::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_SMEM__S_STORE_DWORDX4::Inst_SMEM__S_STORE_DWORDX4(InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_store_dwordx4")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_SMEM__S_STORE_DWORDX4
+
+ Inst_SMEM__S_STORE_DWORDX4::~Inst_SMEM__S_STORE_DWORDX4()
+ {
+ } // ~Inst_SMEM__S_STORE_DWORDX4
+
+ // Write 4 dwords to scalar data cache. See S_STORE_DWORD for details on
+ // the offset input.
+ void
+ Inst_SMEM__S_STORE_DWORDX4::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+ ScalarRegU32 offset(0);
+ ConstScalarOperandU64 addr(gpuDynInst, instData.SBASE << 1);
+
+ addr.read();
+
+ if (instData.IMM) {
+ offset = extData.OFFSET;
+ } else {
+ ConstScalarOperandU32 off_sgpr(gpuDynInst, extData.OFFSET);
+ off_sgpr.read();
+ offset = off_sgpr.rawData();
+ }
+
+ calcAddr(gpuDynInst, addr, offset);
+
+ gpuDynInst->computeUnit()->scalarMemoryPipe.
+ getGMReqFIFO().push(gpuDynInst);
+
+ wf->scalarWrGmReqsInPipe--;
+ wf->scalarOutstandingReqsWrGm++;
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ }
+
+ void
+ Inst_SMEM__S_STORE_DWORDX4::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU64 sdata(gpuDynInst, instData.SDATA);
+ sdata.read();
+ std::memcpy((void*)gpuDynInst->scalar_data, sdata.rawDataPtr(),
+ 4 * sizeof(ScalarRegU32));
+ initMemWrite<4>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_SMEM__S_STORE_DWORDX4::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_SMEM__S_BUFFER_STORE_DWORD::Inst_SMEM__S_BUFFER_STORE_DWORD(
+ InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_buffer_store_dword")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_SMEM__S_BUFFER_STORE_DWORD
+
+ Inst_SMEM__S_BUFFER_STORE_DWORD::~Inst_SMEM__S_BUFFER_STORE_DWORD()
+ {
+ } // ~Inst_SMEM__S_BUFFER_STORE_DWORD
+
+ // Write 1 dword to scalar data cache. See S_STORE_DWORD for details on the
+ // offset input.
+ void
+ Inst_SMEM__S_BUFFER_STORE_DWORD::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_SMEM__S_BUFFER_STORE_DWORD::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_SMEM__S_BUFFER_STORE_DWORD::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_SMEM__S_BUFFER_STORE_DWORDX2::Inst_SMEM__S_BUFFER_STORE_DWORDX2(
+ InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_buffer_store_dwordx2")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_SMEM__S_BUFFER_STORE_DWORDX2
+
+ Inst_SMEM__S_BUFFER_STORE_DWORDX2::~Inst_SMEM__S_BUFFER_STORE_DWORDX2()
+ {
+ } // ~Inst_SMEM__S_BUFFER_STORE_DWORDX2
+
+ // Write 2 dwords to scalar data cache. See S_STORE_DWORD for details on
+ // the offset input.
+ void
+ Inst_SMEM__S_BUFFER_STORE_DWORDX2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_SMEM__S_BUFFER_STORE_DWORDX2::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_SMEM__S_BUFFER_STORE_DWORDX2::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_SMEM__S_BUFFER_STORE_DWORDX4::Inst_SMEM__S_BUFFER_STORE_DWORDX4(
+ InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_buffer_store_dwordx4")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_SMEM__S_BUFFER_STORE_DWORDX4
+
+ Inst_SMEM__S_BUFFER_STORE_DWORDX4::~Inst_SMEM__S_BUFFER_STORE_DWORDX4()
+ {
+ } // ~Inst_SMEM__S_BUFFER_STORE_DWORDX4
+
+ // Write 4 dwords to scalar data cache. See S_STORE_DWORD for details on
+ // the offset input.
+ void
+ Inst_SMEM__S_BUFFER_STORE_DWORDX4::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_SMEM__S_BUFFER_STORE_DWORDX4::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_SMEM__S_BUFFER_STORE_DWORDX4::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_SMEM__S_DCACHE_INV::Inst_SMEM__S_DCACHE_INV(InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_dcache_inv")
+ {
+ } // Inst_SMEM__S_DCACHE_INV
+
+ Inst_SMEM__S_DCACHE_INV::~Inst_SMEM__S_DCACHE_INV()
+ {
+ } // ~Inst_SMEM__S_DCACHE_INV
+
+ // Invalidate the scalar data cache.
+ void
+ Inst_SMEM__S_DCACHE_INV::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SMEM__S_DCACHE_WB::Inst_SMEM__S_DCACHE_WB(InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_dcache_wb")
+ {
+ } // Inst_SMEM__S_DCACHE_WB
+
+ Inst_SMEM__S_DCACHE_WB::~Inst_SMEM__S_DCACHE_WB()
+ {
+ } // ~Inst_SMEM__S_DCACHE_WB
+
+ // Write back dirty data in the scalar data cache.
+ void
+ Inst_SMEM__S_DCACHE_WB::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SMEM__S_DCACHE_INV_VOL::Inst_SMEM__S_DCACHE_INV_VOL(InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_dcache_inv_vol")
+ {
+ } // Inst_SMEM__S_DCACHE_INV_VOL
+
+ Inst_SMEM__S_DCACHE_INV_VOL::~Inst_SMEM__S_DCACHE_INV_VOL()
+ {
+ } // ~Inst_SMEM__S_DCACHE_INV_VOL
+
+ // Invalidate the scalar data cache volatile lines.
+ void
+ Inst_SMEM__S_DCACHE_INV_VOL::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SMEM__S_DCACHE_WB_VOL::Inst_SMEM__S_DCACHE_WB_VOL(InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_dcache_wb_vol")
+ {
+ } // Inst_SMEM__S_DCACHE_WB_VOL
+
+ Inst_SMEM__S_DCACHE_WB_VOL::~Inst_SMEM__S_DCACHE_WB_VOL()
+ {
+ } // ~Inst_SMEM__S_DCACHE_WB_VOL
+
+ // Write back dirty data in the scalar data cache volatile lines.
+ void
+ Inst_SMEM__S_DCACHE_WB_VOL::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SMEM__S_MEMTIME::Inst_SMEM__S_MEMTIME(InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_memtime")
+ {
+ } // Inst_SMEM__S_MEMTIME
+
+ Inst_SMEM__S_MEMTIME::~Inst_SMEM__S_MEMTIME()
+ {
+ } // ~Inst_SMEM__S_MEMTIME
+
+ // Return current 64-bit timestamp.
+ void
+ Inst_SMEM__S_MEMTIME::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SMEM__S_MEMREALTIME::Inst_SMEM__S_MEMREALTIME(InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_memrealtime")
+ {
+ } // Inst_SMEM__S_MEMREALTIME
+
+ Inst_SMEM__S_MEMREALTIME::~Inst_SMEM__S_MEMREALTIME()
+ {
+ } // ~Inst_SMEM__S_MEMREALTIME
+
+ // Return current 64-bit RTC.
+ void
+ Inst_SMEM__S_MEMREALTIME::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SMEM__S_ATC_PROBE::Inst_SMEM__S_ATC_PROBE(InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_atc_probe")
+ {
+ } // Inst_SMEM__S_ATC_PROBE
+
+ Inst_SMEM__S_ATC_PROBE::~Inst_SMEM__S_ATC_PROBE()
+ {
+ } // ~Inst_SMEM__S_ATC_PROBE
+
+ void
+ Inst_SMEM__S_ATC_PROBE::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_SMEM__S_ATC_PROBE_BUFFER::Inst_SMEM__S_ATC_PROBE_BUFFER(
+ InFmt_SMEM *iFmt)
+ : Inst_SMEM(iFmt, "s_atc_probe_buffer")
+ {
+ } // Inst_SMEM__S_ATC_PROBE_BUFFER
+
+ Inst_SMEM__S_ATC_PROBE_BUFFER::~Inst_SMEM__S_ATC_PROBE_BUFFER()
+ {
+ } // ~Inst_SMEM__S_ATC_PROBE_BUFFER
+
+ void
+ Inst_SMEM__S_ATC_PROBE_BUFFER::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP2__V_CNDMASK_B32::Inst_VOP2__V_CNDMASK_B32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_cndmask_b32")
+ {
+ setFlag(ALU);
+ setFlag(ReadsVCC);
+ } // Inst_VOP2__V_CNDMASK_B32
+
+ Inst_VOP2__V_CNDMASK_B32::~Inst_VOP2__V_CNDMASK_B32()
+ {
+ } // ~Inst_VOP2__V_CNDMASK_B32
+
+ // D.u = (VCC[i] ? S1.u : S0.u) (i = threadID in wave); VOP3: specify VCC
+ // as a scalar GPR in S2.
+ void
+ Inst_VOP2__V_CNDMASK_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+ ConstScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+ vcc.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane]
+ = bits(vcc.rawData(), lane) ? src1[lane] : src0[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_ADD_F32::Inst_VOP2__V_ADD_F32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_add_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP2__V_ADD_F32
+
+ Inst_VOP2__V_ADD_F32::~Inst_VOP2__V_ADD_F32()
+ {
+ } // ~Inst_VOP2__V_ADD_F32
+
+ // D.f = S0.f + S1.f.
+ void
+ Inst_VOP2__V_ADD_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ VecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ if (isDPPInst()) {
+ VecOperandF32 src0_dpp(gpuDynInst, extData.iFmt_VOP_DPP.SRC0);
+
+ DPRINTF(GCN3, "Handling V_ADD_F32 SRC DPP. SRC0: register v[%d], "
+ "DPP_CTRL: 0x%#x, SRC0_ABS: %d, SRC0_NEG: %d, "
+ "SRC1_ABS: %d, SRC1_NEG: %d, BOUND_CTRL: %d, "
+ "BANK_MASK: %d, ROW_MASK: %d\n", extData.iFmt_VOP_DPP.SRC0,
+ extData.iFmt_VOP_DPP.DPP_CTRL,
+ extData.iFmt_VOP_DPP.SRC0_ABS,
+ extData.iFmt_VOP_DPP.SRC0_NEG,
+ extData.iFmt_VOP_DPP.SRC1_ABS,
+ extData.iFmt_VOP_DPP.SRC1_NEG,
+ extData.iFmt_VOP_DPP.BOUND_CTRL,
+ extData.iFmt_VOP_DPP.BANK_MASK,
+ extData.iFmt_VOP_DPP.ROW_MASK);
+
+ processDPP(gpuDynInst, extData.iFmt_VOP_DPP, src0_dpp, src1);
+ }
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] + src1[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_SUB_F32::Inst_VOP2__V_SUB_F32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_sub_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP2__V_SUB_F32
+
+ Inst_VOP2__V_SUB_F32::~Inst_VOP2__V_SUB_F32()
+ {
+ } // ~Inst_VOP2__V_SUB_F32
+
+ // D.f = S0.f - S1.f.
+ void
+ Inst_VOP2__V_SUB_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] - src1[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_SUBREV_F32::Inst_VOP2__V_SUBREV_F32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_subrev_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP2__V_SUBREV_F32
+
+ Inst_VOP2__V_SUBREV_F32::~Inst_VOP2__V_SUBREV_F32()
+ {
+ } // ~Inst_VOP2__V_SUBREV_F32
+
+ // D.f = S1.f - S0.f.
+ void
+ Inst_VOP2__V_SUBREV_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src1[lane] - src0[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_MUL_LEGACY_F32::Inst_VOP2__V_MUL_LEGACY_F32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_mul_legacy_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP2__V_MUL_LEGACY_F32
+
+ Inst_VOP2__V_MUL_LEGACY_F32::~Inst_VOP2__V_MUL_LEGACY_F32()
+ {
+ } // ~Inst_VOP2__V_MUL_LEGACY_F32
+
+ // D.f = S0.f * S1.f
+ void
+ Inst_VOP2__V_MUL_LEGACY_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] * src1[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_MUL_F32::Inst_VOP2__V_MUL_F32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_mul_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP2__V_MUL_F32
+
+ Inst_VOP2__V_MUL_F32::~Inst_VOP2__V_MUL_F32()
+ {
+ } // ~Inst_VOP2__V_MUL_F32
+
+ // D.f = S0.f * S1.f.
+ void
+ Inst_VOP2__V_MUL_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::isnan(src0[lane]) ||
+ std::isnan(src1[lane])) {
+ vdst[lane] = NAN;
+ } else if ((std::fpclassify(src0[lane]) == FP_SUBNORMAL ||
+ std::fpclassify(src0[lane]) == FP_ZERO) &&
+ !std::signbit(src0[lane])) {
+ if (std::isinf(src1[lane])) {
+ vdst[lane] = NAN;
+ } else if (!std::signbit(src1[lane])) {
+ vdst[lane] = +0.0;
+ } else {
+ vdst[lane] = -0.0;
+ }
+ } else if ((std::fpclassify(src0[lane]) == FP_SUBNORMAL ||
+ std::fpclassify(src0[lane]) == FP_ZERO) &&
+ std::signbit(src0[lane])) {
+ if (std::isinf(src1[lane])) {
+ vdst[lane] = NAN;
+ } else if (std::signbit(src1[lane])) {
+ vdst[lane] = +0.0;
+ } else {
+ vdst[lane] = -0.0;
+ }
+ } else if (std::isinf(src0[lane]) &&
+ !std::signbit(src0[lane])) {
+ if (std::fpclassify(src1[lane]) == FP_SUBNORMAL ||
+ std::fpclassify(src1[lane]) == FP_ZERO) {
+ vdst[lane] = NAN;
+ } else if (!std::signbit(src1[lane])) {
+ vdst[lane] = +INFINITY;
+ } else {
+ vdst[lane] = -INFINITY;
+ }
+ } else if (std::isinf(src0[lane]) &&
+ std::signbit(src0[lane])) {
+ if (std::fpclassify(src1[lane]) == FP_SUBNORMAL ||
+ std::fpclassify(src1[lane]) == FP_ZERO) {
+ vdst[lane] = NAN;
+ } else if (std::signbit(src1[lane])) {
+ vdst[lane] = +INFINITY;
+ } else {
+ vdst[lane] = -INFINITY;
+ }
+ } else {
+ vdst[lane] = src0[lane] * src1[lane];
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_MUL_I32_I24::Inst_VOP2__V_MUL_I32_I24(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_mul_i32_i24")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_MUL_I32_I24
+
+ Inst_VOP2__V_MUL_I32_I24::~Inst_VOP2__V_MUL_I32_I24()
+ {
+ } // ~Inst_VOP2__V_MUL_I32_I24
+
+ // D.i = S0.i[23:0] * S1.i[23:0].
+ void
+ Inst_VOP2__V_MUL_I32_I24::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = sext<24>(bits(src0[lane], 23, 0))
+ * sext<24>(bits(src1[lane], 23, 0));
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_MUL_HI_I32_I24::Inst_VOP2__V_MUL_HI_I32_I24(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_mul_hi_i32_i24")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_MUL_HI_I32_I24
+
+ Inst_VOP2__V_MUL_HI_I32_I24::~Inst_VOP2__V_MUL_HI_I32_I24()
+ {
+ } // ~Inst_VOP2__V_MUL_HI_I32_I24
+
+ // D.i = (S0.i[23:0] * S1.i[23:0]) >> 32.
+ void
+ Inst_VOP2__V_MUL_HI_I32_I24::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ VecElemI64 tmp_src0
+ = (VecElemI64)sext<24>(bits(src0[lane], 23, 0));
+ VecElemI64 tmp_src1
+ = (VecElemI64)sext<24>(bits(src1[lane], 23, 0));
+
+ vdst[lane] = (VecElemI32)((tmp_src0 * tmp_src1) >> 32);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_MUL_U32_U24::Inst_VOP2__V_MUL_U32_U24(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_mul_u32_u24")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_MUL_U32_U24
+
+ Inst_VOP2__V_MUL_U32_U24::~Inst_VOP2__V_MUL_U32_U24()
+ {
+ } // ~Inst_VOP2__V_MUL_U32_U24
+
+ // D.u = S0.u[23:0] * S1.u[23:0].
+ void
+ Inst_VOP2__V_MUL_U32_U24::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ VecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ if (isSDWAInst()) {
+ VecOperandU32 src0_sdwa(gpuDynInst, extData.iFmt_VOP_SDWA.SRC0);
+ // use copies of original src0 and src1 during selecting
+ VecOperandU32 origSrc0_sdwa(gpuDynInst,
+ extData.iFmt_VOP_SDWA.SRC0);
+ VecOperandU32 origSrc1(gpuDynInst, instData.VSRC1);
+
+ DPRINTF(GCN3, "Handling V_MUL_U32_U24 SRC SDWA. SRC0: register "
+ "v[%d], DST_SEL: %d, DST_UNUSED: %d, CLAMP: %d, SRC0_SEL: "
+ "%d, SRC0_SEXT: %d, SRC0_NEG: %d, SRC0_ABS: %d, SRC1_SEL: "
+ "%d, SRC1_SEXT: %d, SRC1_NEG: %d, SRC1_ABS: %d\n",
+ extData.iFmt_VOP_SDWA.SRC0, extData.iFmt_VOP_SDWA.DST_SEL,
+ extData.iFmt_VOP_SDWA.DST_UNUSED,
+ extData.iFmt_VOP_SDWA.CLAMP,
+ extData.iFmt_VOP_SDWA.SRC0_SEL,
+ extData.iFmt_VOP_SDWA.SRC0_SEXT,
+ extData.iFmt_VOP_SDWA.SRC0_NEG,
+ extData.iFmt_VOP_SDWA.SRC0_ABS,
+ extData.iFmt_VOP_SDWA.SRC1_SEL,
+ extData.iFmt_VOP_SDWA.SRC1_SEXT,
+ extData.iFmt_VOP_SDWA.SRC1_NEG,
+ extData.iFmt_VOP_SDWA.SRC1_ABS);
+
+ processSDWA_src(gpuDynInst, extData.iFmt_VOP_SDWA, src0_sdwa,
+ origSrc0_sdwa, src1, origSrc1);
+ }
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = bits(src0[lane], 23, 0) * bits(src1[lane], 23, 0);
+ }
+ }
+
+ // SDWA instructions also may select bytes/words of dest register
+ // (vdst)
+ if (isSDWAInst()) {
+ // use extra copy of dest to retain original values
+ VecOperandU32 vdst_orig(gpuDynInst, instData.VDST);
+ processSDWA_dst(gpuDynInst, extData.iFmt_VOP_SDWA, vdst,
+ vdst_orig);
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_MUL_HI_U32_U24::Inst_VOP2__V_MUL_HI_U32_U24(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_mul_hi_u32_u24")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_MUL_HI_U32_U24
+
+ Inst_VOP2__V_MUL_HI_U32_U24::~Inst_VOP2__V_MUL_HI_U32_U24()
+ {
+ } // ~Inst_VOP2__V_MUL_HI_U32_U24
+
+ // D.i = (S0.u[23:0] * S1.u[23:0]) >> 32.
+ void
+ Inst_VOP2__V_MUL_HI_U32_U24::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ VecElemU64 tmp_src0 = (VecElemU64)bits(src0[lane], 23, 0);
+ VecElemU64 tmp_src1 = (VecElemU64)bits(src1[lane], 23, 0);
+ vdst[lane] = (VecElemU32)((tmp_src0 * tmp_src1) >> 32);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_MIN_F32::Inst_VOP2__V_MIN_F32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_min_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP2__V_MIN_F32
+
+ Inst_VOP2__V_MIN_F32::~Inst_VOP2__V_MIN_F32()
+ {
+ } // ~Inst_VOP2__V_MIN_F32
+
+ // D.f = (S0.f < S1.f ? S0.f : S1.f).
+ void
+ Inst_VOP2__V_MIN_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::fmin(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_MAX_F32::Inst_VOP2__V_MAX_F32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_max_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP2__V_MAX_F32
+
+ Inst_VOP2__V_MAX_F32::~Inst_VOP2__V_MAX_F32()
+ {
+ } // ~Inst_VOP2__V_MAX_F32
+
+ // D.f = (S0.f >= S1.f ? S0.f : S1.f).
+ void
+ Inst_VOP2__V_MAX_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::fmax(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_MIN_I32::Inst_VOP2__V_MIN_I32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_min_i32")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_MIN_I32
+
+ Inst_VOP2__V_MIN_I32::~Inst_VOP2__V_MIN_I32()
+ {
+ } // ~Inst_VOP2__V_MIN_I32
+
+ // D.i = min(S0.i, S1.i).
+ void
+ Inst_VOP2__V_MIN_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::min(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_MAX_I32::Inst_VOP2__V_MAX_I32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_max_i32")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_MAX_I32
+
+ Inst_VOP2__V_MAX_I32::~Inst_VOP2__V_MAX_I32()
+ {
+ } // ~Inst_VOP2__V_MAX_I32
+
+ // D.i = max(S0.i, S1.i).
+ void
+ Inst_VOP2__V_MAX_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::max(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_MIN_U32::Inst_VOP2__V_MIN_U32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_min_u32")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_MIN_U32
+
+ Inst_VOP2__V_MIN_U32::~Inst_VOP2__V_MIN_U32()
+ {
+ } // ~Inst_VOP2__V_MIN_U32
+
+ // D.u = min(S0.u, S1.u).
+ void
+ Inst_VOP2__V_MIN_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::min(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_MAX_U32::Inst_VOP2__V_MAX_U32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_max_u32")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_MAX_U32
+
+ Inst_VOP2__V_MAX_U32::~Inst_VOP2__V_MAX_U32()
+ {
+ } // ~Inst_VOP2__V_MAX_U32
+
+ // D.u = max(S0.u, S1.u).
+ void
+ Inst_VOP2__V_MAX_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::max(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_LSHRREV_B32::Inst_VOP2__V_LSHRREV_B32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_lshrrev_b32")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_LSHRREV_B32
+
+ Inst_VOP2__V_LSHRREV_B32::~Inst_VOP2__V_LSHRREV_B32()
+ {
+ } // ~Inst_VOP2__V_LSHRREV_B32
+
+ // D.u = S1.u >> S0.u[4:0].
+ // The vacated bits are set to zero.
+ void
+ Inst_VOP2__V_LSHRREV_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src1[lane] >> bits(src0[lane], 4, 0);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_ASHRREV_I32::Inst_VOP2__V_ASHRREV_I32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_ashrrev_i32")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_ASHRREV_I32
+
+ Inst_VOP2__V_ASHRREV_I32::~Inst_VOP2__V_ASHRREV_I32()
+ {
+ } // ~Inst_VOP2__V_ASHRREV_I32
+
+ // D.i = signext(S1.i) >> S0.i[4:0].
+ // The vacated bits are set to the sign bit of the input value.
+ void
+ Inst_VOP2__V_ASHRREV_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src1[lane] >> bits(src0[lane], 4, 0);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_LSHLREV_B32::Inst_VOP2__V_LSHLREV_B32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_lshlrev_b32")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_LSHLREV_B32
+
+ Inst_VOP2__V_LSHLREV_B32::~Inst_VOP2__V_LSHLREV_B32()
+ {
+ } // ~Inst_VOP2__V_LSHLREV_B32
+
+ // D.u = S1.u << S0.u[4:0].
+ void
+ Inst_VOP2__V_LSHLREV_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ VecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ if (isSDWAInst()) {
+ VecOperandU32 src0_sdwa(gpuDynInst, extData.iFmt_VOP_SDWA.SRC0);
+ // use copies of original src0 and src1 during selecting
+ VecOperandU32 origSrc0_sdwa(gpuDynInst,
+ extData.iFmt_VOP_SDWA.SRC0);
+ VecOperandU32 origSrc1(gpuDynInst, instData.VSRC1);
+
+ DPRINTF(GCN3, "Handling V_LSHLREV_B32 SRC SDWA. SRC0: register "
+ "v[%d], DST_SEL: %d, DST_UNUSED: %d, CLAMP: %d, SRC0_SEL: "
+ "%d, SRC0_SEXT: %d, SRC0_NEG: %d, SRC0_ABS: %d, SRC1_SEL: "
+ "%d, SRC1_SEXT: %d, SRC1_NEG: %d, SRC1_ABS: %d\n",
+ extData.iFmt_VOP_SDWA.SRC0, extData.iFmt_VOP_SDWA.DST_SEL,
+ extData.iFmt_VOP_SDWA.DST_UNUSED,
+ extData.iFmt_VOP_SDWA.CLAMP,
+ extData.iFmt_VOP_SDWA.SRC0_SEL,
+ extData.iFmt_VOP_SDWA.SRC0_SEXT,
+ extData.iFmt_VOP_SDWA.SRC0_NEG,
+ extData.iFmt_VOP_SDWA.SRC0_ABS,
+ extData.iFmt_VOP_SDWA.SRC1_SEL,
+ extData.iFmt_VOP_SDWA.SRC1_SEXT,
+ extData.iFmt_VOP_SDWA.SRC1_NEG,
+ extData.iFmt_VOP_SDWA.SRC1_ABS);
+
+ processSDWA_src(gpuDynInst, extData.iFmt_VOP_SDWA, src0_sdwa,
+ origSrc0_sdwa, src1, origSrc1);
+ }
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src1[lane] << bits(src0[lane], 4, 0);
+ }
+ }
+
+ // SDWA instructions also may select bytes/words of dest register
+ // (vdst)
+ if (isSDWAInst()) {
+ // use extra copy of dest to retain original values
+ VecOperandU32 vdst_orig(gpuDynInst, instData.VDST);
+ processSDWA_dst(gpuDynInst, extData.iFmt_VOP_SDWA, vdst,
+ vdst_orig);
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_AND_B32::Inst_VOP2__V_AND_B32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_and_b32")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_AND_B32
+
+ Inst_VOP2__V_AND_B32::~Inst_VOP2__V_AND_B32()
+ {
+ } // ~Inst_VOP2__V_AND_B32
+
+ // D.u = S0.u & S1.u.
+ // Input and output modifiers not supported.
+ void
+ Inst_VOP2__V_AND_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] & src1[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_OR_B32::Inst_VOP2__V_OR_B32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_or_b32")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_OR_B32
+
+ Inst_VOP2__V_OR_B32::~Inst_VOP2__V_OR_B32()
+ {
+ } // ~Inst_VOP2__V_OR_B32
+
+ // D.u = S0.u | S1.u.
+ // Input and output modifiers not supported.
+ void
+ Inst_VOP2__V_OR_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ VecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ if (isSDWAInst()) {
+ VecOperandU32 src0_sdwa(gpuDynInst, extData.iFmt_VOP_SDWA.SRC0);
+ // use copies of original src0 and src1 during selecting
+ VecOperandU32 origSrc0_sdwa(gpuDynInst,
+ extData.iFmt_VOP_SDWA.SRC0);
+ VecOperandU32 origSrc1(gpuDynInst, instData.VSRC1);
+
+ DPRINTF(GCN3, "Handling V_OR_B32 SRC SDWA. SRC0: register v[%d], "
+ "DST_SEL: %d, DST_UNUSED: %d, CLAMP: %d, SRC0_SEL: %d, "
+ "SRC0_SEXT: %d, SRC0_NEG: %d, SRC0_ABS: %d, SRC1_SEL: %d, "
+ "SRC1_SEXT: %d, SRC1_NEG: %d, SRC1_ABS: %d\n",
+ extData.iFmt_VOP_SDWA.SRC0, extData.iFmt_VOP_SDWA.DST_SEL,
+ extData.iFmt_VOP_SDWA.DST_UNUSED,
+ extData.iFmt_VOP_SDWA.CLAMP,
+ extData.iFmt_VOP_SDWA.SRC0_SEL,
+ extData.iFmt_VOP_SDWA.SRC0_SEXT,
+ extData.iFmt_VOP_SDWA.SRC0_NEG,
+ extData.iFmt_VOP_SDWA.SRC0_ABS,
+ extData.iFmt_VOP_SDWA.SRC1_SEL,
+ extData.iFmt_VOP_SDWA.SRC1_SEXT,
+ extData.iFmt_VOP_SDWA.SRC1_NEG,
+ extData.iFmt_VOP_SDWA.SRC1_ABS);
+
+ processSDWA_src(gpuDynInst, extData.iFmt_VOP_SDWA, src0_sdwa,
+ origSrc0_sdwa, src1, origSrc1);
+ }
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] | src1[lane];
+ }
+ }
+
+ // SDWA instructions also may select bytes/words of dest register
+ // (vdst)
+ if (isSDWAInst()) {
+ // use extra copy of dest to retain original values
+ VecOperandU32 vdst_orig(gpuDynInst, instData.VDST);
+ processSDWA_dst(gpuDynInst, extData.iFmt_VOP_SDWA, vdst,
+ vdst_orig);
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_XOR_B32::Inst_VOP2__V_XOR_B32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_xor_b32")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_XOR_B32
+
+ Inst_VOP2__V_XOR_B32::~Inst_VOP2__V_XOR_B32()
+ {
+ } // ~Inst_VOP2__V_XOR_B32
+
+ // D.u = S0.u ^ S1.u.
+ // Input and output modifiers not supported.
+ void
+ Inst_VOP2__V_XOR_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] ^ src1[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_MAC_F32::Inst_VOP2__V_MAC_F32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_mac_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ setFlag(MAC);
+ } // Inst_VOP2__V_MAC_F32
+
+ Inst_VOP2__V_MAC_F32::~Inst_VOP2__V_MAC_F32()
+ {
+ } // ~Inst_VOP2__V_MAC_F32
+
+ // D.f = S0.f * S1.f + D.f.
+ void
+ Inst_VOP2__V_MAC_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ VecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+ vdst.read();
+
+ if (isDPPInst()) {
+ VecOperandF32 src0_dpp(gpuDynInst, extData.iFmt_VOP_DPP.SRC0);
+
+ DPRINTF(GCN3, "Handling V_MAC_F32 SRC DPP. SRC0: register v[%d], "
+ "DPP_CTRL: 0x%#x, SRC0_ABS: %d, SRC0_NEG: %d, "
+ "SRC1_ABS: %d, SRC1_NEG: %d, BOUND_CTRL: %d, "
+ "BANK_MASK: %d, ROW_MASK: %d\n", extData.iFmt_VOP_DPP.SRC0,
+ extData.iFmt_VOP_DPP.DPP_CTRL,
+ extData.iFmt_VOP_DPP.SRC0_ABS,
+ extData.iFmt_VOP_DPP.SRC0_NEG,
+ extData.iFmt_VOP_DPP.SRC1_ABS,
+ extData.iFmt_VOP_DPP.SRC1_NEG,
+ extData.iFmt_VOP_DPP.BOUND_CTRL,
+ extData.iFmt_VOP_DPP.BANK_MASK,
+ extData.iFmt_VOP_DPP.ROW_MASK);
+
+ processDPP(gpuDynInst, extData.iFmt_VOP_DPP, src0_dpp, src1);
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::fma(src0[lane], src1[lane], vdst[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_MADMK_F32::Inst_VOP2__V_MADMK_F32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_madmk_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ setFlag(MAD);
+ } // Inst_VOP2__V_MADMK_F32
+
+ Inst_VOP2__V_MADMK_F32::~Inst_VOP2__V_MADMK_F32()
+ {
+ } // ~Inst_VOP2__V_MADMK_F32
+
+ // D.f = S0.f * K + S1.f; K is a 32-bit inline constant.
+ // This opcode cannot use the input/output modifiers.
+ void
+ Inst_VOP2__V_MADMK_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+ VecElemF32 k = extData.imm_f32;
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::fma(src0[lane], k, src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_MADAK_F32::Inst_VOP2__V_MADAK_F32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_madak_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ setFlag(MAD);
+ } // Inst_VOP2__V_MADAK_F32
+
+ Inst_VOP2__V_MADAK_F32::~Inst_VOP2__V_MADAK_F32()
+ {
+ } // ~Inst_VOP2__V_MADAK_F32
+
+ // D.f = S0.f * S1.f + K; K is a 32-bit inline constant.
+ // This opcode cannot use input/output modifiers.
+ void
+ Inst_VOP2__V_MADAK_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+ VecElemF32 k = extData.imm_f32;
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::fma(src0[lane], src1[lane], k);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_ADD_U32::Inst_VOP2__V_ADD_U32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_add_u32")
+ {
+ setFlag(ALU);
+ setFlag(WritesVCC);
+ } // Inst_VOP2__V_ADD_U32
+
+ Inst_VOP2__V_ADD_U32::~Inst_VOP2__V_ADD_U32()
+ {
+ } // ~Inst_VOP2__V_ADD_U32
+
+ // D.u = S0.u + S1.u;
+ // VCC[threadId] = (S0.u + S1.u >= 0x100000000ULL ? 1 : 0) is an UNSIGNED
+ // overflow or carry-out.
+ // In VOP3 the VCC destination may be an arbitrary SGPR-pair.
+ void
+ Inst_VOP2__V_ADD_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ VecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ if (isSDWAInst()) {
+ VecOperandU32 src0_sdwa(gpuDynInst, extData.iFmt_VOP_SDWA.SRC0);
+ // use copies of original src0 and src1 during selecting
+ VecOperandU32 origSrc0_sdwa(gpuDynInst,
+ extData.iFmt_VOP_SDWA.SRC0);
+ VecOperandU32 origSrc1(gpuDynInst, instData.VSRC1);
+
+ DPRINTF(GCN3, "Handling V_ADD_U32 SRC SDWA. SRC0: register v[%d], "
+ "DST_SEL: %d, DST_UNUSED: %d, CLAMP: %d, SRC0_SEL: %d, "
+ "SRC0_SEXT: %d, SRC0_NEG: %d, SRC0_ABS: %d, SRC1_SEL: %d, "
+ "SRC1_SEXT: %d, SRC1_NEG: %d, SRC1_ABS: %d\n",
+ extData.iFmt_VOP_SDWA.SRC0, extData.iFmt_VOP_SDWA.DST_SEL,
+ extData.iFmt_VOP_SDWA.DST_UNUSED,
+ extData.iFmt_VOP_SDWA.CLAMP,
+ extData.iFmt_VOP_SDWA.SRC0_SEL,
+ extData.iFmt_VOP_SDWA.SRC0_SEXT,
+ extData.iFmt_VOP_SDWA.SRC0_NEG,
+ extData.iFmt_VOP_SDWA.SRC0_ABS,
+ extData.iFmt_VOP_SDWA.SRC1_SEL,
+ extData.iFmt_VOP_SDWA.SRC1_SEXT,
+ extData.iFmt_VOP_SDWA.SRC1_NEG,
+ extData.iFmt_VOP_SDWA.SRC1_ABS);
+
+ processSDWA_src(gpuDynInst, extData.iFmt_VOP_SDWA, src0_sdwa,
+ origSrc0_sdwa, src1, origSrc1);
+ }
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] + src1[lane];
+ vcc.setBit(lane, ((VecElemU64)src0[lane]
+ + (VecElemU64)src1[lane] >= 0x100000000ULL) ? 1 : 0);
+ }
+ }
+
+ // SDWA instructions also may select bytes/words of dest register
+ // (vdst)
+ if (isSDWAInst()) {
+ // use extra copy of dest to retain original values
+ VecOperandU32 vdst_orig(gpuDynInst, instData.VDST);
+ processSDWA_dst(gpuDynInst, extData.iFmt_VOP_SDWA, vdst,
+ vdst_orig);
+ }
+
+ vcc.write();
+ vdst.write();
+ }
+
+ Inst_VOP2__V_SUB_U32::Inst_VOP2__V_SUB_U32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_sub_u32")
+ {
+ setFlag(ALU);
+ setFlag(WritesVCC);
+ } // Inst_VOP2__V_SUB_U32
+
+ Inst_VOP2__V_SUB_U32::~Inst_VOP2__V_SUB_U32()
+ {
+ } // ~Inst_VOP2__V_SUB_U32
+
+ // D.u = S0.u - S1.u;
+ // VCC[threadId] = (S1.u > S0.u ? 1 : 0) is an UNSIGNED overflow or
+ // carry-out.
+ // In VOP3 the VCC destination may be an arbitrary SGPR-pair.
+ void
+ Inst_VOP2__V_SUB_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] - src1[lane];
+ vcc.setBit(lane, src1[lane] > src0[lane] ? 1 : 0);
+ }
+ }
+
+ vdst.write();
+ vcc.write();
+ }
+
+ Inst_VOP2__V_SUBREV_U32::Inst_VOP2__V_SUBREV_U32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_subrev_u32")
+ {
+ setFlag(ALU);
+ setFlag(WritesVCC);
+ } // Inst_VOP2__V_SUBREV_U32
+
+ Inst_VOP2__V_SUBREV_U32::~Inst_VOP2__V_SUBREV_U32()
+ {
+ } // ~Inst_VOP2__V_SUBREV_U32
+
+ // D.u = S1.u - S0.u;
+ // VCC[threadId] = (S0.u > S1.u ? 1 : 0) is an UNSIGNED overflow or
+ // carry-out.
+ // In VOP3 the VCC destination may be an arbitrary SGPR-pair.
+ void
+ Inst_VOP2__V_SUBREV_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src1[lane] - src0[lane];
+ vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ vdst.write();
+ vcc.write();
+ }
+
+ Inst_VOP2__V_ADDC_U32::Inst_VOP2__V_ADDC_U32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_addc_u32")
+ {
+ setFlag(ALU);
+ setFlag(WritesVCC);
+ setFlag(ReadsVCC);
+ } // Inst_VOP2__V_ADDC_U32
+
+ Inst_VOP2__V_ADDC_U32::~Inst_VOP2__V_ADDC_U32()
+ {
+ } // ~Inst_VOP2__V_ADDC_U32
+
+ // D.u = S0.u + S1.u + VCC[threadId];
+ // VCC[threadId] = (S0.u + S1.u + VCC[threadId] >= 0x100000000ULL ? 1 : 0)
+ // is an UNSIGNED overflow.
+ // In VOP3 the VCC destination may be an arbitrary SGPR-pair, and the VCC
+ // source comes from the SGPR-pair at S2.u.
+ void
+ Inst_VOP2__V_ADDC_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+ vcc.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] + src1[lane]
+ + bits(vcc.rawData(), lane);
+ vcc.setBit(lane, ((VecElemU64)src0[lane]
+ + (VecElemU64)src1[lane]
+ + (VecElemU64)bits(vcc.rawData(), lane, lane))
+ >= 0x100000000 ? 1 : 0);
+ }
+ }
+
+ vdst.write();
+ vcc.write();
+ }
+
+ Inst_VOP2__V_SUBB_U32::Inst_VOP2__V_SUBB_U32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_subb_u32")
+ {
+ setFlag(ALU);
+ setFlag(WritesVCC);
+ setFlag(ReadsVCC);
+ } // Inst_VOP2__V_SUBB_U32
+
+ Inst_VOP2__V_SUBB_U32::~Inst_VOP2__V_SUBB_U32()
+ {
+ } // ~Inst_VOP2__V_SUBB_U32
+
+ // D.u = S0.u - S1.u - VCC[threadId];
+ // VCC[threadId] = (S1.u + VCC[threadId] > S0.u ? 1 : 0) is an UNSIGNED
+ // overflow.
+ // In VOP3 the VCC destination may be an arbitrary SGPR-pair, and the VCC
+ // source comes from the SGPR-pair at S2.u.
+ void
+ Inst_VOP2__V_SUBB_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+ vcc.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane]
+ = src0[lane] - src1[lane] - bits(vcc.rawData(), lane);
+ vcc.setBit(lane, (src1[lane] + bits(vcc.rawData(), lane))
+ > src0[lane] ? 1 : 0);
+ }
+ }
+
+ vdst.write();
+ vcc.write();
+ }
+
+ Inst_VOP2__V_SUBBREV_U32::Inst_VOP2__V_SUBBREV_U32(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_subbrev_u32")
+ {
+ setFlag(ALU);
+ setFlag(WritesVCC);
+ setFlag(ReadsVCC);
+ } // Inst_VOP2__V_SUBBREV_U32
+
+ Inst_VOP2__V_SUBBREV_U32::~Inst_VOP2__V_SUBBREV_U32()
+ {
+ } // ~Inst_VOP2__V_SUBBREV_U32
+
+ // D.u = S1.u - S0.u - VCC[threadId];
+ // VCC[threadId] = (S1.u + VCC[threadId] > S0.u ? 1 : 0) is an UNSIGNED
+ // overflow.
+ // In VOP3 the VCC destination may be an arbitrary SGPR-pair, and the VCC
+ // source comes from the SGPR-pair at S2.u.
+ void
+ Inst_VOP2__V_SUBBREV_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+ vcc.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane]
+ = src1[lane] - src0[lane] - bits(vcc.rawData(), lane);
+ vcc.setBit(lane, (src0[lane] + bits(vcc.rawData(), lane))
+ > src1[lane] ? 1 : 0);
+ }
+ }
+
+ vdst.write();
+ vcc.write();
+ }
+
+ Inst_VOP2__V_ADD_F16::Inst_VOP2__V_ADD_F16(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_add_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP2__V_ADD_F16
+
+ Inst_VOP2__V_ADD_F16::~Inst_VOP2__V_ADD_F16()
+ {
+ } // ~Inst_VOP2__V_ADD_F16
+
+ // D.f16 = S0.f16 + S1.f16.
+ void
+ Inst_VOP2__V_ADD_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP2__V_SUB_F16::Inst_VOP2__V_SUB_F16(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_sub_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP2__V_SUB_F16
+
+ Inst_VOP2__V_SUB_F16::~Inst_VOP2__V_SUB_F16()
+ {
+ } // ~Inst_VOP2__V_SUB_F16
+
+ // D.f16 = S0.f16 - S1.f16.
+ void
+ Inst_VOP2__V_SUB_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP2__V_SUBREV_F16::Inst_VOP2__V_SUBREV_F16(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_subrev_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP2__V_SUBREV_F16
+
+ Inst_VOP2__V_SUBREV_F16::~Inst_VOP2__V_SUBREV_F16()
+ {
+ } // ~Inst_VOP2__V_SUBREV_F16
+
+ // D.f16 = S1.f16 - S0.f16.
+ void
+ Inst_VOP2__V_SUBREV_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP2__V_MUL_F16::Inst_VOP2__V_MUL_F16(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_mul_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP2__V_MUL_F16
+
+ Inst_VOP2__V_MUL_F16::~Inst_VOP2__V_MUL_F16()
+ {
+ } // ~Inst_VOP2__V_MUL_F16
+
+ // D.f16 = S0.f16 * S1.f16.
+ void
+ Inst_VOP2__V_MUL_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP2__V_MAC_F16::Inst_VOP2__V_MAC_F16(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_mac_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ setFlag(MAC);
+ } // Inst_VOP2__V_MAC_F16
+
+ Inst_VOP2__V_MAC_F16::~Inst_VOP2__V_MAC_F16()
+ {
+ } // ~Inst_VOP2__V_MAC_F16
+
+ // D.f16 = S0.f16 * S1.f16 + D.f16.
+ void
+ Inst_VOP2__V_MAC_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP2__V_MADMK_F16::Inst_VOP2__V_MADMK_F16(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_madmk_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ setFlag(MAD);
+ } // Inst_VOP2__V_MADMK_F16
+
+ Inst_VOP2__V_MADMK_F16::~Inst_VOP2__V_MADMK_F16()
+ {
+ } // ~Inst_VOP2__V_MADMK_F16
+
+ // D.f16 = S0.f16 * K.f16 + S1.f16; K is a 16-bit inline constant stored
+ // in the following literal DWORD.
+ // This opcode cannot use the VOP3 encoding and cannot use input/output
+ // modifiers.
+ void
+ Inst_VOP2__V_MADMK_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP2__V_MADAK_F16::Inst_VOP2__V_MADAK_F16(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_madak_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ setFlag(MAD);
+ } // Inst_VOP2__V_MADAK_F16
+
+ Inst_VOP2__V_MADAK_F16::~Inst_VOP2__V_MADAK_F16()
+ {
+ } // ~Inst_VOP2__V_MADAK_F16
+
+ // D.f16 = S0.f16 * S1.f16 + K.f16; K is a 16-bit inline constant stored
+ // in the following literal DWORD.
+ // This opcode cannot use the VOP3 encoding and cannot use input/output
+ // modifiers.
+ void
+ Inst_VOP2__V_MADAK_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP2__V_ADD_U16::Inst_VOP2__V_ADD_U16(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_add_u16")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_ADD_U16
+
+ Inst_VOP2__V_ADD_U16::~Inst_VOP2__V_ADD_U16()
+ {
+ } // ~Inst_VOP2__V_ADD_U16
+
+ // D.u16 = S0.u16 + S1.u16.
+ void
+ Inst_VOP2__V_ADD_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] + src1[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_SUB_U16::Inst_VOP2__V_SUB_U16(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_sub_u16")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_SUB_U16
+
+ Inst_VOP2__V_SUB_U16::~Inst_VOP2__V_SUB_U16()
+ {
+ } // ~Inst_VOP2__V_SUB_U16
+
+ // D.u16 = S0.u16 - S1.u16.
+ void
+ Inst_VOP2__V_SUB_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] - src1[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_SUBREV_U16::Inst_VOP2__V_SUBREV_U16(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_subrev_u16")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_SUBREV_U16
+
+ Inst_VOP2__V_SUBREV_U16::~Inst_VOP2__V_SUBREV_U16()
+ {
+ } // ~Inst_VOP2__V_SUBREV_U16
+
+ // D.u16 = S1.u16 - S0.u16.
+ void
+ Inst_VOP2__V_SUBREV_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src1[lane] - src0[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_MUL_LO_U16::Inst_VOP2__V_MUL_LO_U16(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_mul_lo_u16")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_MUL_LO_U16
+
+ Inst_VOP2__V_MUL_LO_U16::~Inst_VOP2__V_MUL_LO_U16()
+ {
+ } // ~Inst_VOP2__V_MUL_LO_U16
+
+ // D.u16 = S0.u16 * S1.u16.
+ void
+ Inst_VOP2__V_MUL_LO_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] * src1[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_LSHLREV_B16::Inst_VOP2__V_LSHLREV_B16(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_lshlrev_b16")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_LSHLREV_B16
+
+ Inst_VOP2__V_LSHLREV_B16::~Inst_VOP2__V_LSHLREV_B16()
+ {
+ } // ~Inst_VOP2__V_LSHLREV_B16
+
+ // D.u[15:0] = S1.u[15:0] << S0.u[3:0].
+ void
+ Inst_VOP2__V_LSHLREV_B16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src1[lane] << bits(src0[lane], 3, 0);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_LSHRREV_B16::Inst_VOP2__V_LSHRREV_B16(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_lshrrev_b16")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_LSHRREV_B16
+
+ Inst_VOP2__V_LSHRREV_B16::~Inst_VOP2__V_LSHRREV_B16()
+ {
+ } // ~Inst_VOP2__V_LSHRREV_B16
+
+ // D.u[15:0] = S1.u[15:0] >> S0.u[3:0].
+ // The vacated bits are set to zero.
+ void
+ Inst_VOP2__V_LSHRREV_B16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src1[lane] >> src0[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_ASHRREV_I16::Inst_VOP2__V_ASHRREV_I16(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_ashrrev_i16")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_ASHRREV_I16
+
+ Inst_VOP2__V_ASHRREV_I16::~Inst_VOP2__V_ASHRREV_I16()
+ {
+ } // ~Inst_VOP2__V_ASHRREV_I16
+
+ // D.i[15:0] = signext(S1.i[15:0]) >> S0.i[3:0].
+ // The vacated bits are set to the sign bit of the input value.
+ void
+ Inst_VOP2__V_ASHRREV_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
+ VecOperandI16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src1[lane] >> src0[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_MAX_F16::Inst_VOP2__V_MAX_F16(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_max_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP2__V_MAX_F16
+
+ Inst_VOP2__V_MAX_F16::~Inst_VOP2__V_MAX_F16()
+ {
+ } // ~Inst_VOP2__V_MAX_F16
+
+ // D.f16 = max(S0.f16, S1.f16).
+ void
+ Inst_VOP2__V_MAX_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP2__V_MIN_F16::Inst_VOP2__V_MIN_F16(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_min_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP2__V_MIN_F16
+
+ Inst_VOP2__V_MIN_F16::~Inst_VOP2__V_MIN_F16()
+ {
+ } // ~Inst_VOP2__V_MIN_F16
+
+ // D.f16 = min(S0.f16, S1.f16).
+ void
+ Inst_VOP2__V_MIN_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP2__V_MAX_U16::Inst_VOP2__V_MAX_U16(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_max_u16")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_MAX_U16
+
+ Inst_VOP2__V_MAX_U16::~Inst_VOP2__V_MAX_U16()
+ {
+ } // ~Inst_VOP2__V_MAX_U16
+
+ // D.u[15:0] = max(S0.u[15:0], S1.u[15:0]).
+ void
+ Inst_VOP2__V_MAX_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::max(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_MAX_I16::Inst_VOP2__V_MAX_I16(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_max_i16")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_MAX_I16
+
+ Inst_VOP2__V_MAX_I16::~Inst_VOP2__V_MAX_I16()
+ {
+ } // ~Inst_VOP2__V_MAX_I16
+
+ // D.i[15:0] = max(S0.i[15:0], S1.i[15:0]).
+ void
+ Inst_VOP2__V_MAX_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
+ VecOperandI16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::max(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_MIN_U16::Inst_VOP2__V_MIN_U16(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_min_u16")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_MIN_U16
+
+ Inst_VOP2__V_MIN_U16::~Inst_VOP2__V_MIN_U16()
+ {
+ } // ~Inst_VOP2__V_MIN_U16
+
+ // D.u[15:0] = min(S0.u[15:0], S1.u[15:0]).
+ void
+ Inst_VOP2__V_MIN_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
+ VecOperandU16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::min(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_MIN_I16::Inst_VOP2__V_MIN_I16(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_min_i16")
+ {
+ setFlag(ALU);
+ } // Inst_VOP2__V_MIN_I16
+
+ Inst_VOP2__V_MIN_I16::~Inst_VOP2__V_MIN_I16()
+ {
+ } // ~Inst_VOP2__V_MIN_I16
+
+ // D.i[15:0] = min(S0.i[15:0], S1.i[15:0]).
+ void
+ Inst_VOP2__V_MIN_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
+ VecOperandI16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::min(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP2__V_LDEXP_F16::Inst_VOP2__V_LDEXP_F16(InFmt_VOP2 *iFmt)
+ : Inst_VOP2(iFmt, "v_ldexp_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP2__V_LDEXP_F16
+
+ Inst_VOP2__V_LDEXP_F16::~Inst_VOP2__V_LDEXP_F16()
+ {
+ } // ~Inst_VOP2__V_LDEXP_F16
+
+ // D.f16 = S0.f16 * (2 ** S1.i16).
+ void
+ Inst_VOP2__V_LDEXP_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_NOP::Inst_VOP1__V_NOP(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_nop")
+ {
+ setFlag(Nop);
+ setFlag(ALU);
+ } // Inst_VOP1__V_NOP
+
+ Inst_VOP1__V_NOP::~Inst_VOP1__V_NOP()
+ {
+ } // ~Inst_VOP1__V_NOP
+
+ // Do nothing.
+ void
+ Inst_VOP1__V_NOP::execute(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_VOP1__V_MOV_B32::Inst_VOP1__V_MOV_B32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_mov_b32")
+ {
+ setFlag(ALU);
+ } // Inst_VOP1__V_MOV_B32
+
+ Inst_VOP1__V_MOV_B32::~Inst_VOP1__V_MOV_B32()
+ {
+ } // ~Inst_VOP1__V_MOV_B32
+
+ // D.u = S0.u.
+ // Input and output modifiers not supported; this is an untyped operation.
+ void
+ Inst_VOP1__V_MOV_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src(gpuDynInst, instData.SRC0);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ if (isDPPInst()) {
+ VecOperandU32 src0_dpp(gpuDynInst, extData.iFmt_VOP_DPP.SRC0);
+
+ DPRINTF(GCN3, "Handling V_MOV_B32 SRC DPP. SRC0: register v[%d], "
+ "DPP_CTRL: 0x%#x, SRC0_ABS: %d, SRC0_NEG: %d, "
+ "SRC1_ABS: %d, SRC1_NEG: %d, BOUND_CTRL: %d, "
+ "BANK_MASK: %d, ROW_MASK: %d\n", extData.iFmt_VOP_DPP.SRC0,
+ extData.iFmt_VOP_DPP.DPP_CTRL,
+ extData.iFmt_VOP_DPP.SRC0_ABS,
+ extData.iFmt_VOP_DPP.SRC0_NEG,
+ extData.iFmt_VOP_DPP.SRC1_ABS,
+ extData.iFmt_VOP_DPP.SRC1_NEG,
+ extData.iFmt_VOP_DPP.BOUND_CTRL,
+ extData.iFmt_VOP_DPP.BANK_MASK,
+ extData.iFmt_VOP_DPP.ROW_MASK);
+
+ // NOTE: For VOP1, there is no SRC1, so make sure we're not trying
+ // to negate it or take the absolute value of it
+ assert(!extData.iFmt_VOP_DPP.SRC1_ABS);
+ assert(!extData.iFmt_VOP_DPP.SRC1_NEG);
+ processDPP(gpuDynInst, extData.iFmt_VOP_DPP, src0_dpp);
+ }
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_READFIRSTLANE_B32::Inst_VOP1__V_READFIRSTLANE_B32(
+ InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_readfirstlane_b32")
+ {
+ setFlag(ALU);
+ } // Inst_VOP1__V_READFIRSTLANE_B32
+
+ Inst_VOP1__V_READFIRSTLANE_B32::~Inst_VOP1__V_READFIRSTLANE_B32()
+ {
+ } // ~Inst_VOP1__V_READFIRSTLANE_B32
+
+ // Copy one VGPR value to one SGPR. D = SGPR destination, S0 = source data
+ // (VGPR# or M0 for lds direct access), Lane# = FindFirst1fromLSB(exec)
+ // (Lane# = 0 if exec is zero). Ignores exec mask for the access.
+ // Input and output modifiers not supported; this is an untyped operation.
+ void
+ Inst_VOP1__V_READFIRSTLANE_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarRegI32 src_lane(0);
+ ScalarRegU64 exec_mask = wf->execMask().to_ullong();
+ ConstVecOperandU32 src(gpuDynInst, instData.SRC0);
+ ScalarOperandU32 sdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (exec_mask) {
+ src_lane = findLsbSet(exec_mask);
+ }
+
+ sdst = src[src_lane];
+
+ sdst.write();
+ }
+
+ Inst_VOP1__V_CVT_I32_F64::Inst_VOP1__V_CVT_I32_F64(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_i32_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP1__V_CVT_I32_F64
+
+ Inst_VOP1__V_CVT_I32_F64::~Inst_VOP1__V_CVT_I32_F64()
+ {
+ } // ~Inst_VOP1__V_CVT_I32_F64
+
+ // D.i = (int)S0.d.
+ // Out-of-range floating point values (including infinity) saturate. NaN
+ // is converted to 0.
+ void
+ Inst_VOP1__V_CVT_I32_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, instData.SRC0);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::isnan(src[lane])) {
+ vdst[lane] = 0;
+ } else {
+ vdst[lane] = (VecElemI32)src[lane];
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_CVT_F64_I32::Inst_VOP1__V_CVT_F64_I32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_f64_i32")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP1__V_CVT_F64_I32
+
+ Inst_VOP1__V_CVT_F64_I32::~Inst_VOP1__V_CVT_F64_I32()
+ {
+ } // ~Inst_VOP1__V_CVT_F64_I32
+
+ // D.d = (double)S0.i.
+ void
+ Inst_VOP1__V_CVT_F64_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src(gpuDynInst, instData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemF64)src[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_CVT_F32_I32::Inst_VOP1__V_CVT_F32_I32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_f32_i32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_CVT_F32_I32
+
+ Inst_VOP1__V_CVT_F32_I32::~Inst_VOP1__V_CVT_F32_I32()
+ {
+ } // ~Inst_VOP1__V_CVT_F32_I32
+
+ // D.f = (float)S0.i.
+ void
+ Inst_VOP1__V_CVT_F32_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src(gpuDynInst, instData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemF32)src[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_CVT_F32_U32::Inst_VOP1__V_CVT_F32_U32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_f32_u32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_CVT_F32_U32
+
+ Inst_VOP1__V_CVT_F32_U32::~Inst_VOP1__V_CVT_F32_U32()
+ {
+ } // ~Inst_VOP1__V_CVT_F32_U32
+
+ // D.f = (float)S0.u.
+ void
+ Inst_VOP1__V_CVT_F32_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src(gpuDynInst, instData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemF32)src[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_CVT_U32_F32::Inst_VOP1__V_CVT_U32_F32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_u32_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_CVT_U32_F32
+
+ Inst_VOP1__V_CVT_U32_F32::~Inst_VOP1__V_CVT_U32_F32()
+ {
+ } // ~Inst_VOP1__V_CVT_U32_F32
+
+ // D.u = (unsigned)S0.f.
+ // Out-of-range floating point values (including infinity) saturate. NaN
+ // is converted to 0.
+ void
+ Inst_VOP1__V_CVT_U32_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, instData.SRC0);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::isnan(src[lane])) {
+ vdst[lane] = 0;
+ } else {
+ vdst[lane] = (VecElemU32)src[lane];
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_CVT_I32_F32::Inst_VOP1__V_CVT_I32_F32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_i32_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_CVT_I32_F32
+
+ Inst_VOP1__V_CVT_I32_F32::~Inst_VOP1__V_CVT_I32_F32()
+ {
+ } // ~Inst_VOP1__V_CVT_I32_F32
+
+ // D.i = (int)S0.f.
+ // Out-of-range floating point values (including infinity) saturate. NaN
+ // is converted to 0.
+ void
+ Inst_VOP1__V_CVT_I32_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, instData.SRC0);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::isnan(src[lane])) {
+ vdst[lane] = 0;
+ } else {
+ vdst[lane] = (VecElemI32)src[lane];
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_MOV_FED_B32::Inst_VOP1__V_MOV_FED_B32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_mov_fed_b32")
+ {
+ setFlag(ALU);
+ } // Inst_VOP1__V_MOV_FED_B32
+
+ Inst_VOP1__V_MOV_FED_B32::~Inst_VOP1__V_MOV_FED_B32()
+ {
+ } // ~Inst_VOP1__V_MOV_FED_B32
+
+ // D.u = S0.u;
+ // Input and output modifiers not supported; this is an untyped operation.
+ void
+ Inst_VOP1__V_MOV_FED_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_CVT_F16_F32::Inst_VOP1__V_CVT_F16_F32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_f16_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_CVT_F16_F32
+
+ Inst_VOP1__V_CVT_F16_F32::~Inst_VOP1__V_CVT_F16_F32()
+ {
+ } // ~Inst_VOP1__V_CVT_F16_F32
+
+ // D.f16 = flt32_to_flt16(S0.f).
+ void
+ Inst_VOP1__V_CVT_F16_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_CVT_F32_F16::Inst_VOP1__V_CVT_F32_F16(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_f32_f16")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_CVT_F32_F16
+
+ Inst_VOP1__V_CVT_F32_F16::~Inst_VOP1__V_CVT_F32_F16()
+ {
+ } // ~Inst_VOP1__V_CVT_F32_F16
+
+ // D.f = flt16_to_flt32(S0.f16).
+ void
+ Inst_VOP1__V_CVT_F32_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_CVT_RPI_I32_F32::Inst_VOP1__V_CVT_RPI_I32_F32(
+ InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_rpi_i32_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_CVT_RPI_I32_F32
+
+ Inst_VOP1__V_CVT_RPI_I32_F32::~Inst_VOP1__V_CVT_RPI_I32_F32()
+ {
+ } // ~Inst_VOP1__V_CVT_RPI_I32_F32
+
+ // D.i = (int)floor(S0.f + 0.5).
+ void
+ Inst_VOP1__V_CVT_RPI_I32_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, instData.SRC0);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemI32)std::floor(src[lane] + 0.5);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_CVT_FLR_I32_F32::Inst_VOP1__V_CVT_FLR_I32_F32(
+ InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_flr_i32_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_CVT_FLR_I32_F32
+
+ Inst_VOP1__V_CVT_FLR_I32_F32::~Inst_VOP1__V_CVT_FLR_I32_F32()
+ {
+ } // ~Inst_VOP1__V_CVT_FLR_I32_F32
+
+ // D.i = (int)floor(S0.f).
+ void
+ Inst_VOP1__V_CVT_FLR_I32_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, instData.SRC0);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemI32)std::floor(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_CVT_OFF_F32_I4::Inst_VOP1__V_CVT_OFF_F32_I4(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_off_f32_i4")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_CVT_OFF_F32_I4
+
+ Inst_VOP1__V_CVT_OFF_F32_I4::~Inst_VOP1__V_CVT_OFF_F32_I4()
+ {
+ } // ~Inst_VOP1__V_CVT_OFF_F32_I4
+
+ // 4-bit signed int to 32-bit float.
+ void
+ Inst_VOP1__V_CVT_OFF_F32_I4::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_CVT_F32_F64::Inst_VOP1__V_CVT_F32_F64(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_f32_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP1__V_CVT_F32_F64
+
+ Inst_VOP1__V_CVT_F32_F64::~Inst_VOP1__V_CVT_F32_F64()
+ {
+ } // ~Inst_VOP1__V_CVT_F32_F64
+
+ // D.f = (float)S0.d.
+ void
+ Inst_VOP1__V_CVT_F32_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, instData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemF32)src[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_CVT_F64_F32::Inst_VOP1__V_CVT_F64_F32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_f64_f32")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP1__V_CVT_F64_F32
+
+ Inst_VOP1__V_CVT_F64_F32::~Inst_VOP1__V_CVT_F64_F32()
+ {
+ } // ~Inst_VOP1__V_CVT_F64_F32
+
+ // D.d = (double)S0.f.
+ void
+ Inst_VOP1__V_CVT_F64_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, instData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemF64)src[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_CVT_F32_UBYTE0::Inst_VOP1__V_CVT_F32_UBYTE0(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_f32_ubyte0")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_CVT_F32_UBYTE0
+
+ Inst_VOP1__V_CVT_F32_UBYTE0::~Inst_VOP1__V_CVT_F32_UBYTE0()
+ {
+ } // ~Inst_VOP1__V_CVT_F32_UBYTE0
+
+ // D.f = (float)(S0.u[7:0]).
+ void
+ Inst_VOP1__V_CVT_F32_UBYTE0::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src(gpuDynInst, instData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemF32)(bits(src[lane], 7, 0));
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_CVT_F32_UBYTE1::Inst_VOP1__V_CVT_F32_UBYTE1(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_f32_ubyte1")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_CVT_F32_UBYTE1
+
+ Inst_VOP1__V_CVT_F32_UBYTE1::~Inst_VOP1__V_CVT_F32_UBYTE1()
+ {
+ } // ~Inst_VOP1__V_CVT_F32_UBYTE1
+
+ // D.f = (float)(S0.u[15:8]).
+ void
+ Inst_VOP1__V_CVT_F32_UBYTE1::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src(gpuDynInst, instData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemF32)(bits(src[lane], 15, 8));
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_CVT_F32_UBYTE2::Inst_VOP1__V_CVT_F32_UBYTE2(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_f32_ubyte2")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_CVT_F32_UBYTE2
+
+ Inst_VOP1__V_CVT_F32_UBYTE2::~Inst_VOP1__V_CVT_F32_UBYTE2()
+ {
+ } // ~Inst_VOP1__V_CVT_F32_UBYTE2
+
+ // D.f = (float)(S0.u[23:16]).
+ void
+ Inst_VOP1__V_CVT_F32_UBYTE2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src(gpuDynInst, instData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemF32)(bits(src[lane], 23, 16));
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_CVT_F32_UBYTE3::Inst_VOP1__V_CVT_F32_UBYTE3(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_f32_ubyte3")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_CVT_F32_UBYTE3
+
+ Inst_VOP1__V_CVT_F32_UBYTE3::~Inst_VOP1__V_CVT_F32_UBYTE3()
+ {
+ } // ~Inst_VOP1__V_CVT_F32_UBYTE3
+
+ // D.f = (float)(S0.u[31:24]).
+ void
+ Inst_VOP1__V_CVT_F32_UBYTE3::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src(gpuDynInst, instData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemF32)(bits(src[lane], 31, 24));
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_CVT_U32_F64::Inst_VOP1__V_CVT_U32_F64(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_u32_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP1__V_CVT_U32_F64
+
+ Inst_VOP1__V_CVT_U32_F64::~Inst_VOP1__V_CVT_U32_F64()
+ {
+ } // ~Inst_VOP1__V_CVT_U32_F64
+
+ // D.u = (unsigned)S0.d.
+ // Out-of-range floating point values (including infinity) saturate. NaN
+ // is converted to 0.
+ void
+ Inst_VOP1__V_CVT_U32_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, instData.SRC0);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::isnan(src[lane])) {
+ vdst[lane] = 0;
+ } else {
+ vdst[lane] = (VecElemU32)src[lane];
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_CVT_F64_U32::Inst_VOP1__V_CVT_F64_U32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_f64_u32")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP1__V_CVT_F64_U32
+
+ Inst_VOP1__V_CVT_F64_U32::~Inst_VOP1__V_CVT_F64_U32()
+ {
+ } // ~Inst_VOP1__V_CVT_F64_U32
+
+ // D.d = (double)S0.u.
+ void
+ Inst_VOP1__V_CVT_F64_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src(gpuDynInst, instData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemF64)src[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_TRUNC_F64::Inst_VOP1__V_TRUNC_F64(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_trunc_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP1__V_TRUNC_F64
+
+ Inst_VOP1__V_TRUNC_F64::~Inst_VOP1__V_TRUNC_F64()
+ {
+ } // ~Inst_VOP1__V_TRUNC_F64
+
+ // D.d = trunc(S0.d), return integer part of S0.d.
+ void
+ Inst_VOP1__V_TRUNC_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, instData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::trunc(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_CEIL_F64::Inst_VOP1__V_CEIL_F64(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_ceil_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP1__V_CEIL_F64
+
+ Inst_VOP1__V_CEIL_F64::~Inst_VOP1__V_CEIL_F64()
+ {
+ } // ~Inst_VOP1__V_CEIL_F64
+
+ // D.d = ceil(S0.d);
+ void
+ Inst_VOP1__V_CEIL_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, instData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::ceil(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_RNDNE_F64::Inst_VOP1__V_RNDNE_F64(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_rndne_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP1__V_RNDNE_F64
+
+ Inst_VOP1__V_RNDNE_F64::~Inst_VOP1__V_RNDNE_F64()
+ {
+ } // ~Inst_VOP1__V_RNDNE_F64
+
+ // D.d = round_nearest_even(S0.d).
+ void
+ Inst_VOP1__V_RNDNE_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, instData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = roundNearestEven(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_FLOOR_F64::Inst_VOP1__V_FLOOR_F64(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_floor_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP1__V_FLOOR_F64
+
+ Inst_VOP1__V_FLOOR_F64::~Inst_VOP1__V_FLOOR_F64()
+ {
+ } // ~Inst_VOP1__V_FLOOR_F64
+
+ // D.d = floor(S0.d);
+ void
+ Inst_VOP1__V_FLOOR_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, instData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::floor(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_FRACT_F32::Inst_VOP1__V_FRACT_F32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_fract_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_FRACT_F32
+
+ Inst_VOP1__V_FRACT_F32::~Inst_VOP1__V_FRACT_F32()
+ {
+ } // ~Inst_VOP1__V_FRACT_F32
+
+ // D.f = modf(S0.f).
+ void
+ Inst_VOP1__V_FRACT_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, instData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ VecElemF32 int_part(0.0);
+ vdst[lane] = std::modf(src[lane], &int_part);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_TRUNC_F32::Inst_VOP1__V_TRUNC_F32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_trunc_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_TRUNC_F32
+
+ Inst_VOP1__V_TRUNC_F32::~Inst_VOP1__V_TRUNC_F32()
+ {
+ } // ~Inst_VOP1__V_TRUNC_F32
+
+ // D.f = trunc(S0.f), return integer part of S0.f.
+ void
+ Inst_VOP1__V_TRUNC_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, instData.SRC0);
+ VecOperandF32 vdst (gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::trunc(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_CEIL_F32::Inst_VOP1__V_CEIL_F32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_ceil_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_CEIL_F32
+
+ Inst_VOP1__V_CEIL_F32::~Inst_VOP1__V_CEIL_F32()
+ {
+ } // ~Inst_VOP1__V_CEIL_F32
+
+ // D.f = ceil(S0.f);
+ void
+ Inst_VOP1__V_CEIL_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, instData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::ceil(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_RNDNE_F32::Inst_VOP1__V_RNDNE_F32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_rndne_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_RNDNE_F32
+
+ Inst_VOP1__V_RNDNE_F32::~Inst_VOP1__V_RNDNE_F32()
+ {
+ } // ~Inst_VOP1__V_RNDNE_F32
+
+ // D.f = round_nearest_even(S0.f).
+ void
+ Inst_VOP1__V_RNDNE_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, instData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = roundNearestEven(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_FLOOR_F32::Inst_VOP1__V_FLOOR_F32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_floor_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_FLOOR_F32
+
+ Inst_VOP1__V_FLOOR_F32::~Inst_VOP1__V_FLOOR_F32()
+ {
+ } // ~Inst_VOP1__V_FLOOR_F32
+
+ // D.f = floor(S0.f);
+ void
+ Inst_VOP1__V_FLOOR_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, instData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::floor(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_EXP_F32::Inst_VOP1__V_EXP_F32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_exp_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_EXP_F32
+
+ Inst_VOP1__V_EXP_F32::~Inst_VOP1__V_EXP_F32()
+ {
+ } // ~Inst_VOP1__V_EXP_F32
+
+ // D.f = pow(2.0, S0.f).
+ void
+ Inst_VOP1__V_EXP_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, instData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::pow(2.0, src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_LOG_F32::Inst_VOP1__V_LOG_F32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_log_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_LOG_F32
+
+ Inst_VOP1__V_LOG_F32::~Inst_VOP1__V_LOG_F32()
+ {
+ } // ~Inst_VOP1__V_LOG_F32
+
+ // D.f = log2(S0.f).
+ void
+ Inst_VOP1__V_LOG_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, instData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::log2(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_RCP_F32::Inst_VOP1__V_RCP_F32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_rcp_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_RCP_F32
+
+ Inst_VOP1__V_RCP_F32::~Inst_VOP1__V_RCP_F32()
+ {
+ } // ~Inst_VOP1__V_RCP_F32
+
+ // D.f = 1.0 / S0.f.
+ void
+ Inst_VOP1__V_RCP_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, instData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = 1.0 / src[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_RCP_IFLAG_F32::Inst_VOP1__V_RCP_IFLAG_F32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_rcp_iflag_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_RCP_IFLAG_F32
+
+ Inst_VOP1__V_RCP_IFLAG_F32::~Inst_VOP1__V_RCP_IFLAG_F32()
+ {
+ } // ~Inst_VOP1__V_RCP_IFLAG_F32
+
+ // D.f = 1.0 / S0.f.
+ void
+ Inst_VOP1__V_RCP_IFLAG_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, instData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = 1.0 / src[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_RSQ_F32::Inst_VOP1__V_RSQ_F32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_rsq_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_RSQ_F32
+
+ Inst_VOP1__V_RSQ_F32::~Inst_VOP1__V_RSQ_F32()
+ {
+ } // ~Inst_VOP1__V_RSQ_F32
+
+ // D.f = 1.0 / sqrt(S0.f).
+ void
+ Inst_VOP1__V_RSQ_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, instData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = 1.0 / std::sqrt(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_RCP_F64::Inst_VOP1__V_RCP_F64(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_rcp_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP1__V_RCP_F64
+
+ Inst_VOP1__V_RCP_F64::~Inst_VOP1__V_RCP_F64()
+ {
+ } // ~Inst_VOP1__V_RCP_F64
+
+ // D.d = 1.0 / S0.d.
+ void
+ Inst_VOP1__V_RCP_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, instData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::fpclassify(src[lane]) == FP_ZERO) {
+ vdst[lane] = +INFINITY;
+ } else if (std::isnan(src[lane])) {
+ vdst[lane] = NAN;
+ } else if (std::isinf(src[lane])) {
+ if (std::signbit(src[lane])) {
+ vdst[lane] = -0.0;
+ } else {
+ vdst[lane] = 0.0;
+ }
+ } else {
+ vdst[lane] = 1.0 / src[lane];
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_RSQ_F64::Inst_VOP1__V_RSQ_F64(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_rsq_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP1__V_RSQ_F64
+
+ Inst_VOP1__V_RSQ_F64::~Inst_VOP1__V_RSQ_F64()
+ {
+ } // ~Inst_VOP1__V_RSQ_F64
+
+ // D.d = 1.0 / sqrt(S0.d).
+ void
+ Inst_VOP1__V_RSQ_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, instData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::fpclassify(src[lane]) == FP_ZERO) {
+ vdst[lane] = +INFINITY;
+ } else if (std::isnan(src[lane])) {
+ vdst[lane] = NAN;
+ } else if (std::isinf(src[lane])
+ && !std::signbit(src[lane])) {
+ vdst[lane] = 0.0;
+ } else if (std::signbit(src[lane])) {
+ vdst[lane] = NAN;
+ } else {
+ vdst[lane] = 1.0 / std::sqrt(src[lane]);
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_SQRT_F32::Inst_VOP1__V_SQRT_F32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_sqrt_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_SQRT_F32
+
+ Inst_VOP1__V_SQRT_F32::~Inst_VOP1__V_SQRT_F32()
+ {
+ } // ~Inst_VOP1__V_SQRT_F32
+
+ // D.f = sqrt(S0.f).
+ void
+ Inst_VOP1__V_SQRT_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, instData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::sqrt(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_SQRT_F64::Inst_VOP1__V_SQRT_F64(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_sqrt_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP1__V_SQRT_F64
+
+ Inst_VOP1__V_SQRT_F64::~Inst_VOP1__V_SQRT_F64()
+ {
+ } // ~Inst_VOP1__V_SQRT_F64
+
+ // D.d = sqrt(S0.d).
+ void
+ Inst_VOP1__V_SQRT_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, instData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::sqrt(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_SIN_F32::Inst_VOP1__V_SIN_F32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_sin_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_SIN_F32
+
+ Inst_VOP1__V_SIN_F32::~Inst_VOP1__V_SIN_F32()
+ {
+ } // ~Inst_VOP1__V_SIN_F32
+
+ // D.f = sin(S0.f * 2 * PI).
+ void
+ Inst_VOP1__V_SIN_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, instData.SRC0);
+ ConstScalarOperandF32 pi(gpuDynInst, REG_PI);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+ pi.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (src[lane] < -256.0 || src[lane] > 256.0) {
+ vdst[lane] = 0.0;
+ } else {
+ vdst[lane] = std::sin(src[lane] * 2.0 * pi.rawData());
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_COS_F32::Inst_VOP1__V_COS_F32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cos_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_COS_F32
+
+ Inst_VOP1__V_COS_F32::~Inst_VOP1__V_COS_F32()
+ {
+ } // ~Inst_VOP1__V_COS_F32
+
+ // D.f = cos(S0.f * 2 * PI).
+ void
+ Inst_VOP1__V_COS_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, instData.SRC0);
+ ConstScalarOperandF32 pi(gpuDynInst, REG_PI);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+ pi.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (src[lane] < -256.0 || src[lane] > 256.0) {
+ vdst[lane] = 0.0;
+ } else {
+ vdst[lane] = std::cos(src[lane] * 2.0 * pi.rawData());
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_NOT_B32::Inst_VOP1__V_NOT_B32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_not_b32")
+ {
+ setFlag(ALU);
+ } // Inst_VOP1__V_NOT_B32
+
+ Inst_VOP1__V_NOT_B32::~Inst_VOP1__V_NOT_B32()
+ {
+ } // ~Inst_VOP1__V_NOT_B32
+
+ // D.u = ~S0.u.
+ // Input and output modifiers not supported.
+ void
+ Inst_VOP1__V_NOT_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src(gpuDynInst, instData.SRC0);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = ~src[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_BFREV_B32::Inst_VOP1__V_BFREV_B32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_bfrev_b32")
+ {
+ setFlag(ALU);
+ } // Inst_VOP1__V_BFREV_B32
+
+ Inst_VOP1__V_BFREV_B32::~Inst_VOP1__V_BFREV_B32()
+ {
+ } // ~Inst_VOP1__V_BFREV_B32
+
+ // D.u[31:0] = S0.u[0:31], bitfield reverse.
+ // Input and output modifiers not supported.
+ void
+ Inst_VOP1__V_BFREV_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src(gpuDynInst, instData.SRC0);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = reverseBits(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_FFBH_U32::Inst_VOP1__V_FFBH_U32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_ffbh_u32")
+ {
+ setFlag(ALU);
+ } // Inst_VOP1__V_FFBH_U32
+
+ Inst_VOP1__V_FFBH_U32::~Inst_VOP1__V_FFBH_U32()
+ {
+ } // ~Inst_VOP1__V_FFBH_U32
+
+ // D.u = position of first 1 in S0.u from MSB;
+ // D.u = 0xffffffff if S0.u == 0.
+ void
+ Inst_VOP1__V_FFBH_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src(gpuDynInst, instData.SRC0);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = findFirstOneMsb(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_FFBL_B32::Inst_VOP1__V_FFBL_B32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_ffbl_b32")
+ {
+ setFlag(ALU);
+ } // Inst_VOP1__V_FFBL_B32
+
+ Inst_VOP1__V_FFBL_B32::~Inst_VOP1__V_FFBL_B32()
+ {
+ } // ~Inst_VOP1__V_FFBL_B32
+
+ // D.u = position of first 1 in S0.u from LSB;
+ // D.u = 0xffffffff if S0.u == 0.
+ void
+ Inst_VOP1__V_FFBL_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src(gpuDynInst, instData.SRC0);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = findFirstOne(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_FFBH_I32::Inst_VOP1__V_FFBH_I32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_ffbh_i32")
+ {
+ setFlag(ALU);
+ } // Inst_VOP1__V_FFBH_I32
+
+ Inst_VOP1__V_FFBH_I32::~Inst_VOP1__V_FFBH_I32()
+ {
+ } // ~Inst_VOP1__V_FFBH_I32
+
+ // D.u = position of first bit different from sign bit in S0.i from MSB;
+ // D.u = 0xffffffff if S0.i == 0 or S0.i == 0xffffffff.
+ void
+ Inst_VOP1__V_FFBH_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src(gpuDynInst, instData.SRC0);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = firstOppositeSignBit(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_FREXP_EXP_I32_F64::Inst_VOP1__V_FREXP_EXP_I32_F64(
+ InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_frexp_exp_i32_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP1__V_FREXP_EXP_I32_F64
+
+ Inst_VOP1__V_FREXP_EXP_I32_F64::~Inst_VOP1__V_FREXP_EXP_I32_F64()
+ {
+ } // ~Inst_VOP1__V_FREXP_EXP_I32_F64
+
+ void
+ Inst_VOP1__V_FREXP_EXP_I32_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, instData.SRC0);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::isinf(src[lane]) || std::isnan(src[lane])) {
+ vdst[lane] = 0;
+ } else {
+ VecElemI32 exp = 0;
+ std::frexp(src[lane], &exp);
+ vdst[lane] = exp;
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_FREXP_MANT_F64::Inst_VOP1__V_FREXP_MANT_F64(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_frexp_mant_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP1__V_FREXP_MANT_F64
+
+ Inst_VOP1__V_FREXP_MANT_F64::~Inst_VOP1__V_FREXP_MANT_F64()
+ {
+ } // ~Inst_VOP1__V_FREXP_MANT_F64
+
+ void
+ Inst_VOP1__V_FREXP_MANT_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, instData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::isinf(src[lane]) || std::isnan(src[lane])) {
+ vdst[lane] = src[lane];
+ } else {
+ VecElemI32 exp(0);
+ vdst[lane] = std::frexp(src[lane], &exp);
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_FRACT_F64::Inst_VOP1__V_FRACT_F64(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_fract_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP1__V_FRACT_F64
+
+ Inst_VOP1__V_FRACT_F64::~Inst_VOP1__V_FRACT_F64()
+ {
+ } // ~Inst_VOP1__V_FRACT_F64
+
+ void
+ Inst_VOP1__V_FRACT_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, instData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ VecElemF64 int_part(0.0);
+ vdst[lane] = std::modf(src[lane], &int_part);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_FREXP_EXP_I32_F32::Inst_VOP1__V_FREXP_EXP_I32_F32(
+ InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_frexp_exp_i32_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_FREXP_EXP_I32_F32
+
+ Inst_VOP1__V_FREXP_EXP_I32_F32::~Inst_VOP1__V_FREXP_EXP_I32_F32()
+ {
+ } // ~Inst_VOP1__V_FREXP_EXP_I32_F32
+
+ // frexp(S0.f, Exponent(S0.f))
+ // if (S0.f == INF || S0.f == NAN) then D.i = 0;
+ // else D.i = Exponent(S0.f);
+ void
+ Inst_VOP1__V_FREXP_EXP_I32_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, instData.SRC0);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::isinf(src[lane]) || std::isnan(src[lane])) {
+ vdst[lane] = 0;
+ } else {
+ VecElemI32 exp(0);
+ std::frexp(src[lane], &exp);
+ vdst[lane] = exp;
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_FREXP_MANT_F32::Inst_VOP1__V_FREXP_MANT_F32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_frexp_mant_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_FREXP_MANT_F32
+
+ Inst_VOP1__V_FREXP_MANT_F32::~Inst_VOP1__V_FREXP_MANT_F32()
+ {
+ } // ~Inst_VOP1__V_FREXP_MANT_F32
+
+ // if (S0.f == INF || S0.f == NAN) then D.f = S0.f;
+ // else D.f = frexp(S0.f, Exponent(S0.f)).
+ void
+ Inst_VOP1__V_FREXP_MANT_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, instData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::isinf(src[lane]) || std::isnan(src[lane])) {
+ vdst[lane] = src[lane];
+ } else {
+ VecElemI32 exp(0);
+ vdst[lane] = std::frexp(src[lane], &exp);
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_CLREXCP::Inst_VOP1__V_CLREXCP(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_clrexcp")
+ {
+ setFlag(ALU);
+ } // Inst_VOP1__V_CLREXCP
+
+ Inst_VOP1__V_CLREXCP::~Inst_VOP1__V_CLREXCP()
+ {
+ } // ~Inst_VOP1__V_CLREXCP
+
+ void
+ Inst_VOP1__V_CLREXCP::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_CVT_F16_U16::Inst_VOP1__V_CVT_F16_U16(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_f16_u16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP1__V_CVT_F16_U16
+
+ Inst_VOP1__V_CVT_F16_U16::~Inst_VOP1__V_CVT_F16_U16()
+ {
+ } // ~Inst_VOP1__V_CVT_F16_U16
+
+ // D.f16 = uint16_to_flt16(S.u16).
+ void
+ Inst_VOP1__V_CVT_F16_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_CVT_F16_I16::Inst_VOP1__V_CVT_F16_I16(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_f16_i16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP1__V_CVT_F16_I16
+
+ Inst_VOP1__V_CVT_F16_I16::~Inst_VOP1__V_CVT_F16_I16()
+ {
+ } // ~Inst_VOP1__V_CVT_F16_I16
+
+ // D.f16 = int16_to_flt16(S.i16).
+ void
+ Inst_VOP1__V_CVT_F16_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_CVT_U16_F16::Inst_VOP1__V_CVT_U16_F16(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_u16_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP1__V_CVT_U16_F16
+
+ Inst_VOP1__V_CVT_U16_F16::~Inst_VOP1__V_CVT_U16_F16()
+ {
+ } // ~Inst_VOP1__V_CVT_U16_F16
+
+ // D.u16 = flt16_to_uint16(S.f16).
+ void
+ Inst_VOP1__V_CVT_U16_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_CVT_I16_F16::Inst_VOP1__V_CVT_I16_F16(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cvt_i16_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP1__V_CVT_I16_F16
+
+ Inst_VOP1__V_CVT_I16_F16::~Inst_VOP1__V_CVT_I16_F16()
+ {
+ } // ~Inst_VOP1__V_CVT_I16_F16
+
+ // D.i16 = flt16_to_int16(S.f16).
+ void
+ Inst_VOP1__V_CVT_I16_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_RCP_F16::Inst_VOP1__V_RCP_F16(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_rcp_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP1__V_RCP_F16
+
+ Inst_VOP1__V_RCP_F16::~Inst_VOP1__V_RCP_F16()
+ {
+ } // ~Inst_VOP1__V_RCP_F16
+
+ // if (S0.f16 == 1.0f)
+ // D.f16 = 1.0f;
+ // else
+ // D.f16 = 1 / S0.f16;
+ void
+ Inst_VOP1__V_RCP_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_SQRT_F16::Inst_VOP1__V_SQRT_F16(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_sqrt_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP1__V_SQRT_F16
+
+ Inst_VOP1__V_SQRT_F16::~Inst_VOP1__V_SQRT_F16()
+ {
+ } // ~Inst_VOP1__V_SQRT_F16
+
+ // if (S0.f16 == 1.0f)
+ // D.f16 = 1.0f;
+ // else
+ // D.f16 = sqrt(S0.f16);
+ void
+ Inst_VOP1__V_SQRT_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_RSQ_F16::Inst_VOP1__V_RSQ_F16(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_rsq_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP1__V_RSQ_F16
+
+ Inst_VOP1__V_RSQ_F16::~Inst_VOP1__V_RSQ_F16()
+ {
+ } // ~Inst_VOP1__V_RSQ_F16
+
+ // if (S0.f16 == 1.0f)
+ // D.f16 = 1.0f;
+ // else
+ // D.f16 = 1 / sqrt(S0.f16);
+ void
+ Inst_VOP1__V_RSQ_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_LOG_F16::Inst_VOP1__V_LOG_F16(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_log_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP1__V_LOG_F16
+
+ Inst_VOP1__V_LOG_F16::~Inst_VOP1__V_LOG_F16()
+ {
+ } // ~Inst_VOP1__V_LOG_F16
+
+ // if (S0.f16 == 1.0f)
+ // D.f16 = 0.0f;
+ // else
+ // D.f16 = log2(S0.f16);
+ void
+ Inst_VOP1__V_LOG_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_EXP_F16::Inst_VOP1__V_EXP_F16(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_exp_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP1__V_EXP_F16
+
+ Inst_VOP1__V_EXP_F16::~Inst_VOP1__V_EXP_F16()
+ {
+ } // ~Inst_VOP1__V_EXP_F16
+
+ // if (S0.f16 == 0.0f)
+ // D.f16 = 1.0f;
+ // else
+ // D.f16 = pow(2.0, S0.f16).
+ void
+ Inst_VOP1__V_EXP_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_FREXP_MANT_F16::Inst_VOP1__V_FREXP_MANT_F16(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_frexp_mant_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP1__V_FREXP_MANT_F16
+
+ Inst_VOP1__V_FREXP_MANT_F16::~Inst_VOP1__V_FREXP_MANT_F16()
+ {
+ } // ~Inst_VOP1__V_FREXP_MANT_F16
+
+ // if (S0.f16 == +-INF || S0.f16 == NAN)
+ // D.f16 = S0.f16;
+ // else
+ // D.f16 = mantissa(S0.f16).
+ void
+ Inst_VOP1__V_FREXP_MANT_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_FREXP_EXP_I16_F16::Inst_VOP1__V_FREXP_EXP_I16_F16(
+ InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_frexp_exp_i16_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP1__V_FREXP_EXP_I16_F16
+
+ Inst_VOP1__V_FREXP_EXP_I16_F16::~Inst_VOP1__V_FREXP_EXP_I16_F16()
+ {
+ } // ~Inst_VOP1__V_FREXP_EXP_I16_F16
+
+ // frexp(S0.f16, Exponent(S0.f16))
+ // if (S0.f16 == +-INF || S0.f16 == NAN)
+ // D.i16 = 0;
+ // else
+ // D.i16 = Exponent(S0.f16);
+ void
+ Inst_VOP1__V_FREXP_EXP_I16_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_FLOOR_F16::Inst_VOP1__V_FLOOR_F16(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_floor_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP1__V_FLOOR_F16
+
+ Inst_VOP1__V_FLOOR_F16::~Inst_VOP1__V_FLOOR_F16()
+ {
+ } // ~Inst_VOP1__V_FLOOR_F16
+
+ // D.f16 = floor(S0.f16);
+ void
+ Inst_VOP1__V_FLOOR_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_CEIL_F16::Inst_VOP1__V_CEIL_F16(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_ceil_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP1__V_CEIL_F16
+
+ Inst_VOP1__V_CEIL_F16::~Inst_VOP1__V_CEIL_F16()
+ {
+ } // ~Inst_VOP1__V_CEIL_F16
+
+ // D.f16 = ceil(S0.f16);
+ void
+ Inst_VOP1__V_CEIL_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_TRUNC_F16::Inst_VOP1__V_TRUNC_F16(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_trunc_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP1__V_TRUNC_F16
+
+ Inst_VOP1__V_TRUNC_F16::~Inst_VOP1__V_TRUNC_F16()
+ {
+ } // ~Inst_VOP1__V_TRUNC_F16
+
+ // D.f16 = trunc(S0.f16).
+ void
+ Inst_VOP1__V_TRUNC_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_RNDNE_F16::Inst_VOP1__V_RNDNE_F16(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_rndne_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP1__V_RNDNE_F16
+
+ Inst_VOP1__V_RNDNE_F16::~Inst_VOP1__V_RNDNE_F16()
+ {
+ } // ~Inst_VOP1__V_RNDNE_F16
+
+ // D.f16 = roundNearestEven(S0.f16);
+ void
+ Inst_VOP1__V_RNDNE_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_FRACT_F16::Inst_VOP1__V_FRACT_F16(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_fract_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP1__V_FRACT_F16
+
+ Inst_VOP1__V_FRACT_F16::~Inst_VOP1__V_FRACT_F16()
+ {
+ } // ~Inst_VOP1__V_FRACT_F16
+
+ // D.f16 = S0.f16 + -floor(S0.f16).
+ void
+ Inst_VOP1__V_FRACT_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_SIN_F16::Inst_VOP1__V_SIN_F16(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_sin_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP1__V_SIN_F16
+
+ Inst_VOP1__V_SIN_F16::~Inst_VOP1__V_SIN_F16()
+ {
+ } // ~Inst_VOP1__V_SIN_F16
+
+ // D.f16 = sin(S0.f16 * 2 * PI).
+ void
+ Inst_VOP1__V_SIN_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_COS_F16::Inst_VOP1__V_COS_F16(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_cos_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP1__V_COS_F16
+
+ Inst_VOP1__V_COS_F16::~Inst_VOP1__V_COS_F16()
+ {
+ } // ~Inst_VOP1__V_COS_F16
+
+ // D.f16 = cos(S0.f16 * 2 * PI).
+ void
+ Inst_VOP1__V_COS_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP1__V_EXP_LEGACY_F32::Inst_VOP1__V_EXP_LEGACY_F32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_exp_legacy_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_EXP_LEGACY_F32
+
+ Inst_VOP1__V_EXP_LEGACY_F32::~Inst_VOP1__V_EXP_LEGACY_F32()
+ {
+ } // ~Inst_VOP1__V_EXP_LEGACY_F32
+
+ // D.f = pow(2.0, S0.f)
+ void
+ Inst_VOP1__V_EXP_LEGACY_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, instData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::pow(2.0, src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP1__V_LOG_LEGACY_F32::Inst_VOP1__V_LOG_LEGACY_F32(InFmt_VOP1 *iFmt)
+ : Inst_VOP1(iFmt, "v_log_legacy_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP1__V_LOG_LEGACY_F32
+
+ Inst_VOP1__V_LOG_LEGACY_F32::~Inst_VOP1__V_LOG_LEGACY_F32()
+ {
+ } // ~Inst_VOP1__V_LOG_LEGACY_F32
+
+ // D.f = log2(S0.f).
+ void
+ Inst_VOP1__V_LOG_LEGACY_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, instData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::log2(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOPC__V_CMP_CLASS_F32::Inst_VOPC__V_CMP_CLASS_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_class_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMP_CLASS_F32
+
+ Inst_VOPC__V_CMP_CLASS_F32::~Inst_VOPC__V_CMP_CLASS_F32()
+ {
+ } // ~Inst_VOPC__V_CMP_CLASS_F32
+
+ // VCC = IEEE numeric class function specified in S1.u, performed on S0.f
+ // The function reports true if the floating point value is any of the
+ // numeric types selected in S1.u according to the following list:
+ // S1.u[0] -- value is a signaling NaN.
+ // S1.u[1] -- value is a quiet NaN.
+ // S1.u[2] -- value is negative infinity.
+ // S1.u[3] -- value is a negative normal value.
+ // S1.u[4] -- value is a negative denormal value.
+ // S1.u[5] -- value is negative zero.
+ // S1.u[6] -- value is positive zero.
+ // S1.u[7] -- value is a positive denormal value.
+ // S1.u[8] -- value is a positive normal value.
+ // S1.u[9] -- value is positive infinity.
+ void
+ Inst_VOPC__V_CMP_CLASS_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ ConstScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (bits(src1[lane], 0) || bits(src1[lane], 1)) {
+ // is NaN
+ if (std::isnan(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 2)) {
+ // is -infinity
+ if (std::isinf(src0[lane]) && std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 3)) {
+ // is -normal
+ if (std::isnormal(src0[lane])
+ && std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 4)) {
+ // is -denormal
+ if (!std::isnormal(src0[lane])
+ && std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 5)) {
+ // is -zero
+ if (std::fpclassify(src0[lane]) == FP_ZERO
+ && std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 6)) {
+ // is +zero
+ if (std::fpclassify(src0[lane]) == FP_ZERO
+ && !std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 7)) {
+ // is +denormal
+ if (!std::isnormal(src0[lane])
+ && !std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 8)) {
+ // is +normal
+ if (std::isnormal(src0[lane])
+ && !std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 9)) {
+ // is +infinity
+ if (std::isinf(src0[lane]) && !std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_CLASS_F32::Inst_VOPC__V_CMPX_CLASS_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_class_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMPX_CLASS_F32
+
+ Inst_VOPC__V_CMPX_CLASS_F32::~Inst_VOPC__V_CMPX_CLASS_F32()
+ {
+ } // ~Inst_VOPC__V_CMPX_CLASS_F32
+
+ // EXEC, VCC = IEEE numeric class function specified in S1.u, performed on
+ // S0.f The function reports true if the floating point value is any of
+ // the numeric types selected in S1.u according to the following list:
+ // S1.u[0] -- value is a signaling NaN.
+ // S1.u[1] -- value is a quiet NaN.
+ // S1.u[2] -- value is negative infinity.
+ // S1.u[3] -- value is a negative normal value.
+ // S1.u[4] -- value is a negative denormal value.
+ // S1.u[5] -- value is negative zero.
+ // S1.u[6] -- value is positive zero.
+ // S1.u[7] -- value is a positive denormal value.
+ // S1.u[8] -- value is a positive normal value.
+ // S1.u[9] -- value is positive infinity.
+ void
+ Inst_VOPC__V_CMPX_CLASS_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ ConstScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (bits(src1[lane], 0) || bits(src1[lane], 1)) {
+ // is NaN
+ if (std::isnan(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 2)) {
+ // is -infinity
+ if (std::isinf(src0[lane]) && std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 3)) {
+ // is -normal
+ if (std::isnormal(src0[lane])
+ && std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 4)) {
+ // is -denormal
+ if (!std::isnormal(src0[lane])
+ && std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 5)) {
+ // is -zero
+ if (std::fpclassify(src0[lane]) == FP_ZERO
+ && std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 6)) {
+ // is +zero
+ if (std::fpclassify(src0[lane]) == FP_ZERO
+ && !std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 7)) {
+ // is +denormal
+ if (!std::isnormal(src0[lane])
+ && !std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 8)) {
+ // is +normal
+ if (std::isnormal(src0[lane])
+ && !std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 9)) {
+ // is +infinity
+ if (std::isinf(src0[lane]) && !std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ }
+ }
+
+ vcc.write();
+ wf->execMask() = vcc.rawData();
+ }
+
+ Inst_VOPC__V_CMP_CLASS_F64::Inst_VOPC__V_CMP_CLASS_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_class_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMP_CLASS_F64
+
+ Inst_VOPC__V_CMP_CLASS_F64::~Inst_VOPC__V_CMP_CLASS_F64()
+ {
+ } // ~Inst_VOPC__V_CMP_CLASS_F64
+
+ // VCC = IEEE numeric class function specified in S1.u, performed on S0.d
+ // The function reports true if the floating point value is any of the
+ // numeric types selected in S1.u according to the following list:
+ // S1.u[0] -- value is a signaling NaN.
+ // S1.u[1] -- value is a quiet NaN.
+ // S1.u[2] -- value is negative infinity.
+ // S1.u[3] -- value is a negative normal value.
+ // S1.u[4] -- value is a negative denormal value.
+ // S1.u[5] -- value is negative zero.
+ // S1.u[6] -- value is positive zero.
+ // S1.u[7] -- value is a positive denormal value.
+ // S1.u[8] -- value is a positive normal value.
+ // S1.u[9] -- value is positive infinity.
+ void
+ Inst_VOPC__V_CMP_CLASS_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ ConstScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (bits(src1[lane], 0) || bits(src1[lane], 1)) {
+ // is NaN
+ if (std::isnan(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 2)) {
+ // is -infinity
+ if (std::isinf(src0[lane]) && std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 3)) {
+ // is -normal
+ if (std::isnormal(src0[lane])
+ && std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 4)) {
+ // is -denormal
+ if (!std::isnormal(src0[lane])
+ && std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 5)) {
+ // is -zero
+ if (std::fpclassify(src0[lane]) == FP_ZERO
+ && std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 6)) {
+ // is +zero
+ if (std::fpclassify(src0[lane]) == FP_ZERO
+ && !std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 7)) {
+ // is +denormal
+ if (!std::isnormal(src0[lane])
+ && !std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 8)) {
+ // is +normal
+ if (std::isnormal(src0[lane])
+ && !std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 9)) {
+ // is +infinity
+ if (std::isinf(src0[lane])
+ && !std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_CLASS_F64::Inst_VOPC__V_CMPX_CLASS_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_class_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMPX_CLASS_F64
+
+ Inst_VOPC__V_CMPX_CLASS_F64::~Inst_VOPC__V_CMPX_CLASS_F64()
+ {
+ } // ~Inst_VOPC__V_CMPX_CLASS_F64
+
+ // EXEC, VCC = IEEE numeric class function specified in S1.u, performed on
+ // S0.d The function reports true if the floating point value is any of
+ // the numeric types selected in S1.u according to the following list:
+ // S1.u[0] -- value is a signaling NaN.
+ // S1.u[1] -- value is a quiet NaN.
+ // S1.u[2] -- value is negative infinity.
+ // S1.u[3] -- value is a negative normal value.
+ // S1.u[4] -- value is a negative denormal value.
+ // S1.u[5] -- value is negative zero.
+ // S1.u[6] -- value is positive zero.
+ // S1.u[7] -- value is a positive denormal value.
+ // S1.u[8] -- value is a positive normal value.
+ // S1.u[9] -- value is positive infinity.
+ void
+ Inst_VOPC__V_CMPX_CLASS_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ ConstScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (bits(src1[lane], 0) || bits(src1[lane], 1)) {
+ // is NaN
+ if (std::isnan(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 2)) {
+ // is -infinity
+ if (std::isinf(src0[lane]) && std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 3)) {
+ // is -normal
+ if (std::isnormal(src0[lane])
+ && std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 4)) {
+ // is -denormal
+ if (!std::isnormal(src0[lane])
+ && std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 5)) {
+ // is -zero
+ if (std::fpclassify(src0[lane]) == FP_ZERO
+ && std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 6)) {
+ // is +zero
+ if (std::fpclassify(src0[lane]) == FP_ZERO
+ && !std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 7)) {
+ // is +denormal
+ if (!std::isnormal(src0[lane])
+ && !std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 8)) {
+ // is +normal
+ if (std::isnormal(src0[lane])
+ && !std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 9)) {
+ // is +infinity
+ if (std::isinf(src0[lane])
+ && !std::signbit(src0[lane])) {
+ vcc.setBit(lane, 1);
+ continue;
+ }
+ }
+ }
+ }
+
+ vcc.write();
+ wf->execMask() = vcc.rawData();
+ }
+
+ Inst_VOPC__V_CMP_CLASS_F16::Inst_VOPC__V_CMP_CLASS_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_class_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMP_CLASS_F16
+
+ Inst_VOPC__V_CMP_CLASS_F16::~Inst_VOPC__V_CMP_CLASS_F16()
+ {
+ } // ~Inst_VOPC__V_CMP_CLASS_F16
+
+ // VCC = IEEE numeric class function specified in S1.u, performed on S0.f16
+ // The function reports true if the floating point value is any of the
+ // numeric types selected in S1.u according to the following list:
+ // S1.u[0] -- value is a signaling NaN.
+ // S1.u[1] -- value is a quiet NaN.
+ // S1.u[2] -- value is negative infinity.
+ // S1.u[3] -- value is a negative normal value.
+ // S1.u[4] -- value is a negative denormal value.
+ // S1.u[5] -- value is negative zero.
+ // S1.u[6] -- value is positive zero.
+ // S1.u[7] -- value is a positive denormal value.
+ // S1.u[8] -- value is a positive normal value.
+ // S1.u[9] -- value is positive infinity.
+ void
+ Inst_VOPC__V_CMP_CLASS_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMPX_CLASS_F16::Inst_VOPC__V_CMPX_CLASS_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_class_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMPX_CLASS_F16
+
+ Inst_VOPC__V_CMPX_CLASS_F16::~Inst_VOPC__V_CMPX_CLASS_F16()
+ {
+ } // ~Inst_VOPC__V_CMPX_CLASS_F16
+
+ // EXEC, VCC = IEEE numeric class function specified in S1.u, performed on
+ // S0.f16
+ // The function reports true if the floating point value is any of the
+ // numeric types selected in S1.u according to the following list:
+ // S1.u[0] -- value is a signaling NaN.
+ // S1.u[1] -- value is a quiet NaN.
+ // S1.u[2] -- value is negative infinity.
+ // S1.u[3] -- value is a negative normal value.
+ // S1.u[4] -- value is a negative denormal value.
+ // S1.u[5] -- value is negative zero.
+ // S1.u[6] -- value is positive zero.
+ // S1.u[7] -- value is a positive denormal value.
+ // S1.u[8] -- value is a positive normal value.
+ // S1.u[9] -- value is positive infinity.
+ void
+ Inst_VOPC__V_CMPX_CLASS_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMP_F_F16::Inst_VOPC__V_CMP_F_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_f_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMP_F_F16
+
+ Inst_VOPC__V_CMP_F_F16::~Inst_VOPC__V_CMP_F_F16()
+ {
+ } // ~Inst_VOPC__V_CMP_F_F16
+
+ // D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_F_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMP_LT_F16::Inst_VOPC__V_CMP_LT_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_lt_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMP_LT_F16
+
+ Inst_VOPC__V_CMP_LT_F16::~Inst_VOPC__V_CMP_LT_F16()
+ {
+ } // ~Inst_VOPC__V_CMP_LT_F16
+
+ // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_LT_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMP_EQ_F16::Inst_VOPC__V_CMP_EQ_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_eq_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMP_EQ_F16
+
+ Inst_VOPC__V_CMP_EQ_F16::~Inst_VOPC__V_CMP_EQ_F16()
+ {
+ } // ~Inst_VOPC__V_CMP_EQ_F16
+
+ // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_EQ_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMP_LE_F16::Inst_VOPC__V_CMP_LE_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_le_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMP_LE_F16
+
+ Inst_VOPC__V_CMP_LE_F16::~Inst_VOPC__V_CMP_LE_F16()
+ {
+ } // ~Inst_VOPC__V_CMP_LE_F16
+
+ // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_LE_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMP_GT_F16::Inst_VOPC__V_CMP_GT_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_gt_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMP_GT_F16
+
+ Inst_VOPC__V_CMP_GT_F16::~Inst_VOPC__V_CMP_GT_F16()
+ {
+ } // ~Inst_VOPC__V_CMP_GT_F16
+
+ // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_GT_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMP_LG_F16::Inst_VOPC__V_CMP_LG_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_lg_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMP_LG_F16
+
+ Inst_VOPC__V_CMP_LG_F16::~Inst_VOPC__V_CMP_LG_F16()
+ {
+ } // ~Inst_VOPC__V_CMP_LG_F16
+
+ // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_LG_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMP_GE_F16::Inst_VOPC__V_CMP_GE_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_ge_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMP_GE_F16
+
+ Inst_VOPC__V_CMP_GE_F16::~Inst_VOPC__V_CMP_GE_F16()
+ {
+ } // ~Inst_VOPC__V_CMP_GE_F16
+
+ // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_GE_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMP_O_F16::Inst_VOPC__V_CMP_O_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_o_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMP_O_F16
+
+ Inst_VOPC__V_CMP_O_F16::~Inst_VOPC__V_CMP_O_F16()
+ {
+ } // ~Inst_VOPC__V_CMP_O_F16
+
+ // D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_O_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMP_U_F16::Inst_VOPC__V_CMP_U_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_u_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMP_U_F16
+
+ Inst_VOPC__V_CMP_U_F16::~Inst_VOPC__V_CMP_U_F16()
+ {
+ } // ~Inst_VOPC__V_CMP_U_F16
+
+ // D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_U_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMP_NGE_F16::Inst_VOPC__V_CMP_NGE_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_nge_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMP_NGE_F16
+
+ Inst_VOPC__V_CMP_NGE_F16::~Inst_VOPC__V_CMP_NGE_F16()
+ {
+ } // ~Inst_VOPC__V_CMP_NGE_F16
+
+ // D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NGE_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMP_NLG_F16::Inst_VOPC__V_CMP_NLG_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_nlg_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMP_NLG_F16
+
+ Inst_VOPC__V_CMP_NLG_F16::~Inst_VOPC__V_CMP_NLG_F16()
+ {
+ } // ~Inst_VOPC__V_CMP_NLG_F16
+
+ // D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NLG_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMP_NGT_F16::Inst_VOPC__V_CMP_NGT_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_ngt_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMP_NGT_F16
+
+ Inst_VOPC__V_CMP_NGT_F16::~Inst_VOPC__V_CMP_NGT_F16()
+ {
+ } // ~Inst_VOPC__V_CMP_NGT_F16
+
+ // D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NGT_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMP_NLE_F16::Inst_VOPC__V_CMP_NLE_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_nle_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMP_NLE_F16
+
+ Inst_VOPC__V_CMP_NLE_F16::~Inst_VOPC__V_CMP_NLE_F16()
+ {
+ } // ~Inst_VOPC__V_CMP_NLE_F16
+
+ // D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NLE_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMP_NEQ_F16::Inst_VOPC__V_CMP_NEQ_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_neq_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMP_NEQ_F16
+
+ Inst_VOPC__V_CMP_NEQ_F16::~Inst_VOPC__V_CMP_NEQ_F16()
+ {
+ } // ~Inst_VOPC__V_CMP_NEQ_F16
+
+ // D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NEQ_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMP_NLT_F16::Inst_VOPC__V_CMP_NLT_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_nlt_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMP_NLT_F16
+
+ Inst_VOPC__V_CMP_NLT_F16::~Inst_VOPC__V_CMP_NLT_F16()
+ {
+ } // ~Inst_VOPC__V_CMP_NLT_F16
+
+ // D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NLT_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMP_TRU_F16::Inst_VOPC__V_CMP_TRU_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_tru_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMP_TRU_F16
+
+ Inst_VOPC__V_CMP_TRU_F16::~Inst_VOPC__V_CMP_TRU_F16()
+ {
+ } // ~Inst_VOPC__V_CMP_TRU_F16
+
+ // D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_TRU_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMPX_F_F16::Inst_VOPC__V_CMPX_F_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_f_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMPX_F_F16
+
+ Inst_VOPC__V_CMPX_F_F16::~Inst_VOPC__V_CMPX_F_F16()
+ {
+ } // ~Inst_VOPC__V_CMPX_F_F16
+
+ // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_F_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMPX_LT_F16::Inst_VOPC__V_CMPX_LT_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_lt_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMPX_LT_F16
+
+ Inst_VOPC__V_CMPX_LT_F16::~Inst_VOPC__V_CMPX_LT_F16()
+ {
+ } // ~Inst_VOPC__V_CMPX_LT_F16
+
+ // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_LT_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMPX_EQ_F16::Inst_VOPC__V_CMPX_EQ_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_eq_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMPX_EQ_F16
+
+ Inst_VOPC__V_CMPX_EQ_F16::~Inst_VOPC__V_CMPX_EQ_F16()
+ {
+ } // ~Inst_VOPC__V_CMPX_EQ_F16
+
+ // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_EQ_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMPX_LE_F16::Inst_VOPC__V_CMPX_LE_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_le_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMPX_LE_F16
+
+ Inst_VOPC__V_CMPX_LE_F16::~Inst_VOPC__V_CMPX_LE_F16()
+ {
+ } // ~Inst_VOPC__V_CMPX_LE_F16
+
+ // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_LE_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMPX_GT_F16::Inst_VOPC__V_CMPX_GT_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_gt_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMPX_GT_F16
+
+ Inst_VOPC__V_CMPX_GT_F16::~Inst_VOPC__V_CMPX_GT_F16()
+ {
+ } // ~Inst_VOPC__V_CMPX_GT_F16
+
+ // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_GT_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMPX_LG_F16::Inst_VOPC__V_CMPX_LG_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_lg_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMPX_LG_F16
+
+ Inst_VOPC__V_CMPX_LG_F16::~Inst_VOPC__V_CMPX_LG_F16()
+ {
+ } // ~Inst_VOPC__V_CMPX_LG_F16
+
+ // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_LG_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMPX_GE_F16::Inst_VOPC__V_CMPX_GE_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_ge_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMPX_GE_F16
+
+ Inst_VOPC__V_CMPX_GE_F16::~Inst_VOPC__V_CMPX_GE_F16()
+ {
+ } // ~Inst_VOPC__V_CMPX_GE_F16
+
+ // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_GE_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMPX_O_F16::Inst_VOPC__V_CMPX_O_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_o_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMPX_O_F16
+
+ Inst_VOPC__V_CMPX_O_F16::~Inst_VOPC__V_CMPX_O_F16()
+ {
+ } // ~Inst_VOPC__V_CMPX_O_F16
+
+ // EXEC,D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC
+ // encoding.
+ void
+ Inst_VOPC__V_CMPX_O_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMPX_U_F16::Inst_VOPC__V_CMPX_U_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_u_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMPX_U_F16
+
+ Inst_VOPC__V_CMPX_U_F16::~Inst_VOPC__V_CMPX_U_F16()
+ {
+ } // ~Inst_VOPC__V_CMPX_U_F16
+
+ // EXEC,D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC
+ // encoding.
+ void
+ Inst_VOPC__V_CMPX_U_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMPX_NGE_F16::Inst_VOPC__V_CMPX_NGE_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_nge_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMPX_NGE_F16
+
+ Inst_VOPC__V_CMPX_NGE_F16::~Inst_VOPC__V_CMPX_NGE_F16()
+ {
+ } // ~Inst_VOPC__V_CMPX_NGE_F16
+
+ // EXEC,D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NGE_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMPX_NLG_F16::Inst_VOPC__V_CMPX_NLG_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_nlg_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMPX_NLG_F16
+
+ Inst_VOPC__V_CMPX_NLG_F16::~Inst_VOPC__V_CMPX_NLG_F16()
+ {
+ } // ~Inst_VOPC__V_CMPX_NLG_F16
+
+ // EXEC,D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NLG_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMPX_NGT_F16::Inst_VOPC__V_CMPX_NGT_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_ngt_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMPX_NGT_F16
+
+ Inst_VOPC__V_CMPX_NGT_F16::~Inst_VOPC__V_CMPX_NGT_F16()
+ {
+ } // ~Inst_VOPC__V_CMPX_NGT_F16
+
+ // EXEC,D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NGT_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMPX_NLE_F16::Inst_VOPC__V_CMPX_NLE_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_nle_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMPX_NLE_F16
+
+ Inst_VOPC__V_CMPX_NLE_F16::~Inst_VOPC__V_CMPX_NLE_F16()
+ {
+ } // ~Inst_VOPC__V_CMPX_NLE_F16
+
+ // EXEC,D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NLE_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMPX_NEQ_F16::Inst_VOPC__V_CMPX_NEQ_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_neq_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMPX_NEQ_F16
+
+ Inst_VOPC__V_CMPX_NEQ_F16::~Inst_VOPC__V_CMPX_NEQ_F16()
+ {
+ } // ~Inst_VOPC__V_CMPX_NEQ_F16
+
+ // EXEC,D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NEQ_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMPX_NLT_F16::Inst_VOPC__V_CMPX_NLT_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_nlt_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMPX_NLT_F16
+
+ Inst_VOPC__V_CMPX_NLT_F16::~Inst_VOPC__V_CMPX_NLT_F16()
+ {
+ } // ~Inst_VOPC__V_CMPX_NLT_F16
+
+ // EXEC,D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NLT_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMPX_TRU_F16::Inst_VOPC__V_CMPX_TRU_F16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_tru_f16")
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOPC__V_CMPX_TRU_F16
+
+ Inst_VOPC__V_CMPX_TRU_F16::~Inst_VOPC__V_CMPX_TRU_F16()
+ {
+ } // ~Inst_VOPC__V_CMPX_TRU_F16
+
+ // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_TRU_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOPC__V_CMP_F_F32::Inst_VOPC__V_CMP_F_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_f_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMP_F_F32
+
+ Inst_VOPC__V_CMP_F_F32::~Inst_VOPC__V_CMP_F_F32()
+ {
+ } // ~Inst_VOPC__V_CMP_F_F32
+
+ // D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_F_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_LT_F32::Inst_VOPC__V_CMP_LT_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_lt_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMP_LT_F32
+
+ Inst_VOPC__V_CMP_LT_F32::~Inst_VOPC__V_CMP_LT_F32()
+ {
+ } // ~Inst_VOPC__V_CMP_LT_F32
+
+ // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_LT_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_EQ_F32::Inst_VOPC__V_CMP_EQ_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_eq_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMP_EQ_F32
+
+ Inst_VOPC__V_CMP_EQ_F32::~Inst_VOPC__V_CMP_EQ_F32()
+ {
+ } // ~Inst_VOPC__V_CMP_EQ_F32
+
+ // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_EQ_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_LE_F32::Inst_VOPC__V_CMP_LE_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_le_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMP_LE_F32
+
+ Inst_VOPC__V_CMP_LE_F32::~Inst_VOPC__V_CMP_LE_F32()
+ {
+ } // ~Inst_VOPC__V_CMP_LE_F32
+
+ // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_LE_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_GT_F32::Inst_VOPC__V_CMP_GT_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_gt_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMP_GT_F32
+
+ Inst_VOPC__V_CMP_GT_F32::~Inst_VOPC__V_CMP_GT_F32()
+ {
+ } // ~Inst_VOPC__V_CMP_GT_F32
+
+ // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_GT_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_LG_F32::Inst_VOPC__V_CMP_LG_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_lg_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMP_LG_F32
+
+ Inst_VOPC__V_CMP_LG_F32::~Inst_VOPC__V_CMP_LG_F32()
+ {
+ } // ~Inst_VOPC__V_CMP_LG_F32
+
+ // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_LG_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, (src0[lane] < src1[lane]
+ || src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_GE_F32::Inst_VOPC__V_CMP_GE_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_ge_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMP_GE_F32
+
+ Inst_VOPC__V_CMP_GE_F32::~Inst_VOPC__V_CMP_GE_F32()
+ {
+ } // ~Inst_VOPC__V_CMP_GE_F32
+
+ // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_GE_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_O_F32::Inst_VOPC__V_CMP_O_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_o_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMP_O_F32
+
+ Inst_VOPC__V_CMP_O_F32::~Inst_VOPC__V_CMP_O_F32()
+ {
+ } // ~Inst_VOPC__V_CMP_O_F32
+
+ // D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_O_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, (!std::isnan(src0[lane])
+ && !std::isnan(src1[lane])) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_U_F32::Inst_VOPC__V_CMP_U_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_u_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMP_U_F32
+
+ Inst_VOPC__V_CMP_U_F32::~Inst_VOPC__V_CMP_U_F32()
+ {
+ } // ~Inst_VOPC__V_CMP_U_F32
+
+ // D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_U_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, (std::isnan(src0[lane])
+ || std::isnan(src1[lane])) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_NGE_F32::Inst_VOPC__V_CMP_NGE_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_nge_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMP_NGE_F32
+
+ Inst_VOPC__V_CMP_NGE_F32::~Inst_VOPC__V_CMP_NGE_F32()
+ {
+ } // ~Inst_VOPC__V_CMP_NGE_F32
+
+ // D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NGE_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_NLG_F32::Inst_VOPC__V_CMP_NLG_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_nlg_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMP_NLG_F32
+
+ Inst_VOPC__V_CMP_NLG_F32::~Inst_VOPC__V_CMP_NLG_F32()
+ {
+ } // ~Inst_VOPC__V_CMP_NLG_F32
+
+ // D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NLG_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, !(src0[lane] < src1[lane]
+ || src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_NGT_F32::Inst_VOPC__V_CMP_NGT_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_ngt_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMP_NGT_F32
+
+ Inst_VOPC__V_CMP_NGT_F32::~Inst_VOPC__V_CMP_NGT_F32()
+ {
+ } // ~Inst_VOPC__V_CMP_NGT_F32
+
+ // D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NGT_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_NLE_F32::Inst_VOPC__V_CMP_NLE_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_nle_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMP_NLE_F32
+
+ Inst_VOPC__V_CMP_NLE_F32::~Inst_VOPC__V_CMP_NLE_F32()
+ {
+ } // ~Inst_VOPC__V_CMP_NLE_F32
+
+ // D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NLE_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_NEQ_F32::Inst_VOPC__V_CMP_NEQ_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_neq_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMP_NEQ_F32
+
+ Inst_VOPC__V_CMP_NEQ_F32::~Inst_VOPC__V_CMP_NEQ_F32()
+ {
+ } // ~Inst_VOPC__V_CMP_NEQ_F32
+
+ // D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NEQ_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_NLT_F32::Inst_VOPC__V_CMP_NLT_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_nlt_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMP_NLT_F32
+
+ Inst_VOPC__V_CMP_NLT_F32::~Inst_VOPC__V_CMP_NLT_F32()
+ {
+ } // ~Inst_VOPC__V_CMP_NLT_F32
+
+ // D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NLT_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_TRU_F32::Inst_VOPC__V_CMP_TRU_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_tru_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMP_TRU_F32
+
+ Inst_VOPC__V_CMP_TRU_F32::~Inst_VOPC__V_CMP_TRU_F32()
+ {
+ } // ~Inst_VOPC__V_CMP_TRU_F32
+
+ // D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_TRU_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 1);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_F_F32::Inst_VOPC__V_CMPX_F_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_f_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMPX_F_F32
+
+ Inst_VOPC__V_CMPX_F_F32::~Inst_VOPC__V_CMPX_F_F32()
+ {
+ } // ~Inst_VOPC__V_CMPX_F_F32
+
+ // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_F_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 0);
+ }
+ }
+
+ vcc.write();
+ wf->execMask() = vcc.rawData();
+ }
+
+ Inst_VOPC__V_CMPX_LT_F32::Inst_VOPC__V_CMPX_LT_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_lt_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMPX_LT_F32
+
+ Inst_VOPC__V_CMPX_LT_F32::~Inst_VOPC__V_CMPX_LT_F32()
+ {
+ } // ~Inst_VOPC__V_CMPX_LT_F32
+
+ // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_LT_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ wf->execMask() = vcc.rawData();
+ }
+
+ Inst_VOPC__V_CMPX_EQ_F32::Inst_VOPC__V_CMPX_EQ_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_eq_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMPX_EQ_F32
+
+ Inst_VOPC__V_CMPX_EQ_F32::~Inst_VOPC__V_CMPX_EQ_F32()
+ {
+ } // ~Inst_VOPC__V_CMPX_EQ_F32
+
+ // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_EQ_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ wf->execMask() = vcc.rawData();
+ }
+
+ Inst_VOPC__V_CMPX_LE_F32::Inst_VOPC__V_CMPX_LE_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_le_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMPX_LE_F32
+
+ Inst_VOPC__V_CMPX_LE_F32::~Inst_VOPC__V_CMPX_LE_F32()
+ {
+ } // ~Inst_VOPC__V_CMPX_LE_F32
+
+ // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_LE_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ wf->execMask() = vcc.rawData();
+ }
+
+ Inst_VOPC__V_CMPX_GT_F32::Inst_VOPC__V_CMPX_GT_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_gt_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMPX_GT_F32
+
+ Inst_VOPC__V_CMPX_GT_F32::~Inst_VOPC__V_CMPX_GT_F32()
+ {
+ } // ~Inst_VOPC__V_CMPX_GT_F32
+
+ // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_GT_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ wf->execMask() = vcc.rawData();
+ }
+
+ Inst_VOPC__V_CMPX_LG_F32::Inst_VOPC__V_CMPX_LG_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_lg_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMPX_LG_F32
+
+ Inst_VOPC__V_CMPX_LG_F32::~Inst_VOPC__V_CMPX_LG_F32()
+ {
+ } // ~Inst_VOPC__V_CMPX_LG_F32
+
+ // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_LG_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, (src0[lane] < src1[lane]
+ || src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ wf->execMask() = vcc.rawData();
+ }
+
+ Inst_VOPC__V_CMPX_GE_F32::Inst_VOPC__V_CMPX_GE_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_ge_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMPX_GE_F32
+
+ Inst_VOPC__V_CMPX_GE_F32::~Inst_VOPC__V_CMPX_GE_F32()
+ {
+ } // ~Inst_VOPC__V_CMPX_GE_F32
+
+ // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_GE_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ wf->execMask() = vcc.rawData();
+ }
+
+ Inst_VOPC__V_CMPX_O_F32::Inst_VOPC__V_CMPX_O_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_o_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMPX_O_F32
+
+ Inst_VOPC__V_CMPX_O_F32::~Inst_VOPC__V_CMPX_O_F32()
+ {
+ } // ~Inst_VOPC__V_CMPX_O_F32
+
+ // EXEC,D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC
+ // encoding.
+ void
+ Inst_VOPC__V_CMPX_O_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, (!std::isnan(src0[lane])
+ && !std::isnan(src1[lane])) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ wf->execMask() = vcc.rawData();
+ }
+
+ Inst_VOPC__V_CMPX_U_F32::Inst_VOPC__V_CMPX_U_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_u_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMPX_U_F32
+
+ Inst_VOPC__V_CMPX_U_F32::~Inst_VOPC__V_CMPX_U_F32()
+ {
+ } // ~Inst_VOPC__V_CMPX_U_F32
+
+ // EXEC,D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC
+ // encoding.
+ void
+ Inst_VOPC__V_CMPX_U_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, (std::isnan(src0[lane])
+ || std::isnan(src1[lane])) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ wf->execMask() = vcc.rawData();
+ }
+
+ Inst_VOPC__V_CMPX_NGE_F32::Inst_VOPC__V_CMPX_NGE_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_nge_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMPX_NGE_F32
+
+ Inst_VOPC__V_CMPX_NGE_F32::~Inst_VOPC__V_CMPX_NGE_F32()
+ {
+ } // ~Inst_VOPC__V_CMPX_NGE_F32
+
+ // EXEC,D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NGE_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ wf->execMask() = vcc.rawData();
+ }
+
+ Inst_VOPC__V_CMPX_NLG_F32::Inst_VOPC__V_CMPX_NLG_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_nlg_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMPX_NLG_F32
+
+ Inst_VOPC__V_CMPX_NLG_F32::~Inst_VOPC__V_CMPX_NLG_F32()
+ {
+ } // ~Inst_VOPC__V_CMPX_NLG_F32
+
+ // EXEC,D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NLG_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, !(src0[lane] < src1[lane]
+ || src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ wf->execMask() = vcc.rawData();
+ }
+
+ Inst_VOPC__V_CMPX_NGT_F32::Inst_VOPC__V_CMPX_NGT_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_ngt_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMPX_NGT_F32
+
+ Inst_VOPC__V_CMPX_NGT_F32::~Inst_VOPC__V_CMPX_NGT_F32()
+ {
+ } // ~Inst_VOPC__V_CMPX_NGT_F32
+
+ // EXEC,D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NGT_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ wf->execMask() = vcc.rawData();
+ }
+
+ Inst_VOPC__V_CMPX_NLE_F32::Inst_VOPC__V_CMPX_NLE_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_nle_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMPX_NLE_F32
+
+ Inst_VOPC__V_CMPX_NLE_F32::~Inst_VOPC__V_CMPX_NLE_F32()
+ {
+ } // ~Inst_VOPC__V_CMPX_NLE_F32
+
+ // EXEC,D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NLE_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ wf->execMask() = vcc.rawData();
+ }
+
+ Inst_VOPC__V_CMPX_NEQ_F32::Inst_VOPC__V_CMPX_NEQ_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_neq_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMPX_NEQ_F32
+
+ Inst_VOPC__V_CMPX_NEQ_F32::~Inst_VOPC__V_CMPX_NEQ_F32()
+ {
+ } // ~Inst_VOPC__V_CMPX_NEQ_F32
+
+ // EXEC,D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NEQ_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, !(src0[lane] == src1[lane]) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_NLT_F32::Inst_VOPC__V_CMPX_NLT_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_nlt_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMPX_NLT_F32
+
+ Inst_VOPC__V_CMPX_NLT_F32::~Inst_VOPC__V_CMPX_NLT_F32()
+ {
+ } // ~Inst_VOPC__V_CMPX_NLT_F32
+
+ // EXEC,D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NLT_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ wf->execMask() = vcc.rawData();
+ }
+
+ Inst_VOPC__V_CMPX_TRU_F32::Inst_VOPC__V_CMPX_TRU_F32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_tru_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOPC__V_CMPX_TRU_F32
+
+ Inst_VOPC__V_CMPX_TRU_F32::~Inst_VOPC__V_CMPX_TRU_F32()
+ {
+ } // ~Inst_VOPC__V_CMPX_TRU_F32
+
+ // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_TRU_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 1);
+ }
+ }
+
+ vcc.write();
+ wf->execMask() = vcc.rawData();
+ }
+
+ Inst_VOPC__V_CMP_F_F64::Inst_VOPC__V_CMP_F_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_f_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMP_F_F64
+
+ Inst_VOPC__V_CMP_F_F64::~Inst_VOPC__V_CMP_F_F64()
+ {
+ } // ~Inst_VOPC__V_CMP_F_F64
+
+ // D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_F_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_LT_F64::Inst_VOPC__V_CMP_LT_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_lt_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMP_LT_F64
+
+ Inst_VOPC__V_CMP_LT_F64::~Inst_VOPC__V_CMP_LT_F64()
+ {
+ } // ~Inst_VOPC__V_CMP_LT_F64
+
+ // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_LT_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_EQ_F64::Inst_VOPC__V_CMP_EQ_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_eq_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMP_EQ_F64
+
+ Inst_VOPC__V_CMP_EQ_F64::~Inst_VOPC__V_CMP_EQ_F64()
+ {
+ } // ~Inst_VOPC__V_CMP_EQ_F64
+
+ // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_EQ_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_LE_F64::Inst_VOPC__V_CMP_LE_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_le_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMP_LE_F64
+
+ Inst_VOPC__V_CMP_LE_F64::~Inst_VOPC__V_CMP_LE_F64()
+ {
+ } // ~Inst_VOPC__V_CMP_LE_F64
+
+ // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_LE_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_GT_F64::Inst_VOPC__V_CMP_GT_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_gt_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMP_GT_F64
+
+ Inst_VOPC__V_CMP_GT_F64::~Inst_VOPC__V_CMP_GT_F64()
+ {
+ } // ~Inst_VOPC__V_CMP_GT_F64
+
+ // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_GT_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_LG_F64::Inst_VOPC__V_CMP_LG_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_lg_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMP_LG_F64
+
+ Inst_VOPC__V_CMP_LG_F64::~Inst_VOPC__V_CMP_LG_F64()
+ {
+ } // ~Inst_VOPC__V_CMP_LG_F64
+
+ // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_LG_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, (src0[lane] < src1[lane]
+ || src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_GE_F64::Inst_VOPC__V_CMP_GE_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_ge_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMP_GE_F64
+
+ Inst_VOPC__V_CMP_GE_F64::~Inst_VOPC__V_CMP_GE_F64()
+ {
+ } // ~Inst_VOPC__V_CMP_GE_F64
+
+ // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_GE_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_O_F64::Inst_VOPC__V_CMP_O_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_o_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMP_O_F64
+
+ Inst_VOPC__V_CMP_O_F64::~Inst_VOPC__V_CMP_O_F64()
+ {
+ } // ~Inst_VOPC__V_CMP_O_F64
+
+ // D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_O_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, (!std::isnan(src0[lane])
+ && !std::isnan(src1[lane])) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_U_F64::Inst_VOPC__V_CMP_U_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_u_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMP_U_F64
+
+ Inst_VOPC__V_CMP_U_F64::~Inst_VOPC__V_CMP_U_F64()
+ {
+ } // ~Inst_VOPC__V_CMP_U_F64
+
+ // D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_U_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, (std::isnan(src0[lane])
+ || std::isnan(src1[lane])) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_NGE_F64::Inst_VOPC__V_CMP_NGE_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_nge_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMP_NGE_F64
+
+ Inst_VOPC__V_CMP_NGE_F64::~Inst_VOPC__V_CMP_NGE_F64()
+ {
+ } // ~Inst_VOPC__V_CMP_NGE_F64
+
+ // D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NGE_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_NLG_F64::Inst_VOPC__V_CMP_NLG_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_nlg_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMP_NLG_F64
+
+ Inst_VOPC__V_CMP_NLG_F64::~Inst_VOPC__V_CMP_NLG_F64()
+ {
+ } // ~Inst_VOPC__V_CMP_NLG_F64
+
+ // D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NLG_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, !(src0[lane] < src1[lane]
+ || src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_NGT_F64::Inst_VOPC__V_CMP_NGT_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_ngt_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMP_NGT_F64
+
+ Inst_VOPC__V_CMP_NGT_F64::~Inst_VOPC__V_CMP_NGT_F64()
+ {
+ } // ~Inst_VOPC__V_CMP_NGT_F64
+
+ // D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NGT_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_NLE_F64::Inst_VOPC__V_CMP_NLE_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_nle_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMP_NLE_F64
+
+ Inst_VOPC__V_CMP_NLE_F64::~Inst_VOPC__V_CMP_NLE_F64()
+ {
+ } // ~Inst_VOPC__V_CMP_NLE_F64
+
+ // D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NLE_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_NEQ_F64::Inst_VOPC__V_CMP_NEQ_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_neq_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMP_NEQ_F64
+
+ Inst_VOPC__V_CMP_NEQ_F64::~Inst_VOPC__V_CMP_NEQ_F64()
+ {
+ } // ~Inst_VOPC__V_CMP_NEQ_F64
+
+ // D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NEQ_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_NLT_F64::Inst_VOPC__V_CMP_NLT_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_nlt_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMP_NLT_F64
+
+ Inst_VOPC__V_CMP_NLT_F64::~Inst_VOPC__V_CMP_NLT_F64()
+ {
+ } // ~Inst_VOPC__V_CMP_NLT_F64
+
+ // D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NLT_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_TRU_F64::Inst_VOPC__V_CMP_TRU_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_tru_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMP_TRU_F64
+
+ Inst_VOPC__V_CMP_TRU_F64::~Inst_VOPC__V_CMP_TRU_F64()
+ {
+ } // ~Inst_VOPC__V_CMP_TRU_F64
+
+ // D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_TRU_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 1);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_F_F64::Inst_VOPC__V_CMPX_F_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_f_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMPX_F_F64
+
+ Inst_VOPC__V_CMPX_F_F64::~Inst_VOPC__V_CMPX_F_F64()
+ {
+ } // ~Inst_VOPC__V_CMPX_F_F64
+
+ // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_F_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 0);
+ }
+ }
+
+ vcc.write();
+ wf->execMask() = vcc.rawData();
+ }
+
+ Inst_VOPC__V_CMPX_LT_F64::Inst_VOPC__V_CMPX_LT_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_lt_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMPX_LT_F64
+
+ Inst_VOPC__V_CMPX_LT_F64::~Inst_VOPC__V_CMPX_LT_F64()
+ {
+ } // ~Inst_VOPC__V_CMPX_LT_F64
+
+ // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_LT_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ wf->execMask() = vcc.rawData();
+ }
+
+ Inst_VOPC__V_CMPX_EQ_F64::Inst_VOPC__V_CMPX_EQ_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_eq_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMPX_EQ_F64
+
+ Inst_VOPC__V_CMPX_EQ_F64::~Inst_VOPC__V_CMPX_EQ_F64()
+ {
+ } // ~Inst_VOPC__V_CMPX_EQ_F64
+
+ // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_EQ_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ wf->execMask() = vcc.rawData();
+ }
+
+ Inst_VOPC__V_CMPX_LE_F64::Inst_VOPC__V_CMPX_LE_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_le_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMPX_LE_F64
+
+ Inst_VOPC__V_CMPX_LE_F64::~Inst_VOPC__V_CMPX_LE_F64()
+ {
+ } // ~Inst_VOPC__V_CMPX_LE_F64
+
+ // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_LE_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_GT_F64::Inst_VOPC__V_CMPX_GT_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_gt_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMPX_GT_F64
+
+ Inst_VOPC__V_CMPX_GT_F64::~Inst_VOPC__V_CMPX_GT_F64()
+ {
+ } // ~Inst_VOPC__V_CMPX_GT_F64
+
+ // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_GT_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_LG_F64::Inst_VOPC__V_CMPX_LG_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_lg_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMPX_LG_F64
+
+ Inst_VOPC__V_CMPX_LG_F64::~Inst_VOPC__V_CMPX_LG_F64()
+ {
+ } // ~Inst_VOPC__V_CMPX_LG_F64
+
+ // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_LG_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, (src0[lane] < src1[lane]
+ || src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_GE_F64::Inst_VOPC__V_CMPX_GE_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_ge_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMPX_GE_F64
+
+ Inst_VOPC__V_CMPX_GE_F64::~Inst_VOPC__V_CMPX_GE_F64()
+ {
+ } // ~Inst_VOPC__V_CMPX_GE_F64
+
+ // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_GE_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_O_F64::Inst_VOPC__V_CMPX_O_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_o_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMPX_O_F64
+
+ Inst_VOPC__V_CMPX_O_F64::~Inst_VOPC__V_CMPX_O_F64()
+ {
+ } // ~Inst_VOPC__V_CMPX_O_F64
+
+ // EXEC,D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC
+ // encoding.
+ void
+ Inst_VOPC__V_CMPX_O_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, (!std::isnan(src0[lane])
+ && !std::isnan(src1[lane])) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_U_F64::Inst_VOPC__V_CMPX_U_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_u_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMPX_U_F64
+
+ Inst_VOPC__V_CMPX_U_F64::~Inst_VOPC__V_CMPX_U_F64()
+ {
+ } // ~Inst_VOPC__V_CMPX_U_F64
+
+ // EXEC,D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC
+ // encoding.
+ void
+ Inst_VOPC__V_CMPX_U_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, (std::isnan(src0[lane])
+ || std::isnan(src1[lane])) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_NGE_F64::Inst_VOPC__V_CMPX_NGE_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_nge_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMPX_NGE_F64
+
+ Inst_VOPC__V_CMPX_NGE_F64::~Inst_VOPC__V_CMPX_NGE_F64()
+ {
+ } // ~Inst_VOPC__V_CMPX_NGE_F64
+
+ // EXEC,D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NGE_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_NLG_F64::Inst_VOPC__V_CMPX_NLG_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_nlg_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMPX_NLG_F64
+
+ Inst_VOPC__V_CMPX_NLG_F64::~Inst_VOPC__V_CMPX_NLG_F64()
+ {
+ } // ~Inst_VOPC__V_CMPX_NLG_F64
+
+ // EXEC,D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NLG_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, !(src0[lane] < src1[lane]
+ || src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_NGT_F64::Inst_VOPC__V_CMPX_NGT_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_ngt_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMPX_NGT_F64
+
+ Inst_VOPC__V_CMPX_NGT_F64::~Inst_VOPC__V_CMPX_NGT_F64()
+ {
+ } // ~Inst_VOPC__V_CMPX_NGT_F64
+
+ // EXEC,D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NGT_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_NLE_F64::Inst_VOPC__V_CMPX_NLE_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_nle_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMPX_NLE_F64
+
+ Inst_VOPC__V_CMPX_NLE_F64::~Inst_VOPC__V_CMPX_NLE_F64()
+ {
+ } // ~Inst_VOPC__V_CMPX_NLE_F64
+
+ // EXEC,D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NLE_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_NEQ_F64::Inst_VOPC__V_CMPX_NEQ_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_neq_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMPX_NEQ_F64
+
+ Inst_VOPC__V_CMPX_NEQ_F64::~Inst_VOPC__V_CMPX_NEQ_F64()
+ {
+ } // ~Inst_VOPC__V_CMPX_NEQ_F64
+
+ // EXEC,D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NEQ_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_NLT_F64::Inst_VOPC__V_CMPX_NLT_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_nlt_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMPX_NLT_F64
+
+ Inst_VOPC__V_CMPX_NLT_F64::~Inst_VOPC__V_CMPX_NLT_F64()
+ {
+ } // ~Inst_VOPC__V_CMPX_NLT_F64
+
+ // EXEC,D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NLT_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_TRU_F64::Inst_VOPC__V_CMPX_TRU_F64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_tru_f64")
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOPC__V_CMPX_TRU_F64
+
+ Inst_VOPC__V_CMPX_TRU_F64::~Inst_VOPC__V_CMPX_TRU_F64()
+ {
+ } // ~Inst_VOPC__V_CMPX_TRU_F64
+
+ // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_TRU_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 1);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_F_I16::Inst_VOPC__V_CMP_F_I16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_f_i16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_F_I16
+
+ Inst_VOPC__V_CMP_F_I16::~Inst_VOPC__V_CMP_F_I16()
+ {
+ } // ~Inst_VOPC__V_CMP_F_I16
+
+ // D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_F_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_LT_I16::Inst_VOPC__V_CMP_LT_I16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_lt_i16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_LT_I16
+
+ Inst_VOPC__V_CMP_LT_I16::~Inst_VOPC__V_CMP_LT_I16()
+ {
+ } // ~Inst_VOPC__V_CMP_LT_I16
+
+ // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_LT_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_EQ_I16::Inst_VOPC__V_CMP_EQ_I16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_eq_i16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_EQ_I16
+
+ Inst_VOPC__V_CMP_EQ_I16::~Inst_VOPC__V_CMP_EQ_I16()
+ {
+ } // ~Inst_VOPC__V_CMP_EQ_I16
+
+ // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_EQ_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_LE_I16::Inst_VOPC__V_CMP_LE_I16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_le_i16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_LE_I16
+
+ Inst_VOPC__V_CMP_LE_I16::~Inst_VOPC__V_CMP_LE_I16()
+ {
+ } // ~Inst_VOPC__V_CMP_LE_I16
+
+ // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_LE_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_GT_I16::Inst_VOPC__V_CMP_GT_I16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_gt_i16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_GT_I16
+
+ Inst_VOPC__V_CMP_GT_I16::~Inst_VOPC__V_CMP_GT_I16()
+ {
+ } // ~Inst_VOPC__V_CMP_GT_I16
+
+ // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_GT_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_NE_I16::Inst_VOPC__V_CMP_NE_I16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_ne_i16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_NE_I16
+
+ Inst_VOPC__V_CMP_NE_I16::~Inst_VOPC__V_CMP_NE_I16()
+ {
+ } // ~Inst_VOPC__V_CMP_NE_I16
+
+ // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NE_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_GE_I16::Inst_VOPC__V_CMP_GE_I16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_ge_i16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_GE_I16
+
+ Inst_VOPC__V_CMP_GE_I16::~Inst_VOPC__V_CMP_GE_I16()
+ {
+ } // ~Inst_VOPC__V_CMP_GE_I16
+
+ // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_GE_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_T_I16::Inst_VOPC__V_CMP_T_I16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_t_i16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_T_I16
+
+ Inst_VOPC__V_CMP_T_I16::~Inst_VOPC__V_CMP_T_I16()
+ {
+ } // ~Inst_VOPC__V_CMP_T_I16
+
+ // D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_T_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 1);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_F_U16::Inst_VOPC__V_CMP_F_U16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_f_u16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_F_U16
+
+ Inst_VOPC__V_CMP_F_U16::~Inst_VOPC__V_CMP_F_U16()
+ {
+ } // ~Inst_VOPC__V_CMP_F_U16
+
+ // D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_F_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_LT_U16::Inst_VOPC__V_CMP_LT_U16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_lt_u16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_LT_U16
+
+ Inst_VOPC__V_CMP_LT_U16::~Inst_VOPC__V_CMP_LT_U16()
+ {
+ } // ~Inst_VOPC__V_CMP_LT_U16
+
+ // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_LT_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_EQ_U16::Inst_VOPC__V_CMP_EQ_U16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_eq_u16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_EQ_U16
+
+ Inst_VOPC__V_CMP_EQ_U16::~Inst_VOPC__V_CMP_EQ_U16()
+ {
+ } // ~Inst_VOPC__V_CMP_EQ_U16
+
+ // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_EQ_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_LE_U16::Inst_VOPC__V_CMP_LE_U16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_le_u16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_LE_U16
+
+ Inst_VOPC__V_CMP_LE_U16::~Inst_VOPC__V_CMP_LE_U16()
+ {
+ } // ~Inst_VOPC__V_CMP_LE_U16
+
+ // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_LE_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_GT_U16::Inst_VOPC__V_CMP_GT_U16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_gt_u16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_GT_U16
+
+ Inst_VOPC__V_CMP_GT_U16::~Inst_VOPC__V_CMP_GT_U16()
+ {
+ } // ~Inst_VOPC__V_CMP_GT_U16
+
+ // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_GT_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_NE_U16::Inst_VOPC__V_CMP_NE_U16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_ne_u16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_NE_U16
+
+ Inst_VOPC__V_CMP_NE_U16::~Inst_VOPC__V_CMP_NE_U16()
+ {
+ } // ~Inst_VOPC__V_CMP_NE_U16
+
+ // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NE_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_GE_U16::Inst_VOPC__V_CMP_GE_U16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_ge_u16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_GE_U16
+
+ Inst_VOPC__V_CMP_GE_U16::~Inst_VOPC__V_CMP_GE_U16()
+ {
+ } // ~Inst_VOPC__V_CMP_GE_U16
+
+ // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_GE_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_T_U16::Inst_VOPC__V_CMP_T_U16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_t_u16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_T_U16
+
+ Inst_VOPC__V_CMP_T_U16::~Inst_VOPC__V_CMP_T_U16()
+ {
+ } // ~Inst_VOPC__V_CMP_T_U16
+
+ // D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_T_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 1);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_F_I16::Inst_VOPC__V_CMPX_F_I16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_f_i16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_F_I16
+
+ Inst_VOPC__V_CMPX_F_I16::~Inst_VOPC__V_CMPX_F_I16()
+ {
+ } // ~Inst_VOPC__V_CMPX_F_I16
+
+ // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_F_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_LT_I16::Inst_VOPC__V_CMPX_LT_I16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_lt_i16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_LT_I16
+
+ Inst_VOPC__V_CMPX_LT_I16::~Inst_VOPC__V_CMPX_LT_I16()
+ {
+ } // ~Inst_VOPC__V_CMPX_LT_I16
+
+ // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_LT_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_EQ_I16::Inst_VOPC__V_CMPX_EQ_I16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_eq_i16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_EQ_I16
+
+ Inst_VOPC__V_CMPX_EQ_I16::~Inst_VOPC__V_CMPX_EQ_I16()
+ {
+ } // ~Inst_VOPC__V_CMPX_EQ_I16
+
+ // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_EQ_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_LE_I16::Inst_VOPC__V_CMPX_LE_I16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_le_i16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_LE_I16
+
+ Inst_VOPC__V_CMPX_LE_I16::~Inst_VOPC__V_CMPX_LE_I16()
+ {
+ } // ~Inst_VOPC__V_CMPX_LE_I16
+
+ // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_LE_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_GT_I16::Inst_VOPC__V_CMPX_GT_I16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_gt_i16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_GT_I16
+
+ Inst_VOPC__V_CMPX_GT_I16::~Inst_VOPC__V_CMPX_GT_I16()
+ {
+ } // ~Inst_VOPC__V_CMPX_GT_I16
+
+ // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_GT_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_NE_I16::Inst_VOPC__V_CMPX_NE_I16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_ne_i16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_NE_I16
+
+ Inst_VOPC__V_CMPX_NE_I16::~Inst_VOPC__V_CMPX_NE_I16()
+ {
+ } // ~Inst_VOPC__V_CMPX_NE_I16
+
+ // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NE_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_GE_I16::Inst_VOPC__V_CMPX_GE_I16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_ge_i16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_GE_I16
+
+ Inst_VOPC__V_CMPX_GE_I16::~Inst_VOPC__V_CMPX_GE_I16()
+ {
+ } // ~Inst_VOPC__V_CMPX_GE_I16
+
+ // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_GE_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_T_I16::Inst_VOPC__V_CMPX_T_I16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_t_i16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_T_I16
+
+ Inst_VOPC__V_CMPX_T_I16::~Inst_VOPC__V_CMPX_T_I16()
+ {
+ } // ~Inst_VOPC__V_CMPX_T_I16
+
+ // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_T_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 1);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_F_U16::Inst_VOPC__V_CMPX_F_U16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_f_u16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_F_U16
+
+ Inst_VOPC__V_CMPX_F_U16::~Inst_VOPC__V_CMPX_F_U16()
+ {
+ } // ~Inst_VOPC__V_CMPX_F_U16
+
+ // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_F_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_LT_U16::Inst_VOPC__V_CMPX_LT_U16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_lt_u16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_LT_U16
+
+ Inst_VOPC__V_CMPX_LT_U16::~Inst_VOPC__V_CMPX_LT_U16()
+ {
+ } // ~Inst_VOPC__V_CMPX_LT_U16
+
+ // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_LT_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_EQ_U16::Inst_VOPC__V_CMPX_EQ_U16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_eq_u16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_EQ_U16
+
+ Inst_VOPC__V_CMPX_EQ_U16::~Inst_VOPC__V_CMPX_EQ_U16()
+ {
+ } // ~Inst_VOPC__V_CMPX_EQ_U16
+
+ // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_EQ_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_LE_U16::Inst_VOPC__V_CMPX_LE_U16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_le_u16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_LE_U16
+
+ Inst_VOPC__V_CMPX_LE_U16::~Inst_VOPC__V_CMPX_LE_U16()
+ {
+ } // ~Inst_VOPC__V_CMPX_LE_U16
+
+ // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_LE_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_GT_U16::Inst_VOPC__V_CMPX_GT_U16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_gt_u16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_GT_U16
+
+ Inst_VOPC__V_CMPX_GT_U16::~Inst_VOPC__V_CMPX_GT_U16()
+ {
+ } // ~Inst_VOPC__V_CMPX_GT_U16
+
+ // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_GT_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_NE_U16::Inst_VOPC__V_CMPX_NE_U16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_ne_u16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_NE_U16
+
+ Inst_VOPC__V_CMPX_NE_U16::~Inst_VOPC__V_CMPX_NE_U16()
+ {
+ } // ~Inst_VOPC__V_CMPX_NE_U16
+
+ // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NE_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_GE_U16::Inst_VOPC__V_CMPX_GE_U16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_ge_u16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_GE_U16
+
+ Inst_VOPC__V_CMPX_GE_U16::~Inst_VOPC__V_CMPX_GE_U16()
+ {
+ } // ~Inst_VOPC__V_CMPX_GE_U16
+
+ // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_GE_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_T_U16::Inst_VOPC__V_CMPX_T_U16(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_t_u16")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_T_U16
+
+ Inst_VOPC__V_CMPX_T_U16::~Inst_VOPC__V_CMPX_T_U16()
+ {
+ } // ~Inst_VOPC__V_CMPX_T_U16
+
+ // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_T_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 1);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_F_I32::Inst_VOPC__V_CMP_F_I32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_f_i32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_F_I32
+
+ Inst_VOPC__V_CMP_F_I32::~Inst_VOPC__V_CMP_F_I32()
+ {
+ } // ~Inst_VOPC__V_CMP_F_I32
+
+ // D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_F_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_LT_I32::Inst_VOPC__V_CMP_LT_I32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_lt_i32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_LT_I32
+
+ Inst_VOPC__V_CMP_LT_I32::~Inst_VOPC__V_CMP_LT_I32()
+ {
+ } // ~Inst_VOPC__V_CMP_LT_I32
+
+ // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_LT_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_EQ_I32::Inst_VOPC__V_CMP_EQ_I32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_eq_i32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_EQ_I32
+
+ Inst_VOPC__V_CMP_EQ_I32::~Inst_VOPC__V_CMP_EQ_I32()
+ {
+ } // ~Inst_VOPC__V_CMP_EQ_I32
+
+ // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_EQ_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_LE_I32::Inst_VOPC__V_CMP_LE_I32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_le_i32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_LE_I32
+
+ Inst_VOPC__V_CMP_LE_I32::~Inst_VOPC__V_CMP_LE_I32()
+ {
+ } // ~Inst_VOPC__V_CMP_LE_I32
+
+ // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_LE_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_GT_I32::Inst_VOPC__V_CMP_GT_I32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_gt_i32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_GT_I32
+
+ Inst_VOPC__V_CMP_GT_I32::~Inst_VOPC__V_CMP_GT_I32()
+ {
+ } // ~Inst_VOPC__V_CMP_GT_I32
+
+ // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_GT_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_NE_I32::Inst_VOPC__V_CMP_NE_I32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_ne_i32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_NE_I32
+
+ Inst_VOPC__V_CMP_NE_I32::~Inst_VOPC__V_CMP_NE_I32()
+ {
+ } // ~Inst_VOPC__V_CMP_NE_I32
+
+ // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NE_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_GE_I32::Inst_VOPC__V_CMP_GE_I32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_ge_i32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_GE_I32
+
+ Inst_VOPC__V_CMP_GE_I32::~Inst_VOPC__V_CMP_GE_I32()
+ {
+ } // ~Inst_VOPC__V_CMP_GE_I32
+
+ // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_GE_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_T_I32::Inst_VOPC__V_CMP_T_I32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_t_i32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_T_I32
+
+ Inst_VOPC__V_CMP_T_I32::~Inst_VOPC__V_CMP_T_I32()
+ {
+ } // ~Inst_VOPC__V_CMP_T_I32
+
+ // D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_T_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 1);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_F_U32::Inst_VOPC__V_CMP_F_U32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_f_u32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_F_U32
+
+ Inst_VOPC__V_CMP_F_U32::~Inst_VOPC__V_CMP_F_U32()
+ {
+ } // ~Inst_VOPC__V_CMP_F_U32
+
+ // D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_F_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_LT_U32::Inst_VOPC__V_CMP_LT_U32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_lt_u32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_LT_U32
+
+ Inst_VOPC__V_CMP_LT_U32::~Inst_VOPC__V_CMP_LT_U32()
+ {
+ } // ~Inst_VOPC__V_CMP_LT_U32
+
+ // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_LT_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_EQ_U32::Inst_VOPC__V_CMP_EQ_U32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_eq_u32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_EQ_U32
+
+ Inst_VOPC__V_CMP_EQ_U32::~Inst_VOPC__V_CMP_EQ_U32()
+ {
+ } // ~Inst_VOPC__V_CMP_EQ_U32
+
+ // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_EQ_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_LE_U32::Inst_VOPC__V_CMP_LE_U32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_le_u32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_LE_U32
+
+ Inst_VOPC__V_CMP_LE_U32::~Inst_VOPC__V_CMP_LE_U32()
+ {
+ } // ~Inst_VOPC__V_CMP_LE_U32
+
+ // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_LE_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_GT_U32::Inst_VOPC__V_CMP_GT_U32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_gt_u32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_GT_U32
+
+ Inst_VOPC__V_CMP_GT_U32::~Inst_VOPC__V_CMP_GT_U32()
+ {
+ } // ~Inst_VOPC__V_CMP_GT_U32
+
+ // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_GT_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_NE_U32::Inst_VOPC__V_CMP_NE_U32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_ne_u32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_NE_U32
+
+ Inst_VOPC__V_CMP_NE_U32::~Inst_VOPC__V_CMP_NE_U32()
+ {
+ } // ~Inst_VOPC__V_CMP_NE_U32
+
+ // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NE_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_GE_U32::Inst_VOPC__V_CMP_GE_U32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_ge_u32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_GE_U32
+
+ Inst_VOPC__V_CMP_GE_U32::~Inst_VOPC__V_CMP_GE_U32()
+ {
+ } // ~Inst_VOPC__V_CMP_GE_U32
+
+ // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_GE_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_T_U32::Inst_VOPC__V_CMP_T_U32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_t_u32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_T_U32
+
+ Inst_VOPC__V_CMP_T_U32::~Inst_VOPC__V_CMP_T_U32()
+ {
+ } // ~Inst_VOPC__V_CMP_T_U32
+
+ // D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_T_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 1);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_F_I32::Inst_VOPC__V_CMPX_F_I32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_f_i32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_F_I32
+
+ Inst_VOPC__V_CMPX_F_I32::~Inst_VOPC__V_CMPX_F_I32()
+ {
+ } // ~Inst_VOPC__V_CMPX_F_I32
+
+ // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_F_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_LT_I32::Inst_VOPC__V_CMPX_LT_I32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_lt_i32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_LT_I32
+
+ Inst_VOPC__V_CMPX_LT_I32::~Inst_VOPC__V_CMPX_LT_I32()
+ {
+ } // ~Inst_VOPC__V_CMPX_LT_I32
+
+ // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_LT_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_EQ_I32::Inst_VOPC__V_CMPX_EQ_I32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_eq_i32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_EQ_I32
+
+ Inst_VOPC__V_CMPX_EQ_I32::~Inst_VOPC__V_CMPX_EQ_I32()
+ {
+ } // ~Inst_VOPC__V_CMPX_EQ_I32
+
+ // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_EQ_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_LE_I32::Inst_VOPC__V_CMPX_LE_I32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_le_i32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_LE_I32
+
+ Inst_VOPC__V_CMPX_LE_I32::~Inst_VOPC__V_CMPX_LE_I32()
+ {
+ } // ~Inst_VOPC__V_CMPX_LE_I32
+
+ // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_LE_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_GT_I32::Inst_VOPC__V_CMPX_GT_I32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_gt_i32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_GT_I32
+
+ Inst_VOPC__V_CMPX_GT_I32::~Inst_VOPC__V_CMPX_GT_I32()
+ {
+ } // ~Inst_VOPC__V_CMPX_GT_I32
+
+ // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_GT_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_NE_I32::Inst_VOPC__V_CMPX_NE_I32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_ne_i32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_NE_I32
+
+ Inst_VOPC__V_CMPX_NE_I32::~Inst_VOPC__V_CMPX_NE_I32()
+ {
+ } // ~Inst_VOPC__V_CMPX_NE_I32
+
+ // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NE_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_GE_I32::Inst_VOPC__V_CMPX_GE_I32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_ge_i32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_GE_I32
+
+ Inst_VOPC__V_CMPX_GE_I32::~Inst_VOPC__V_CMPX_GE_I32()
+ {
+ } // ~Inst_VOPC__V_CMPX_GE_I32
+
+ // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_GE_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_T_I32::Inst_VOPC__V_CMPX_T_I32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_t_i32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_T_I32
+
+ Inst_VOPC__V_CMPX_T_I32::~Inst_VOPC__V_CMPX_T_I32()
+ {
+ } // ~Inst_VOPC__V_CMPX_T_I32
+
+ // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_T_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 1);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_F_U32::Inst_VOPC__V_CMPX_F_U32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_f_u32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_F_U32
+
+ Inst_VOPC__V_CMPX_F_U32::~Inst_VOPC__V_CMPX_F_U32()
+ {
+ } // ~Inst_VOPC__V_CMPX_F_U32
+
+ // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_F_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_LT_U32::Inst_VOPC__V_CMPX_LT_U32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_lt_u32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_LT_U32
+
+ Inst_VOPC__V_CMPX_LT_U32::~Inst_VOPC__V_CMPX_LT_U32()
+ {
+ } // ~Inst_VOPC__V_CMPX_LT_U32
+
+ // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_LT_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_EQ_U32::Inst_VOPC__V_CMPX_EQ_U32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_eq_u32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_EQ_U32
+
+ Inst_VOPC__V_CMPX_EQ_U32::~Inst_VOPC__V_CMPX_EQ_U32()
+ {
+ } // ~Inst_VOPC__V_CMPX_EQ_U32
+
+ // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_EQ_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_LE_U32::Inst_VOPC__V_CMPX_LE_U32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_le_u32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_LE_U32
+
+ Inst_VOPC__V_CMPX_LE_U32::~Inst_VOPC__V_CMPX_LE_U32()
+ {
+ } // ~Inst_VOPC__V_CMPX_LE_U32
+
+ // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_LE_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_GT_U32::Inst_VOPC__V_CMPX_GT_U32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_gt_u32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_GT_U32
+
+ Inst_VOPC__V_CMPX_GT_U32::~Inst_VOPC__V_CMPX_GT_U32()
+ {
+ } // ~Inst_VOPC__V_CMPX_GT_U32
+
+ // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_GT_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_NE_U32::Inst_VOPC__V_CMPX_NE_U32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_ne_u32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_NE_U32
+
+ Inst_VOPC__V_CMPX_NE_U32::~Inst_VOPC__V_CMPX_NE_U32()
+ {
+ } // ~Inst_VOPC__V_CMPX_NE_U32
+
+ // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NE_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_GE_U32::Inst_VOPC__V_CMPX_GE_U32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_ge_u32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_GE_U32
+
+ Inst_VOPC__V_CMPX_GE_U32::~Inst_VOPC__V_CMPX_GE_U32()
+ {
+ } // ~Inst_VOPC__V_CMPX_GE_U32
+
+ // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_GE_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_T_U32::Inst_VOPC__V_CMPX_T_U32(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_t_u32")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_T_U32
+
+ Inst_VOPC__V_CMPX_T_U32::~Inst_VOPC__V_CMPX_T_U32()
+ {
+ } // ~Inst_VOPC__V_CMPX_T_U32
+
+ // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_T_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 1);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_F_I64::Inst_VOPC__V_CMP_F_I64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_f_i64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_F_I64
+
+ Inst_VOPC__V_CMP_F_I64::~Inst_VOPC__V_CMP_F_I64()
+ {
+ } // ~Inst_VOPC__V_CMP_F_I64
+
+ // D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_F_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_LT_I64::Inst_VOPC__V_CMP_LT_I64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_lt_i64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_LT_I64
+
+ Inst_VOPC__V_CMP_LT_I64::~Inst_VOPC__V_CMP_LT_I64()
+ {
+ } // ~Inst_VOPC__V_CMP_LT_I64
+
+ // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_LT_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_EQ_I64::Inst_VOPC__V_CMP_EQ_I64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_eq_i64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_EQ_I64
+
+ Inst_VOPC__V_CMP_EQ_I64::~Inst_VOPC__V_CMP_EQ_I64()
+ {
+ } // ~Inst_VOPC__V_CMP_EQ_I64
+
+ // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_EQ_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_LE_I64::Inst_VOPC__V_CMP_LE_I64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_le_i64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_LE_I64
+
+ Inst_VOPC__V_CMP_LE_I64::~Inst_VOPC__V_CMP_LE_I64()
+ {
+ } // ~Inst_VOPC__V_CMP_LE_I64
+
+ // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_LE_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_GT_I64::Inst_VOPC__V_CMP_GT_I64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_gt_i64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_GT_I64
+
+ Inst_VOPC__V_CMP_GT_I64::~Inst_VOPC__V_CMP_GT_I64()
+ {
+ } // ~Inst_VOPC__V_CMP_GT_I64
+
+ // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_GT_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_NE_I64::Inst_VOPC__V_CMP_NE_I64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_ne_i64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_NE_I64
+
+ Inst_VOPC__V_CMP_NE_I64::~Inst_VOPC__V_CMP_NE_I64()
+ {
+ } // ~Inst_VOPC__V_CMP_NE_I64
+
+ // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NE_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_GE_I64::Inst_VOPC__V_CMP_GE_I64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_ge_i64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_GE_I64
+
+ Inst_VOPC__V_CMP_GE_I64::~Inst_VOPC__V_CMP_GE_I64()
+ {
+ } // ~Inst_VOPC__V_CMP_GE_I64
+
+ // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_GE_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_T_I64::Inst_VOPC__V_CMP_T_I64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_t_i64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_T_I64
+
+ Inst_VOPC__V_CMP_T_I64::~Inst_VOPC__V_CMP_T_I64()
+ {
+ } // ~Inst_VOPC__V_CMP_T_I64
+
+ // D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_T_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 1);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_F_U64::Inst_VOPC__V_CMP_F_U64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_f_u64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_F_U64
+
+ Inst_VOPC__V_CMP_F_U64::~Inst_VOPC__V_CMP_F_U64()
+ {
+ } // ~Inst_VOPC__V_CMP_F_U64
+
+ // D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_F_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_LT_U64::Inst_VOPC__V_CMP_LT_U64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_lt_u64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_LT_U64
+
+ Inst_VOPC__V_CMP_LT_U64::~Inst_VOPC__V_CMP_LT_U64()
+ {
+ } // ~Inst_VOPC__V_CMP_LT_U64
+
+ // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_LT_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_EQ_U64::Inst_VOPC__V_CMP_EQ_U64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_eq_u64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_EQ_U64
+
+ Inst_VOPC__V_CMP_EQ_U64::~Inst_VOPC__V_CMP_EQ_U64()
+ {
+ } // ~Inst_VOPC__V_CMP_EQ_U64
+
+ // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_EQ_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_LE_U64::Inst_VOPC__V_CMP_LE_U64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_le_u64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_LE_U64
+
+ Inst_VOPC__V_CMP_LE_U64::~Inst_VOPC__V_CMP_LE_U64()
+ {
+ } // ~Inst_VOPC__V_CMP_LE_U64
+
+ // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_LE_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_GT_U64::Inst_VOPC__V_CMP_GT_U64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_gt_u64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_GT_U64
+
+ Inst_VOPC__V_CMP_GT_U64::~Inst_VOPC__V_CMP_GT_U64()
+ {
+ } // ~Inst_VOPC__V_CMP_GT_U64
+
+ // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_GT_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_NE_U64::Inst_VOPC__V_CMP_NE_U64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_ne_u64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_NE_U64
+
+ Inst_VOPC__V_CMP_NE_U64::~Inst_VOPC__V_CMP_NE_U64()
+ {
+ } // ~Inst_VOPC__V_CMP_NE_U64
+
+ // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_NE_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_GE_U64::Inst_VOPC__V_CMP_GE_U64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_ge_u64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_GE_U64
+
+ Inst_VOPC__V_CMP_GE_U64::~Inst_VOPC__V_CMP_GE_U64()
+ {
+ } // ~Inst_VOPC__V_CMP_GE_U64
+
+ // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_GE_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMP_T_U64::Inst_VOPC__V_CMP_T_U64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmp_t_u64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMP_T_U64
+
+ Inst_VOPC__V_CMP_T_U64::~Inst_VOPC__V_CMP_T_U64()
+ {
+ } // ~Inst_VOPC__V_CMP_T_U64
+
+ // D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMP_T_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 1);
+ }
+ }
+
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_F_I64::Inst_VOPC__V_CMPX_F_I64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_f_i64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_F_I64
+
+ Inst_VOPC__V_CMPX_F_I64::~Inst_VOPC__V_CMPX_F_I64()
+ {
+ } // ~Inst_VOPC__V_CMPX_F_I64
+
+ // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_F_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_LT_I64::Inst_VOPC__V_CMPX_LT_I64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_lt_i64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_LT_I64
+
+ Inst_VOPC__V_CMPX_LT_I64::~Inst_VOPC__V_CMPX_LT_I64()
+ {
+ } // ~Inst_VOPC__V_CMPX_LT_I64
+
+ // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_LT_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_EQ_I64::Inst_VOPC__V_CMPX_EQ_I64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_eq_i64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_EQ_I64
+
+ Inst_VOPC__V_CMPX_EQ_I64::~Inst_VOPC__V_CMPX_EQ_I64()
+ {
+ } // ~Inst_VOPC__V_CMPX_EQ_I64
+
+ // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_EQ_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_LE_I64::Inst_VOPC__V_CMPX_LE_I64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_le_i64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_LE_I64
+
+ Inst_VOPC__V_CMPX_LE_I64::~Inst_VOPC__V_CMPX_LE_I64()
+ {
+ } // ~Inst_VOPC__V_CMPX_LE_I64
+
+ // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_LE_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_GT_I64::Inst_VOPC__V_CMPX_GT_I64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_gt_i64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_GT_I64
+
+ Inst_VOPC__V_CMPX_GT_I64::~Inst_VOPC__V_CMPX_GT_I64()
+ {
+ } // ~Inst_VOPC__V_CMPX_GT_I64
+
+ // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_GT_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_NE_I64::Inst_VOPC__V_CMPX_NE_I64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_ne_i64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_NE_I64
+
+ Inst_VOPC__V_CMPX_NE_I64::~Inst_VOPC__V_CMPX_NE_I64()
+ {
+ } // ~Inst_VOPC__V_CMPX_NE_I64
+
+ // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NE_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_GE_I64::Inst_VOPC__V_CMPX_GE_I64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_ge_i64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_GE_I64
+
+ Inst_VOPC__V_CMPX_GE_I64::~Inst_VOPC__V_CMPX_GE_I64()
+ {
+ } // ~Inst_VOPC__V_CMPX_GE_I64
+
+ // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_GE_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_T_I64::Inst_VOPC__V_CMPX_T_I64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_t_i64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_T_I64
+
+ Inst_VOPC__V_CMPX_T_I64::~Inst_VOPC__V_CMPX_T_I64()
+ {
+ } // ~Inst_VOPC__V_CMPX_T_I64
+
+ // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_T_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 1);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_F_U64::Inst_VOPC__V_CMPX_F_U64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_f_u64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_F_U64
+
+ Inst_VOPC__V_CMPX_F_U64::~Inst_VOPC__V_CMPX_F_U64()
+ {
+ } // ~Inst_VOPC__V_CMPX_F_U64
+
+ // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_F_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_LT_U64::Inst_VOPC__V_CMPX_LT_U64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_lt_u64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_LT_U64
+
+ Inst_VOPC__V_CMPX_LT_U64::~Inst_VOPC__V_CMPX_LT_U64()
+ {
+ } // ~Inst_VOPC__V_CMPX_LT_U64
+
+ // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_LT_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_EQ_U64::Inst_VOPC__V_CMPX_EQ_U64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_eq_u64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_EQ_U64
+
+ Inst_VOPC__V_CMPX_EQ_U64::~Inst_VOPC__V_CMPX_EQ_U64()
+ {
+ } // ~Inst_VOPC__V_CMPX_EQ_U64
+
+ // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_EQ_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_LE_U64::Inst_VOPC__V_CMPX_LE_U64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_le_u64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_LE_U64
+
+ Inst_VOPC__V_CMPX_LE_U64::~Inst_VOPC__V_CMPX_LE_U64()
+ {
+ } // ~Inst_VOPC__V_CMPX_LE_U64
+
+ // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_LE_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_GT_U64::Inst_VOPC__V_CMPX_GT_U64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_gt_u64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_GT_U64
+
+ Inst_VOPC__V_CMPX_GT_U64::~Inst_VOPC__V_CMPX_GT_U64()
+ {
+ } // ~Inst_VOPC__V_CMPX_GT_U64
+
+ // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_GT_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_NE_U64::Inst_VOPC__V_CMPX_NE_U64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_ne_u64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_NE_U64
+
+ Inst_VOPC__V_CMPX_NE_U64::~Inst_VOPC__V_CMPX_NE_U64()
+ {
+ } // ~Inst_VOPC__V_CMPX_NE_U64
+
+ // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_NE_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_GE_U64::Inst_VOPC__V_CMPX_GE_U64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_ge_u64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_GE_U64
+
+ Inst_VOPC__V_CMPX_GE_U64::~Inst_VOPC__V_CMPX_GE_U64()
+ {
+ } // ~Inst_VOPC__V_CMPX_GE_U64
+
+ // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_GE_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ src0.readSrc();
+ src1.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VOPC__V_CMPX_T_U64::Inst_VOPC__V_CMPX_T_U64(InFmt_VOPC *iFmt)
+ : Inst_VOPC(iFmt, "v_cmpx_t_u64")
+ {
+ setFlag(ALU);
+ } // Inst_VOPC__V_CMPX_T_U64
+
+ Inst_VOPC__V_CMPX_T_U64::~Inst_VOPC__V_CMPX_T_U64()
+ {
+ } // ~Inst_VOPC__V_CMPX_T_U64
+
+ // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOPC__V_CMPX_T_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, 1);
+ }
+ }
+
+ wf->execMask() = vcc.rawData();
+ vcc.write();
+ }
+
+ Inst_VINTRP__V_INTERP_P1_F32::Inst_VINTRP__V_INTERP_P1_F32(
+ InFmt_VINTRP *iFmt)
+ : Inst_VINTRP(iFmt, "v_interp_p1_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VINTRP__V_INTERP_P1_F32
+
+ Inst_VINTRP__V_INTERP_P1_F32::~Inst_VINTRP__V_INTERP_P1_F32()
+ {
+ } // ~Inst_VINTRP__V_INTERP_P1_F32
+
+ // D.f = P10 * S.f + P0; parameter interpolation
+ void
+ Inst_VINTRP__V_INTERP_P1_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VINTRP__V_INTERP_P2_F32::Inst_VINTRP__V_INTERP_P2_F32(
+ InFmt_VINTRP *iFmt)
+ : Inst_VINTRP(iFmt, "v_interp_p2_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VINTRP__V_INTERP_P2_F32
+
+ Inst_VINTRP__V_INTERP_P2_F32::~Inst_VINTRP__V_INTERP_P2_F32()
+ {
+ } // ~Inst_VINTRP__V_INTERP_P2_F32
+
+ // D.f = P20 * S.f + D.f; parameter interpolation
+ void
+ Inst_VINTRP__V_INTERP_P2_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VINTRP__V_INTERP_MOV_F32::Inst_VINTRP__V_INTERP_MOV_F32(
+ InFmt_VINTRP *iFmt)
+ : Inst_VINTRP(iFmt, "v_interp_mov_f32")
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VINTRP__V_INTERP_MOV_F32
+
+ Inst_VINTRP__V_INTERP_MOV_F32::~Inst_VINTRP__V_INTERP_MOV_F32()
+ {
+ } // ~Inst_VINTRP__V_INTERP_MOV_F32
+
+ void
+ Inst_VINTRP__V_INTERP_MOV_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMP_CLASS_F32::Inst_VOP3__V_CMP_CLASS_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_class_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMP_CLASS_F32
+
+ Inst_VOP3__V_CMP_CLASS_F32::~Inst_VOP3__V_CMP_CLASS_F32()
+ {
+ } // ~Inst_VOP3__V_CMP_CLASS_F32
+
+ // VCC = IEEE numeric class function specified in S1.u, performed on S0.f
+ // The function reports true if the floating point value is any of the
+ // numeric types selected in S1.u according to the following list:
+ // S1.u[0] -- value is a signaling NaN.
+ // S1.u[1] -- value is a quiet NaN.
+ // S1.u[2] -- value is negative infinity.
+ // S1.u[3] -- value is a negative normal value.
+ // S1.u[4] -- value is a negative denormal value.
+ // S1.u[5] -- value is negative zero.
+ // S1.u[6] -- value is positive zero.
+ // S1.u[7] -- value is a positive denormal value.
+ // S1.u[8] -- value is a positive normal value.
+ // S1.u[9] -- value is positive infinity.
+ void
+ Inst_VOP3__V_CMP_CLASS_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (bits(src1[lane], 0) || bits(src1[lane], 1)) {
+ // is NaN
+ if (std::isnan(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 2)) {
+ // is -infinity
+ if (std::isinf(src0[lane]) && std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 3)) {
+ // is -normal
+ if (std::isnormal(src0[lane])
+ && std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 4)) {
+ // is -denormal
+ if (!std::isnormal(src0[lane])
+ && std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 5)) {
+ // is -zero
+ if (std::fpclassify(src0[lane]) == FP_ZERO
+ && std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 6)) {
+ // is +zero
+ if (std::fpclassify(src0[lane]) == FP_ZERO
+ && !std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 7)) {
+ // is +denormal
+ if (!std::isnormal(src0[lane])
+ && !std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 8)) {
+ // is +normal
+ if (std::isnormal(src0[lane])
+ && !std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 9)) {
+ // is +infinity
+ if (std::isinf(src0[lane])
+ && !std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_CLASS_F32::Inst_VOP3__V_CMPX_CLASS_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_class_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMPX_CLASS_F32
+
+ Inst_VOP3__V_CMPX_CLASS_F32::~Inst_VOP3__V_CMPX_CLASS_F32()
+ {
+ } // ~Inst_VOP3__V_CMPX_CLASS_F32
+
+ // EXEC, VCC = IEEE numeric class function specified in S1.u, performed on
+ // S0.f
+ // The function reports true if the floating point value is any of the
+ // numeric types selected in S1.u according to the following list:
+ // S1.u[0] -- value is a signaling NaN.
+ // S1.u[1] -- value is a quiet NaN.
+ // S1.u[2] -- value is negative infinity.
+ // S1.u[3] -- value is a negative normal value.
+ // S1.u[4] -- value is a negative denormal value.
+ // S1.u[5] -- value is negative zero.
+ // S1.u[6] -- value is positive zero.
+ // S1.u[7] -- value is a positive denormal value.
+ // S1.u[8] -- value is a positive normal value.
+ // S1.u[9] -- value is positive infinity.
+ void
+ Inst_VOP3__V_CMPX_CLASS_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (bits(src1[lane], 0) || bits(src1[lane], 1)) {
+ // is NaN
+ if (std::isnan(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 2)) {
+ // is -infinity
+ if (std::isinf(src0[lane]) && std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 3)) {
+ // is -normal
+ if (std::isnormal(src0[lane])
+ && std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 4)) {
+ // is -denormal
+ if (!std::isnormal(src0[lane])
+ && std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 5)) {
+ // is -zero
+ if (std::fpclassify(src0[lane]) == FP_ZERO
+ && std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 6)) {
+ // is +zero
+ if (std::fpclassify(src0[lane]) == FP_ZERO
+ && !std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 7)) {
+ // is +denormal
+ if (!std::isnormal(src0[lane])
+ && !std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 8)) {
+ // is +normal
+ if (std::isnormal(src0[lane])
+ && !std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 9)) {
+ // is +infinity
+ if (std::isinf(src0[lane])
+ && !std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_CLASS_F64::Inst_VOP3__V_CMP_CLASS_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_class_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMP_CLASS_F64
+
+ Inst_VOP3__V_CMP_CLASS_F64::~Inst_VOP3__V_CMP_CLASS_F64()
+ {
+ } // ~Inst_VOP3__V_CMP_CLASS_F64
+
+ // VCC = IEEE numeric class function specified in S1.u, performed on S0.d
+ // The function reports true if the floating point value is any of the
+ // numeric types selected in S1.u according to the following list:
+ // S1.u[0] -- value is a signaling NaN.
+ // S1.u[1] -- value is a quiet NaN.
+ // S1.u[2] -- value is negative infinity.
+ // S1.u[3] -- value is a negative normal value.
+ // S1.u[4] -- value is a negative denormal value.
+ // S1.u[5] -- value is negative zero.
+ // S1.u[6] -- value is positive zero.
+ // S1.u[7] -- value is a positive denormal value.
+ // S1.u[8] -- value is a positive normal value.
+ // S1.u[9] -- value is positive infinity.
+ void
+ Inst_VOP3__V_CMP_CLASS_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (bits(src1[lane], 0) || bits(src1[lane], 1)) {
+ // is NaN
+ if (std::isnan(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 2)) {
+ // is -infinity
+ if (std::isinf(src0[lane]) && std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 3)) {
+ // is -normal
+ if (std::isnormal(src0[lane])
+ && std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 4)) {
+ // is -denormal
+ if (!std::isnormal(src0[lane])
+ && std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 5)) {
+ // is -zero
+ if (std::fpclassify(src0[lane]) == FP_ZERO
+ && std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 6)) {
+ // is +zero
+ if (std::fpclassify(src0[lane]) == FP_ZERO
+ && !std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 7)) {
+ // is +denormal
+ if (!std::isnormal(src0[lane])
+ && !std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 8)) {
+ // is +normal
+ if (std::isnormal(src0[lane])
+ && !std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 9)) {
+ // is +infinity
+ if (std::isinf(src0[lane])
+ && !std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_CLASS_F64::Inst_VOP3__V_CMPX_CLASS_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_class_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMPX_CLASS_F64
+
+ Inst_VOP3__V_CMPX_CLASS_F64::~Inst_VOP3__V_CMPX_CLASS_F64()
+ {
+ } // ~Inst_VOP3__V_CMPX_CLASS_F64
+
+ // EXEC, VCC = IEEE numeric class function specified in S1.u, performed on
+ // S0.d
+ // The function reports true if the floating point value is any of the
+ // numeric types selected in S1.u according to the following list:
+ // S1.u[0] -- value is a signaling NaN.
+ // S1.u[1] -- value is a quiet NaN.
+ // S1.u[2] -- value is negative infinity.
+ // S1.u[3] -- value is a negative normal value.
+ // S1.u[4] -- value is a negative denormal value.
+ // S1.u[5] -- value is negative zero.
+ // S1.u[6] -- value is positive zero.
+ // S1.u[7] -- value is a positive denormal value.
+ // S1.u[8] -- value is a positive normal value.
+ // S1.u[9] -- value is positive infinity.
+ void
+ Inst_VOP3__V_CMPX_CLASS_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (bits(src1[lane], 0) || bits(src1[lane], 1)) {
+ // is NaN
+ if (std::isnan(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 2)) {
+ // is -infinity
+ if (std::isinf(src0[lane]) && std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 3)) {
+ // is -normal
+ if (std::isnormal(src0[lane])
+ && std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 4)) {
+ // is -denormal
+ if (!std::isnormal(src0[lane])
+ && std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 5)) {
+ // is -zero
+ if (std::fpclassify(src0[lane]) == FP_ZERO
+ && std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 6)) {
+ // is +zero
+ if (std::fpclassify(src0[lane]) == FP_ZERO
+ && !std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 7)) {
+ // is +denormal
+ if (!std::isnormal(src0[lane])
+ && !std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 8)) {
+ // is +normal
+ if (std::isnormal(src0[lane])
+ && !std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ if (bits(src1[lane], 9)) {
+ // is +infinity
+ if (std::isinf(src0[lane])
+ && !std::signbit(src0[lane])) {
+ sdst.setBit(lane, 1);
+ continue;
+ }
+ }
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_CLASS_F16::Inst_VOP3__V_CMP_CLASS_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_class_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMP_CLASS_F16
+
+ Inst_VOP3__V_CMP_CLASS_F16::~Inst_VOP3__V_CMP_CLASS_F16()
+ {
+ } // ~Inst_VOP3__V_CMP_CLASS_F16
+
+ // VCC = IEEE numeric class function specified in S1.u, performed on S0.f16
+ // The function reports true if the floating point value is any of the
+ // numeric types selected in S1.u according to the following list:
+ // S1.u[0] -- value is a signaling NaN.
+ // S1.u[1] -- value is a quiet NaN.
+ // S1.u[2] -- value is negative infinity.
+ // S1.u[3] -- value is a negative normal value.
+ // S1.u[4] -- value is a negative denormal value.
+ // S1.u[5] -- value is negative zero.
+ // S1.u[6] -- value is positive zero.
+ // S1.u[7] -- value is a positive denormal value.
+ // S1.u[8] -- value is a positive normal value.
+ // S1.u[9] -- value is positive infinity.
+ void
+ Inst_VOP3__V_CMP_CLASS_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMPX_CLASS_F16::Inst_VOP3__V_CMPX_CLASS_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_class_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMPX_CLASS_F16
+
+ Inst_VOP3__V_CMPX_CLASS_F16::~Inst_VOP3__V_CMPX_CLASS_F16()
+ {
+ } // ~Inst_VOP3__V_CMPX_CLASS_F16
+
+ // EXEC, VCC = IEEE numeric class function specified in S1.u, performed on
+ // S0.f16
+ // The function reports true if the floating point value is any of the
+ // numeric types selected in S1.u according to the following list:
+ // S1.u[0] -- value is a signaling NaN.
+ // S1.u[1] -- value is a quiet NaN.
+ // S1.u[2] -- value is negative infinity.
+ // S1.u[3] -- value is a negative normal value.
+ // S1.u[4] -- value is a negative denormal value.
+ // S1.u[5] -- value is negative zero.
+ // S1.u[6] -- value is positive zero.
+ // S1.u[7] -- value is a positive denormal value.
+ // S1.u[8] -- value is a positive normal value.
+ // S1.u[9] -- value is positive infinity.
+ void
+ Inst_VOP3__V_CMPX_CLASS_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMP_F_F16::Inst_VOP3__V_CMP_F_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_f_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMP_F_F16
+
+ Inst_VOP3__V_CMP_F_F16::~Inst_VOP3__V_CMP_F_F16()
+ {
+ } // ~Inst_VOP3__V_CMP_F_F16
+
+ // D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_F_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMP_LT_F16::Inst_VOP3__V_CMP_LT_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_lt_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMP_LT_F16
+
+ Inst_VOP3__V_CMP_LT_F16::~Inst_VOP3__V_CMP_LT_F16()
+ {
+ } // ~Inst_VOP3__V_CMP_LT_F16
+
+ // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_LT_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMP_EQ_F16::Inst_VOP3__V_CMP_EQ_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_eq_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMP_EQ_F16
+
+ Inst_VOP3__V_CMP_EQ_F16::~Inst_VOP3__V_CMP_EQ_F16()
+ {
+ } // ~Inst_VOP3__V_CMP_EQ_F16
+
+ // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_EQ_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMP_LE_F16::Inst_VOP3__V_CMP_LE_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_le_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMP_LE_F16
+
+ Inst_VOP3__V_CMP_LE_F16::~Inst_VOP3__V_CMP_LE_F16()
+ {
+ } // ~Inst_VOP3__V_CMP_LE_F16
+
+ // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_LE_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMP_GT_F16::Inst_VOP3__V_CMP_GT_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_gt_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMP_GT_F16
+
+ Inst_VOP3__V_CMP_GT_F16::~Inst_VOP3__V_CMP_GT_F16()
+ {
+ } // ~Inst_VOP3__V_CMP_GT_F16
+
+ // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_GT_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMP_LG_F16::Inst_VOP3__V_CMP_LG_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_lg_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMP_LG_F16
+
+ Inst_VOP3__V_CMP_LG_F16::~Inst_VOP3__V_CMP_LG_F16()
+ {
+ } // ~Inst_VOP3__V_CMP_LG_F16
+
+ // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_LG_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMP_GE_F16::Inst_VOP3__V_CMP_GE_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_ge_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMP_GE_F16
+
+ Inst_VOP3__V_CMP_GE_F16::~Inst_VOP3__V_CMP_GE_F16()
+ {
+ } // ~Inst_VOP3__V_CMP_GE_F16
+
+ // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_GE_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMP_O_F16::Inst_VOP3__V_CMP_O_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_o_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMP_O_F16
+
+ Inst_VOP3__V_CMP_O_F16::~Inst_VOP3__V_CMP_O_F16()
+ {
+ } // ~Inst_VOP3__V_CMP_O_F16
+
+ // D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_O_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMP_U_F16::Inst_VOP3__V_CMP_U_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_u_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMP_U_F16
+
+ Inst_VOP3__V_CMP_U_F16::~Inst_VOP3__V_CMP_U_F16()
+ {
+ } // ~Inst_VOP3__V_CMP_U_F16
+
+ // D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_U_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMP_NGE_F16::Inst_VOP3__V_CMP_NGE_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_nge_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMP_NGE_F16
+
+ Inst_VOP3__V_CMP_NGE_F16::~Inst_VOP3__V_CMP_NGE_F16()
+ {
+ } // ~Inst_VOP3__V_CMP_NGE_F16
+
+ // D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NGE_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMP_NLG_F16::Inst_VOP3__V_CMP_NLG_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_nlg_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMP_NLG_F16
+
+ Inst_VOP3__V_CMP_NLG_F16::~Inst_VOP3__V_CMP_NLG_F16()
+ {
+ } // ~Inst_VOP3__V_CMP_NLG_F16
+
+ // D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NLG_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMP_NGT_F16::Inst_VOP3__V_CMP_NGT_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_ngt_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMP_NGT_F16
+
+ Inst_VOP3__V_CMP_NGT_F16::~Inst_VOP3__V_CMP_NGT_F16()
+ {
+ } // ~Inst_VOP3__V_CMP_NGT_F16
+
+ // D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NGT_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMP_NLE_F16::Inst_VOP3__V_CMP_NLE_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_nle_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMP_NLE_F16
+
+ Inst_VOP3__V_CMP_NLE_F16::~Inst_VOP3__V_CMP_NLE_F16()
+ {
+ } // ~Inst_VOP3__V_CMP_NLE_F16
+
+ // D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NLE_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMP_NEQ_F16::Inst_VOP3__V_CMP_NEQ_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_neq_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMP_NEQ_F16
+
+ Inst_VOP3__V_CMP_NEQ_F16::~Inst_VOP3__V_CMP_NEQ_F16()
+ {
+ } // ~Inst_VOP3__V_CMP_NEQ_F16
+
+ // D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NEQ_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMP_NLT_F16::Inst_VOP3__V_CMP_NLT_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_nlt_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMP_NLT_F16
+
+ Inst_VOP3__V_CMP_NLT_F16::~Inst_VOP3__V_CMP_NLT_F16()
+ {
+ } // ~Inst_VOP3__V_CMP_NLT_F16
+
+ // D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NLT_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMP_TRU_F16::Inst_VOP3__V_CMP_TRU_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_tru_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMP_TRU_F16
+
+ Inst_VOP3__V_CMP_TRU_F16::~Inst_VOP3__V_CMP_TRU_F16()
+ {
+ } // ~Inst_VOP3__V_CMP_TRU_F16
+
+ // D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_TRU_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 1);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_F_F16::Inst_VOP3__V_CMPX_F_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_f_f16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_F_F16
+
+ Inst_VOP3__V_CMPX_F_F16::~Inst_VOP3__V_CMPX_F_F16()
+ {
+ } // ~Inst_VOP3__V_CMPX_F_F16
+
+ // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_F_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_LT_F16::Inst_VOP3__V_CMPX_LT_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_lt_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMPX_LT_F16
+
+ Inst_VOP3__V_CMPX_LT_F16::~Inst_VOP3__V_CMPX_LT_F16()
+ {
+ } // ~Inst_VOP3__V_CMPX_LT_F16
+
+ // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_LT_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMPX_EQ_F16::Inst_VOP3__V_CMPX_EQ_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_eq_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMPX_EQ_F16
+
+ Inst_VOP3__V_CMPX_EQ_F16::~Inst_VOP3__V_CMPX_EQ_F16()
+ {
+ } // ~Inst_VOP3__V_CMPX_EQ_F16
+
+ // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_EQ_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMPX_LE_F16::Inst_VOP3__V_CMPX_LE_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_le_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMPX_LE_F16
+
+ Inst_VOP3__V_CMPX_LE_F16::~Inst_VOP3__V_CMPX_LE_F16()
+ {
+ } // ~Inst_VOP3__V_CMPX_LE_F16
+
+ // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_LE_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMPX_GT_F16::Inst_VOP3__V_CMPX_GT_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_gt_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMPX_GT_F16
+
+ Inst_VOP3__V_CMPX_GT_F16::~Inst_VOP3__V_CMPX_GT_F16()
+ {
+ } // ~Inst_VOP3__V_CMPX_GT_F16
+
+ // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_GT_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMPX_LG_F16::Inst_VOP3__V_CMPX_LG_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_lg_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMPX_LG_F16
+
+ Inst_VOP3__V_CMPX_LG_F16::~Inst_VOP3__V_CMPX_LG_F16()
+ {
+ } // ~Inst_VOP3__V_CMPX_LG_F16
+
+ // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_LG_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMPX_GE_F16::Inst_VOP3__V_CMPX_GE_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_ge_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMPX_GE_F16
+
+ Inst_VOP3__V_CMPX_GE_F16::~Inst_VOP3__V_CMPX_GE_F16()
+ {
+ } // ~Inst_VOP3__V_CMPX_GE_F16
+
+ // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_GE_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMPX_O_F16::Inst_VOP3__V_CMPX_O_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_o_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMPX_O_F16
+
+ Inst_VOP3__V_CMPX_O_F16::~Inst_VOP3__V_CMPX_O_F16()
+ {
+ } // ~Inst_VOP3__V_CMPX_O_F16
+
+ // EXEC,D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC
+ // encoding.
+ void
+ Inst_VOP3__V_CMPX_O_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMPX_U_F16::Inst_VOP3__V_CMPX_U_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_u_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMPX_U_F16
+
+ Inst_VOP3__V_CMPX_U_F16::~Inst_VOP3__V_CMPX_U_F16()
+ {
+ } // ~Inst_VOP3__V_CMPX_U_F16
+
+ // EXEC,D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC
+ // encoding.
+ void
+ Inst_VOP3__V_CMPX_U_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMPX_NGE_F16::Inst_VOP3__V_CMPX_NGE_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_nge_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMPX_NGE_F16
+
+ Inst_VOP3__V_CMPX_NGE_F16::~Inst_VOP3__V_CMPX_NGE_F16()
+ {
+ } // ~Inst_VOP3__V_CMPX_NGE_F16
+
+ // EXEC,D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NGE_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMPX_NLG_F16::Inst_VOP3__V_CMPX_NLG_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_nlg_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMPX_NLG_F16
+
+ Inst_VOP3__V_CMPX_NLG_F16::~Inst_VOP3__V_CMPX_NLG_F16()
+ {
+ } // ~Inst_VOP3__V_CMPX_NLG_F16
+
+ // EXEC,D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NLG_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMPX_NGT_F16::Inst_VOP3__V_CMPX_NGT_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_ngt_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMPX_NGT_F16
+
+ Inst_VOP3__V_CMPX_NGT_F16::~Inst_VOP3__V_CMPX_NGT_F16()
+ {
+ } // ~Inst_VOP3__V_CMPX_NGT_F16
+
+ // EXEC,D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NGT_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMPX_NLE_F16::Inst_VOP3__V_CMPX_NLE_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_nle_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMPX_NLE_F16
+
+ Inst_VOP3__V_CMPX_NLE_F16::~Inst_VOP3__V_CMPX_NLE_F16()
+ {
+ } // ~Inst_VOP3__V_CMPX_NLE_F16
+
+ // EXEC,D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NLE_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMPX_NEQ_F16::Inst_VOP3__V_CMPX_NEQ_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_neq_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMPX_NEQ_F16
+
+ Inst_VOP3__V_CMPX_NEQ_F16::~Inst_VOP3__V_CMPX_NEQ_F16()
+ {
+ } // ~Inst_VOP3__V_CMPX_NEQ_F16
+
+ // EXEC,D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NEQ_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMPX_NLT_F16::Inst_VOP3__V_CMPX_NLT_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_nlt_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMPX_NLT_F16
+
+ Inst_VOP3__V_CMPX_NLT_F16::~Inst_VOP3__V_CMPX_NLT_F16()
+ {
+ } // ~Inst_VOP3__V_CMPX_NLT_F16
+
+ // EXEC,D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NLT_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CMPX_TRU_F16::Inst_VOP3__V_CMPX_TRU_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_tru_f16", true)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CMPX_TRU_F16
+
+ Inst_VOP3__V_CMPX_TRU_F16::~Inst_VOP3__V_CMPX_TRU_F16()
+ {
+ } // ~Inst_VOP3__V_CMPX_TRU_F16
+
+ // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_TRU_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 1);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_F_F32::Inst_VOP3__V_CMP_F_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_f_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMP_F_F32
+
+ Inst_VOP3__V_CMP_F_F32::~Inst_VOP3__V_CMP_F_F32()
+ {
+ } // ~Inst_VOP3__V_CMP_F_F32
+
+ // D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_F_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_LT_F32::Inst_VOP3__V_CMP_LT_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_lt_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMP_LT_F32
+
+ Inst_VOP3__V_CMP_LT_F32::~Inst_VOP3__V_CMP_LT_F32()
+ {
+ } // ~Inst_VOP3__V_CMP_LT_F32
+
+ // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_LT_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_EQ_F32::Inst_VOP3__V_CMP_EQ_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_eq_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMP_EQ_F32
+
+ Inst_VOP3__V_CMP_EQ_F32::~Inst_VOP3__V_CMP_EQ_F32()
+ {
+ } // ~Inst_VOP3__V_CMP_EQ_F32
+
+ // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_EQ_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_LE_F32::Inst_VOP3__V_CMP_LE_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_le_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMP_LE_F32
+
+ Inst_VOP3__V_CMP_LE_F32::~Inst_VOP3__V_CMP_LE_F32()
+ {
+ } // ~Inst_VOP3__V_CMP_LE_F32
+
+ // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_LE_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_GT_F32::Inst_VOP3__V_CMP_GT_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_gt_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMP_GT_F32
+
+ Inst_VOP3__V_CMP_GT_F32::~Inst_VOP3__V_CMP_GT_F32()
+ {
+ } // ~Inst_VOP3__V_CMP_GT_F32
+
+ // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_GT_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_LG_F32::Inst_VOP3__V_CMP_LG_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_lg_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMP_LG_F32
+
+ Inst_VOP3__V_CMP_LG_F32::~Inst_VOP3__V_CMP_LG_F32()
+ {
+ } // ~Inst_VOP3__V_CMP_LG_F32
+
+ // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_LG_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_GE_F32::Inst_VOP3__V_CMP_GE_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_ge_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMP_GE_F32
+
+ Inst_VOP3__V_CMP_GE_F32::~Inst_VOP3__V_CMP_GE_F32()
+ {
+ } // ~Inst_VOP3__V_CMP_GE_F32
+
+ // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_GE_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_O_F32::Inst_VOP3__V_CMP_O_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_o_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMP_O_F32
+
+ Inst_VOP3__V_CMP_O_F32::~Inst_VOP3__V_CMP_O_F32()
+ {
+ } // ~Inst_VOP3__V_CMP_O_F32
+
+ // D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_O_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, (!std::isnan(src0[lane])
+ && !std::isnan(src1[lane])) ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_U_F32::Inst_VOP3__V_CMP_U_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_u_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMP_U_F32
+
+ Inst_VOP3__V_CMP_U_F32::~Inst_VOP3__V_CMP_U_F32()
+ {
+ } // ~Inst_VOP3__V_CMP_U_F32
+
+ // D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_U_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, (std::isnan(src0[lane])
+ || std::isnan(src1[lane])) ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_NGE_F32::Inst_VOP3__V_CMP_NGE_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_nge_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMP_NGE_F32
+
+ Inst_VOP3__V_CMP_NGE_F32::~Inst_VOP3__V_CMP_NGE_F32()
+ {
+ } // ~Inst_VOP3__V_CMP_NGE_F32
+
+ // D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NGE_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_NLG_F32::Inst_VOP3__V_CMP_NLG_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_nlg_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMP_NLG_F32
+
+ Inst_VOP3__V_CMP_NLG_F32::~Inst_VOP3__V_CMP_NLG_F32()
+ {
+ } // ~Inst_VOP3__V_CMP_NLG_F32
+
+ // D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NLG_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, !(src0[lane] < src1[lane]
+ || src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_NGT_F32::Inst_VOP3__V_CMP_NGT_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_ngt_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMP_NGT_F32
+
+ Inst_VOP3__V_CMP_NGT_F32::~Inst_VOP3__V_CMP_NGT_F32()
+ {
+ } // ~Inst_VOP3__V_CMP_NGT_F32
+
+ // D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NGT_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_NLE_F32::Inst_VOP3__V_CMP_NLE_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_nle_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMP_NLE_F32
+
+ Inst_VOP3__V_CMP_NLE_F32::~Inst_VOP3__V_CMP_NLE_F32()
+ {
+ } // ~Inst_VOP3__V_CMP_NLE_F32
+
+ // D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NLE_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_NEQ_F32::Inst_VOP3__V_CMP_NEQ_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_neq_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMP_NEQ_F32
+
+ Inst_VOP3__V_CMP_NEQ_F32::~Inst_VOP3__V_CMP_NEQ_F32()
+ {
+ } // ~Inst_VOP3__V_CMP_NEQ_F32
+
+ // D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NEQ_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_NLT_F32::Inst_VOP3__V_CMP_NLT_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_nlt_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMP_NLT_F32
+
+ Inst_VOP3__V_CMP_NLT_F32::~Inst_VOP3__V_CMP_NLT_F32()
+ {
+ } // ~Inst_VOP3__V_CMP_NLT_F32
+
+ // D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NLT_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_TRU_F32::Inst_VOP3__V_CMP_TRU_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_tru_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMP_TRU_F32
+
+ Inst_VOP3__V_CMP_TRU_F32::~Inst_VOP3__V_CMP_TRU_F32()
+ {
+ } // ~Inst_VOP3__V_CMP_TRU_F32
+
+ // D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_TRU_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 1);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_F_F32::Inst_VOP3__V_CMPX_F_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_f_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMPX_F_F32
+
+ Inst_VOP3__V_CMPX_F_F32::~Inst_VOP3__V_CMPX_F_F32()
+ {
+ } // ~Inst_VOP3__V_CMPX_F_F32
+
+ // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_F_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_LT_F32::Inst_VOP3__V_CMPX_LT_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_lt_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMPX_LT_F32
+
+ Inst_VOP3__V_CMPX_LT_F32::~Inst_VOP3__V_CMPX_LT_F32()
+ {
+ } // ~Inst_VOP3__V_CMPX_LT_F32
+
+ // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_LT_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_EQ_F32::Inst_VOP3__V_CMPX_EQ_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_eq_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMPX_EQ_F32
+
+ Inst_VOP3__V_CMPX_EQ_F32::~Inst_VOP3__V_CMPX_EQ_F32()
+ {
+ } // ~Inst_VOP3__V_CMPX_EQ_F32
+
+ // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_EQ_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_LE_F32::Inst_VOP3__V_CMPX_LE_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_le_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMPX_LE_F32
+
+ Inst_VOP3__V_CMPX_LE_F32::~Inst_VOP3__V_CMPX_LE_F32()
+ {
+ } // ~Inst_VOP3__V_CMPX_LE_F32
+
+ // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_LE_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_GT_F32::Inst_VOP3__V_CMPX_GT_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_gt_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMPX_GT_F32
+
+ Inst_VOP3__V_CMPX_GT_F32::~Inst_VOP3__V_CMPX_GT_F32()
+ {
+ } // ~Inst_VOP3__V_CMPX_GT_F32
+
+ // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_GT_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_LG_F32::Inst_VOP3__V_CMPX_LG_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_lg_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMPX_LG_F32
+
+ Inst_VOP3__V_CMPX_LG_F32::~Inst_VOP3__V_CMPX_LG_F32()
+ {
+ } // ~Inst_VOP3__V_CMPX_LG_F32
+
+ // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_LG_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, (src0[lane] < src1[lane]
+ || src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_GE_F32::Inst_VOP3__V_CMPX_GE_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_ge_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMPX_GE_F32
+
+ Inst_VOP3__V_CMPX_GE_F32::~Inst_VOP3__V_CMPX_GE_F32()
+ {
+ } // ~Inst_VOP3__V_CMPX_GE_F32
+
+ // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_GE_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_O_F32::Inst_VOP3__V_CMPX_O_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_o_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMPX_O_F32
+
+ Inst_VOP3__V_CMPX_O_F32::~Inst_VOP3__V_CMPX_O_F32()
+ {
+ } // ~Inst_VOP3__V_CMPX_O_F32
+
+ // EXEC,D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC
+ // encoding.
+ void
+ Inst_VOP3__V_CMPX_O_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, (!std::isnan(src0[lane])
+ && !std::isnan(src1[lane])) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_U_F32::Inst_VOP3__V_CMPX_U_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_u_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMPX_U_F32
+
+ Inst_VOP3__V_CMPX_U_F32::~Inst_VOP3__V_CMPX_U_F32()
+ {
+ } // ~Inst_VOP3__V_CMPX_U_F32
+
+ // EXEC,D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC
+ // encoding.
+ void
+ Inst_VOP3__V_CMPX_U_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, (std::isnan(src0[lane])
+ || std::isnan(src1[lane])) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_NGE_F32::Inst_VOP3__V_CMPX_NGE_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_nge_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMPX_NGE_F32
+
+ Inst_VOP3__V_CMPX_NGE_F32::~Inst_VOP3__V_CMPX_NGE_F32()
+ {
+ } // ~Inst_VOP3__V_CMPX_NGE_F32
+
+ // EXEC,D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NGE_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_NLG_F32::Inst_VOP3__V_CMPX_NLG_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_nlg_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMPX_NLG_F32
+
+ Inst_VOP3__V_CMPX_NLG_F32::~Inst_VOP3__V_CMPX_NLG_F32()
+ {
+ } // ~Inst_VOP3__V_CMPX_NLG_F32
+
+ // EXEC,D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NLG_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, !(src0[lane] < src1[lane]
+ || src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_NGT_F32::Inst_VOP3__V_CMPX_NGT_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_ngt_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMPX_NGT_F32
+
+ Inst_VOP3__V_CMPX_NGT_F32::~Inst_VOP3__V_CMPX_NGT_F32()
+ {
+ } // ~Inst_VOP3__V_CMPX_NGT_F32
+
+ // EXEC,D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NGT_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_NLE_F32::Inst_VOP3__V_CMPX_NLE_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_nle_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMPX_NLE_F32
+
+ Inst_VOP3__V_CMPX_NLE_F32::~Inst_VOP3__V_CMPX_NLE_F32()
+ {
+ } // ~Inst_VOP3__V_CMPX_NLE_F32
+
+ // EXEC,D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NLE_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_NEQ_F32::Inst_VOP3__V_CMPX_NEQ_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_neq_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMPX_NEQ_F32
+
+ Inst_VOP3__V_CMPX_NEQ_F32::~Inst_VOP3__V_CMPX_NEQ_F32()
+ {
+ } // ~Inst_VOP3__V_CMPX_NEQ_F32
+
+ // EXEC,D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NEQ_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_NLT_F32::Inst_VOP3__V_CMPX_NLT_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_nlt_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMPX_NLT_F32
+
+ Inst_VOP3__V_CMPX_NLT_F32::~Inst_VOP3__V_CMPX_NLT_F32()
+ {
+ } // ~Inst_VOP3__V_CMPX_NLT_F32
+
+ // EXEC,D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NLT_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_TRU_F32::Inst_VOP3__V_CMPX_TRU_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_tru_f32", true)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CMPX_TRU_F32
+
+ Inst_VOP3__V_CMPX_TRU_F32::~Inst_VOP3__V_CMPX_TRU_F32()
+ {
+ } // ~Inst_VOP3__V_CMPX_TRU_F32
+
+ // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_TRU_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 1);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_F_F64::Inst_VOP3__V_CMP_F_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_f_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMP_F_F64
+
+ Inst_VOP3__V_CMP_F_F64::~Inst_VOP3__V_CMP_F_F64()
+ {
+ } // ~Inst_VOP3__V_CMP_F_F64
+
+ // D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_F_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_LT_F64::Inst_VOP3__V_CMP_LT_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_lt_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMP_LT_F64
+
+ Inst_VOP3__V_CMP_LT_F64::~Inst_VOP3__V_CMP_LT_F64()
+ {
+ } // ~Inst_VOP3__V_CMP_LT_F64
+
+ // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_LT_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_EQ_F64::Inst_VOP3__V_CMP_EQ_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_eq_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMP_EQ_F64
+
+ Inst_VOP3__V_CMP_EQ_F64::~Inst_VOP3__V_CMP_EQ_F64()
+ {
+ } // ~Inst_VOP3__V_CMP_EQ_F64
+
+ // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_EQ_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_LE_F64::Inst_VOP3__V_CMP_LE_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_le_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMP_LE_F64
+
+ Inst_VOP3__V_CMP_LE_F64::~Inst_VOP3__V_CMP_LE_F64()
+ {
+ } // ~Inst_VOP3__V_CMP_LE_F64
+
+ // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_LE_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_GT_F64::Inst_VOP3__V_CMP_GT_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_gt_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMP_GT_F64
+
+ Inst_VOP3__V_CMP_GT_F64::~Inst_VOP3__V_CMP_GT_F64()
+ {
+ } // ~Inst_VOP3__V_CMP_GT_F64
+
+ // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_GT_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_LG_F64::Inst_VOP3__V_CMP_LG_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_lg_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMP_LG_F64
+
+ Inst_VOP3__V_CMP_LG_F64::~Inst_VOP3__V_CMP_LG_F64()
+ {
+ } // ~Inst_VOP3__V_CMP_LG_F64
+
+ // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_LG_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, (src0[lane] < src1[lane]
+ || src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_GE_F64::Inst_VOP3__V_CMP_GE_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_ge_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMP_GE_F64
+
+ Inst_VOP3__V_CMP_GE_F64::~Inst_VOP3__V_CMP_GE_F64()
+ {
+ } // ~Inst_VOP3__V_CMP_GE_F64
+
+ // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_GE_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_O_F64::Inst_VOP3__V_CMP_O_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_o_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMP_O_F64
+
+ Inst_VOP3__V_CMP_O_F64::~Inst_VOP3__V_CMP_O_F64()
+ {
+ } // ~Inst_VOP3__V_CMP_O_F64
+
+ // D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_O_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, (!std::isnan(src0[lane])
+ && !std::isnan(src1[lane])) ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_U_F64::Inst_VOP3__V_CMP_U_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_u_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMP_U_F64
+
+ Inst_VOP3__V_CMP_U_F64::~Inst_VOP3__V_CMP_U_F64()
+ {
+ } // ~Inst_VOP3__V_CMP_U_F64
+
+ // D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_U_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, (std::isnan(src0[lane])
+ || std::isnan(src1[lane])) ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_NGE_F64::Inst_VOP3__V_CMP_NGE_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_nge_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMP_NGE_F64
+
+ Inst_VOP3__V_CMP_NGE_F64::~Inst_VOP3__V_CMP_NGE_F64()
+ {
+ } // ~Inst_VOP3__V_CMP_NGE_F64
+
+ // D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NGE_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_NLG_F64::Inst_VOP3__V_CMP_NLG_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_nlg_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMP_NLG_F64
+
+ Inst_VOP3__V_CMP_NLG_F64::~Inst_VOP3__V_CMP_NLG_F64()
+ {
+ } // ~Inst_VOP3__V_CMP_NLG_F64
+
+ // D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NLG_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, !(src0[lane] < src1[lane]
+ || src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_NGT_F64::Inst_VOP3__V_CMP_NGT_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_ngt_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMP_NGT_F64
+
+ Inst_VOP3__V_CMP_NGT_F64::~Inst_VOP3__V_CMP_NGT_F64()
+ {
+ } // ~Inst_VOP3__V_CMP_NGT_F64
+
+ // D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NGT_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_NLE_F64::Inst_VOP3__V_CMP_NLE_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_nle_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMP_NLE_F64
+
+ Inst_VOP3__V_CMP_NLE_F64::~Inst_VOP3__V_CMP_NLE_F64()
+ {
+ } // ~Inst_VOP3__V_CMP_NLE_F64
+
+ // D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NLE_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_NEQ_F64::Inst_VOP3__V_CMP_NEQ_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_neq_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMP_NEQ_F64
+
+ Inst_VOP3__V_CMP_NEQ_F64::~Inst_VOP3__V_CMP_NEQ_F64()
+ {
+ } // ~Inst_VOP3__V_CMP_NEQ_F64
+
+ // D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NEQ_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_NLT_F64::Inst_VOP3__V_CMP_NLT_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_nlt_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMP_NLT_F64
+
+ Inst_VOP3__V_CMP_NLT_F64::~Inst_VOP3__V_CMP_NLT_F64()
+ {
+ } // ~Inst_VOP3__V_CMP_NLT_F64
+
+ // D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NLT_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_TRU_F64::Inst_VOP3__V_CMP_TRU_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_tru_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMP_TRU_F64
+
+ Inst_VOP3__V_CMP_TRU_F64::~Inst_VOP3__V_CMP_TRU_F64()
+ {
+ } // ~Inst_VOP3__V_CMP_TRU_F64
+
+ // D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_TRU_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 1);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_F_F64::Inst_VOP3__V_CMPX_F_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_f_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMPX_F_F64
+
+ Inst_VOP3__V_CMPX_F_F64::~Inst_VOP3__V_CMPX_F_F64()
+ {
+ } // ~Inst_VOP3__V_CMPX_F_F64
+
+ // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_F_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_LT_F64::Inst_VOP3__V_CMPX_LT_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_lt_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMPX_LT_F64
+
+ Inst_VOP3__V_CMPX_LT_F64::~Inst_VOP3__V_CMPX_LT_F64()
+ {
+ } // ~Inst_VOP3__V_CMPX_LT_F64
+
+ // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_LT_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_EQ_F64::Inst_VOP3__V_CMPX_EQ_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_eq_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMPX_EQ_F64
+
+ Inst_VOP3__V_CMPX_EQ_F64::~Inst_VOP3__V_CMPX_EQ_F64()
+ {
+ } // ~Inst_VOP3__V_CMPX_EQ_F64
+
+ // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_EQ_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_LE_F64::Inst_VOP3__V_CMPX_LE_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_le_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMPX_LE_F64
+
+ Inst_VOP3__V_CMPX_LE_F64::~Inst_VOP3__V_CMPX_LE_F64()
+ {
+ } // ~Inst_VOP3__V_CMPX_LE_F64
+
+ // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_LE_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_GT_F64::Inst_VOP3__V_CMPX_GT_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_gt_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMPX_GT_F64
+
+ Inst_VOP3__V_CMPX_GT_F64::~Inst_VOP3__V_CMPX_GT_F64()
+ {
+ } // ~Inst_VOP3__V_CMPX_GT_F64
+
+ // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_GT_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_LG_F64::Inst_VOP3__V_CMPX_LG_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_lg_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMPX_LG_F64
+
+ Inst_VOP3__V_CMPX_LG_F64::~Inst_VOP3__V_CMPX_LG_F64()
+ {
+ } // ~Inst_VOP3__V_CMPX_LG_F64
+
+ // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_LG_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, (src0[lane] < src1[lane]
+ || src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_GE_F64::Inst_VOP3__V_CMPX_GE_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_ge_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMPX_GE_F64
+
+ Inst_VOP3__V_CMPX_GE_F64::~Inst_VOP3__V_CMPX_GE_F64()
+ {
+ } // ~Inst_VOP3__V_CMPX_GE_F64
+
+ // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_GE_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_O_F64::Inst_VOP3__V_CMPX_O_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_o_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMPX_O_F64
+
+ Inst_VOP3__V_CMPX_O_F64::~Inst_VOP3__V_CMPX_O_F64()
+ {
+ } // ~Inst_VOP3__V_CMPX_O_F64
+
+ // EXEC,D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC
+ // encoding.
+ void
+ Inst_VOP3__V_CMPX_O_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, (!std::isnan(src0[lane])
+ && !std::isnan(src1[lane])) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_U_F64::Inst_VOP3__V_CMPX_U_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_u_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMPX_U_F64
+
+ Inst_VOP3__V_CMPX_U_F64::~Inst_VOP3__V_CMPX_U_F64()
+ {
+ } // ~Inst_VOP3__V_CMPX_U_F64
+
+ // EXEC,D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC
+ // encoding.
+ void
+ Inst_VOP3__V_CMPX_U_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, (std::isnan(src0[lane])
+ || std::isnan(src1[lane])) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_NGE_F64::Inst_VOP3__V_CMPX_NGE_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_nge_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMPX_NGE_F64
+
+ Inst_VOP3__V_CMPX_NGE_F64::~Inst_VOP3__V_CMPX_NGE_F64()
+ {
+ } // ~Inst_VOP3__V_CMPX_NGE_F64
+
+ // EXEC,D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NGE_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_NLG_F64::Inst_VOP3__V_CMPX_NLG_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_nlg_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMPX_NLG_F64
+
+ Inst_VOP3__V_CMPX_NLG_F64::~Inst_VOP3__V_CMPX_NLG_F64()
+ {
+ } // ~Inst_VOP3__V_CMPX_NLG_F64
+
+ // EXEC,D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NLG_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, !(src0[lane] < src1[lane]
+ || src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_NGT_F64::Inst_VOP3__V_CMPX_NGT_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_ngt_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMPX_NGT_F64
+
+ Inst_VOP3__V_CMPX_NGT_F64::~Inst_VOP3__V_CMPX_NGT_F64()
+ {
+ } // ~Inst_VOP3__V_CMPX_NGT_F64
+
+ // EXEC,D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NGT_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_NLE_F64::Inst_VOP3__V_CMPX_NLE_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_nle_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMPX_NLE_F64
+
+ Inst_VOP3__V_CMPX_NLE_F64::~Inst_VOP3__V_CMPX_NLE_F64()
+ {
+ } // ~Inst_VOP3__V_CMPX_NLE_F64
+
+ // EXEC,D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NLE_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_NEQ_F64::Inst_VOP3__V_CMPX_NEQ_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_neq_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMPX_NEQ_F64
+
+ Inst_VOP3__V_CMPX_NEQ_F64::~Inst_VOP3__V_CMPX_NEQ_F64()
+ {
+ } // ~Inst_VOP3__V_CMPX_NEQ_F64
+
+ // EXEC,D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NEQ_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_NLT_F64::Inst_VOP3__V_CMPX_NLT_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_nlt_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMPX_NLT_F64
+
+ Inst_VOP3__V_CMPX_NLT_F64::~Inst_VOP3__V_CMPX_NLT_F64()
+ {
+ } // ~Inst_VOP3__V_CMPX_NLT_F64
+
+ // EXEC,D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NLT_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_TRU_F64::Inst_VOP3__V_CMPX_TRU_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_tru_f64", true)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CMPX_TRU_F64
+
+ Inst_VOP3__V_CMPX_TRU_F64::~Inst_VOP3__V_CMPX_TRU_F64()
+ {
+ } // ~Inst_VOP3__V_CMPX_TRU_F64
+
+ // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_TRU_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 1);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_F_I16::Inst_VOP3__V_CMP_F_I16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_f_i16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_F_I16
+
+ Inst_VOP3__V_CMP_F_I16::~Inst_VOP3__V_CMP_F_I16()
+ {
+ } // ~Inst_VOP3__V_CMP_F_I16
+
+ // D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_F_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_LT_I16::Inst_VOP3__V_CMP_LT_I16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_lt_i16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_LT_I16
+
+ Inst_VOP3__V_CMP_LT_I16::~Inst_VOP3__V_CMP_LT_I16()
+ {
+ } // ~Inst_VOP3__V_CMP_LT_I16
+
+ // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_LT_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_EQ_I16::Inst_VOP3__V_CMP_EQ_I16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_eq_i16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_EQ_I16
+
+ Inst_VOP3__V_CMP_EQ_I16::~Inst_VOP3__V_CMP_EQ_I16()
+ {
+ } // ~Inst_VOP3__V_CMP_EQ_I16
+
+ // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_EQ_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_LE_I16::Inst_VOP3__V_CMP_LE_I16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_le_i16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_LE_I16
+
+ Inst_VOP3__V_CMP_LE_I16::~Inst_VOP3__V_CMP_LE_I16()
+ {
+ } // ~Inst_VOP3__V_CMP_LE_I16
+
+ // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_LE_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_GT_I16::Inst_VOP3__V_CMP_GT_I16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_gt_i16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_GT_I16
+
+ Inst_VOP3__V_CMP_GT_I16::~Inst_VOP3__V_CMP_GT_I16()
+ {
+ } // ~Inst_VOP3__V_CMP_GT_I16
+
+ // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_GT_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_NE_I16::Inst_VOP3__V_CMP_NE_I16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_ne_i16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_NE_I16
+
+ Inst_VOP3__V_CMP_NE_I16::~Inst_VOP3__V_CMP_NE_I16()
+ {
+ } // ~Inst_VOP3__V_CMP_NE_I16
+
+ // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NE_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_GE_I16::Inst_VOP3__V_CMP_GE_I16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_ge_i16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_GE_I16
+
+ Inst_VOP3__V_CMP_GE_I16::~Inst_VOP3__V_CMP_GE_I16()
+ {
+ } // ~Inst_VOP3__V_CMP_GE_I16
+
+ // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_GE_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_T_I16::Inst_VOP3__V_CMP_T_I16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_t_i16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_T_I16
+
+ Inst_VOP3__V_CMP_T_I16::~Inst_VOP3__V_CMP_T_I16()
+ {
+ } // ~Inst_VOP3__V_CMP_T_I16
+
+ // D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_T_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 1);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_F_U16::Inst_VOP3__V_CMP_F_U16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_f_u16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_F_U16
+
+ Inst_VOP3__V_CMP_F_U16::~Inst_VOP3__V_CMP_F_U16()
+ {
+ } // ~Inst_VOP3__V_CMP_F_U16
+
+ // D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_F_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_LT_U16::Inst_VOP3__V_CMP_LT_U16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_lt_u16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_LT_U16
+
+ Inst_VOP3__V_CMP_LT_U16::~Inst_VOP3__V_CMP_LT_U16()
+ {
+ } // ~Inst_VOP3__V_CMP_LT_U16
+
+ // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_LT_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_EQ_U16::Inst_VOP3__V_CMP_EQ_U16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_eq_u16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_EQ_U16
+
+ Inst_VOP3__V_CMP_EQ_U16::~Inst_VOP3__V_CMP_EQ_U16()
+ {
+ } // ~Inst_VOP3__V_CMP_EQ_U16
+
+ // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_EQ_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_LE_U16::Inst_VOP3__V_CMP_LE_U16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_le_u16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_LE_U16
+
+ Inst_VOP3__V_CMP_LE_U16::~Inst_VOP3__V_CMP_LE_U16()
+ {
+ } // ~Inst_VOP3__V_CMP_LE_U16
+
+ // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_LE_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_GT_U16::Inst_VOP3__V_CMP_GT_U16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_gt_u16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_GT_U16
+
+ Inst_VOP3__V_CMP_GT_U16::~Inst_VOP3__V_CMP_GT_U16()
+ {
+ } // ~Inst_VOP3__V_CMP_GT_U16
+
+ // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_GT_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_NE_U16::Inst_VOP3__V_CMP_NE_U16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_ne_u16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_NE_U16
+
+ Inst_VOP3__V_CMP_NE_U16::~Inst_VOP3__V_CMP_NE_U16()
+ {
+ } // ~Inst_VOP3__V_CMP_NE_U16
+
+ // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NE_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_GE_U16::Inst_VOP3__V_CMP_GE_U16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_ge_u16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_GE_U16
+
+ Inst_VOP3__V_CMP_GE_U16::~Inst_VOP3__V_CMP_GE_U16()
+ {
+ } // ~Inst_VOP3__V_CMP_GE_U16
+
+ // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_GE_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_T_U16::Inst_VOP3__V_CMP_T_U16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_t_u16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_T_U16
+
+ Inst_VOP3__V_CMP_T_U16::~Inst_VOP3__V_CMP_T_U16()
+ {
+ } // ~Inst_VOP3__V_CMP_T_U16
+
+ // D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_T_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 1);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_F_I16::Inst_VOP3__V_CMPX_F_I16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_f_i16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_F_I16
+
+ Inst_VOP3__V_CMPX_F_I16::~Inst_VOP3__V_CMPX_F_I16()
+ {
+ } // ~Inst_VOP3__V_CMPX_F_I16
+
+ // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_F_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_LT_I16::Inst_VOP3__V_CMPX_LT_I16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_lt_i16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_LT_I16
+
+ Inst_VOP3__V_CMPX_LT_I16::~Inst_VOP3__V_CMPX_LT_I16()
+ {
+ } // ~Inst_VOP3__V_CMPX_LT_I16
+
+ // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_LT_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_EQ_I16::Inst_VOP3__V_CMPX_EQ_I16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_eq_i16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_EQ_I16
+
+ Inst_VOP3__V_CMPX_EQ_I16::~Inst_VOP3__V_CMPX_EQ_I16()
+ {
+ } // ~Inst_VOP3__V_CMPX_EQ_I16
+
+ // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_EQ_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_LE_I16::Inst_VOP3__V_CMPX_LE_I16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_le_i16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_LE_I16
+
+ Inst_VOP3__V_CMPX_LE_I16::~Inst_VOP3__V_CMPX_LE_I16()
+ {
+ } // ~Inst_VOP3__V_CMPX_LE_I16
+
+ // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_LE_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_GT_I16::Inst_VOP3__V_CMPX_GT_I16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_gt_i16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_GT_I16
+
+ Inst_VOP3__V_CMPX_GT_I16::~Inst_VOP3__V_CMPX_GT_I16()
+ {
+ } // ~Inst_VOP3__V_CMPX_GT_I16
+
+ // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_GT_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_NE_I16::Inst_VOP3__V_CMPX_NE_I16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_ne_i16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_NE_I16
+
+ Inst_VOP3__V_CMPX_NE_I16::~Inst_VOP3__V_CMPX_NE_I16()
+ {
+ } // ~Inst_VOP3__V_CMPX_NE_I16
+
+ // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NE_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_GE_I16::Inst_VOP3__V_CMPX_GE_I16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_ge_i16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_GE_I16
+
+ Inst_VOP3__V_CMPX_GE_I16::~Inst_VOP3__V_CMPX_GE_I16()
+ {
+ } // ~Inst_VOP3__V_CMPX_GE_I16
+
+ // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_GE_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_T_I16::Inst_VOP3__V_CMPX_T_I16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_t_i16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_T_I16
+
+ Inst_VOP3__V_CMPX_T_I16::~Inst_VOP3__V_CMPX_T_I16()
+ {
+ } // ~Inst_VOP3__V_CMPX_T_I16
+
+ // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_T_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 1);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_F_U16::Inst_VOP3__V_CMPX_F_U16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_f_u16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_F_U16
+
+ Inst_VOP3__V_CMPX_F_U16::~Inst_VOP3__V_CMPX_F_U16()
+ {
+ } // ~Inst_VOP3__V_CMPX_F_U16
+
+ // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_F_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_LT_U16::Inst_VOP3__V_CMPX_LT_U16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_lt_u16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_LT_U16
+
+ Inst_VOP3__V_CMPX_LT_U16::~Inst_VOP3__V_CMPX_LT_U16()
+ {
+ } // ~Inst_VOP3__V_CMPX_LT_U16
+
+ // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_LT_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_EQ_U16::Inst_VOP3__V_CMPX_EQ_U16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_eq_u16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_EQ_U16
+
+ Inst_VOP3__V_CMPX_EQ_U16::~Inst_VOP3__V_CMPX_EQ_U16()
+ {
+ } // ~Inst_VOP3__V_CMPX_EQ_U16
+
+ // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_EQ_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_LE_U16::Inst_VOP3__V_CMPX_LE_U16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_le_u16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_LE_U16
+
+ Inst_VOP3__V_CMPX_LE_U16::~Inst_VOP3__V_CMPX_LE_U16()
+ {
+ } // ~Inst_VOP3__V_CMPX_LE_U16
+
+ // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_LE_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_GT_U16::Inst_VOP3__V_CMPX_GT_U16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_gt_u16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_GT_U16
+
+ Inst_VOP3__V_CMPX_GT_U16::~Inst_VOP3__V_CMPX_GT_U16()
+ {
+ } // ~Inst_VOP3__V_CMPX_GT_U16
+
+ // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_GT_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_NE_U16::Inst_VOP3__V_CMPX_NE_U16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_ne_u16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_NE_U16
+
+ Inst_VOP3__V_CMPX_NE_U16::~Inst_VOP3__V_CMPX_NE_U16()
+ {
+ } // ~Inst_VOP3__V_CMPX_NE_U16
+
+ // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NE_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_GE_U16::Inst_VOP3__V_CMPX_GE_U16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_ge_u16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_GE_U16
+
+ Inst_VOP3__V_CMPX_GE_U16::~Inst_VOP3__V_CMPX_GE_U16()
+ {
+ } // ~Inst_VOP3__V_CMPX_GE_U16
+
+ // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_GE_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_T_U16::Inst_VOP3__V_CMPX_T_U16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_t_u16", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_T_U16
+
+ Inst_VOP3__V_CMPX_T_U16::~Inst_VOP3__V_CMPX_T_U16()
+ {
+ } // ~Inst_VOP3__V_CMPX_T_U16
+
+ // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_T_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 1);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_F_I32::Inst_VOP3__V_CMP_F_I32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_f_i32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_F_I32
+
+ Inst_VOP3__V_CMP_F_I32::~Inst_VOP3__V_CMP_F_I32()
+ {
+ } // ~Inst_VOP3__V_CMP_F_I32
+
+ // D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_F_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_LT_I32::Inst_VOP3__V_CMP_LT_I32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_lt_i32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_LT_I32
+
+ Inst_VOP3__V_CMP_LT_I32::~Inst_VOP3__V_CMP_LT_I32()
+ {
+ } // ~Inst_VOP3__V_CMP_LT_I32
+
+ // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_LT_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_EQ_I32::Inst_VOP3__V_CMP_EQ_I32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_eq_i32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_EQ_I32
+
+ Inst_VOP3__V_CMP_EQ_I32::~Inst_VOP3__V_CMP_EQ_I32()
+ {
+ } // ~Inst_VOP3__V_CMP_EQ_I32
+
+ // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_EQ_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_LE_I32::Inst_VOP3__V_CMP_LE_I32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_le_i32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_LE_I32
+
+ Inst_VOP3__V_CMP_LE_I32::~Inst_VOP3__V_CMP_LE_I32()
+ {
+ } // ~Inst_VOP3__V_CMP_LE_I32
+
+ // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_LE_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_GT_I32::Inst_VOP3__V_CMP_GT_I32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_gt_i32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_GT_I32
+
+ Inst_VOP3__V_CMP_GT_I32::~Inst_VOP3__V_CMP_GT_I32()
+ {
+ } // ~Inst_VOP3__V_CMP_GT_I32
+
+ // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_GT_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_NE_I32::Inst_VOP3__V_CMP_NE_I32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_ne_i32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_NE_I32
+
+ Inst_VOP3__V_CMP_NE_I32::~Inst_VOP3__V_CMP_NE_I32()
+ {
+ } // ~Inst_VOP3__V_CMP_NE_I32
+
+ // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NE_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_GE_I32::Inst_VOP3__V_CMP_GE_I32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_ge_i32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_GE_I32
+
+ Inst_VOP3__V_CMP_GE_I32::~Inst_VOP3__V_CMP_GE_I32()
+ {
+ } // ~Inst_VOP3__V_CMP_GE_I32
+
+ // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_GE_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_T_I32::Inst_VOP3__V_CMP_T_I32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_t_i32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_T_I32
+
+ Inst_VOP3__V_CMP_T_I32::~Inst_VOP3__V_CMP_T_I32()
+ {
+ } // ~Inst_VOP3__V_CMP_T_I32
+
+ // D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_T_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 1);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_F_U32::Inst_VOP3__V_CMP_F_U32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_f_u32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_F_U32
+
+ Inst_VOP3__V_CMP_F_U32::~Inst_VOP3__V_CMP_F_U32()
+ {
+ } // ~Inst_VOP3__V_CMP_F_U32
+
+ // D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_F_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_LT_U32::Inst_VOP3__V_CMP_LT_U32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_lt_u32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_LT_U32
+
+ Inst_VOP3__V_CMP_LT_U32::~Inst_VOP3__V_CMP_LT_U32()
+ {
+ } // ~Inst_VOP3__V_CMP_LT_U32
+
+ // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_LT_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_EQ_U32::Inst_VOP3__V_CMP_EQ_U32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_eq_u32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_EQ_U32
+
+ Inst_VOP3__V_CMP_EQ_U32::~Inst_VOP3__V_CMP_EQ_U32()
+ {
+ } // ~Inst_VOP3__V_CMP_EQ_U32
+
+ // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_EQ_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_LE_U32::Inst_VOP3__V_CMP_LE_U32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_le_u32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_LE_U32
+
+ Inst_VOP3__V_CMP_LE_U32::~Inst_VOP3__V_CMP_LE_U32()
+ {
+ } // ~Inst_VOP3__V_CMP_LE_U32
+
+ // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_LE_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_GT_U32::Inst_VOP3__V_CMP_GT_U32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_gt_u32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_GT_U32
+
+ Inst_VOP3__V_CMP_GT_U32::~Inst_VOP3__V_CMP_GT_U32()
+ {
+ } // ~Inst_VOP3__V_CMP_GT_U32
+
+ // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_GT_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_NE_U32::Inst_VOP3__V_CMP_NE_U32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_ne_u32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_NE_U32
+
+ Inst_VOP3__V_CMP_NE_U32::~Inst_VOP3__V_CMP_NE_U32()
+ {
+ } // ~Inst_VOP3__V_CMP_NE_U32
+
+ // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NE_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_GE_U32::Inst_VOP3__V_CMP_GE_U32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_ge_u32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_GE_U32
+
+ Inst_VOP3__V_CMP_GE_U32::~Inst_VOP3__V_CMP_GE_U32()
+ {
+ } // ~Inst_VOP3__V_CMP_GE_U32
+
+ // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_GE_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_T_U32::Inst_VOP3__V_CMP_T_U32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_t_u32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_T_U32
+
+ Inst_VOP3__V_CMP_T_U32::~Inst_VOP3__V_CMP_T_U32()
+ {
+ } // ~Inst_VOP3__V_CMP_T_U32
+
+ // D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_T_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 1);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_F_I32::Inst_VOP3__V_CMPX_F_I32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_f_i32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_F_I32
+
+ Inst_VOP3__V_CMPX_F_I32::~Inst_VOP3__V_CMPX_F_I32()
+ {
+ } // ~Inst_VOP3__V_CMPX_F_I32
+
+ // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_F_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_LT_I32::Inst_VOP3__V_CMPX_LT_I32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_lt_i32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_LT_I32
+
+ Inst_VOP3__V_CMPX_LT_I32::~Inst_VOP3__V_CMPX_LT_I32()
+ {
+ } // ~Inst_VOP3__V_CMPX_LT_I32
+
+ // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_LT_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_EQ_I32::Inst_VOP3__V_CMPX_EQ_I32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_eq_i32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_EQ_I32
+
+ Inst_VOP3__V_CMPX_EQ_I32::~Inst_VOP3__V_CMPX_EQ_I32()
+ {
+ } // ~Inst_VOP3__V_CMPX_EQ_I32
+
+ // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_EQ_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_LE_I32::Inst_VOP3__V_CMPX_LE_I32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_le_i32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_LE_I32
+
+ Inst_VOP3__V_CMPX_LE_I32::~Inst_VOP3__V_CMPX_LE_I32()
+ {
+ } // ~Inst_VOP3__V_CMPX_LE_I32
+
+ // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_LE_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_GT_I32::Inst_VOP3__V_CMPX_GT_I32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_gt_i32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_GT_I32
+
+ Inst_VOP3__V_CMPX_GT_I32::~Inst_VOP3__V_CMPX_GT_I32()
+ {
+ } // ~Inst_VOP3__V_CMPX_GT_I32
+
+ // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_GT_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_NE_I32::Inst_VOP3__V_CMPX_NE_I32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_ne_i32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_NE_I32
+
+ Inst_VOP3__V_CMPX_NE_I32::~Inst_VOP3__V_CMPX_NE_I32()
+ {
+ } // ~Inst_VOP3__V_CMPX_NE_I32
+
+ // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NE_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_GE_I32::Inst_VOP3__V_CMPX_GE_I32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_ge_i32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_GE_I32
+
+ Inst_VOP3__V_CMPX_GE_I32::~Inst_VOP3__V_CMPX_GE_I32()
+ {
+ } // ~Inst_VOP3__V_CMPX_GE_I32
+
+ // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_GE_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_T_I32::Inst_VOP3__V_CMPX_T_I32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_t_i32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_T_I32
+
+ Inst_VOP3__V_CMPX_T_I32::~Inst_VOP3__V_CMPX_T_I32()
+ {
+ } // ~Inst_VOP3__V_CMPX_T_I32
+
+ // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_T_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 1);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_F_U32::Inst_VOP3__V_CMPX_F_U32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_f_u32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_F_U32
+
+ Inst_VOP3__V_CMPX_F_U32::~Inst_VOP3__V_CMPX_F_U32()
+ {
+ } // ~Inst_VOP3__V_CMPX_F_U32
+
+ // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_F_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_LT_U32::Inst_VOP3__V_CMPX_LT_U32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_lt_u32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_LT_U32
+
+ Inst_VOP3__V_CMPX_LT_U32::~Inst_VOP3__V_CMPX_LT_U32()
+ {
+ } // ~Inst_VOP3__V_CMPX_LT_U32
+
+ // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_LT_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_EQ_U32::Inst_VOP3__V_CMPX_EQ_U32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_eq_u32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_EQ_U32
+
+ Inst_VOP3__V_CMPX_EQ_U32::~Inst_VOP3__V_CMPX_EQ_U32()
+ {
+ } // ~Inst_VOP3__V_CMPX_EQ_U32
+
+ // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_EQ_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_LE_U32::Inst_VOP3__V_CMPX_LE_U32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_le_u32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_LE_U32
+
+ Inst_VOP3__V_CMPX_LE_U32::~Inst_VOP3__V_CMPX_LE_U32()
+ {
+ } // ~Inst_VOP3__V_CMPX_LE_U32
+
+ // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_LE_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_GT_U32::Inst_VOP3__V_CMPX_GT_U32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_gt_u32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_GT_U32
+
+ Inst_VOP3__V_CMPX_GT_U32::~Inst_VOP3__V_CMPX_GT_U32()
+ {
+ } // ~Inst_VOP3__V_CMPX_GT_U32
+
+ // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_GT_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_NE_U32::Inst_VOP3__V_CMPX_NE_U32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_ne_u32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_NE_U32
+
+ Inst_VOP3__V_CMPX_NE_U32::~Inst_VOP3__V_CMPX_NE_U32()
+ {
+ } // ~Inst_VOP3__V_CMPX_NE_U32
+
+ // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NE_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_GE_U32::Inst_VOP3__V_CMPX_GE_U32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_ge_u32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_GE_U32
+
+ Inst_VOP3__V_CMPX_GE_U32::~Inst_VOP3__V_CMPX_GE_U32()
+ {
+ } // ~Inst_VOP3__V_CMPX_GE_U32
+
+ // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_GE_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_T_U32::Inst_VOP3__V_CMPX_T_U32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_t_u32", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_T_U32
+
+ Inst_VOP3__V_CMPX_T_U32::~Inst_VOP3__V_CMPX_T_U32()
+ {
+ } // ~Inst_VOP3__V_CMPX_T_U32
+
+ // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_T_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 1);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_F_I64::Inst_VOP3__V_CMP_F_I64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_f_i64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_F_I64
+
+ Inst_VOP3__V_CMP_F_I64::~Inst_VOP3__V_CMP_F_I64()
+ {
+ } // ~Inst_VOP3__V_CMP_F_I64
+
+ // D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_F_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_LT_I64::Inst_VOP3__V_CMP_LT_I64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_lt_i64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_LT_I64
+
+ Inst_VOP3__V_CMP_LT_I64::~Inst_VOP3__V_CMP_LT_I64()
+ {
+ } // ~Inst_VOP3__V_CMP_LT_I64
+
+ // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_LT_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_EQ_I64::Inst_VOP3__V_CMP_EQ_I64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_eq_i64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_EQ_I64
+
+ Inst_VOP3__V_CMP_EQ_I64::~Inst_VOP3__V_CMP_EQ_I64()
+ {
+ } // ~Inst_VOP3__V_CMP_EQ_I64
+
+ // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_EQ_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_LE_I64::Inst_VOP3__V_CMP_LE_I64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_le_i64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_LE_I64
+
+ Inst_VOP3__V_CMP_LE_I64::~Inst_VOP3__V_CMP_LE_I64()
+ {
+ } // ~Inst_VOP3__V_CMP_LE_I64
+
+ // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_LE_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_GT_I64::Inst_VOP3__V_CMP_GT_I64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_gt_i64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_GT_I64
+
+ Inst_VOP3__V_CMP_GT_I64::~Inst_VOP3__V_CMP_GT_I64()
+ {
+ } // ~Inst_VOP3__V_CMP_GT_I64
+
+ // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_GT_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_NE_I64::Inst_VOP3__V_CMP_NE_I64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_ne_i64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_NE_I64
+
+ Inst_VOP3__V_CMP_NE_I64::~Inst_VOP3__V_CMP_NE_I64()
+ {
+ } // ~Inst_VOP3__V_CMP_NE_I64
+
+ // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NE_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_GE_I64::Inst_VOP3__V_CMP_GE_I64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_ge_i64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_GE_I64
+
+ Inst_VOP3__V_CMP_GE_I64::~Inst_VOP3__V_CMP_GE_I64()
+ {
+ } // ~Inst_VOP3__V_CMP_GE_I64
+
+ // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_GE_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_T_I64::Inst_VOP3__V_CMP_T_I64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_t_i64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_T_I64
+
+ Inst_VOP3__V_CMP_T_I64::~Inst_VOP3__V_CMP_T_I64()
+ {
+ } // ~Inst_VOP3__V_CMP_T_I64
+
+ // D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_T_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 1);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_F_U64::Inst_VOP3__V_CMP_F_U64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_f_u64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_F_U64
+
+ Inst_VOP3__V_CMP_F_U64::~Inst_VOP3__V_CMP_F_U64()
+ {
+ } // ~Inst_VOP3__V_CMP_F_U64
+
+ // D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_F_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_LT_U64::Inst_VOP3__V_CMP_LT_U64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_lt_u64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_LT_U64
+
+ Inst_VOP3__V_CMP_LT_U64::~Inst_VOP3__V_CMP_LT_U64()
+ {
+ } // ~Inst_VOP3__V_CMP_LT_U64
+
+ // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_LT_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_EQ_U64::Inst_VOP3__V_CMP_EQ_U64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_eq_u64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_EQ_U64
+
+ Inst_VOP3__V_CMP_EQ_U64::~Inst_VOP3__V_CMP_EQ_U64()
+ {
+ } // ~Inst_VOP3__V_CMP_EQ_U64
+
+ // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_EQ_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_LE_U64::Inst_VOP3__V_CMP_LE_U64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_le_u64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_LE_U64
+
+ Inst_VOP3__V_CMP_LE_U64::~Inst_VOP3__V_CMP_LE_U64()
+ {
+ } // ~Inst_VOP3__V_CMP_LE_U64
+
+ // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_LE_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_GT_U64::Inst_VOP3__V_CMP_GT_U64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_gt_u64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_GT_U64
+
+ Inst_VOP3__V_CMP_GT_U64::~Inst_VOP3__V_CMP_GT_U64()
+ {
+ } // ~Inst_VOP3__V_CMP_GT_U64
+
+ // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_GT_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_NE_U64::Inst_VOP3__V_CMP_NE_U64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_ne_u64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_NE_U64
+
+ Inst_VOP3__V_CMP_NE_U64::~Inst_VOP3__V_CMP_NE_U64()
+ {
+ } // ~Inst_VOP3__V_CMP_NE_U64
+
+ // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_NE_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_GE_U64::Inst_VOP3__V_CMP_GE_U64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_ge_u64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_GE_U64
+
+ Inst_VOP3__V_CMP_GE_U64::~Inst_VOP3__V_CMP_GE_U64()
+ {
+ } // ~Inst_VOP3__V_CMP_GE_U64
+
+ // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_GE_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMP_T_U64::Inst_VOP3__V_CMP_T_U64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmp_t_u64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMP_T_U64
+
+ Inst_VOP3__V_CMP_T_U64::~Inst_VOP3__V_CMP_T_U64()
+ {
+ } // ~Inst_VOP3__V_CMP_T_U64
+
+ // D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMP_T_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 1);
+ }
+ }
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_F_I64::Inst_VOP3__V_CMPX_F_I64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_f_i64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_F_I64
+
+ Inst_VOP3__V_CMPX_F_I64::~Inst_VOP3__V_CMPX_F_I64()
+ {
+ } // ~Inst_VOP3__V_CMPX_F_I64
+
+ // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_F_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_LT_I64::Inst_VOP3__V_CMPX_LT_I64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_lt_i64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_LT_I64
+
+ Inst_VOP3__V_CMPX_LT_I64::~Inst_VOP3__V_CMPX_LT_I64()
+ {
+ } // ~Inst_VOP3__V_CMPX_LT_I64
+
+ // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_LT_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_EQ_I64::Inst_VOP3__V_CMPX_EQ_I64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_eq_i64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_EQ_I64
+
+ Inst_VOP3__V_CMPX_EQ_I64::~Inst_VOP3__V_CMPX_EQ_I64()
+ {
+ } // ~Inst_VOP3__V_CMPX_EQ_I64
+
+ // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_EQ_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_LE_I64::Inst_VOP3__V_CMPX_LE_I64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_le_i64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_LE_I64
+
+ Inst_VOP3__V_CMPX_LE_I64::~Inst_VOP3__V_CMPX_LE_I64()
+ {
+ } // ~Inst_VOP3__V_CMPX_LE_I64
+
+ // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_LE_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_GT_I64::Inst_VOP3__V_CMPX_GT_I64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_gt_i64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_GT_I64
+
+ Inst_VOP3__V_CMPX_GT_I64::~Inst_VOP3__V_CMPX_GT_I64()
+ {
+ } // ~Inst_VOP3__V_CMPX_GT_I64
+
+ // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_GT_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_NE_I64::Inst_VOP3__V_CMPX_NE_I64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_ne_i64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_NE_I64
+
+ Inst_VOP3__V_CMPX_NE_I64::~Inst_VOP3__V_CMPX_NE_I64()
+ {
+ } // ~Inst_VOP3__V_CMPX_NE_I64
+
+ // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NE_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_GE_I64::Inst_VOP3__V_CMPX_GE_I64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_ge_i64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_GE_I64
+
+ Inst_VOP3__V_CMPX_GE_I64::~Inst_VOP3__V_CMPX_GE_I64()
+ {
+ } // ~Inst_VOP3__V_CMPX_GE_I64
+
+ // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_GE_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_T_I64::Inst_VOP3__V_CMPX_T_I64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_t_i64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_T_I64
+
+ Inst_VOP3__V_CMPX_T_I64::~Inst_VOP3__V_CMPX_T_I64()
+ {
+ } // ~Inst_VOP3__V_CMPX_T_I64
+
+ // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_T_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 1);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_F_U64::Inst_VOP3__V_CMPX_F_U64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_f_u64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_F_U64
+
+ Inst_VOP3__V_CMPX_F_U64::~Inst_VOP3__V_CMPX_F_U64()
+ {
+ } // ~Inst_VOP3__V_CMPX_F_U64
+
+ // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_F_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_LT_U64::Inst_VOP3__V_CMPX_LT_U64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_lt_u64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_LT_U64
+
+ Inst_VOP3__V_CMPX_LT_U64::~Inst_VOP3__V_CMPX_LT_U64()
+ {
+ } // ~Inst_VOP3__V_CMPX_LT_U64
+
+ // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_LT_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_EQ_U64::Inst_VOP3__V_CMPX_EQ_U64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_eq_u64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_EQ_U64
+
+ Inst_VOP3__V_CMPX_EQ_U64::~Inst_VOP3__V_CMPX_EQ_U64()
+ {
+ } // ~Inst_VOP3__V_CMPX_EQ_U64
+
+ // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_EQ_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_LE_U64::Inst_VOP3__V_CMPX_LE_U64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_le_u64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_LE_U64
+
+ Inst_VOP3__V_CMPX_LE_U64::~Inst_VOP3__V_CMPX_LE_U64()
+ {
+ } // ~Inst_VOP3__V_CMPX_LE_U64
+
+ // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_LE_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_GT_U64::Inst_VOP3__V_CMPX_GT_U64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_gt_u64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_GT_U64
+
+ Inst_VOP3__V_CMPX_GT_U64::~Inst_VOP3__V_CMPX_GT_U64()
+ {
+ } // ~Inst_VOP3__V_CMPX_GT_U64
+
+ // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_GT_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_NE_U64::Inst_VOP3__V_CMPX_NE_U64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_ne_u64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_NE_U64
+
+ Inst_VOP3__V_CMPX_NE_U64::~Inst_VOP3__V_CMPX_NE_U64()
+ {
+ } // ~Inst_VOP3__V_CMPX_NE_U64
+
+ // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_NE_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_GE_U64::Inst_VOP3__V_CMPX_GE_U64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_ge_u64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_GE_U64
+
+ Inst_VOP3__V_CMPX_GE_U64::~Inst_VOP3__V_CMPX_GE_U64()
+ {
+ } // ~Inst_VOP3__V_CMPX_GE_U64
+
+ // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_GE_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CMPX_T_U64::Inst_VOP3__V_CMPX_T_U64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cmpx_t_u64", true)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CMPX_T_U64
+
+ Inst_VOP3__V_CMPX_T_U64::~Inst_VOP3__V_CMPX_T_U64()
+ {
+ } // ~Inst_VOP3__V_CMPX_T_U64
+
+ // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
+ void
+ Inst_VOP3__V_CMPX_T_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ sdst.setBit(lane, 1);
+ }
+ }
+
+ wf->execMask() = sdst.rawData();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_CNDMASK_B32::Inst_VOP3__V_CNDMASK_B32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cndmask_b32", false)
+ {
+ setFlag(ALU);
+ setFlag(ReadsVCC);
+ } // Inst_VOP3__V_CNDMASK_B32
+
+ Inst_VOP3__V_CNDMASK_B32::~Inst_VOP3__V_CNDMASK_B32()
+ {
+ } // ~Inst_VOP3__V_CNDMASK_B32
+
+ // D.u = (VCC[i] ? S1.u : S0.u) (i = threadID in wave); VOP3: specify VCC
+ // as a scalar GPR in S2.
+ void
+ Inst_VOP3__V_CNDMASK_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ConstScalarOperandU64 vcc(gpuDynInst, extData.SRC2);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ vcc.read();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = bits(vcc.rawData(), lane)
+ ? src1[lane] : src0[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_ADD_F32::Inst_VOP3__V_ADD_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_add_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_ADD_F32
+
+ Inst_VOP3__V_ADD_F32::~Inst_VOP3__V_ADD_F32()
+ {
+ } // ~Inst_VOP3__V_ADD_F32
+
+ // D.f = S0.f + S1.f.
+ void
+ Inst_VOP3__V_ADD_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] + src1[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_SUB_F32::Inst_VOP3__V_SUB_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_sub_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_SUB_F32
+
+ Inst_VOP3__V_SUB_F32::~Inst_VOP3__V_SUB_F32()
+ {
+ } // ~Inst_VOP3__V_SUB_F32
+
+ // D.f = S0.f - S1.f.
+ void
+ Inst_VOP3__V_SUB_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] - src1[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_SUBREV_F32::Inst_VOP3__V_SUBREV_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_subrev_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_SUBREV_F32
+
+ Inst_VOP3__V_SUBREV_F32::~Inst_VOP3__V_SUBREV_F32()
+ {
+ } // ~Inst_VOP3__V_SUBREV_F32
+
+ // D.f = S1.f - S0.f.
+ void
+ Inst_VOP3__V_SUBREV_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src1[lane] - src0[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MUL_LEGACY_F32::Inst_VOP3__V_MUL_LEGACY_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mul_legacy_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_MUL_LEGACY_F32
+
+ Inst_VOP3__V_MUL_LEGACY_F32::~Inst_VOP3__V_MUL_LEGACY_F32()
+ {
+ } // ~Inst_VOP3__V_MUL_LEGACY_F32
+
+ // D.f = S0.f * S1.f
+ void
+ Inst_VOP3__V_MUL_LEGACY_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::isnan(src0[lane]) ||
+ std::isnan(src1[lane])) {
+ vdst[lane] = NAN;
+ } else if ((std::fpclassify(src0[lane]) == FP_SUBNORMAL ||
+ std::fpclassify(src0[lane]) == FP_ZERO) &&
+ !std::signbit(src0[lane])) {
+ if (std::isinf(src1[lane])) {
+ vdst[lane] = NAN;
+ } else if (!std::signbit(src1[lane])) {
+ vdst[lane] = +0.0;
+ } else {
+ vdst[lane] = -0.0;
+ }
+ } else if ((std::fpclassify(src0[lane]) == FP_SUBNORMAL ||
+ std::fpclassify(src0[lane]) == FP_ZERO) &&
+ std::signbit(src0[lane])) {
+ if (std::isinf(src1[lane])) {
+ vdst[lane] = NAN;
+ } else if (std::signbit(src1[lane])) {
+ vdst[lane] = +0.0;
+ } else {
+ vdst[lane] = -0.0;
+ }
+ } else if (std::isinf(src0[lane]) &&
+ !std::signbit(src0[lane])) {
+ if (std::fpclassify(src1[lane]) == FP_SUBNORMAL ||
+ std::fpclassify(src1[lane]) == FP_ZERO) {
+ vdst[lane] = NAN;
+ } else if (!std::signbit(src1[lane])) {
+ vdst[lane] = +INFINITY;
+ } else {
+ vdst[lane] = -INFINITY;
+ }
+ } else if (std::isinf(src0[lane]) &&
+ std::signbit(src0[lane])) {
+ if (std::fpclassify(src1[lane]) == FP_SUBNORMAL ||
+ std::fpclassify(src1[lane]) == FP_ZERO) {
+ vdst[lane] = NAN;
+ } else if (std::signbit(src1[lane])) {
+ vdst[lane] = +INFINITY;
+ } else {
+ vdst[lane] = -INFINITY;
+ }
+ } else {
+ vdst[lane] = src0[lane] * src1[lane];
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MUL_F32::Inst_VOP3__V_MUL_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mul_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_MUL_F32
+
+ Inst_VOP3__V_MUL_F32::~Inst_VOP3__V_MUL_F32()
+ {
+ } // ~Inst_VOP3__V_MUL_F32
+
+ // D.f = S0.f * S1.f.
+ void
+ Inst_VOP3__V_MUL_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::isnan(src0[lane]) ||
+ std::isnan(src1[lane])) {
+ vdst[lane] = NAN;
+ } else if ((std::fpclassify(src0[lane]) == FP_SUBNORMAL ||
+ std::fpclassify(src0[lane]) == FP_ZERO) &&
+ !std::signbit(src0[lane])) {
+ if (std::isinf(src1[lane])) {
+ vdst[lane] = NAN;
+ } else if (!std::signbit(src1[lane])) {
+ vdst[lane] = +0.0;
+ } else {
+ vdst[lane] = -0.0;
+ }
+ } else if ((std::fpclassify(src0[lane]) == FP_SUBNORMAL ||
+ std::fpclassify(src0[lane]) == FP_ZERO) &&
+ std::signbit(src0[lane])) {
+ if (std::isinf(src1[lane])) {
+ vdst[lane] = NAN;
+ } else if (std::signbit(src1[lane])) {
+ vdst[lane] = +0.0;
+ } else {
+ vdst[lane] = -0.0;
+ }
+ } else if (std::isinf(src0[lane]) &&
+ !std::signbit(src0[lane])) {
+ if (std::fpclassify(src1[lane]) == FP_SUBNORMAL ||
+ std::fpclassify(src1[lane]) == FP_ZERO) {
+ vdst[lane] = NAN;
+ } else if (!std::signbit(src1[lane])) {
+ vdst[lane] = +INFINITY;
+ } else {
+ vdst[lane] = -INFINITY;
+ }
+ } else if (std::isinf(src0[lane]) &&
+ std::signbit(src0[lane])) {
+ if (std::fpclassify(src1[lane]) == FP_SUBNORMAL ||
+ std::fpclassify(src1[lane]) == FP_ZERO) {
+ vdst[lane] = NAN;
+ } else if (std::signbit(src1[lane])) {
+ vdst[lane] = +INFINITY;
+ } else {
+ vdst[lane] = -INFINITY;
+ }
+ } else {
+ vdst[lane] = src0[lane] * src1[lane];
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MUL_I32_I24::Inst_VOP3__V_MUL_I32_I24(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mul_i32_i24", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MUL_I32_I24
+
+ Inst_VOP3__V_MUL_I32_I24::~Inst_VOP3__V_MUL_I32_I24()
+ {
+ } // ~Inst_VOP3__V_MUL_I32_I24
+
+ // D.i = S0.i[23:0] * S1.i[23:0].
+ void
+ Inst_VOP3__V_MUL_I32_I24::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = sext<24>(bits(src0[lane], 23, 0))
+ * sext<24>(bits(src1[lane], 23, 0));
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MUL_HI_I32_I24::Inst_VOP3__V_MUL_HI_I32_I24(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mul_hi_i32_i24", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MUL_HI_I32_I24
+
+ Inst_VOP3__V_MUL_HI_I32_I24::~Inst_VOP3__V_MUL_HI_I32_I24()
+ {
+ } // ~Inst_VOP3__V_MUL_HI_I32_I24
+
+ // D.i = (S0.i[23:0] * S1.i[23:0]) >> 32.
+ void
+ Inst_VOP3__V_MUL_HI_I32_I24::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ VecElemI64 tmp_src0
+ = (VecElemI64)sext<24>(bits(src0[lane], 23, 0));
+ VecElemI64 tmp_src1
+ = (VecElemI64)sext<24>(bits(src1[lane], 23, 0));
+
+ vdst[lane] = (VecElemI32)((tmp_src0 * tmp_src1) >> 32);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MUL_U32_U24::Inst_VOP3__V_MUL_U32_U24(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mul_u32_u24", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MUL_U32_U24
+
+ Inst_VOP3__V_MUL_U32_U24::~Inst_VOP3__V_MUL_U32_U24()
+ {
+ } // ~Inst_VOP3__V_MUL_U32_U24
+
+ // D.u = S0.u[23:0] * S1.u[23:0].
+ void
+ Inst_VOP3__V_MUL_U32_U24::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = bits(src0[lane], 23, 0) * bits(src1[lane], 23, 0);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MUL_HI_U32_U24::Inst_VOP3__V_MUL_HI_U32_U24(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mul_hi_u32_u24", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MUL_HI_U32_U24
+
+ Inst_VOP3__V_MUL_HI_U32_U24::~Inst_VOP3__V_MUL_HI_U32_U24()
+ {
+ } // ~Inst_VOP3__V_MUL_HI_U32_U24
+
+ // D.i = (S0.u[23:0] * S1.u[23:0]) >> 32.
+ void
+ Inst_VOP3__V_MUL_HI_U32_U24::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ VecElemU64 tmp_src0 = (VecElemU64)bits(src0[lane], 23, 0);
+ VecElemU64 tmp_src1 = (VecElemU64)bits(src1[lane], 23, 0);
+ vdst[lane] = (VecElemU32)((tmp_src0 * tmp_src1) >> 32);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MIN_F32::Inst_VOP3__V_MIN_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_min_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_MIN_F32
+
+ Inst_VOP3__V_MIN_F32::~Inst_VOP3__V_MIN_F32()
+ {
+ } // ~Inst_VOP3__V_MIN_F32
+
+ // D.f = (S0.f < S1.f ? S0.f : S1.f).
+ void
+ Inst_VOP3__V_MIN_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::fmin(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MAX_F32::Inst_VOP3__V_MAX_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_max_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_MAX_F32
+
+ Inst_VOP3__V_MAX_F32::~Inst_VOP3__V_MAX_F32()
+ {
+ } // ~Inst_VOP3__V_MAX_F32
+
+ // D.f = (S0.f >= S1.f ? S0.f : S1.f).
+ void
+ Inst_VOP3__V_MAX_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::fmax(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MIN_I32::Inst_VOP3__V_MIN_I32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_min_i32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MIN_I32
+
+ Inst_VOP3__V_MIN_I32::~Inst_VOP3__V_MIN_I32()
+ {
+ } // ~Inst_VOP3__V_MIN_I32
+
+ // D.i = min(S0.i, S1.i).
+ void
+ Inst_VOP3__V_MIN_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::min(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MAX_I32::Inst_VOP3__V_MAX_I32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_max_i32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MAX_I32
+
+ Inst_VOP3__V_MAX_I32::~Inst_VOP3__V_MAX_I32()
+ {
+ } // ~Inst_VOP3__V_MAX_I32
+
+ // D.i = max(S0.i, S1.i).
+ void
+ Inst_VOP3__V_MAX_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::max(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MIN_U32::Inst_VOP3__V_MIN_U32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_min_u32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MIN_U32
+
+ Inst_VOP3__V_MIN_U32::~Inst_VOP3__V_MIN_U32()
+ {
+ } // ~Inst_VOP3__V_MIN_U32
+
+ // D.u = min(S0.u, S1.u).
+ void
+ Inst_VOP3__V_MIN_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::min(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MAX_U32::Inst_VOP3__V_MAX_U32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_max_u32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MAX_U32
+
+ Inst_VOP3__V_MAX_U32::~Inst_VOP3__V_MAX_U32()
+ {
+ } // ~Inst_VOP3__V_MAX_U32
+
+ // D.u = max(S0.u, S1.u).
+ void
+ Inst_VOP3__V_MAX_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::max(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_LSHRREV_B32::Inst_VOP3__V_LSHRREV_B32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_lshrrev_b32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_LSHRREV_B32
+
+ Inst_VOP3__V_LSHRREV_B32::~Inst_VOP3__V_LSHRREV_B32()
+ {
+ } // ~Inst_VOP3__V_LSHRREV_B32
+
+ // D.u = S1.u >> S0.u[4:0].
+ // The vacated bits are set to zero.
+ void
+ Inst_VOP3__V_LSHRREV_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src1[lane] >> bits(src0[lane], 4, 0);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_ASHRREV_I32::Inst_VOP3__V_ASHRREV_I32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_ashrrev_i32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_ASHRREV_I32
+
+ Inst_VOP3__V_ASHRREV_I32::~Inst_VOP3__V_ASHRREV_I32()
+ {
+ } // ~Inst_VOP3__V_ASHRREV_I32
+
+ // D.i = signext(S1.i) >> S0.i[4:0].
+ // The vacated bits are set to the sign bit of the input value.
+ void
+ Inst_VOP3__V_ASHRREV_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src1[lane] >> bits(src0[lane], 4, 0);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_LSHLREV_B32::Inst_VOP3__V_LSHLREV_B32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_lshlrev_b32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_LSHLREV_B32
+
+ Inst_VOP3__V_LSHLREV_B32::~Inst_VOP3__V_LSHLREV_B32()
+ {
+ } // ~Inst_VOP3__V_LSHLREV_B32
+
+ // D.u = S1.u << S0.u[4:0].
+ void
+ Inst_VOP3__V_LSHLREV_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src1[lane] << bits(src0[lane], 4, 0);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_AND_B32::Inst_VOP3__V_AND_B32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_and_b32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_AND_B32
+
+ Inst_VOP3__V_AND_B32::~Inst_VOP3__V_AND_B32()
+ {
+ } // ~Inst_VOP3__V_AND_B32
+
+ // D.u = S0.u & S1.u.
+ // Input and output modifiers not supported.
+ void
+ Inst_VOP3__V_AND_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] & src1[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_OR_B32::Inst_VOP3__V_OR_B32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_or_b32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_OR_B32
+
+ Inst_VOP3__V_OR_B32::~Inst_VOP3__V_OR_B32()
+ {
+ } // ~Inst_VOP3__V_OR_B32
+
+ // D.u = S0.u | S1.u.
+ // Input and output modifiers not supported.
+ void
+ Inst_VOP3__V_OR_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] | src1[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_XOR_B32::Inst_VOP3__V_XOR_B32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_xor_b32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_XOR_B32
+
+ Inst_VOP3__V_XOR_B32::~Inst_VOP3__V_XOR_B32()
+ {
+ } // ~Inst_VOP3__V_XOR_B32
+
+ // D.u = S0.u ^ S1.u.
+ // Input and output modifiers not supported.
+ void
+ Inst_VOP3__V_XOR_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] ^ src1[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MAC_F32::Inst_VOP3__V_MAC_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mac_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ setFlag(MAC);
+ } // Inst_VOP3__V_MAC_F32
+
+ Inst_VOP3__V_MAC_F32::~Inst_VOP3__V_MAC_F32()
+ {
+ } // ~Inst_VOP3__V_MAC_F32
+
+ // D.f = S0.f * S1.f + D.f.
+ void
+ Inst_VOP3__V_MAC_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ vdst.read();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::fma(src0[lane], src1[lane], vdst[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_ADD_U32::Inst_VOP3__V_ADD_U32(InFmt_VOP3_SDST_ENC *iFmt)
+ : Inst_VOP3_SDST_ENC(iFmt, "v_add_u32")
+ {
+ setFlag(ALU);
+ setFlag(WritesVCC);
+ } // Inst_VOP3__V_ADD_U32
+
+ Inst_VOP3__V_ADD_U32::~Inst_VOP3__V_ADD_U32()
+ {
+ } // ~Inst_VOP3__V_ADD_U32
+
+ // D.u = S0.u + S1.u;
+ // VCC[threadId] = (S0.u + S1.u >= 0x800000000ULL ? 1 : 0) is an UNSIGNED
+ // overflow or carry-out.
+ // In VOP3 the VCC destination may be an arbitrary SGPR-pair.
+ void
+ Inst_VOP3__V_ADD_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+ ScalarOperandU64 vcc(gpuDynInst, instData.SDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] + src1[lane];
+ vcc.setBit(lane, ((VecElemU64)src0[lane]
+ + (VecElemU64)src1[lane]) >= 0x100000000ULL ? 1 : 0);
+ }
+ }
+
+ vdst.write();
+ vcc.write();
+ }
+
+ Inst_VOP3__V_SUB_U32::Inst_VOP3__V_SUB_U32(InFmt_VOP3_SDST_ENC *iFmt)
+ : Inst_VOP3_SDST_ENC(iFmt, "v_sub_u32")
+ {
+ setFlag(ALU);
+ setFlag(WritesVCC);
+ } // Inst_VOP3__V_SUB_U32
+
+ Inst_VOP3__V_SUB_U32::~Inst_VOP3__V_SUB_U32()
+ {
+ } // ~Inst_VOP3__V_SUB_U32
+
+ // D.u = S0.u - S1.u;
+ // VCC[threadId] = (S1.u > S0.u ? 1 : 0) is an UNSIGNED overflow or
+ // carry-out.
+ // In VOP3 the VCC destination may be an arbitrary SGPR-pair.
+ void
+ Inst_VOP3__V_SUB_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+ ScalarOperandU64 vcc(gpuDynInst, instData.SDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] - src1[lane];
+ vcc.setBit(lane, src1[lane] > src0[lane] ? 1 : 0);
+ }
+ }
+
+ vdst.write();
+ vcc.write();
+ }
+
+ Inst_VOP3__V_SUBREV_U32::Inst_VOP3__V_SUBREV_U32(
+ InFmt_VOP3_SDST_ENC *iFmt)
+ : Inst_VOP3_SDST_ENC(iFmt, "v_subrev_u32")
+ {
+ setFlag(ALU);
+ setFlag(WritesVCC);
+ } // Inst_VOP3__V_SUBREV_U32
+
+ Inst_VOP3__V_SUBREV_U32::~Inst_VOP3__V_SUBREV_U32()
+ {
+ } // ~Inst_VOP3__V_SUBREV_U32
+
+ // D.u = S1.u - S0.u;
+ // VCC[threadId] = (S0.u > S1.u ? 1 : 0) is an UNSIGNED overflow or
+ // carry-out.
+ // In VOP3 the VCC destination may be an arbitrary SGPR-pair.
+ void
+ Inst_VOP3__V_SUBREV_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+ ScalarOperandU64 vcc(gpuDynInst, instData.SDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src1[lane] - src0[lane];
+ vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
+ }
+ }
+
+ vdst.write();
+ vcc.write();
+ }
+
+ Inst_VOP3__V_ADDC_U32::Inst_VOP3__V_ADDC_U32(InFmt_VOP3_SDST_ENC *iFmt)
+ : Inst_VOP3_SDST_ENC(iFmt, "v_addc_u32")
+ {
+ setFlag(ALU);
+ setFlag(WritesVCC);
+ setFlag(ReadsVCC);
+ } // Inst_VOP3__V_ADDC_U32
+
+ Inst_VOP3__V_ADDC_U32::~Inst_VOP3__V_ADDC_U32()
+ {
+ } // ~Inst_VOP3__V_ADDC_U32
+
+ // D.u = S0.u + S1.u + VCC[threadId];
+ // VCC[threadId] = (S0.u + S1.u + VCC[threadId] >= 0x100000000ULL ? 1 : 0)
+ // is an UNSIGNED overflow.
+ // In VOP3 the VCC destination may be an arbitrary SGPR-pair, and the VCC
+ // source comes from the SGPR-pair at S2.u.
+ void
+ Inst_VOP3__V_ADDC_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ConstScalarOperandU64 vcc(gpuDynInst, extData.SRC2);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ vcc.read();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] + src1[lane]
+ + bits(vcc.rawData(), lane);
+ sdst.setBit(lane, ((VecElemU64)src0[lane]
+ + (VecElemU64)src1[lane]
+ + (VecElemU64)bits(vcc.rawData(), lane))
+ >= 0x100000000 ? 1 : 0);
+ }
+ }
+
+ vdst.write();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_SUBB_U32::Inst_VOP3__V_SUBB_U32(InFmt_VOP3_SDST_ENC *iFmt)
+ : Inst_VOP3_SDST_ENC(iFmt, "v_subb_u32")
+ {
+ setFlag(ALU);
+ setFlag(WritesVCC);
+ setFlag(ReadsVCC);
+ } // Inst_VOP3__V_SUBB_U32
+
+ Inst_VOP3__V_SUBB_U32::~Inst_VOP3__V_SUBB_U32()
+ {
+ } // ~Inst_VOP3__V_SUBB_U32
+
+ // D.u = S0.u - S1.u - VCC[threadId];
+ // VCC[threadId] = (S1.u + VCC[threadId] > S0.u ? 1 : 0) is an UNSIGNED
+ // overflow.
+ // In VOP3 the VCC destination may be an arbitrary SGPR-pair, and the VCC
+ // source comes from the SGPR-pair at S2.u.
+ void
+ Inst_VOP3__V_SUBB_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ConstScalarOperandU64 vcc(gpuDynInst, extData.SRC2);
+ ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ vcc.read();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] - src1[lane]
+ - bits(vcc.rawData(), lane);
+ sdst.setBit(lane, (src1[lane] + bits(vcc.rawData(), lane))
+ > src0[lane] ? 1 : 0);
+ }
+ }
+
+ vdst.write();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_SUBBREV_U32::Inst_VOP3__V_SUBBREV_U32(
+ InFmt_VOP3_SDST_ENC *iFmt)
+ : Inst_VOP3_SDST_ENC(iFmt, "v_subbrev_u32")
+ {
+ setFlag(ALU);
+ setFlag(WritesVCC);
+ setFlag(ReadsVCC);
+ } // Inst_VOP3__V_SUBBREV_U32
+
+ Inst_VOP3__V_SUBBREV_U32::~Inst_VOP3__V_SUBBREV_U32()
+ {
+ } // ~Inst_VOP3__V_SUBBREV_U32
+
+ // D.u = S1.u - S0.u - VCC[threadId];
+ // VCC[threadId] = (S1.u + VCC[threadId] > S0.u ? 1 : 0) is an UNSIGNED
+ // overflow.
+ // In VOP3 the VCC destination may be an arbitrary SGPR-pair, and the VCC
+ // source comes from the SGPR-pair at S2.u.
+ void
+ Inst_VOP3__V_SUBBREV_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstScalarOperandU64 sdst(gpuDynInst, instData.SDST);
+ ScalarOperandU64 vcc(gpuDynInst, extData.SRC2);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ vcc.read();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src1[lane] - src0[lane]
+ - bits(vcc.rawData(), lane);
+ sdst.setBit(lane, (src1[lane] + bits(vcc.rawData(), lane))
+ > src0[lane] ? 1 : 0);
+ }
+ }
+
+ vdst.write();
+ sdst.write();
+ }
+
+ Inst_VOP3__V_ADD_F16::Inst_VOP3__V_ADD_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_add_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_ADD_F16
+
+ Inst_VOP3__V_ADD_F16::~Inst_VOP3__V_ADD_F16()
+ {
+ } // ~Inst_VOP3__V_ADD_F16
+
+ // D.f16 = S0.f16 + S1.f16.
+ void
+ Inst_VOP3__V_ADD_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_SUB_F16::Inst_VOP3__V_SUB_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_sub_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_SUB_F16
+
+ Inst_VOP3__V_SUB_F16::~Inst_VOP3__V_SUB_F16()
+ {
+ } // ~Inst_VOP3__V_SUB_F16
+
+ // D.f16 = S0.f16 - S1.f16.
+ void
+ Inst_VOP3__V_SUB_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_SUBREV_F16::Inst_VOP3__V_SUBREV_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_subrev_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_SUBREV_F16
+
+ Inst_VOP3__V_SUBREV_F16::~Inst_VOP3__V_SUBREV_F16()
+ {
+ } // ~Inst_VOP3__V_SUBREV_F16
+
+ // D.f16 = S1.f16 - S0.f16.
+ void
+ Inst_VOP3__V_SUBREV_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_MUL_F16::Inst_VOP3__V_MUL_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mul_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_MUL_F16
+
+ Inst_VOP3__V_MUL_F16::~Inst_VOP3__V_MUL_F16()
+ {
+ } // ~Inst_VOP3__V_MUL_F16
+
+ // D.f16 = S0.f16 * S1.f16.
+ void
+ Inst_VOP3__V_MUL_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_MAC_F16::Inst_VOP3__V_MAC_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mac_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ setFlag(MAC);
+ } // Inst_VOP3__V_MAC_F16
+
+ Inst_VOP3__V_MAC_F16::~Inst_VOP3__V_MAC_F16()
+ {
+ } // ~Inst_VOP3__V_MAC_F16
+
+ // D.f16 = S0.f16 * S1.f16 + D.f16.
+ void
+ Inst_VOP3__V_MAC_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_ADD_U16::Inst_VOP3__V_ADD_U16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_add_u16", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_ADD_U16
+
+ Inst_VOP3__V_ADD_U16::~Inst_VOP3__V_ADD_U16()
+ {
+ } // ~Inst_VOP3__V_ADD_U16
+
+ // D.u16 = S0.u16 + S1.u16.
+ void
+ Inst_VOP3__V_ADD_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
+ VecOperandU16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] + src1[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_SUB_U16::Inst_VOP3__V_SUB_U16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_sub_u16", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_SUB_U16
+
+ Inst_VOP3__V_SUB_U16::~Inst_VOP3__V_SUB_U16()
+ {
+ } // ~Inst_VOP3__V_SUB_U16
+
+ // D.u16 = S0.u16 - S1.u16.
+ void
+ Inst_VOP3__V_SUB_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
+ VecOperandU16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] - src1[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_SUBREV_U16::Inst_VOP3__V_SUBREV_U16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_subrev_u16", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_SUBREV_U16
+
+ Inst_VOP3__V_SUBREV_U16::~Inst_VOP3__V_SUBREV_U16()
+ {
+ } // ~Inst_VOP3__V_SUBREV_U16
+
+ // D.u16 = S1.u16 - S0.u16.
+ void
+ Inst_VOP3__V_SUBREV_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
+ VecOperandU16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src1[lane] - src0[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MUL_LO_U16::Inst_VOP3__V_MUL_LO_U16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mul_lo_u16", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MUL_LO_U16
+
+ Inst_VOP3__V_MUL_LO_U16::~Inst_VOP3__V_MUL_LO_U16()
+ {
+ } // ~Inst_VOP3__V_MUL_LO_U16
+
+ // D.u16 = S0.u16 * S1.u16.
+ void
+ Inst_VOP3__V_MUL_LO_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
+ VecOperandU16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] * src1[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_LSHLREV_B16::Inst_VOP3__V_LSHLREV_B16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_lshlrev_b16", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_LSHLREV_B16
+
+ Inst_VOP3__V_LSHLREV_B16::~Inst_VOP3__V_LSHLREV_B16()
+ {
+ } // ~Inst_VOP3__V_LSHLREV_B16
+
+ // D.u[15:0] = S1.u[15:0] << S0.u[3:0].
+ void
+ Inst_VOP3__V_LSHLREV_B16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
+ VecOperandU16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src1[lane] << bits(src0[lane], 3, 0);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_LSHRREV_B16::Inst_VOP3__V_LSHRREV_B16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_lshrrev_b16", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_LSHRREV_B16
+
+ Inst_VOP3__V_LSHRREV_B16::~Inst_VOP3__V_LSHRREV_B16()
+ {
+ } // ~Inst_VOP3__V_LSHRREV_B16
+
+ // D.u[15:0] = S1.u[15:0] >> S0.u[3:0].
+ // The vacated bits are set to zero.
+ void
+ Inst_VOP3__V_LSHRREV_B16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
+ VecOperandU16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src1[lane] >> bits(src0[lane], 3, 0);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_ASHRREV_I16::Inst_VOP3__V_ASHRREV_I16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_ashrrev_i16", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_ASHRREV_I16
+
+ Inst_VOP3__V_ASHRREV_I16::~Inst_VOP3__V_ASHRREV_I16()
+ {
+ } // ~Inst_VOP3__V_ASHRREV_I16
+
+ // D.i[15:0] = signext(S1.i[15:0]) >> S0.i[3:0].
+ // The vacated bits are set to the sign bit of the input value.
+ void
+ Inst_VOP3__V_ASHRREV_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
+ VecOperandI16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src1[lane] >> bits(src0[lane], 3, 0);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MAX_F16::Inst_VOP3__V_MAX_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_max_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_MAX_F16
+
+ Inst_VOP3__V_MAX_F16::~Inst_VOP3__V_MAX_F16()
+ {
+ } // ~Inst_VOP3__V_MAX_F16
+
+ // D.f16 = max(S0.f16, S1.f16).
+ void
+ Inst_VOP3__V_MAX_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_MIN_F16::Inst_VOP3__V_MIN_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_min_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_MIN_F16
+
+ Inst_VOP3__V_MIN_F16::~Inst_VOP3__V_MIN_F16()
+ {
+ } // ~Inst_VOP3__V_MIN_F16
+
+ // D.f16 = min(S0.f16, S1.f16).
+ void
+ Inst_VOP3__V_MIN_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_MAX_U16::Inst_VOP3__V_MAX_U16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_max_u16", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MAX_U16
+
+ Inst_VOP3__V_MAX_U16::~Inst_VOP3__V_MAX_U16()
+ {
+ } // ~Inst_VOP3__V_MAX_U16
+
+ // D.u[15:0] = max(S0.u[15:0], S1.u[15:0]).
+ void
+ Inst_VOP3__V_MAX_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
+ VecOperandU16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::max(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MAX_I16::Inst_VOP3__V_MAX_I16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_max_i16", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MAX_I16
+
+ Inst_VOP3__V_MAX_I16::~Inst_VOP3__V_MAX_I16()
+ {
+ } // ~Inst_VOP3__V_MAX_I16
+
+ // D.i[15:0] = max(S0.i[15:0], S1.i[15:0]).
+ void
+ Inst_VOP3__V_MAX_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
+ VecOperandI16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::max(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MIN_U16::Inst_VOP3__V_MIN_U16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_min_u16", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MIN_U16
+
+ Inst_VOP3__V_MIN_U16::~Inst_VOP3__V_MIN_U16()
+ {
+ } // ~Inst_VOP3__V_MIN_U16
+
+ // D.u[15:0] = min(S0.u[15:0], S1.u[15:0]).
+ void
+ Inst_VOP3__V_MIN_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
+ VecOperandU16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::min(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MIN_I16::Inst_VOP3__V_MIN_I16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_min_i16", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MIN_I16
+
+ Inst_VOP3__V_MIN_I16::~Inst_VOP3__V_MIN_I16()
+ {
+ } // ~Inst_VOP3__V_MIN_I16
+
+ // D.i[15:0] = min(S0.i[15:0], S1.i[15:0]).
+ void
+ Inst_VOP3__V_MIN_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
+ VecOperandI16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::min(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_LDEXP_F16::Inst_VOP3__V_LDEXP_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_ldexp_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_LDEXP_F16
+
+ Inst_VOP3__V_LDEXP_F16::~Inst_VOP3__V_LDEXP_F16()
+ {
+ } // ~Inst_VOP3__V_LDEXP_F16
+
+ // D.f16 = S0.f16 * (2 ** S1.i16).
+ void
+ Inst_VOP3__V_LDEXP_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_NOP::Inst_VOP3__V_NOP(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_nop", false)
+ {
+ setFlag(Nop);
+ setFlag(ALU);
+ } // Inst_VOP3__V_NOP
+
+ Inst_VOP3__V_NOP::~Inst_VOP3__V_NOP()
+ {
+ } // ~Inst_VOP3__V_NOP
+
+ // Do nothing.
+ void
+ Inst_VOP3__V_NOP::execute(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_VOP3__V_MOV_B32::Inst_VOP3__V_MOV_B32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mov_b32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MOV_B32
+
+ Inst_VOP3__V_MOV_B32::~Inst_VOP3__V_MOV_B32()
+ {
+ } // ~Inst_VOP3__V_MOV_B32
+
+ // D.u = S0.u.
+ // Input and output modifiers not supported; this is an untyped operation.
+ void
+ Inst_VOP3__V_MOV_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src(gpuDynInst, extData.SRC0);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_CVT_I32_F64::Inst_VOP3__V_CVT_I32_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_i32_f64", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CVT_I32_F64
+
+ Inst_VOP3__V_CVT_I32_F64::~Inst_VOP3__V_CVT_I32_F64()
+ {
+ } // ~Inst_VOP3__V_CVT_I32_F64
+
+ // D.i = (int)S0.d.
+ // Out-of-range floating point values (including infinity) saturate. NaN
+ // is converted to 0.
+ void
+ Inst_VOP3__V_CVT_I32_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, extData.SRC0);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::isnan(src[lane])) {
+ vdst[lane] = 0;
+ } else {
+ vdst[lane] = (VecElemI32)src[lane];
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_CVT_F64_I32::Inst_VOP3__V_CVT_F64_I32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_f64_i32", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CVT_F64_I32
+
+ Inst_VOP3__V_CVT_F64_I32::~Inst_VOP3__V_CVT_F64_I32()
+ {
+ } // ~Inst_VOP3__V_CVT_F64_I32
+
+ // D.d = (double)S0.i.
+ void
+ Inst_VOP3__V_CVT_F64_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src(gpuDynInst, extData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemF64)src[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_CVT_F32_I32::Inst_VOP3__V_CVT_F32_I32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_f32_i32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CVT_F32_I32
+
+ Inst_VOP3__V_CVT_F32_I32::~Inst_VOP3__V_CVT_F32_I32()
+ {
+ } // ~Inst_VOP3__V_CVT_F32_I32
+
+ // D.f = (float)S0.i.
+ void
+ Inst_VOP3__V_CVT_F32_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ VecOperandI32 src(gpuDynInst, extData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemF32)src[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_CVT_F32_U32::Inst_VOP3__V_CVT_F32_U32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_f32_u32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CVT_F32_U32
+
+ Inst_VOP3__V_CVT_F32_U32::~Inst_VOP3__V_CVT_F32_U32()
+ {
+ } // ~Inst_VOP3__V_CVT_F32_U32
+
+ // D.f = (float)S0.u.
+ void
+ Inst_VOP3__V_CVT_F32_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src(gpuDynInst, extData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemF32)src[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_CVT_U32_F32::Inst_VOP3__V_CVT_U32_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_u32_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CVT_U32_F32
+
+ Inst_VOP3__V_CVT_U32_F32::~Inst_VOP3__V_CVT_U32_F32()
+ {
+ } // ~Inst_VOP3__V_CVT_U32_F32
+
+ // D.u = (unsigned)S0.f.
+ // Out-of-range floating point values (including infinity) saturate. NaN
+ // is converted to 0.
+ void
+ Inst_VOP3__V_CVT_U32_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, extData.SRC0);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::isnan(src[lane])) {
+ vdst[lane] = 0;
+ } else {
+ vdst[lane] = (VecElemU32)src[lane];
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_CVT_I32_F32::Inst_VOP3__V_CVT_I32_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_i32_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CVT_I32_F32
+
+ Inst_VOP3__V_CVT_I32_F32::~Inst_VOP3__V_CVT_I32_F32()
+ {
+ } // ~Inst_VOP3__V_CVT_I32_F32
+
+ // D.i = (int)S0.f.
+ // Out-of-range floating point values (including infinity) saturate. NaN
+ // is converted to 0.
+ void
+ Inst_VOP3__V_CVT_I32_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, extData.SRC0);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::isnan(src[lane])) {
+ vdst[lane] = 0;
+ } else {
+ vdst[lane] = (VecElemI32)src[lane];
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MOV_FED_B32::Inst_VOP3__V_MOV_FED_B32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mov_fed_b32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MOV_FED_B32
+
+ Inst_VOP3__V_MOV_FED_B32::~Inst_VOP3__V_MOV_FED_B32()
+ {
+ } // ~Inst_VOP3__V_MOV_FED_B32
+
+ // D.u = S0.u;
+ // Input and output modifiers not supported; this is an untyped operation.
+ void
+ Inst_VOP3__V_MOV_FED_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CVT_F16_F32::Inst_VOP3__V_CVT_F16_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_f16_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CVT_F16_F32
+
+ Inst_VOP3__V_CVT_F16_F32::~Inst_VOP3__V_CVT_F16_F32()
+ {
+ } // ~Inst_VOP3__V_CVT_F16_F32
+
+ // D.f16 = flt32_to_flt16(S0.f).
+ void
+ Inst_VOP3__V_CVT_F16_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CVT_F32_F16::Inst_VOP3__V_CVT_F32_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_f32_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CVT_F32_F16
+
+ Inst_VOP3__V_CVT_F32_F16::~Inst_VOP3__V_CVT_F32_F16()
+ {
+ } // ~Inst_VOP3__V_CVT_F32_F16
+
+ // D.f = flt16_to_flt32(S0.f16).
+ void
+ Inst_VOP3__V_CVT_F32_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CVT_RPI_I32_F32::Inst_VOP3__V_CVT_RPI_I32_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_rpi_i32_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CVT_RPI_I32_F32
+
+ Inst_VOP3__V_CVT_RPI_I32_F32::~Inst_VOP3__V_CVT_RPI_I32_F32()
+ {
+ } // ~Inst_VOP3__V_CVT_RPI_I32_F32
+
+ // D.i = (int)floor(S0.f + 0.5).
+ void
+ Inst_VOP3__V_CVT_RPI_I32_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, extData.SRC0);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemI32)std::floor(src[lane] + 0.5);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_CVT_FLR_I32_F32::Inst_VOP3__V_CVT_FLR_I32_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_flr_i32_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CVT_FLR_I32_F32
+
+ Inst_VOP3__V_CVT_FLR_I32_F32::~Inst_VOP3__V_CVT_FLR_I32_F32()
+ {
+ } // ~Inst_VOP3__V_CVT_FLR_I32_F32
+
+ // D.i = (int)floor(S0.f).
+ void
+ Inst_VOP3__V_CVT_FLR_I32_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, extData.SRC0);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemI32)std::floor(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_CVT_OFF_F32_I4::Inst_VOP3__V_CVT_OFF_F32_I4(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_off_f32_i4", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CVT_OFF_F32_I4
+
+ Inst_VOP3__V_CVT_OFF_F32_I4::~Inst_VOP3__V_CVT_OFF_F32_I4()
+ {
+ } // ~Inst_VOP3__V_CVT_OFF_F32_I4
+
+ // 4-bit signed int to 32-bit float.
+ void
+ Inst_VOP3__V_CVT_OFF_F32_I4::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CVT_F32_F64::Inst_VOP3__V_CVT_F32_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_f32_f64", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CVT_F32_F64
+
+ Inst_VOP3__V_CVT_F32_F64::~Inst_VOP3__V_CVT_F32_F64()
+ {
+ } // ~Inst_VOP3__V_CVT_F32_F64
+
+ // D.f = (float)S0.d.
+ void
+ Inst_VOP3__V_CVT_F32_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, extData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemF32)src[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_CVT_F64_F32::Inst_VOP3__V_CVT_F64_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_f64_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CVT_F64_F32
+
+ Inst_VOP3__V_CVT_F64_F32::~Inst_VOP3__V_CVT_F64_F32()
+ {
+ } // ~Inst_VOP3__V_CVT_F64_F32
+
+ // D.d = (double)S0.f.
+ void
+ Inst_VOP3__V_CVT_F64_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, extData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemF64)src[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_CVT_F32_UBYTE0::Inst_VOP3__V_CVT_F32_UBYTE0(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_f32_ubyte0", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CVT_F32_UBYTE0
+
+ Inst_VOP3__V_CVT_F32_UBYTE0::~Inst_VOP3__V_CVT_F32_UBYTE0()
+ {
+ } // ~Inst_VOP3__V_CVT_F32_UBYTE0
+
+ // D.f = (float)(S0.u[7:0]).
+ void
+ Inst_VOP3__V_CVT_F32_UBYTE0::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src(gpuDynInst, extData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemF32)bits(src[lane], 7, 0);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_CVT_F32_UBYTE1::Inst_VOP3__V_CVT_F32_UBYTE1(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_f32_ubyte1", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CVT_F32_UBYTE1
+
+ Inst_VOP3__V_CVT_F32_UBYTE1::~Inst_VOP3__V_CVT_F32_UBYTE1()
+ {
+ } // ~Inst_VOP3__V_CVT_F32_UBYTE1
+
+ // D.f = (float)(S0.u[15:8]).
+ void
+ Inst_VOP3__V_CVT_F32_UBYTE1::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src(gpuDynInst, extData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemF32)bits(src[lane], 15, 8);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_CVT_F32_UBYTE2::Inst_VOP3__V_CVT_F32_UBYTE2(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_f32_ubyte2", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CVT_F32_UBYTE2
+
+ Inst_VOP3__V_CVT_F32_UBYTE2::~Inst_VOP3__V_CVT_F32_UBYTE2()
+ {
+ } // ~Inst_VOP3__V_CVT_F32_UBYTE2
+
+ // D.f = (float)(S0.u[23:16]).
+ void
+ Inst_VOP3__V_CVT_F32_UBYTE2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src(gpuDynInst, extData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemF32)bits(src[lane], 23, 16);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_CVT_F32_UBYTE3::Inst_VOP3__V_CVT_F32_UBYTE3(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_f32_ubyte3", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CVT_F32_UBYTE3
+
+ Inst_VOP3__V_CVT_F32_UBYTE3::~Inst_VOP3__V_CVT_F32_UBYTE3()
+ {
+ } // ~Inst_VOP3__V_CVT_F32_UBYTE3
+
+ // D.f = (float)(S0.u[31:24]).
+ void
+ Inst_VOP3__V_CVT_F32_UBYTE3::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src(gpuDynInst, extData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemF32)bits(src[lane], 31, 24);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_CVT_U32_F64::Inst_VOP3__V_CVT_U32_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_u32_f64", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CVT_U32_F64
+
+ Inst_VOP3__V_CVT_U32_F64::~Inst_VOP3__V_CVT_U32_F64()
+ {
+ } // ~Inst_VOP3__V_CVT_U32_F64
+
+ // D.u = (unsigned)S0.d.
+ // Out-of-range floating point values (including infinity) saturate. NaN
+ // is converted to 0.
+ void
+ Inst_VOP3__V_CVT_U32_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, extData.SRC0);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemU32)src[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_CVT_F64_U32::Inst_VOP3__V_CVT_F64_U32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_f64_u32", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CVT_F64_U32
+
+ Inst_VOP3__V_CVT_F64_U32::~Inst_VOP3__V_CVT_F64_U32()
+ {
+ } // ~Inst_VOP3__V_CVT_F64_U32
+
+ // D.d = (double)S0.u.
+ void
+ Inst_VOP3__V_CVT_F64_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src(gpuDynInst, extData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (VecElemF64)src[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_TRUNC_F64::Inst_VOP3__V_TRUNC_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_trunc_f64", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_TRUNC_F64
+
+ Inst_VOP3__V_TRUNC_F64::~Inst_VOP3__V_TRUNC_F64()
+ {
+ } // ~Inst_VOP3__V_TRUNC_F64
+
+ // D.d = trunc(S0.d), return integer part of S0.d.
+ void
+ Inst_VOP3__V_TRUNC_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, extData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::trunc(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_CEIL_F64::Inst_VOP3__V_CEIL_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_ceil_f64", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_CEIL_F64
+
+ Inst_VOP3__V_CEIL_F64::~Inst_VOP3__V_CEIL_F64()
+ {
+ } // ~Inst_VOP3__V_CEIL_F64
+
+ // D.d = ceil(S0.d);
+ void
+ Inst_VOP3__V_CEIL_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, extData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::ceil(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_RNDNE_F64::Inst_VOP3__V_RNDNE_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_rndne_f64", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_RNDNE_F64
+
+ Inst_VOP3__V_RNDNE_F64::~Inst_VOP3__V_RNDNE_F64()
+ {
+ } // ~Inst_VOP3__V_RNDNE_F64
+
+ // D.d = round_nearest_even(S0.d).
+ void
+ Inst_VOP3__V_RNDNE_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, extData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = roundNearestEven(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_FLOOR_F64::Inst_VOP3__V_FLOOR_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_floor_f64", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_FLOOR_F64
+
+ Inst_VOP3__V_FLOOR_F64::~Inst_VOP3__V_FLOOR_F64()
+ {
+ } // ~Inst_VOP3__V_FLOOR_F64
+
+ // D.d = floor(S0.d);
+ void
+ Inst_VOP3__V_FLOOR_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, extData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::floor(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_FRACT_F32::Inst_VOP3__V_FRACT_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_fract_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_FRACT_F32
+
+ Inst_VOP3__V_FRACT_F32::~Inst_VOP3__V_FRACT_F32()
+ {
+ } // ~Inst_VOP3__V_FRACT_F32
+
+ // D.f = modf(S0.f).
+ void
+ Inst_VOP3__V_FRACT_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, extData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ VecElemF32 int_part(0.0);
+ vdst[lane] = std::modf(src[lane], &int_part);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_TRUNC_F32::Inst_VOP3__V_TRUNC_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_trunc_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_TRUNC_F32
+
+ Inst_VOP3__V_TRUNC_F32::~Inst_VOP3__V_TRUNC_F32()
+ {
+ } // ~Inst_VOP3__V_TRUNC_F32
+
+ // D.f = trunc(S0.f), return integer part of S0.f.
+ void
+ Inst_VOP3__V_TRUNC_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, extData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::trunc(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_CEIL_F32::Inst_VOP3__V_CEIL_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_ceil_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CEIL_F32
+
+ Inst_VOP3__V_CEIL_F32::~Inst_VOP3__V_CEIL_F32()
+ {
+ } // ~Inst_VOP3__V_CEIL_F32
+
+ // D.f = ceil(S0.f);
+ void
+ Inst_VOP3__V_CEIL_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, extData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::ceil(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_RNDNE_F32::Inst_VOP3__V_RNDNE_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_rndne_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_RNDNE_F32
+
+ Inst_VOP3__V_RNDNE_F32::~Inst_VOP3__V_RNDNE_F32()
+ {
+ } // ~Inst_VOP3__V_RNDNE_F32
+
+ // D.f = round_nearest_even(S0.f).
+ void
+ Inst_VOP3__V_RNDNE_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, extData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = roundNearestEven(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_FLOOR_F32::Inst_VOP3__V_FLOOR_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_floor_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_FLOOR_F32
+
+ Inst_VOP3__V_FLOOR_F32::~Inst_VOP3__V_FLOOR_F32()
+ {
+ } // ~Inst_VOP3__V_FLOOR_F32
+
+ // D.f = floor(S0.f);
+ void
+ Inst_VOP3__V_FLOOR_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, extData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::floor(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_EXP_F32::Inst_VOP3__V_EXP_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_exp_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_EXP_F32
+
+ Inst_VOP3__V_EXP_F32::~Inst_VOP3__V_EXP_F32()
+ {
+ } // ~Inst_VOP3__V_EXP_F32
+
+ // D.f = pow(2.0, S0.f).
+ void
+ Inst_VOP3__V_EXP_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, extData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::pow(2.0, src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_LOG_F32::Inst_VOP3__V_LOG_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_log_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_LOG_F32
+
+ Inst_VOP3__V_LOG_F32::~Inst_VOP3__V_LOG_F32()
+ {
+ } // ~Inst_VOP3__V_LOG_F32
+
+ // D.f = log2(S0.f).
+ void
+ Inst_VOP3__V_LOG_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, extData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::log2(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_RCP_F32::Inst_VOP3__V_RCP_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_rcp_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_RCP_F32
+
+ Inst_VOP3__V_RCP_F32::~Inst_VOP3__V_RCP_F32()
+ {
+ } // ~Inst_VOP3__V_RCP_F32
+
+ // D.f = 1.0 / S0.f.
+ void
+ Inst_VOP3__V_RCP_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, extData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = 1.0 / src[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_RCP_IFLAG_F32::Inst_VOP3__V_RCP_IFLAG_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_rcp_iflag_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_RCP_IFLAG_F32
+
+ Inst_VOP3__V_RCP_IFLAG_F32::~Inst_VOP3__V_RCP_IFLAG_F32()
+ {
+ } // ~Inst_VOP3__V_RCP_IFLAG_F32
+
+ // D.f = 1.0 / S0.f.
+ void
+ Inst_VOP3__V_RCP_IFLAG_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, extData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = 1.0 / src[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_RSQ_F32::Inst_VOP3__V_RSQ_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_rsq_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_RSQ_F32
+
+ Inst_VOP3__V_RSQ_F32::~Inst_VOP3__V_RSQ_F32()
+ {
+ } // ~Inst_VOP3__V_RSQ_F32
+
+ // D.f = 1.0 / sqrt(S0.f).
+ void
+ Inst_VOP3__V_RSQ_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, extData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = 1.0 / std::sqrt(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_RCP_F64::Inst_VOP3__V_RCP_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_rcp_f64", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_RCP_F64
+
+ Inst_VOP3__V_RCP_F64::~Inst_VOP3__V_RCP_F64()
+ {
+ } // ~Inst_VOP3__V_RCP_F64
+
+ // D.d = 1.0 / S0.d.
+ void
+ Inst_VOP3__V_RCP_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, extData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::fpclassify(src[lane]) == FP_ZERO) {
+ vdst[lane] = +INFINITY;
+ } else if (std::isnan(src[lane])) {
+ vdst[lane] = NAN;
+ } else if (std::isinf(src[lane])) {
+ if (std::signbit(src[lane])) {
+ vdst[lane] = -0.0;
+ } else {
+ vdst[lane] = 0.0;
+ }
+ } else {
+ vdst[lane] = 1.0 / src[lane];
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_RSQ_F64::Inst_VOP3__V_RSQ_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_rsq_f64", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_RSQ_F64
+
+ Inst_VOP3__V_RSQ_F64::~Inst_VOP3__V_RSQ_F64()
+ {
+ } // ~Inst_VOP3__V_RSQ_F64
+
+ // D.d = 1.0 / sqrt(S0.d).
+ void
+ Inst_VOP3__V_RSQ_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, extData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::fpclassify(src[lane]) == FP_ZERO) {
+ vdst[lane] = +INFINITY;
+ } else if (std::isnan(src[lane])) {
+ vdst[lane] = NAN;
+ } else if (std::isinf(src[lane]) && !std::signbit(src[lane])) {
+ vdst[lane] = 0.0;
+ } else if (std::signbit(src[lane])) {
+ vdst[lane] = NAN;
+ } else {
+ vdst[lane] = 1.0 / std::sqrt(src[lane]);
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_SQRT_F32::Inst_VOP3__V_SQRT_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_sqrt_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_SQRT_F32
+
+ Inst_VOP3__V_SQRT_F32::~Inst_VOP3__V_SQRT_F32()
+ {
+ } // ~Inst_VOP3__V_SQRT_F32
+
+ // D.f = sqrt(S0.f).
+ void
+ Inst_VOP3__V_SQRT_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, extData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::sqrt(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_SQRT_F64::Inst_VOP3__V_SQRT_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_sqrt_f64", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_SQRT_F64
+
+ Inst_VOP3__V_SQRT_F64::~Inst_VOP3__V_SQRT_F64()
+ {
+ } // ~Inst_VOP3__V_SQRT_F64
+
+ // D.d = sqrt(S0.d).
+ void
+ Inst_VOP3__V_SQRT_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, extData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::sqrt(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_SIN_F32::Inst_VOP3__V_SIN_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_sin_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_SIN_F32
+
+ Inst_VOP3__V_SIN_F32::~Inst_VOP3__V_SIN_F32()
+ {
+ } // ~Inst_VOP3__V_SIN_F32
+
+ // D.f = sin(S0.f * 2 * PI).
+ void
+ Inst_VOP3__V_SIN_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, extData.SRC0);
+ ConstScalarOperandF32 pi(gpuDynInst, REG_PI);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+ pi.read();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::sin(src[lane] * 2 * pi.rawData());
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_COS_F32::Inst_VOP3__V_COS_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cos_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_COS_F32
+
+ Inst_VOP3__V_COS_F32::~Inst_VOP3__V_COS_F32()
+ {
+ } // ~Inst_VOP3__V_COS_F32
+
+ // D.f = cos(S0.f * 2 * PI).
+ void
+ Inst_VOP3__V_COS_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, extData.SRC0);
+ ConstScalarOperandF32 pi(gpuDynInst, REG_PI);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+ pi.read();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::cos(src[lane] * 2 * pi.rawData());
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_NOT_B32::Inst_VOP3__V_NOT_B32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_not_b32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_NOT_B32
+
+ Inst_VOP3__V_NOT_B32::~Inst_VOP3__V_NOT_B32()
+ {
+ } // ~Inst_VOP3__V_NOT_B32
+
+ // D.u = ~S0.u.
+ // Input and output modifiers not supported.
+ void
+ Inst_VOP3__V_NOT_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src(gpuDynInst, extData.SRC0);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = ~src[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_BFREV_B32::Inst_VOP3__V_BFREV_B32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_bfrev_b32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_BFREV_B32
+
+ Inst_VOP3__V_BFREV_B32::~Inst_VOP3__V_BFREV_B32()
+ {
+ } // ~Inst_VOP3__V_BFREV_B32
+
+ // D.u[31:0] = S0.u[0:31], bitfield reverse.
+ // Input and output modifiers not supported.
+ void
+ Inst_VOP3__V_BFREV_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src(gpuDynInst, extData.SRC0);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = reverseBits(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_FFBH_U32::Inst_VOP3__V_FFBH_U32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_ffbh_u32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_FFBH_U32
+
+ Inst_VOP3__V_FFBH_U32::~Inst_VOP3__V_FFBH_U32()
+ {
+ } // ~Inst_VOP3__V_FFBH_U32
+
+ // D.u = position of first 1 in S0.u from MSB;
+ // D.u = 0xffffffff if S0.u == 0.
+ void
+ Inst_VOP3__V_FFBH_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src(gpuDynInst, extData.SRC0);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = findFirstOneMsb(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_FFBL_B32::Inst_VOP3__V_FFBL_B32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_ffbl_b32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_FFBL_B32
+
+ Inst_VOP3__V_FFBL_B32::~Inst_VOP3__V_FFBL_B32()
+ {
+ } // ~Inst_VOP3__V_FFBL_B32
+
+ // D.u = position of first 1 in S0.u from LSB;
+ // D.u = 0xffffffff if S0.u == 0.
+ void
+ Inst_VOP3__V_FFBL_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src(gpuDynInst, extData.SRC0);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = findFirstOne(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_FFBH_I32::Inst_VOP3__V_FFBH_I32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_ffbh_i32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_FFBH_I32
+
+ Inst_VOP3__V_FFBH_I32::~Inst_VOP3__V_FFBH_I32()
+ {
+ } // ~Inst_VOP3__V_FFBH_I32
+
+ // D.u = position of first bit different from sign bit in S0.i from MSB;
+ // D.u = 0xffffffff if S0.i == 0 or S0.i == 0xffffffff.
+ void
+ Inst_VOP3__V_FFBH_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src(gpuDynInst, extData.SRC0);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = firstOppositeSignBit(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_FREXP_EXP_I32_F64::Inst_VOP3__V_FREXP_EXP_I32_F64(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_frexp_exp_i32_f64", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_FREXP_EXP_I32_F64
+
+ Inst_VOP3__V_FREXP_EXP_I32_F64::~Inst_VOP3__V_FREXP_EXP_I32_F64()
+ {
+ } // ~Inst_VOP3__V_FREXP_EXP_I32_F64
+
+ // See V_FREXP_EXP_I32_F32.
+ void
+ Inst_VOP3__V_FREXP_EXP_I32_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, extData.SRC0);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::isinf(src[lane]) || std::isnan(src[lane])) {
+ vdst[lane] = 0;
+ } else {
+ VecElemI32 exp(0);
+ std::frexp(src[lane], &exp);
+ vdst[lane] = exp;
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_FREXP_MANT_F64::Inst_VOP3__V_FREXP_MANT_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_frexp_mant_f64", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_FREXP_MANT_F64
+
+ Inst_VOP3__V_FREXP_MANT_F64::~Inst_VOP3__V_FREXP_MANT_F64()
+ {
+ } // ~Inst_VOP3__V_FREXP_MANT_F64
+
+ void
+ Inst_VOP3__V_FREXP_MANT_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, extData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ VecElemI32 exp(0);
+ vdst[lane] = std::frexp(src[lane], &exp);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_FRACT_F64::Inst_VOP3__V_FRACT_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_fract_f64", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_FRACT_F64
+
+ Inst_VOP3__V_FRACT_F64::~Inst_VOP3__V_FRACT_F64()
+ {
+ } // ~Inst_VOP3__V_FRACT_F64
+
+ void
+ Inst_VOP3__V_FRACT_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src(gpuDynInst, extData.SRC0);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ VecElemF32 int_part(0.0);
+ vdst[lane] = std::modf(src[lane], &int_part);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_FREXP_EXP_I32_F32::Inst_VOP3__V_FREXP_EXP_I32_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_frexp_exp_i32_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_FREXP_EXP_I32_F32
+
+ Inst_VOP3__V_FREXP_EXP_I32_F32::~Inst_VOP3__V_FREXP_EXP_I32_F32()
+ {
+ } // ~Inst_VOP3__V_FREXP_EXP_I32_F32
+
+ // frexp(S0.f, Exponenti(S0.f))
+ // if (S0.f == INF || S0.f == NAN) then D.i = 0;
+ // else D.i = Exponent(S0.f)
+ void
+ Inst_VOP3__V_FREXP_EXP_I32_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, extData.SRC0);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::isinf(src[lane])|| std::isnan(src[lane])) {
+ vdst[lane] = 0;
+ } else {
+ VecElemI32 exp(0);
+ std::frexp(src[lane], &exp);
+ vdst[lane] = exp;
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_FREXP_MANT_F32::Inst_VOP3__V_FREXP_MANT_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_frexp_mant_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_FREXP_MANT_F32
+
+ Inst_VOP3__V_FREXP_MANT_F32::~Inst_VOP3__V_FREXP_MANT_F32()
+ {
+ } // ~Inst_VOP3__V_FREXP_MANT_F32
+
+ // if (S0.f == INF || S0.f == NAN) then D.f = S0.f;
+ // else D.f = Mantissa(S0.f).
+ void
+ Inst_VOP3__V_FREXP_MANT_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, extData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::isinf(src[lane]) || std::isnan(src[lane])) {
+ vdst[lane] = src[lane];
+ } else {
+ VecElemI32 exp(0);
+ vdst[lane] = std::frexp(src[lane], &exp);
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_CLREXCP::Inst_VOP3__V_CLREXCP(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_clrexcp", false)
+ {
+ } // Inst_VOP3__V_CLREXCP
+
+ Inst_VOP3__V_CLREXCP::~Inst_VOP3__V_CLREXCP()
+ {
+ } // ~Inst_VOP3__V_CLREXCP
+
+ void
+ Inst_VOP3__V_CLREXCP::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CVT_F16_U16::Inst_VOP3__V_CVT_F16_U16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_f16_u16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CVT_F16_U16
+
+ Inst_VOP3__V_CVT_F16_U16::~Inst_VOP3__V_CVT_F16_U16()
+ {
+ } // ~Inst_VOP3__V_CVT_F16_U16
+
+ // D.f16 = uint16_to_flt16(S.u16).
+ void
+ Inst_VOP3__V_CVT_F16_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CVT_F16_I16::Inst_VOP3__V_CVT_F16_I16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_f16_i16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CVT_F16_I16
+
+ Inst_VOP3__V_CVT_F16_I16::~Inst_VOP3__V_CVT_F16_I16()
+ {
+ } // ~Inst_VOP3__V_CVT_F16_I16
+
+ // D.f16 = int16_to_flt16(S.i16).
+ void
+ Inst_VOP3__V_CVT_F16_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CVT_U16_F16::Inst_VOP3__V_CVT_U16_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_u16_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CVT_U16_F16
+
+ Inst_VOP3__V_CVT_U16_F16::~Inst_VOP3__V_CVT_U16_F16()
+ {
+ } // ~Inst_VOP3__V_CVT_U16_F16
+
+ // D.u16 = flt16_to_uint16(S.f16).
+ void
+ Inst_VOP3__V_CVT_U16_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CVT_I16_F16::Inst_VOP3__V_CVT_I16_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_i16_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CVT_I16_F16
+
+ Inst_VOP3__V_CVT_I16_F16::~Inst_VOP3__V_CVT_I16_F16()
+ {
+ } // ~Inst_VOP3__V_CVT_I16_F16
+
+ // D.i16 = flt16_to_int16(S.f16).
+ void
+ Inst_VOP3__V_CVT_I16_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_RCP_F16::Inst_VOP3__V_RCP_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_rcp_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_RCP_F16
+
+ Inst_VOP3__V_RCP_F16::~Inst_VOP3__V_RCP_F16()
+ {
+ } // ~Inst_VOP3__V_RCP_F16
+
+ // if (S0.f16 == 1.0f)
+ // D.f16 = 1.0f;
+ // else
+ // D.f16 = 1 / S0.f16.
+ void
+ Inst_VOP3__V_RCP_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_SQRT_F16::Inst_VOP3__V_SQRT_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_sqrt_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_SQRT_F16
+
+ Inst_VOP3__V_SQRT_F16::~Inst_VOP3__V_SQRT_F16()
+ {
+ } // ~Inst_VOP3__V_SQRT_F16
+
+ // if (S0.f16 == 1.0f)
+ // D.f16 = 1.0f;
+ // else
+ // D.f16 = sqrt(S0.f16).
+ void
+ Inst_VOP3__V_SQRT_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_RSQ_F16::Inst_VOP3__V_RSQ_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_rsq_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_RSQ_F16
+
+ Inst_VOP3__V_RSQ_F16::~Inst_VOP3__V_RSQ_F16()
+ {
+ } // ~Inst_VOP3__V_RSQ_F16
+
+ // if (S0.f16 == 1.0f)
+ // D.f16 = 1.0f;
+ // else
+ // D.f16 = 1 / sqrt(S0.f16).
+ void
+ Inst_VOP3__V_RSQ_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_LOG_F16::Inst_VOP3__V_LOG_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_log_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_LOG_F16
+
+ Inst_VOP3__V_LOG_F16::~Inst_VOP3__V_LOG_F16()
+ {
+ } // ~Inst_VOP3__V_LOG_F16
+
+ // if (S0.f16 == 1.0f)
+ // D.f16 = 0.0f;
+ // else
+ // D.f16 = log2(S0.f16).
+ void
+ Inst_VOP3__V_LOG_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_EXP_F16::Inst_VOP3__V_EXP_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_exp_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_EXP_F16
+
+ Inst_VOP3__V_EXP_F16::~Inst_VOP3__V_EXP_F16()
+ {
+ } // ~Inst_VOP3__V_EXP_F16
+
+ // if (S0.f16 == 0.0f)
+ // D.f16 = 1.0f;
+ // else
+ // D.f16 = pow(2.0, S0.f16).
+ void
+ Inst_VOP3__V_EXP_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_FREXP_MANT_F16::Inst_VOP3__V_FREXP_MANT_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_frexp_mant_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_FREXP_MANT_F16
+
+ Inst_VOP3__V_FREXP_MANT_F16::~Inst_VOP3__V_FREXP_MANT_F16()
+ {
+ } // ~Inst_VOP3__V_FREXP_MANT_F16
+
+ // if (S0.f16 == +-INF || S0.f16 == NAN)
+ // D.f16 = S0.f16;
+ // else
+ // D.f16 = mantissa(S0.f16).
+ void
+ Inst_VOP3__V_FREXP_MANT_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_FREXP_EXP_I16_F16::Inst_VOP3__V_FREXP_EXP_I16_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_frexp_exp_i16_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_FREXP_EXP_I16_F16
+
+ Inst_VOP3__V_FREXP_EXP_I16_F16::~Inst_VOP3__V_FREXP_EXP_I16_F16()
+ {
+ } // ~Inst_VOP3__V_FREXP_EXP_I16_F16
+
+ void
+ Inst_VOP3__V_FREXP_EXP_I16_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_FLOOR_F16::Inst_VOP3__V_FLOOR_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_floor_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_FLOOR_F16
+
+ Inst_VOP3__V_FLOOR_F16::~Inst_VOP3__V_FLOOR_F16()
+ {
+ } // ~Inst_VOP3__V_FLOOR_F16
+
+ // D.f16 = floor(S0.f16);
+ void
+ Inst_VOP3__V_FLOOR_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CEIL_F16::Inst_VOP3__V_CEIL_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_ceil_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_CEIL_F16
+
+ Inst_VOP3__V_CEIL_F16::~Inst_VOP3__V_CEIL_F16()
+ {
+ } // ~Inst_VOP3__V_CEIL_F16
+
+ // D.f16 = ceil(S0.f16);
+ void
+ Inst_VOP3__V_CEIL_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_TRUNC_F16::Inst_VOP3__V_TRUNC_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_trunc_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_TRUNC_F16
+
+ Inst_VOP3__V_TRUNC_F16::~Inst_VOP3__V_TRUNC_F16()
+ {
+ } // ~Inst_VOP3__V_TRUNC_F16
+
+ // D.f16 = trunc(S0.f16).
+ void
+ Inst_VOP3__V_TRUNC_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_RNDNE_F16::Inst_VOP3__V_RNDNE_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_rndne_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_RNDNE_F16
+
+ Inst_VOP3__V_RNDNE_F16::~Inst_VOP3__V_RNDNE_F16()
+ {
+ } // ~Inst_VOP3__V_RNDNE_F16
+
+ // D.f16 = roundNearestEven(S0.f16);
+ void
+ Inst_VOP3__V_RNDNE_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_FRACT_F16::Inst_VOP3__V_FRACT_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_fract_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_FRACT_F16
+
+ Inst_VOP3__V_FRACT_F16::~Inst_VOP3__V_FRACT_F16()
+ {
+ } // ~Inst_VOP3__V_FRACT_F16
+
+ // D.f16 = S0.f16 + -floor(S0.f16).
+ void
+ Inst_VOP3__V_FRACT_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_SIN_F16::Inst_VOP3__V_SIN_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_sin_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_SIN_F16
+
+ Inst_VOP3__V_SIN_F16::~Inst_VOP3__V_SIN_F16()
+ {
+ } // ~Inst_VOP3__V_SIN_F16
+
+ // D.f16 = sin(S0.f16 * 2 * PI).
+ void
+ Inst_VOP3__V_SIN_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_COS_F16::Inst_VOP3__V_COS_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cos_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_COS_F16
+
+ Inst_VOP3__V_COS_F16::~Inst_VOP3__V_COS_F16()
+ {
+ } // ~Inst_VOP3__V_COS_F16
+
+ // D.f16 = cos(S0.f16 * 2 * PI).
+ void
+ Inst_VOP3__V_COS_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_EXP_LEGACY_F32::Inst_VOP3__V_EXP_LEGACY_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_exp_legacy_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_EXP_LEGACY_F32
+
+ Inst_VOP3__V_EXP_LEGACY_F32::~Inst_VOP3__V_EXP_LEGACY_F32()
+ {
+ } // ~Inst_VOP3__V_EXP_LEGACY_F32
+
+ // D.f = pow(2.0, S0.f)
+ void
+ Inst_VOP3__V_EXP_LEGACY_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, extData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::pow(2.0, src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_LOG_LEGACY_F32::Inst_VOP3__V_LOG_LEGACY_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_log_legacy_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_LOG_LEGACY_F32
+
+ Inst_VOP3__V_LOG_LEGACY_F32::~Inst_VOP3__V_LOG_LEGACY_F32()
+ {
+ } // ~Inst_VOP3__V_LOG_LEGACY_F32
+
+ // D.f = log2(S0.f).
+ void
+ Inst_VOP3__V_LOG_LEGACY_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src(gpuDynInst, extData.SRC0);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::log2(src[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MAD_LEGACY_F32::Inst_VOP3__V_MAD_LEGACY_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mad_legacy_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ setFlag(MAD);
+ } // Inst_VOP3__V_MAD_LEGACY_F32
+
+ Inst_VOP3__V_MAD_LEGACY_F32::~Inst_VOP3__V_MAD_LEGACY_F32()
+ {
+ } // ~Inst_VOP3__V_MAD_LEGACY_F32
+
+ // D.f = S0.f * S1.f + S2.f
+ void
+ Inst_VOP3__V_MAD_LEGACY_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandF32 src2(gpuDynInst, extData.SRC2);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (instData.ABS & 0x4) {
+ src2.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ if (extData.NEG & 0x4) {
+ src2.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::fma(src0[lane], src1[lane], src2[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MAD_F32::Inst_VOP3__V_MAD_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mad_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ setFlag(MAD);
+ } // Inst_VOP3__V_MAD_F32
+
+ Inst_VOP3__V_MAD_F32::~Inst_VOP3__V_MAD_F32()
+ {
+ } // ~Inst_VOP3__V_MAD_F32
+
+ // D.f = S0.f * S1.f + S2.f.
+ void
+ Inst_VOP3__V_MAD_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandF32 src2(gpuDynInst, extData.SRC2);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (instData.ABS & 0x4) {
+ src2.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ if (extData.NEG & 0x4) {
+ src2.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::fma(src0[lane], src1[lane], src2[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MAD_I32_I24::Inst_VOP3__V_MAD_I32_I24(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mad_i32_i24", false)
+ {
+ setFlag(ALU);
+ setFlag(MAD);
+ } // Inst_VOP3__V_MAD_I32_I24
+
+ Inst_VOP3__V_MAD_I32_I24::~Inst_VOP3__V_MAD_I32_I24()
+ {
+ } // ~Inst_VOP3__V_MAD_I32_I24
+
+ // D.i = S0.i[23:0] * S1.i[23:0] + S2.i.
+ void
+ Inst_VOP3__V_MAD_I32_I24::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandI32 src2(gpuDynInst, extData.SRC2);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = bits(src0[lane], 23, 0) * bits(src1[lane], 23, 0)
+ + src2[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MAD_U32_U24::Inst_VOP3__V_MAD_U32_U24(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mad_u32_u24", false)
+ {
+ setFlag(ALU);
+ setFlag(MAD);
+ } // Inst_VOP3__V_MAD_U32_U24
+
+ Inst_VOP3__V_MAD_U32_U24::~Inst_VOP3__V_MAD_U32_U24()
+ {
+ } // ~Inst_VOP3__V_MAD_U32_U24
+
+ // D.u = S0.u[23:0] * S1.u[23:0] + S2.u.
+ void
+ Inst_VOP3__V_MAD_U32_U24::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = bits(src0[lane], 23, 0) * bits(src1[lane], 23, 0)
+ + src2[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_CUBEID_F32::Inst_VOP3__V_CUBEID_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cubeid_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CUBEID_F32
+
+ Inst_VOP3__V_CUBEID_F32::~Inst_VOP3__V_CUBEID_F32()
+ {
+ } // ~Inst_VOP3__V_CUBEID_F32
+
+ void
+ Inst_VOP3__V_CUBEID_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CUBESC_F32::Inst_VOP3__V_CUBESC_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cubesc_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CUBESC_F32
+
+ Inst_VOP3__V_CUBESC_F32::~Inst_VOP3__V_CUBESC_F32()
+ {
+ } // ~Inst_VOP3__V_CUBESC_F32
+
+ void
+ Inst_VOP3__V_CUBESC_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CUBETC_F32::Inst_VOP3__V_CUBETC_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cubetc_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CUBETC_F32
+
+ Inst_VOP3__V_CUBETC_F32::~Inst_VOP3__V_CUBETC_F32()
+ {
+ } // ~Inst_VOP3__V_CUBETC_F32
+
+ void
+ Inst_VOP3__V_CUBETC_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CUBEMA_F32::Inst_VOP3__V_CUBEMA_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cubema_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CUBEMA_F32
+
+ Inst_VOP3__V_CUBEMA_F32::~Inst_VOP3__V_CUBEMA_F32()
+ {
+ } // ~Inst_VOP3__V_CUBEMA_F32
+
+ void
+ Inst_VOP3__V_CUBEMA_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_BFE_U32::Inst_VOP3__V_BFE_U32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_bfe_u32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_BFE_U32
+
+ Inst_VOP3__V_BFE_U32::~Inst_VOP3__V_BFE_U32()
+ {
+ } // ~Inst_VOP3__V_BFE_U32
+
+ // D.u = (S0.u >> S1.u[4:0]) & ((1 << S2.u[4:0]) - 1).
+ // Bitfield extract with S0 = data, S1 = field_offset, S2 = field_width.
+ void
+ Inst_VOP3__V_BFE_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (src0[lane] >> bits(src1[lane], 4, 0))
+ & ((1 << bits(src2[lane], 4, 0)) - 1);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_BFE_I32::Inst_VOP3__V_BFE_I32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_bfe_i32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_BFE_I32
+
+ Inst_VOP3__V_BFE_I32::~Inst_VOP3__V_BFE_I32()
+ {
+ } // ~Inst_VOP3__V_BFE_I32
+
+ // D.i = (S0.i >> S1.u[4:0]) & ((1 << S2.u[4:0]) - 1).
+ // Bitfield extract with S0 = data, S1 = field_offset, S2 = field_width.
+ void
+ Inst_VOP3__V_BFE_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (src0[lane] >> bits(src1[lane], 4, 0))
+ & ((1 << bits(src2[lane], 4, 0)) - 1);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_BFI_B32::Inst_VOP3__V_BFI_B32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_bfi_b32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_BFI_B32
+
+ Inst_VOP3__V_BFI_B32::~Inst_VOP3__V_BFI_B32()
+ {
+ } // ~Inst_VOP3__V_BFI_B32
+
+ // D.u = (S0.u & S1.u) | (~S0.u & S2.u); bitfield insert.
+ void
+ Inst_VOP3__V_BFI_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (src0[lane] & src1[lane]) | (~src0[lane]
+ & src2[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_FMA_F32::Inst_VOP3__V_FMA_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_fma_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ setFlag(FMA);
+ } // Inst_VOP3__V_FMA_F32
+
+ Inst_VOP3__V_FMA_F32::~Inst_VOP3__V_FMA_F32()
+ {
+ } // ~Inst_VOP3__V_FMA_F32
+
+ // D.f = S0.f * S1.f + S2.f.
+ void
+ Inst_VOP3__V_FMA_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandF32 src2(gpuDynInst, extData.SRC2);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (instData.ABS & 0x4) {
+ src2.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ if (extData.NEG & 0x4) {
+ src2.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::fma(src0[lane], src1[lane], src2[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_FMA_F64::Inst_VOP3__V_FMA_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_fma_f64", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ setFlag(FMA);
+ } // Inst_VOP3__V_FMA_F64
+
+ Inst_VOP3__V_FMA_F64::~Inst_VOP3__V_FMA_F64()
+ {
+ } // ~Inst_VOP3__V_FMA_F64
+
+ // D.d = S0.d * S1.d + S2.d.
+ void
+ Inst_VOP3__V_FMA_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandF64 src2(gpuDynInst, extData.SRC2);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (instData.ABS & 0x4) {
+ src2.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ if (extData.NEG & 0x4) {
+ src2.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::fma(src0[lane], src1[lane], src2[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_LERP_U8::Inst_VOP3__V_LERP_U8(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_lerp_u8", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_LERP_U8
+
+ Inst_VOP3__V_LERP_U8::~Inst_VOP3__V_LERP_U8()
+ {
+ } // ~Inst_VOP3__V_LERP_U8
+
+ // D.u = ((S0.u[31:24] + S1.u[31:24] + S2.u[24]) >> 1) << 24
+ // D.u += ((S0.u[23:16] + S1.u[23:16] + S2.u[16]) >> 1) << 16;
+ // D.u += ((S0.u[15:8] + S1.u[15:8] + S2.u[8]) >> 1) << 8;
+ // D.u += ((S0.u[7:0] + S1.u[7:0] + S2.u[0]) >> 1).
+ void
+ Inst_VOP3__V_LERP_U8::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = ((bits(src0[lane], 31, 24)
+ + bits(src1[lane], 31, 24) + bits(src2[lane], 24)) >> 1)
+ << 24;
+ vdst[lane] += ((bits(src0[lane], 23, 16)
+ + bits(src1[lane], 23, 16) + bits(src2[lane], 16)) >> 1)
+ << 16;
+ vdst[lane] += ((bits(src0[lane], 15, 8)
+ + bits(src1[lane], 15, 8) + bits(src2[lane], 8)) >> 1)
+ << 8;
+ vdst[lane] += ((bits(src0[lane], 7, 0) + bits(src1[lane], 7, 0)
+ + bits(src2[lane], 0)) >> 1);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_ALIGNBIT_B32::Inst_VOP3__V_ALIGNBIT_B32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_alignbit_b32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_ALIGNBIT_B32
+
+ Inst_VOP3__V_ALIGNBIT_B32::~Inst_VOP3__V_ALIGNBIT_B32()
+ {
+ } // ~Inst_VOP3__V_ALIGNBIT_B32
+
+ // D.u = ({S0, S1} >> S2.u[4:0]) & 0xffffffff.
+ void
+ Inst_VOP3__V_ALIGNBIT_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ VecElemU64 src_0_1 = (((VecElemU64)src0[lane] << 32)
+ | (VecElemU64)src1[lane]);
+ vdst[lane] = (VecElemU32)((src_0_1
+ >> (VecElemU64)bits(src2[lane], 4, 0)) & 0xffffffff);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_ALIGNBYTE_B32::Inst_VOP3__V_ALIGNBYTE_B32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_alignbyte_b32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_ALIGNBYTE_B32
+
+ Inst_VOP3__V_ALIGNBYTE_B32::~Inst_VOP3__V_ALIGNBYTE_B32()
+ {
+ } // ~Inst_VOP3__V_ALIGNBYTE_B32
+
+ // D.u = ({S0, S1} >> (8 * S2.u[4:0])) & 0xffffffff.
+ void
+ Inst_VOP3__V_ALIGNBYTE_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ VecElemU64 src_0_1 = (((VecElemU64)src0[lane] << 32)
+ | (VecElemU64)src1[lane]);
+ vdst[lane] = (VecElemU32)((src_0_1
+ >> (8ULL * (VecElemU64)bits(src2[lane], 4, 0)))
+ & 0xffffffff);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MIN3_F32::Inst_VOP3__V_MIN3_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_min3_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_MIN3_F32
+
+ Inst_VOP3__V_MIN3_F32::~Inst_VOP3__V_MIN3_F32()
+ {
+ } // ~Inst_VOP3__V_MIN3_F32
+
+ // D.f = min(S0.f, S1.f, S2.f).
+ void
+ Inst_VOP3__V_MIN3_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandF32 src2(gpuDynInst, extData.SRC2);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (instData.ABS & 0x4) {
+ src2.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ if (extData.NEG & 0x4) {
+ src2.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ VecElemF32 min_0_1 = std::fmin(src0[lane], src1[lane]);
+ vdst[lane] = std::fmin(min_0_1, src2[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MIN3_I32::Inst_VOP3__V_MIN3_I32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_min3_i32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MIN3_I32
+
+ Inst_VOP3__V_MIN3_I32::~Inst_VOP3__V_MIN3_I32()
+ {
+ } // ~Inst_VOP3__V_MIN3_I32
+
+ // D.i = min(S0.i, S1.i, S2.i).
+ void
+ Inst_VOP3__V_MIN3_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandI32 src2(gpuDynInst, extData.SRC2);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ VecElemI32 min_0_1 = std::min(src0[lane], src1[lane]);
+ vdst[lane] = std::min(min_0_1, src2[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MIN3_U32::Inst_VOP3__V_MIN3_U32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_min3_u32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MIN3_U32
+
+ Inst_VOP3__V_MIN3_U32::~Inst_VOP3__V_MIN3_U32()
+ {
+ } // ~Inst_VOP3__V_MIN3_U32
+
+ // D.u = min(S0.u, S1.u, S2.u).
+ void
+ Inst_VOP3__V_MIN3_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ VecElemU32 min_0_1 = std::min(src0[lane], src1[lane]);
+ vdst[lane] = std::min(min_0_1, src2[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MAX3_F32::Inst_VOP3__V_MAX3_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_max3_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_MAX3_F32
+
+ Inst_VOP3__V_MAX3_F32::~Inst_VOP3__V_MAX3_F32()
+ {
+ } // ~Inst_VOP3__V_MAX3_F32
+
+ // D.f = max(S0.f, S1.f, S2.f).
+ void
+ Inst_VOP3__V_MAX3_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandF32 src2(gpuDynInst, extData.SRC2);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (instData.ABS & 0x4) {
+ src2.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ if (extData.NEG & 0x4) {
+ src2.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ VecElemF32 max_0_1 = std::fmax(src0[lane], src1[lane]);
+ vdst[lane] = std::fmax(max_0_1, src2[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MAX3_I32::Inst_VOP3__V_MAX3_I32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_max3_i32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MAX3_I32
+
+ Inst_VOP3__V_MAX3_I32::~Inst_VOP3__V_MAX3_I32()
+ {
+ } // ~Inst_VOP3__V_MAX3_I32
+
+ // D.i = max(S0.i, S1.i, S2.i).
+ void
+ Inst_VOP3__V_MAX3_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandI32 src2(gpuDynInst, extData.SRC2);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ VecElemI32 max_0_1 = std::max(src0[lane], src1[lane]);
+ vdst[lane] = std::max(max_0_1, src2[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MAX3_U32::Inst_VOP3__V_MAX3_U32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_max3_u32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MAX3_U32
+
+ Inst_VOP3__V_MAX3_U32::~Inst_VOP3__V_MAX3_U32()
+ {
+ } // ~Inst_VOP3__V_MAX3_U32
+
+ // D.u = max(S0.u, S1.u, S2.u).
+ void
+ Inst_VOP3__V_MAX3_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ VecElemU32 max_0_1 = std::max(src0[lane], src1[lane]);
+ vdst[lane] = std::max(max_0_1, src2[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MED3_F32::Inst_VOP3__V_MED3_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_med3_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_MED3_F32
+
+ Inst_VOP3__V_MED3_F32::~Inst_VOP3__V_MED3_F32()
+ {
+ } // ~Inst_VOP3__V_MED3_F32
+
+ // D.f = median(S0.f, S1.f, S2.f).
+ void
+ Inst_VOP3__V_MED3_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandF32 src2(gpuDynInst, extData.SRC2);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (instData.ABS & 0x4) {
+ src2.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ if (extData.NEG & 0x4) {
+ src2.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = median(src0[lane], src1[lane], src2[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MED3_I32::Inst_VOP3__V_MED3_I32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_med3_i32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MED3_I32
+
+ Inst_VOP3__V_MED3_I32::~Inst_VOP3__V_MED3_I32()
+ {
+ } // ~Inst_VOP3__V_MED3_I32
+
+ // D.i = median(S0.i, S1.i, S2.i).
+ void
+ Inst_VOP3__V_MED3_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandI32 src2(gpuDynInst, extData.SRC2);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = median(src0[lane], src1[lane], src2[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MED3_U32::Inst_VOP3__V_MED3_U32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_med3_u32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MED3_U32
+
+ Inst_VOP3__V_MED3_U32::~Inst_VOP3__V_MED3_U32()
+ {
+ } // ~Inst_VOP3__V_MED3_U32
+
+ // D.u = median(S0.u, S1.u, S2.u).
+ void
+ Inst_VOP3__V_MED3_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = median(src0[lane], src1[lane], src2[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_SAD_U8::Inst_VOP3__V_SAD_U8(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_sad_u8", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_SAD_U8
+
+ Inst_VOP3__V_SAD_U8::~Inst_VOP3__V_SAD_U8()
+ {
+ } // ~Inst_VOP3__V_SAD_U8
+
+ // D.u = abs(S0.i[31:24] - S1.i[31:24]) + abs(S0.i[23:16] - S1.i[23:16]) +
+ // abs(S0.i[15:8] - S1.i[15:8]) + abs(S0.i[7:0] - S1.i[7:0]) + S2.u.
+ // Sum of absolute differences with accumulation, overflow into upper bits
+ // is allowed.
+ void
+ Inst_VOP3__V_SAD_U8::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::abs(bits(src0[lane], 31, 24)
+ - bits(src1[lane], 31, 24))
+ + std::abs(bits(src0[lane], 23, 16)
+ - bits(src1[lane], 23, 16))
+ + std::abs(bits(src0[lane], 15, 8)
+ - bits(src1[lane], 15, 8))
+ + std::abs(bits(src0[lane], 7, 0)
+ - bits(src1[lane], 7, 0)) + src2[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_SAD_HI_U8::Inst_VOP3__V_SAD_HI_U8(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_sad_hi_u8", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_SAD_HI_U8
+
+ Inst_VOP3__V_SAD_HI_U8::~Inst_VOP3__V_SAD_HI_U8()
+ {
+ } // ~Inst_VOP3__V_SAD_HI_U8
+
+ // D.u = (SAD_U8(S0, S1, 0) << 16) + S2.u.
+ // Sum of absolute differences with accumulation, overflow is lost.
+ void
+ Inst_VOP3__V_SAD_HI_U8::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (((bits(src0[lane], 31, 24)
+ - bits(src1[lane], 31, 24)) + (bits(src0[lane], 23, 16)
+ - bits(src1[lane], 23, 16)) + (bits(src0[lane], 15, 8)
+ - bits(src1[lane], 15, 8)) + (bits(src0[lane], 7, 0)
+ - bits(src1[lane], 7, 0))) << 16) + src2[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_SAD_U16::Inst_VOP3__V_SAD_U16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_sad_u16", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_SAD_U16
+
+ Inst_VOP3__V_SAD_U16::~Inst_VOP3__V_SAD_U16()
+ {
+ } // ~Inst_VOP3__V_SAD_U16
+
+ // D.u = abs(S0.i[31:16] - S1.i[31:16]) + abs(S0.i[15:0] - S1.i[15:0])
+ // + S2.u.
+ // Word SAD with accumulation.
+ void
+ Inst_VOP3__V_SAD_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::abs(bits(src0[lane], 31, 16)
+ - bits(src1[lane], 31, 16))
+ + std::abs(bits(src0[lane], 15, 0)
+ - bits(src1[lane], 15, 0)) + src2[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_SAD_U32::Inst_VOP3__V_SAD_U32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_sad_u32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_SAD_U32
+
+ Inst_VOP3__V_SAD_U32::~Inst_VOP3__V_SAD_U32()
+ {
+ } // ~Inst_VOP3__V_SAD_U32
+
+ // D.u = abs(S0.i - S1.i) + S2.u.
+ // Dword SAD with accumulation.
+ void
+ Inst_VOP3__V_SAD_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::abs(src0[lane] - src1[lane]) + src2[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_CVT_PK_U8_F32::Inst_VOP3__V_CVT_PK_U8_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_pk_u8_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CVT_PK_U8_F32
+
+ Inst_VOP3__V_CVT_PK_U8_F32::~Inst_VOP3__V_CVT_PK_U8_F32()
+ {
+ } // ~Inst_VOP3__V_CVT_PK_U8_F32
+
+ // D.u = ((flt32_to_uint8(S0.f) & 0xff) << (8 * S1.u[1:0]))
+ // | (S2.u & ~(0xff << (8 * S1.u[1:0]))).
+ // Convert floating point value S0 to 8-bit unsigned integer and pack the
+ // result into byte S1 of dword S2.
+ void
+ Inst_VOP3__V_CVT_PK_U8_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = (((VecElemU8)src0[lane] & 0xff)
+ << (8 * bits(src1[lane], 1, 0)))
+ | (src2[lane] & ~(0xff << (8 * bits(src1[lane], 1, 0))));
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_DIV_FIXUP_F32::Inst_VOP3__V_DIV_FIXUP_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_div_fixup_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_DIV_FIXUP_F32
+
+ Inst_VOP3__V_DIV_FIXUP_F32::~Inst_VOP3__V_DIV_FIXUP_F32()
+ {
+ } // ~Inst_VOP3__V_DIV_FIXUP_F32
+
+ // D.f = Divide fixup and flags -- s0.f = Quotient, s1.f = Denominator,
+ // s2.f = Numerator.
+ void
+ Inst_VOP3__V_DIV_FIXUP_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ // Could not parse sq_uc.arch desc field
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_DIV_FIXUP_F64::Inst_VOP3__V_DIV_FIXUP_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_div_fixup_f64", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_DIV_FIXUP_F64
+
+ Inst_VOP3__V_DIV_FIXUP_F64::~Inst_VOP3__V_DIV_FIXUP_F64()
+ {
+ } // ~Inst_VOP3__V_DIV_FIXUP_F64
+
+ // D.d = Divide fixup and flags -- s0.d = Quotient, s1.d = Denominator,
+ // s2.d = Numerator.
+ void
+ Inst_VOP3__V_DIV_FIXUP_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandF64 src2(gpuDynInst, extData.SRC2);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (instData.ABS & 0x4) {
+ src2.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ if (extData.NEG & 0x4) {
+ src2.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::fpclassify(src1[lane]) == FP_ZERO) {
+ if (std::signbit(src1[lane])) {
+ vdst[lane] = -INFINITY;
+ } else {
+ vdst[lane] = +INFINITY;
+ }
+ } else if (std::isnan(src2[lane]) || std::isnan(src1[lane])) {
+ vdst[lane] = NAN;
+ } else if (std::isinf(src1[lane])) {
+ if (std::signbit(src1[lane])) {
+ vdst[lane] = -INFINITY;
+ } else {
+ vdst[lane] = +INFINITY;
+ }
+ } else {
+ vdst[lane] = src2[lane] / src1[lane];
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_DIV_SCALE_F32::Inst_VOP3__V_DIV_SCALE_F32(
+ InFmt_VOP3_SDST_ENC *iFmt)
+ : Inst_VOP3_SDST_ENC(iFmt, "v_div_scale_f32")
+ {
+ setFlag(ALU);
+ setFlag(WritesVCC);
+ setFlag(F32);
+ } // Inst_VOP3__V_DIV_SCALE_F32
+
+ Inst_VOP3__V_DIV_SCALE_F32::~Inst_VOP3__V_DIV_SCALE_F32()
+ {
+ } // ~Inst_VOP3__V_DIV_SCALE_F32
+
+ // {vcc,D.f} = Divide preop and flags -- s0.f = Quotient, s1.f =
+ // Denominator, s2.f = Numerator -- s0 must equal s1 or s2. Given a
+ // numerator and denominator, this opcode will appropriately scale inputs
+ // for division to avoid subnormal terms during Newton-Raphson correction
+ // algorithm. This opcode producses a VCC flag for post-scale of quotient.
+ void
+ Inst_VOP3__V_DIV_SCALE_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_DIV_SCALE_F64::Inst_VOP3__V_DIV_SCALE_F64(
+ InFmt_VOP3_SDST_ENC *iFmt)
+ : Inst_VOP3_SDST_ENC(iFmt, "v_div_scale_f64")
+ {
+ setFlag(ALU);
+ setFlag(WritesVCC);
+ setFlag(F64);
+ } // Inst_VOP3__V_DIV_SCALE_F64
+
+ Inst_VOP3__V_DIV_SCALE_F64::~Inst_VOP3__V_DIV_SCALE_F64()
+ {
+ } // ~Inst_VOP3__V_DIV_SCALE_F64
+
+ // {vcc,D.d} = Divide preop and flags -- s0.d = Quotient, s1.d =
+ // Denominator, s2.d = Numerator -- s0 must equal s1 or s2. Given a
+ // numerator and denominator, this opcode will appropriately scale inputs
+ // for division to avoid subnormal terms during Newton-Raphson correction
+ // algorithm. This opcode producses a VCC flag for post-scale of quotient.
+ void
+ Inst_VOP3__V_DIV_SCALE_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandF64 src2(gpuDynInst, extData.SRC2);
+ ScalarOperandU64 vcc(gpuDynInst, instData.SDST);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ if (extData.NEG & 0x4) {
+ src2.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane];
+ vcc.setBit(lane, 0);
+ }
+ }
+
+ vcc.write();
+ vdst.write();
+ }
+
+ Inst_VOP3__V_DIV_FMAS_F32::Inst_VOP3__V_DIV_FMAS_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_div_fmas_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(ReadsVCC);
+ setFlag(F32);
+ setFlag(FMA);
+ } // Inst_VOP3__V_DIV_FMAS_F32
+
+ Inst_VOP3__V_DIV_FMAS_F32::~Inst_VOP3__V_DIV_FMAS_F32()
+ {
+ } // ~Inst_VOP3__V_DIV_FMAS_F32
+
+ // D.f = Special case divide FMA with scale and flags(s0.f = Quotient,
+ // s1.f = Denominator, s2.f = Numerator)
+ void
+ Inst_VOP3__V_DIV_FMAS_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_DIV_FMAS_F64::Inst_VOP3__V_DIV_FMAS_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_div_fmas_f64", false)
+ {
+ setFlag(ALU);
+ setFlag(ReadsVCC);
+ setFlag(F64);
+ setFlag(FMA);
+ } // Inst_VOP3__V_DIV_FMAS_F64
+
+ Inst_VOP3__V_DIV_FMAS_F64::~Inst_VOP3__V_DIV_FMAS_F64()
+ {
+ } // ~Inst_VOP3__V_DIV_FMAS_F64
+
+ // D.d = Special case divide FMA with scale and flags(s0.d = Quotient,
+ // s1.d = Denominator, s2.d = Numerator)
+ void
+ Inst_VOP3__V_DIV_FMAS_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandF64 src2(gpuDynInst, extData.SRC2);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (instData.ABS & 0x4) {
+ src2.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ if (extData.NEG & 0x4) {
+ src2.negModifier();
+ }
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::fma(src0[lane], src1[lane], src2[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MSAD_U8::Inst_VOP3__V_MSAD_U8(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_msad_u8", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MSAD_U8
+
+ Inst_VOP3__V_MSAD_U8::~Inst_VOP3__V_MSAD_U8()
+ {
+ } // ~Inst_VOP3__V_MSAD_U8
+
+ // D.u = Masked Byte SAD with accum_lo(S0.u, S1.u, S2.u).
+ void
+ Inst_VOP3__V_MSAD_U8::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_QSAD_PK_U16_U8::Inst_VOP3__V_QSAD_PK_U16_U8(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_qsad_pk_u16_u8", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_QSAD_PK_U16_U8
+
+ Inst_VOP3__V_QSAD_PK_U16_U8::~Inst_VOP3__V_QSAD_PK_U16_U8()
+ {
+ } // ~Inst_VOP3__V_QSAD_PK_U16_U8
+
+ // D.u = Quad-Byte SAD with 16-bit packed accum_lo/hi(S0.u[63:0],
+ // S1.u[31:0], S2.u[63:0])
+ void
+ Inst_VOP3__V_QSAD_PK_U16_U8::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_MQSAD_PK_U16_U8::Inst_VOP3__V_MQSAD_PK_U16_U8(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mqsad_pk_u16_u8", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MQSAD_PK_U16_U8
+
+ Inst_VOP3__V_MQSAD_PK_U16_U8::~Inst_VOP3__V_MQSAD_PK_U16_U8()
+ {
+ } // ~Inst_VOP3__V_MQSAD_PK_U16_U8
+
+ // D.u = Masked Quad-Byte SAD with 16-bit packed accum_lo/hi(S0.u[63:0],
+ // S1.u[31:0], S2.u[63:0])
+ void
+ Inst_VOP3__V_MQSAD_PK_U16_U8::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_MQSAD_U32_U8::Inst_VOP3__V_MQSAD_U32_U8(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mqsad_u32_u8", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MQSAD_U32_U8
+
+ Inst_VOP3__V_MQSAD_U32_U8::~Inst_VOP3__V_MQSAD_U32_U8()
+ {
+ } // ~Inst_VOP3__V_MQSAD_U32_U8
+
+ // D.u128 = Masked Quad-Byte SAD with 32-bit accum_lo/hi(S0.u[63:0],
+ // S1.u[31:0], S2.u[127:0])
+ void
+ Inst_VOP3__V_MQSAD_U32_U8::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_MAD_U64_U32::Inst_VOP3__V_MAD_U64_U32(
+ InFmt_VOP3_SDST_ENC *iFmt)
+ : Inst_VOP3_SDST_ENC(iFmt, "v_mad_u64_u32")
+ {
+ setFlag(ALU);
+ setFlag(WritesVCC);
+ setFlag(MAD);
+ } // Inst_VOP3__V_MAD_U64_U32
+
+ Inst_VOP3__V_MAD_U64_U32::~Inst_VOP3__V_MAD_U64_U32()
+ {
+ } // ~Inst_VOP3__V_MAD_U64_U32
+
+ // {vcc_out, D.u64} = S0.u32 * S1.u32 + S2.u64.
+ void
+ Inst_VOP3__V_MAD_U64_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU64 src2(gpuDynInst, extData.SRC2);
+ ScalarOperandU64 vcc(gpuDynInst, instData.SDST);
+ VecOperandU64 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+ vdst.read();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, muladd(vdst[lane], src0[lane], src1[lane],
+ src2[lane]));
+ }
+ }
+
+ vcc.write();
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MAD_I64_I32::Inst_VOP3__V_MAD_I64_I32(
+ InFmt_VOP3_SDST_ENC *iFmt)
+ : Inst_VOP3_SDST_ENC(iFmt, "v_mad_i64_i32")
+ {
+ setFlag(ALU);
+ setFlag(WritesVCC);
+ setFlag(MAD);
+ } // Inst_VOP3__V_MAD_I64_I32
+
+ Inst_VOP3__V_MAD_I64_I32::~Inst_VOP3__V_MAD_I64_I32()
+ {
+ } // ~Inst_VOP3__V_MAD_I64_I32
+
+ // {vcc_out,D.i64} = S0.i32 * S1.i32 + S2.i64.
+ void
+ Inst_VOP3__V_MAD_I64_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandI64 src2(gpuDynInst, extData.SRC2);
+ ScalarOperandU64 vcc(gpuDynInst, instData.SDST);
+ VecOperandI64 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vcc.setBit(lane, muladd(vdst[lane], src0[lane], src1[lane],
+ src2[lane]));
+ }
+ }
+
+ vcc.write();
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MAD_F16::Inst_VOP3__V_MAD_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mad_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ setFlag(MAD);
+ } // Inst_VOP3__V_MAD_F16
+
+ Inst_VOP3__V_MAD_F16::~Inst_VOP3__V_MAD_F16()
+ {
+ } // ~Inst_VOP3__V_MAD_F16
+
+ // D.f16 = S0.f16 * S1.f16 + S2.f16.
+ // Supports round mode, exception flags, saturation.
+ void
+ Inst_VOP3__V_MAD_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_MAD_U16::Inst_VOP3__V_MAD_U16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mad_u16", false)
+ {
+ setFlag(ALU);
+ setFlag(MAD);
+ } // Inst_VOP3__V_MAD_U16
+
+ Inst_VOP3__V_MAD_U16::~Inst_VOP3__V_MAD_U16()
+ {
+ } // ~Inst_VOP3__V_MAD_U16
+
+ // D.u16 = S0.u16 * S1.u16 + S2.u16.
+ // Supports saturation (unsigned 16-bit integer domain).
+ void
+ Inst_VOP3__V_MAD_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU16 src2(gpuDynInst, extData.SRC2);
+ VecOperandU16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] * src1[lane] + src2[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MAD_I16::Inst_VOP3__V_MAD_I16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mad_i16", false)
+ {
+ setFlag(ALU);
+ setFlag(MAD);
+ } // Inst_VOP3__V_MAD_I16
+
+ Inst_VOP3__V_MAD_I16::~Inst_VOP3__V_MAD_I16()
+ {
+ } // ~Inst_VOP3__V_MAD_I16
+
+ // D.i16 = S0.i16 * S1.i16 + S2.i16.
+ // Supports saturation (signed 16-bit integer domain).
+ void
+ Inst_VOP3__V_MAD_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandI16 src2(gpuDynInst, extData.SRC2);
+ VecOperandI16 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src0[lane] * src1[lane] + src2[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_PERM_B32::Inst_VOP3__V_PERM_B32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_perm_b32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_PERM_B32
+
+ Inst_VOP3__V_PERM_B32::~Inst_VOP3__V_PERM_B32()
+ {
+ } // ~Inst_VOP3__V_PERM_B32
+
+ // D.u[31:24] = permute({S0.u, S1.u}, S2.u[31:24]);
+ // D.u[23:16] = permute({S0.u, S1.u}, S2.u[23:16]);
+ // D.u[15:8] = permute({S0.u, S1.u}, S2.u[15:8]);
+ // D.u[7:0] = permute({S0.u, S1.u}, S2.u[7:0]);
+ // byte permute(byte in[8], byte sel) {
+ // if(sel>=13) then return 0xff;
+ // elsif(sel==12) then return 0x00;
+ // elsif(sel==11) then return in[7][7] * 0xff;
+ // elsif(sel==10) then return in[5][7] * 0xff;
+ // elsif(sel==9) then return in[3][7] * 0xff;
+ // elsif(sel==8) then return in[1][7] * 0xff;
+ // else return in[sel];
+ // }
+ void
+ Inst_VOP3__V_PERM_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+ src2.readSrc();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ VecElemU64 selector = (VecElemU64)src0[lane];
+ selector = (selector << 32) | (VecElemU64)src1[lane];
+ vdst[lane] = 0;
+
+ DPRINTF(GCN3, "Executing v_perm_b32 src_0 0x%08x, src_1 "
+ "0x%08x, src_2 0x%08x, vdst 0x%08x\n", src0[lane],
+ src1[lane], src2[lane], vdst[lane]);
+ DPRINTF(GCN3, "Selector: 0x%08x \n", selector);
+
+ for (int i = 0; i < 4 ; ++i) {
+ VecElemU32 permuted_val = permute(selector, 0xFF
+ & ((VecElemU32)src2[lane] >> (8 * i)));
+ vdst[lane] |= (permuted_val << i);
+ }
+
+ DPRINTF(GCN3, "v_perm result: 0x%08x\n", vdst[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_FMA_F16::Inst_VOP3__V_FMA_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_fma_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ setFlag(FMA);
+ } // Inst_VOP3__V_FMA_F16
+
+ Inst_VOP3__V_FMA_F16::~Inst_VOP3__V_FMA_F16()
+ {
+ } // ~Inst_VOP3__V_FMA_F16
+
+ // D.f16 = S0.f16 * S1.f16 + S2.f16.
+ // Fused half precision multiply add.
+ void
+ Inst_VOP3__V_FMA_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_DIV_FIXUP_F16::Inst_VOP3__V_DIV_FIXUP_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_div_fixup_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_DIV_FIXUP_F16
+
+ Inst_VOP3__V_DIV_FIXUP_F16::~Inst_VOP3__V_DIV_FIXUP_F16()
+ {
+ } // ~Inst_VOP3__V_DIV_FIXUP_F16
+
+ // sign_out = sign(S1.f16)^sign(S2.f16);
+ // if (S2.f16 == NAN)
+ // D.f16 = Quiet(S2.f16);
+ // else if (S1.f16 == NAN)
+ // D.f16 = Quiet(S1.f16);
+ // else if (S1.f16 == S2.f16 == 0)
+ // # 0/0
+ // D.f16 = pele_nan(0xfe00);
+ // else if (abs(S1.f16) == abs(S2.f16) == +-INF)
+ // # inf/inf
+ // D.f16 = pele_nan(0xfe00);
+ // else if (S1.f16 ==0 || abs(S2.f16) == +-INF)
+ // # x/0, or inf/y
+ // D.f16 = sign_out ? -INF : INF;
+ // else if (abs(S1.f16) == +-INF || S2.f16 == 0)
+ // # x/inf, 0/y
+ // D.f16 = sign_out ? -0 : 0;
+ // else if ((exp(S2.f16) - exp(S1.f16)) < -150)
+ // D.f16 = sign_out ? -underflow : underflow;
+ // else if (exp(S1.f16) == 255)
+ // D.f16 = sign_out ? -overflow : overflow;
+ // else
+ // D.f16 = sign_out ? -abs(S0.f16) : abs(S0.f16).
+ // Half precision division fixup.
+ // S0 = Quotient, S1 = Denominator, S3 = Numerator.
+ // Given a numerator, denominator, and quotient from a divide, this opcode
+ // will detect and apply special case numerics, touching up the quotient if
+ // necessary. This opcode also generates invalid, denorm and divide by
+ // zero exceptions caused by the division.
+ void
+ Inst_VOP3__V_DIV_FIXUP_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CVT_PKACCUM_U8_F32::Inst_VOP3__V_CVT_PKACCUM_U8_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_pkaccum_u8_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CVT_PKACCUM_U8_F32
+
+ Inst_VOP3__V_CVT_PKACCUM_U8_F32::~Inst_VOP3__V_CVT_PKACCUM_U8_F32()
+ {
+ } // ~Inst_VOP3__V_CVT_PKACCUM_U8_F32
+
+ // byte = S1.u[1:0]; bit = byte * 8;
+ // D.u[bit + 7:bit] = flt32_to_uint8(S0.f);
+ // Pack converted value of S0.f into byte S1 of the destination.
+ // SQ translates to V_CVT_PK_U8_F32.
+ // Note: this opcode uses src_c to pass destination in as a source.
+ void
+ Inst_VOP3__V_CVT_PKACCUM_U8_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_INTERP_P1_F32::Inst_VOP3__V_INTERP_P1_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_interp_p1_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_INTERP_P1_F32
+
+ Inst_VOP3__V_INTERP_P1_F32::~Inst_VOP3__V_INTERP_P1_F32()
+ {
+ } // ~Inst_VOP3__V_INTERP_P1_F32
+
+ // D.f = P10 * S.f + P0;
+ void
+ Inst_VOP3__V_INTERP_P1_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_INTERP_P2_F32::Inst_VOP3__V_INTERP_P2_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_interp_p2_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_INTERP_P2_F32
+
+ Inst_VOP3__V_INTERP_P2_F32::~Inst_VOP3__V_INTERP_P2_F32()
+ {
+ } // ~Inst_VOP3__V_INTERP_P2_F32
+
+ // D.f = P20 * S.f + D.f;
+ void
+ Inst_VOP3__V_INTERP_P2_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_INTERP_MOV_F32::Inst_VOP3__V_INTERP_MOV_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_interp_mov_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_INTERP_MOV_F32
+
+ Inst_VOP3__V_INTERP_MOV_F32::~Inst_VOP3__V_INTERP_MOV_F32()
+ {
+ } // ~Inst_VOP3__V_INTERP_MOV_F32
+
+ // D.f = {P10,P20,P0}[S.u]; parameter load.
+ void
+ Inst_VOP3__V_INTERP_MOV_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_INTERP_P1LL_F16::Inst_VOP3__V_INTERP_P1LL_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_interp_p1ll_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_INTERP_P1LL_F16
+
+ Inst_VOP3__V_INTERP_P1LL_F16::~Inst_VOP3__V_INTERP_P1LL_F16()
+ {
+ } // ~Inst_VOP3__V_INTERP_P1LL_F16
+
+ // D.f32 = P10.f16 * S0.f32 + P0.f16.
+ void
+ Inst_VOP3__V_INTERP_P1LL_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_INTERP_P1LV_F16::Inst_VOP3__V_INTERP_P1LV_F16(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_interp_p1lv_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_INTERP_P1LV_F16
+
+ Inst_VOP3__V_INTERP_P1LV_F16::~Inst_VOP3__V_INTERP_P1LV_F16()
+ {
+ } // ~Inst_VOP3__V_INTERP_P1LV_F16
+
+ void
+ Inst_VOP3__V_INTERP_P1LV_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_INTERP_P2_F16::Inst_VOP3__V_INTERP_P2_F16(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_interp_p2_f16", false)
+ {
+ setFlag(ALU);
+ setFlag(F16);
+ } // Inst_VOP3__V_INTERP_P2_F16
+
+ Inst_VOP3__V_INTERP_P2_F16::~Inst_VOP3__V_INTERP_P2_F16()
+ {
+ } // ~Inst_VOP3__V_INTERP_P2_F16
+
+ // D.f16 = P20.f16 * S0.f32 + S2.f32.
+ void
+ Inst_VOP3__V_INTERP_P2_F16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_ADD_F64::Inst_VOP3__V_ADD_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_add_f64", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_ADD_F64
+
+ Inst_VOP3__V_ADD_F64::~Inst_VOP3__V_ADD_F64()
+ {
+ } // ~Inst_VOP3__V_ADD_F64
+
+ // D.d = S0.d + S1.d.
+ void
+ Inst_VOP3__V_ADD_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::isnan(src0[lane]) ||
+ std::isnan(src1[lane]) ) {
+ vdst[lane] = NAN;
+ } else if (std::isinf(src0[lane]) &&
+ std::isinf(src1[lane])) {
+ if (std::signbit(src0[lane]) !=
+ std::signbit(src1[lane])) {
+ vdst[lane] = NAN;
+ } else {
+ vdst[lane] = src0[lane];
+ }
+ } else if (std::isinf(src0[lane])) {
+ vdst[lane] = src0[lane];
+ } else if (std::isinf(src1[lane])) {
+ vdst[lane] = src1[lane];
+ } else if (std::fpclassify(src0[lane]) == FP_SUBNORMAL ||
+ std::fpclassify(src0[lane]) == FP_ZERO) {
+ if (std::fpclassify(src1[lane]) == FP_SUBNORMAL ||
+ std::fpclassify(src1[lane]) == FP_ZERO) {
+ if (std::signbit(src0[lane]) &&
+ std::signbit(src1[lane])) {
+ vdst[lane] = -0.0;
+ } else {
+ vdst[lane] = 0.0;
+ }
+ } else {
+ vdst[lane] = src1[lane];
+ }
+ } else if (std::fpclassify(src1[lane]) == FP_SUBNORMAL ||
+ std::fpclassify(src1[lane]) == FP_ZERO) {
+ if (std::fpclassify(src0[lane]) == FP_SUBNORMAL ||
+ std::fpclassify(src0[lane]) == FP_ZERO) {
+ if (std::signbit(src0[lane]) &&
+ std::signbit(src1[lane])) {
+ vdst[lane] = -0.0;
+ } else {
+ vdst[lane] = 0.0;
+ }
+ } else {
+ vdst[lane] = src0[lane];
+ }
+ } else {
+ vdst[lane] = src0[lane] + src1[lane];
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MUL_F64::Inst_VOP3__V_MUL_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mul_f64", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_MUL_F64
+
+ Inst_VOP3__V_MUL_F64::~Inst_VOP3__V_MUL_F64()
+ {
+ } // ~Inst_VOP3__V_MUL_F64
+
+ // D.d = S0.d * S1.d.
+ void
+ Inst_VOP3__V_MUL_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::isnan(src0[lane]) ||
+ std::isnan(src1[lane])) {
+ vdst[lane] = NAN;
+ } else if ((std::fpclassify(src0[lane]) == FP_SUBNORMAL ||
+ std::fpclassify(src0[lane]) == FP_ZERO) &&
+ !std::signbit(src0[lane])) {
+ if (std::isinf(src1[lane])) {
+ vdst[lane] = NAN;
+ } else if (!std::signbit(src1[lane])) {
+ vdst[lane] = +0.0;
+ } else {
+ vdst[lane] = -0.0;
+ }
+ } else if ((std::fpclassify(src0[lane]) == FP_SUBNORMAL ||
+ std::fpclassify(src0[lane]) == FP_ZERO) &&
+ std::signbit(src0[lane])) {
+ if (std::isinf(src1[lane])) {
+ vdst[lane] = NAN;
+ } else if (std::signbit(src1[lane])) {
+ vdst[lane] = +0.0;
+ } else {
+ vdst[lane] = -0.0;
+ }
+ } else if (std::isinf(src0[lane]) &&
+ !std::signbit(src0[lane])) {
+ if (std::fpclassify(src1[lane]) == FP_SUBNORMAL ||
+ std::fpclassify(src1[lane]) == FP_ZERO) {
+ vdst[lane] = NAN;
+ } else if (!std::signbit(src1[lane])) {
+ vdst[lane] = +INFINITY;
+ } else {
+ vdst[lane] = -INFINITY;
+ }
+ } else if (std::isinf(src0[lane]) &&
+ std::signbit(src0[lane])) {
+ if (std::fpclassify(src1[lane]) == FP_SUBNORMAL ||
+ std::fpclassify(src1[lane]) == FP_ZERO) {
+ vdst[lane] = NAN;
+ } else if (std::signbit(src1[lane])) {
+ vdst[lane] = +INFINITY;
+ } else {
+ vdst[lane] = -INFINITY;
+ }
+ } else {
+ vdst[lane] = src0[lane] * src1[lane];
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MIN_F64::Inst_VOP3__V_MIN_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_min_f64", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_MIN_F64
+
+ Inst_VOP3__V_MIN_F64::~Inst_VOP3__V_MIN_F64()
+ {
+ } // ~Inst_VOP3__V_MIN_F64
+
+ // D.d = min(S0.d, S1.d).
+ void
+ Inst_VOP3__V_MIN_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::fmin(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MAX_F64::Inst_VOP3__V_MAX_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_max_f64", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_MAX_F64
+
+ Inst_VOP3__V_MAX_F64::~Inst_VOP3__V_MAX_F64()
+ {
+ } // ~Inst_VOP3__V_MAX_F64
+
+ // D.d = max(S0.d, S1.d).
+ void
+ Inst_VOP3__V_MAX_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (instData.ABS & 0x2) {
+ src1.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ if (extData.NEG & 0x2) {
+ src1.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::fmax(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_LDEXP_F64::Inst_VOP3__V_LDEXP_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_ldexp_f64", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_LDEXP_F64
+
+ Inst_VOP3__V_LDEXP_F64::~Inst_VOP3__V_LDEXP_F64()
+ {
+ } // ~Inst_VOP3__V_LDEXP_F64
+
+ // D.d = pow(S0.d, S1.i[31:0]).
+ void
+ Inst_VOP3__V_LDEXP_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ VecOperandF64 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ if (instData.ABS & 0x1) {
+ src0.absModifier();
+ }
+
+ if (extData.NEG & 0x1) {
+ src0.negModifier();
+ }
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ if (std::isnan(src1[lane]) || std::isinf(src1[lane])) {
+ vdst[lane] = src0[lane];
+ } else if (!std::isnormal(src1[lane])) {
+ if (std::signbit(src1[lane])) {
+ vdst[lane] = -0.0;
+ } else {
+ vdst[lane] = +0.0;
+ }
+ } else {
+ vdst[lane] = std::ldexp(src0[lane], src1[lane]);
+ }
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MUL_LO_U32::Inst_VOP3__V_MUL_LO_U32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mul_lo_u32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MUL_LO_U32
+
+ Inst_VOP3__V_MUL_LO_U32::~Inst_VOP3__V_MUL_LO_U32()
+ {
+ } // ~Inst_VOP3__V_MUL_LO_U32
+
+ // D.u = S0.u * S1.u.
+ void
+ Inst_VOP3__V_MUL_LO_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ VecElemI64 s0 = (VecElemI64)src0[lane];
+ VecElemI64 s1 = (VecElemI64)src1[lane];
+ vdst[lane] = (VecElemU32)((s0 * s1) & 0xffffffffLL);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MUL_HI_U32::Inst_VOP3__V_MUL_HI_U32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mul_hi_u32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MUL_HI_U32
+
+ Inst_VOP3__V_MUL_HI_U32::~Inst_VOP3__V_MUL_HI_U32()
+ {
+ } // ~Inst_VOP3__V_MUL_HI_U32
+
+ // D.u = (S0.u * S1.u) >> 32.
+ void
+ Inst_VOP3__V_MUL_HI_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ VecElemI64 s0 = (VecElemI64)src0[lane];
+ VecElemI64 s1 = (VecElemI64)src1[lane];
+ vdst[lane]
+ = (VecElemU32)(((s0 * s1) >> 32) & 0xffffffffLL);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MUL_HI_I32::Inst_VOP3__V_MUL_HI_I32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mul_hi_i32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MUL_HI_I32
+
+ Inst_VOP3__V_MUL_HI_I32::~Inst_VOP3__V_MUL_HI_I32()
+ {
+ } // ~Inst_VOP3__V_MUL_HI_I32
+
+ // D.i = (S0.i * S1.i) >> 32.
+ void
+ Inst_VOP3__V_MUL_HI_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ VecOperandI32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ VecElemI64 s0 = (VecElemI64)src0[lane];
+ VecElemI64 s1 = (VecElemI64)src1[lane];
+ vdst[lane]
+ = (VecElemI32)(((s0 * s1) >> 32LL) & 0xffffffffLL);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_LDEXP_F32::Inst_VOP3__V_LDEXP_F32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_ldexp_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_LDEXP_F32
+
+ Inst_VOP3__V_LDEXP_F32::~Inst_VOP3__V_LDEXP_F32()
+ {
+ } // ~Inst_VOP3__V_LDEXP_F32
+
+ // D.f = pow(S0.f, S1.i)
+ void
+ Inst_VOP3__V_LDEXP_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
+ VecOperandF32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = std::ldexp(src0[lane], src1[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_READLANE_B32::Inst_VOP3__V_READLANE_B32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_readlane_b32", true)
+ {
+ setFlag(ALU);
+ setFlag(IgnoreExec);
+ } // Inst_VOP3__V_READLANE_B32
+
+ Inst_VOP3__V_READLANE_B32::~Inst_VOP3__V_READLANE_B32()
+ {
+ } // ~Inst_VOP3__V_READLANE_B32
+
+ // Copy one VGPR value to one SGPR. D = SGPR-dest, S0 = Source Data (VGPR#
+ // or M0(lds-direct)), S1 = Lane Select (SGPR or M0). Ignores exec mask.
+ // Input and output modifiers not supported; this is an untyped operation.
+ void
+ Inst_VOP3__V_READLANE_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, extData.SRC1);
+ ScalarOperandU32 sdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.read();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ sdst = src0[src1.rawData() & 0x3f];
+
+ sdst.write();
+ }
+
+ Inst_VOP3__V_WRITELANE_B32::Inst_VOP3__V_WRITELANE_B32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_writelane_b32", false)
+ {
+ setFlag(ALU);
+ setFlag(IgnoreExec);
+ } // Inst_VOP3__V_WRITELANE_B32
+
+ Inst_VOP3__V_WRITELANE_B32::~Inst_VOP3__V_WRITELANE_B32()
+ {
+ } // ~Inst_VOP3__V_WRITELANE_B32
+
+ // Write value into one VGPR in one lane. D = VGPR-dest, S0 = Source Data
+ // (sgpr, m0, exec or constants), S1 = Lane Select (SGPR or M0). Ignores
+ // exec mask. Input and output modifiers not supported; this is an untyped
+ // operation.
+ void
+ Inst_VOP3__V_WRITELANE_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ ConstScalarOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstScalarOperandU32 src1(gpuDynInst, extData.SRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.read();
+ src1.read();
+ vdst.read();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ vdst[src1.rawData() & 0x3f] = src1.rawData();
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_BCNT_U32_B32::Inst_VOP3__V_BCNT_U32_B32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_bcnt_u32_b32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_BCNT_U32_B32
+
+ Inst_VOP3__V_BCNT_U32_B32::~Inst_VOP3__V_BCNT_U32_B32()
+ {
+ } // ~Inst_VOP3__V_BCNT_U32_B32
+
+ // D.u = CountOneBits(S0.u) + S1.u. Bit count.
+ void
+ Inst_VOP3__V_BCNT_U32_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = popCount(src0[lane]) + src1[lane];
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_MBCNT_LO_U32_B32::Inst_VOP3__V_MBCNT_LO_U32_B32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mbcnt_lo_u32_b32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MBCNT_LO_U32_B32
+
+ Inst_VOP3__V_MBCNT_LO_U32_B32::~Inst_VOP3__V_MBCNT_LO_U32_B32()
+ {
+ } // ~Inst_VOP3__V_MBCNT_LO_U32_B32
+
+ // Masked bit count, ThreadPosition is the position of this thread in the
+ // wavefront (in 0..63).
+ void
+ Inst_VOP3__V_MBCNT_LO_U32_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_MBCNT_HI_U32_B32::Inst_VOP3__V_MBCNT_HI_U32_B32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_mbcnt_hi_u32_b32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_MBCNT_HI_U32_B32
+
+ Inst_VOP3__V_MBCNT_HI_U32_B32::~Inst_VOP3__V_MBCNT_HI_U32_B32()
+ {
+ } // ~Inst_VOP3__V_MBCNT_HI_U32_B32
+
+ // ThreadMask = (1 << ThreadPosition) - 1;
+ // D.u = CountOneBits(S0.u & ThreadMask[63:32]) + S1.u.
+ // Masked bit count, ThreadPosition is the position of this thread in the
+ // wavefront (in 0..63).
+ void
+ Inst_VOP3__V_MBCNT_HI_U32_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_LSHLREV_B64::Inst_VOP3__V_LSHLREV_B64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_lshlrev_b64", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_LSHLREV_B64
+
+ Inst_VOP3__V_LSHLREV_B64::~Inst_VOP3__V_LSHLREV_B64()
+ {
+ } // ~Inst_VOP3__V_LSHLREV_B64
+
+ // D.u64 = S1.u64 << S0.u[5:0].
+ void
+ Inst_VOP3__V_LSHLREV_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
+ VecOperandU64 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src1[lane] << bits(src0[lane], 5, 0);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_LSHRREV_B64::Inst_VOP3__V_LSHRREV_B64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_lshrrev_b64", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_LSHRREV_B64
+
+ Inst_VOP3__V_LSHRREV_B64::~Inst_VOP3__V_LSHRREV_B64()
+ {
+ } // ~Inst_VOP3__V_LSHRREV_B64
+
+ // D.u64 = S1.u64 >> S0.u[5:0].
+ // The vacated bits are set to zero.
+ void
+ Inst_VOP3__V_LSHRREV_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
+ VecOperandU64 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = src1[lane] >> bits(src0[lane], 5, 0);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_ASHRREV_I64::Inst_VOP3__V_ASHRREV_I64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_ashrrev_i64", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_ASHRREV_I64
+
+ Inst_VOP3__V_ASHRREV_I64::~Inst_VOP3__V_ASHRREV_I64()
+ {
+ } // ~Inst_VOP3__V_ASHRREV_I64
+
+ // D.u64 = signext(S1.u64) >> S0.u[5:0].
+ // The vacated bits are set to the sign bit of the input value.
+ void
+ Inst_VOP3__V_ASHRREV_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
+ VecOperandU64 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane]
+ = src1[lane] >> bits(src0[lane], 5, 0);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_TRIG_PREOP_F64::Inst_VOP3__V_TRIG_PREOP_F64(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_trig_preop_f64", false)
+ {
+ setFlag(ALU);
+ setFlag(F64);
+ } // Inst_VOP3__V_TRIG_PREOP_F64
+
+ Inst_VOP3__V_TRIG_PREOP_F64::~Inst_VOP3__V_TRIG_PREOP_F64()
+ {
+ } // ~Inst_VOP3__V_TRIG_PREOP_F64
+
+ void
+ Inst_VOP3__V_TRIG_PREOP_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_BFM_B32::Inst_VOP3__V_BFM_B32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_bfm_b32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_BFM_B32
+
+ Inst_VOP3__V_BFM_B32::~Inst_VOP3__V_BFM_B32()
+ {
+ } // ~Inst_VOP3__V_BFM_B32
+
+ // D.u = ((1 << S0.u[4:0]) - 1) << S1.u[4:0];
+ void
+ Inst_VOP3__V_BFM_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+ src0.readSrc();
+ src1.readSrc();
+
+ /**
+ * input modifiers are supported by FP operations only
+ */
+ assert(!(instData.ABS & 0x1));
+ assert(!(instData.ABS & 0x2));
+ assert(!(instData.ABS & 0x4));
+ assert(!(extData.NEG & 0x1));
+ assert(!(extData.NEG & 0x2));
+ assert(!(extData.NEG & 0x4));
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ vdst[lane] = ((1 << bits(src0[lane], 4, 0)) - 1)
+ << bits(src1[lane], 4, 0);
+ }
+ }
+
+ vdst.write();
+ }
+
+ Inst_VOP3__V_CVT_PKNORM_I16_F32::Inst_VOP3__V_CVT_PKNORM_I16_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_pknorm_i16_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CVT_PKNORM_I16_F32
+
+ Inst_VOP3__V_CVT_PKNORM_I16_F32::~Inst_VOP3__V_CVT_PKNORM_I16_F32()
+ {
+ } // ~Inst_VOP3__V_CVT_PKNORM_I16_F32
+
+ // D = {(snorm)S1.f, (snorm)S0.f}.
+ void
+ Inst_VOP3__V_CVT_PKNORM_I16_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CVT_PKNORM_U16_F32::Inst_VOP3__V_CVT_PKNORM_U16_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_pknorm_u16_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CVT_PKNORM_U16_F32
+
+ Inst_VOP3__V_CVT_PKNORM_U16_F32::~Inst_VOP3__V_CVT_PKNORM_U16_F32()
+ {
+ } // ~Inst_VOP3__V_CVT_PKNORM_U16_F32
+
+ // D = {(unorm)S1.f, (unorm)S0.f}.
+ void
+ Inst_VOP3__V_CVT_PKNORM_U16_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CVT_PKRTZ_F16_F32::Inst_VOP3__V_CVT_PKRTZ_F16_F32(
+ InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_pkrtz_f16_f32", false)
+ {
+ setFlag(ALU);
+ setFlag(F32);
+ } // Inst_VOP3__V_CVT_PKRTZ_F16_F32
+
+ Inst_VOP3__V_CVT_PKRTZ_F16_F32::~Inst_VOP3__V_CVT_PKRTZ_F16_F32()
+ {
+ } // ~Inst_VOP3__V_CVT_PKRTZ_F16_F32
+
+ void
+ Inst_VOP3__V_CVT_PKRTZ_F16_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CVT_PK_U16_U32::Inst_VOP3__V_CVT_PK_U16_U32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_pk_u16_u32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CVT_PK_U16_U32
+
+ Inst_VOP3__V_CVT_PK_U16_U32::~Inst_VOP3__V_CVT_PK_U16_U32()
+ {
+ } // ~Inst_VOP3__V_CVT_PK_U16_U32
+
+ // D = {uint32_to_uint16(S1.u), uint32_to_uint16(S0.u)}.
+ void
+ Inst_VOP3__V_CVT_PK_U16_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_VOP3__V_CVT_PK_I16_I32::Inst_VOP3__V_CVT_PK_I16_I32(InFmt_VOP3 *iFmt)
+ : Inst_VOP3(iFmt, "v_cvt_pk_i16_i32", false)
+ {
+ setFlag(ALU);
+ } // Inst_VOP3__V_CVT_PK_I16_I32
+
+ Inst_VOP3__V_CVT_PK_I16_I32::~Inst_VOP3__V_CVT_PK_I16_I32()
+ {
+ } // ~Inst_VOP3__V_CVT_PK_I16_I32
+
+ // D = {int32_to_int16(S1.i), int32_to_int16(S0.i)}.
+ void
+ Inst_VOP3__V_CVT_PK_I16_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_ADD_U32::Inst_DS__DS_ADD_U32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_add_u32")
+ {
+ } // Inst_DS__DS_ADD_U32
+
+ Inst_DS__DS_ADD_U32::~Inst_DS__DS_ADD_U32()
+ {
+ } // ~Inst_DS__DS_ADD_U32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] += DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_ADD_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_SUB_U32::Inst_DS__DS_SUB_U32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_sub_u32")
+ {
+ } // Inst_DS__DS_SUB_U32
+
+ Inst_DS__DS_SUB_U32::~Inst_DS__DS_SUB_U32()
+ {
+ } // ~Inst_DS__DS_SUB_U32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_SUB_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_RSUB_U32::Inst_DS__DS_RSUB_U32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_rsub_u32")
+ {
+ } // Inst_DS__DS_RSUB_U32
+
+ Inst_DS__DS_RSUB_U32::~Inst_DS__DS_RSUB_U32()
+ {
+ } // ~Inst_DS__DS_RSUB_U32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = DATA - MEM[ADDR];
+ // RETURN_DATA = tmp.
+ // Subtraction with reversed operands.
+ void
+ Inst_DS__DS_RSUB_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_INC_U32::Inst_DS__DS_INC_U32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_inc_u32")
+ {
+ } // Inst_DS__DS_INC_U32
+
+ Inst_DS__DS_INC_U32::~Inst_DS__DS_INC_U32()
+ {
+ } // ~Inst_DS__DS_INC_U32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (tmp >= DATA) ? 0 : tmp + 1 (unsigned compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_INC_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_DEC_U32::Inst_DS__DS_DEC_U32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_dec_u32")
+ {
+ } // Inst_DS__DS_DEC_U32
+
+ Inst_DS__DS_DEC_U32::~Inst_DS__DS_DEC_U32()
+ {
+ } // ~Inst_DS__DS_DEC_U32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (tmp == 0 || tmp > DATA) ? DATA : tmp - 1
+ // (unsigned compare); RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_DEC_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MIN_I32::Inst_DS__DS_MIN_I32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_min_i32")
+ {
+ } // Inst_DS__DS_MIN_I32
+
+ Inst_DS__DS_MIN_I32::~Inst_DS__DS_MIN_I32()
+ {
+ } // ~Inst_DS__DS_MIN_I32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (DATA < tmp) ? DATA : tmp (signed compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_MIN_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MAX_I32::Inst_DS__DS_MAX_I32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_max_i32")
+ {
+ } // Inst_DS__DS_MAX_I32
+
+ Inst_DS__DS_MAX_I32::~Inst_DS__DS_MAX_I32()
+ {
+ } // ~Inst_DS__DS_MAX_I32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (DATA > tmp) ? DATA : tmp (signed compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_MAX_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MIN_U32::Inst_DS__DS_MIN_U32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_min_u32")
+ {
+ } // Inst_DS__DS_MIN_U32
+
+ Inst_DS__DS_MIN_U32::~Inst_DS__DS_MIN_U32()
+ {
+ } // ~Inst_DS__DS_MIN_U32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (DATA < tmp) ? DATA : tmp (unsigned compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_MIN_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MAX_U32::Inst_DS__DS_MAX_U32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_max_u32")
+ {
+ } // Inst_DS__DS_MAX_U32
+
+ Inst_DS__DS_MAX_U32::~Inst_DS__DS_MAX_U32()
+ {
+ } // ~Inst_DS__DS_MAX_U32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (DATA > tmp) ? DATA : tmp (unsigned compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_MAX_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_AND_B32::Inst_DS__DS_AND_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_and_b32")
+ {
+ } // Inst_DS__DS_AND_B32
+
+ Inst_DS__DS_AND_B32::~Inst_DS__DS_AND_B32()
+ {
+ } // ~Inst_DS__DS_AND_B32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] &= DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_AND_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_OR_B32::Inst_DS__DS_OR_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_or_b32")
+ {
+ } // Inst_DS__DS_OR_B32
+
+ Inst_DS__DS_OR_B32::~Inst_DS__DS_OR_B32()
+ {
+ } // ~Inst_DS__DS_OR_B32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] |= DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_OR_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_XOR_B32::Inst_DS__DS_XOR_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_xor_b32")
+ {
+ } // Inst_DS__DS_XOR_B32
+
+ Inst_DS__DS_XOR_B32::~Inst_DS__DS_XOR_B32()
+ {
+ } // ~Inst_DS__DS_XOR_B32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] ^= DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_XOR_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MSKOR_B32::Inst_DS__DS_MSKOR_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_mskor_b32")
+ {
+ } // Inst_DS__DS_MSKOR_B32
+
+ Inst_DS__DS_MSKOR_B32::~Inst_DS__DS_MSKOR_B32()
+ {
+ } // ~Inst_DS__DS_MSKOR_B32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (MEM_ADDR[ADDR] & ~DATA) | DATA2;
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_MSKOR_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_WRITE_B32::Inst_DS__DS_WRITE_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_write_b32")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_DS__DS_WRITE_B32
+
+ Inst_DS__DS_WRITE_B32::~Inst_DS__DS_WRITE_B32()
+ {
+ } // ~Inst_DS__DS_WRITE_B32
+
+ // MEM[ADDR] = DATA.
+ // Write dword.
+ void
+ Inst_DS__DS_WRITE_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(
+ gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ ConstVecOperandU32 data(gpuDynInst, extData.DATA0);
+
+ addr.read();
+ data.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ (reinterpret_cast<VecElemU32*>(gpuDynInst->d_data))[lane]
+ = data[lane];
+ }
+ }
+
+ gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
+
+ wf->wrLmReqsInPipe--;
+ wf->outstandingReqsWrLm++;
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ }
+
+ void
+ Inst_DS__DS_WRITE_B32::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ Addr offset0 = instData.OFFSET0;
+ Addr offset1 = instData.OFFSET1;
+ Addr offset = (offset1 << 8) | offset0;
+
+ initMemWrite<VecElemU32>(gpuDynInst, offset);
+ } // initiateAcc
+
+ void
+ Inst_DS__DS_WRITE_B32::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_DS__DS_WRITE2_B32::Inst_DS__DS_WRITE2_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_write2_b32")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_DS__DS_WRITE2_B32
+
+ Inst_DS__DS_WRITE2_B32::~Inst_DS__DS_WRITE2_B32()
+ {
+ } // ~Inst_DS__DS_WRITE2_B32
+
+ // MEM[ADDR_BASE + OFFSET0 * 4] = DATA;
+ // MEM[ADDR_BASE + OFFSET1 * 4] = DATA2.
+ // Write 2 dwords.
+ void
+ Inst_DS__DS_WRITE2_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(
+ gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ ConstVecOperandU32 data0(gpuDynInst, extData.DATA0);
+ ConstVecOperandU32 data1(gpuDynInst, extData.DATA1);
+
+ addr.read();
+ data0.read();
+ data1.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ (reinterpret_cast<VecElemU32*>(gpuDynInst->d_data))[lane * 2]
+ = data0[lane];
+ (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane * 2 + 1] = data1[lane];
+ }
+ }
+
+ gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
+
+ wf->wrLmReqsInPipe--;
+ wf->outstandingReqsWrLm++;
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ }
+
+ void
+ Inst_DS__DS_WRITE2_B32::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ Addr offset0 = instData.OFFSET0 * 4;
+ Addr offset1 = instData.OFFSET1 * 4;
+
+ initDualMemWrite<VecElemU32>(gpuDynInst, offset0, offset1);
+ }
+
+ void
+ Inst_DS__DS_WRITE2_B32::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_DS__DS_WRITE2ST64_B32::Inst_DS__DS_WRITE2ST64_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_write2st64_b32")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_DS__DS_WRITE2ST64_B32
+
+ Inst_DS__DS_WRITE2ST64_B32::~Inst_DS__DS_WRITE2ST64_B32()
+ {
+ } // ~Inst_DS__DS_WRITE2ST64_B32
+
+ // MEM[ADDR_BASE + OFFSET0 * 4 * 64] = DATA;
+ // MEM[ADDR_BASE + OFFSET1 * 4 * 64] = DATA2;
+ // Write 2 dwords.
+ void
+ Inst_DS__DS_WRITE2ST64_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(
+ gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ ConstVecOperandU32 data0(gpuDynInst, extData.DATA0);
+ ConstVecOperandU32 data1(gpuDynInst, extData.DATA1);
+
+ addr.read();
+ data0.read();
+ data1.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ (reinterpret_cast<VecElemU32*>(gpuDynInst->d_data))[lane * 2]
+ = data0[lane];
+ (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane * 2 + 1] = data1[lane];
+ }
+ }
+
+ gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
+
+ wf->wrLmReqsInPipe--;
+ wf->outstandingReqsWrLm++;
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ } // execute
+
+ void
+ Inst_DS__DS_WRITE2ST64_B32::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ Addr offset0 = instData.OFFSET0 * 4 * 64;
+ Addr offset1 = instData.OFFSET1 * 4 * 64;
+
+ initDualMemWrite<VecElemU32>(gpuDynInst, offset0, offset1);
+ }
+
+ void
+ Inst_DS__DS_WRITE2ST64_B32::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+ // --- Inst_DS__DS_CMPST_B32 class methods ---
+
+ Inst_DS__DS_CMPST_B32::Inst_DS__DS_CMPST_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_cmpst_b32")
+ {
+ } // Inst_DS__DS_CMPST_B32
+
+ Inst_DS__DS_CMPST_B32::~Inst_DS__DS_CMPST_B32()
+ {
+ } // ~Inst_DS__DS_CMPST_B32
+
+ // tmp = MEM[ADDR];
+ // src = DATA2;
+ // cmp = DATA;
+ // MEM[ADDR] = (tmp == cmp) ? src : tmp;
+ // RETURN_DATA[0] = tmp.
+ // Compare and store.
+ void
+ Inst_DS__DS_CMPST_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_CMPST_F32::Inst_DS__DS_CMPST_F32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_cmpst_f32")
+ {
+ setFlag(F32);
+ } // Inst_DS__DS_CMPST_F32
+
+ Inst_DS__DS_CMPST_F32::~Inst_DS__DS_CMPST_F32()
+ {
+ } // ~Inst_DS__DS_CMPST_F32
+
+ // tmp = MEM[ADDR];
+ // src = DATA2;
+ // cmp = DATA;
+ // MEM[ADDR] = (tmp == cmp) ? src : tmp;
+ // RETURN_DATA[0] = tmp.
+ void
+ Inst_DS__DS_CMPST_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MIN_F32::Inst_DS__DS_MIN_F32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_min_f32")
+ {
+ setFlag(F32);
+ } // Inst_DS__DS_MIN_F32
+
+ Inst_DS__DS_MIN_F32::~Inst_DS__DS_MIN_F32()
+ {
+ } // ~Inst_DS__DS_MIN_F32
+
+ // tmp = MEM[ADDR];
+ // src = DATA;
+ // cmp = DATA2;
+ // MEM[ADDR] = (cmp < tmp) ? src : tmp.
+ void
+ Inst_DS__DS_MIN_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MAX_F32::Inst_DS__DS_MAX_F32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_max_f32")
+ {
+ setFlag(F32);
+ } // Inst_DS__DS_MAX_F32
+
+ Inst_DS__DS_MAX_F32::~Inst_DS__DS_MAX_F32()
+ {
+ } // ~Inst_DS__DS_MAX_F32
+
+ // tmp = MEM[ADDR];
+ // src = DATA;
+ // cmp = DATA2;
+ // MEM[ADDR] = (tmp > cmp) ? src : tmp.
+ void
+ Inst_DS__DS_MAX_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_NOP::Inst_DS__DS_NOP(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_nop")
+ {
+ setFlag(Nop);
+ } // Inst_DS__DS_NOP
+
+ Inst_DS__DS_NOP::~Inst_DS__DS_NOP()
+ {
+ } // ~Inst_DS__DS_NOP
+
+ // Do nothing.
+ void
+ Inst_DS__DS_NOP::execute(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_DS__DS_ADD_F32::Inst_DS__DS_ADD_F32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_add_f32")
+ {
+ setFlag(F32);
+ } // Inst_DS__DS_ADD_F32
+
+ Inst_DS__DS_ADD_F32::~Inst_DS__DS_ADD_F32()
+ {
+ } // ~Inst_DS__DS_ADD_F32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] += DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_ADD_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_WRITE_B8::Inst_DS__DS_WRITE_B8(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_write_b8")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_DS__DS_WRITE_B8
+
+ Inst_DS__DS_WRITE_B8::~Inst_DS__DS_WRITE_B8()
+ {
+ } // ~Inst_DS__DS_WRITE_B8
+
+ // MEM[ADDR] = DATA[7:0].
+ void
+ Inst_DS__DS_WRITE_B8::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(
+ gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ ConstVecOperandU8 data(gpuDynInst, extData.DATA0);
+
+ addr.read();
+ data.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ (reinterpret_cast<VecElemU8*>(gpuDynInst->d_data))[lane]
+ = data[lane];
+ }
+ }
+
+ gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
+
+ wf->wrLmReqsInPipe--;
+ wf->outstandingReqsWrLm++;
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ } // execute
+
+ void
+ Inst_DS__DS_WRITE_B8::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ Addr offset0 = instData.OFFSET0;
+ Addr offset1 = instData.OFFSET1;
+ Addr offset = (offset1 << 8) | offset0;
+
+ initMemWrite<VecElemU8>(gpuDynInst, offset);
+ } // initiateAcc
+
+ void
+ Inst_DS__DS_WRITE_B8::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+ // --- Inst_DS__DS_WRITE_B16 class methods ---
+
+ Inst_DS__DS_WRITE_B16::Inst_DS__DS_WRITE_B16(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_write_b16")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_DS__DS_WRITE_B16
+
+ Inst_DS__DS_WRITE_B16::~Inst_DS__DS_WRITE_B16()
+ {
+ } // ~Inst_DS__DS_WRITE_B16
+
+ // MEM[ADDR] = DATA[15:0]
+ void
+ Inst_DS__DS_WRITE_B16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(
+ gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ ConstVecOperandU16 data(gpuDynInst, extData.DATA0);
+
+ addr.read();
+ data.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ (reinterpret_cast<VecElemU16*>(gpuDynInst->d_data))[lane]
+ = data[lane];
+ }
+ }
+
+ gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
+
+ wf->wrLmReqsInPipe--;
+ wf->outstandingReqsWrLm++;
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ } // execute
+
+ void
+ Inst_DS__DS_WRITE_B16::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ Addr offset0 = instData.OFFSET0;
+ Addr offset1 = instData.OFFSET1;
+ Addr offset = (offset1 << 8) | offset0;
+
+ initMemWrite<VecElemU16>(gpuDynInst, offset);
+ } // initiateAcc
+
+ void
+ Inst_DS__DS_WRITE_B16::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+ // --- Inst_DS__DS_ADD_RTN_U32 class methods ---
+
+ Inst_DS__DS_ADD_RTN_U32::Inst_DS__DS_ADD_RTN_U32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_add_rtn_u32")
+ {
+ } // Inst_DS__DS_ADD_RTN_U32
+
+ Inst_DS__DS_ADD_RTN_U32::~Inst_DS__DS_ADD_RTN_U32()
+ {
+ } // ~Inst_DS__DS_ADD_RTN_U32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] += DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_ADD_RTN_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_SUB_RTN_U32::Inst_DS__DS_SUB_RTN_U32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_sub_rtn_u32")
+ {
+ } // Inst_DS__DS_SUB_RTN_U32
+
+ Inst_DS__DS_SUB_RTN_U32::~Inst_DS__DS_SUB_RTN_U32()
+ {
+ } // ~Inst_DS__DS_SUB_RTN_U32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_SUB_RTN_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_RSUB_RTN_U32::Inst_DS__DS_RSUB_RTN_U32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_rsub_rtn_u32")
+ {
+ } // Inst_DS__DS_RSUB_RTN_U32
+
+ Inst_DS__DS_RSUB_RTN_U32::~Inst_DS__DS_RSUB_RTN_U32()
+ {
+ } // ~Inst_DS__DS_RSUB_RTN_U32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = DATA - MEM[ADDR];
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_RSUB_RTN_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_INC_RTN_U32::Inst_DS__DS_INC_RTN_U32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_inc_rtn_u32")
+ {
+ } // Inst_DS__DS_INC_RTN_U32
+
+ Inst_DS__DS_INC_RTN_U32::~Inst_DS__DS_INC_RTN_U32()
+ {
+ } // ~Inst_DS__DS_INC_RTN_U32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (tmp >= DATA) ? 0 : tmp + 1 (unsigned compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_INC_RTN_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_DEC_RTN_U32::Inst_DS__DS_DEC_RTN_U32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_dec_rtn_u32")
+ {
+ } // Inst_DS__DS_DEC_RTN_U32
+
+ Inst_DS__DS_DEC_RTN_U32::~Inst_DS__DS_DEC_RTN_U32()
+ {
+ } // ~Inst_DS__DS_DEC_RTN_U32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (tmp == 0 || tmp > DATA) ? DATA : tmp - 1
+ // (unsigned compare); RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_DEC_RTN_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MIN_RTN_I32::Inst_DS__DS_MIN_RTN_I32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_min_rtn_i32")
+ {
+ } // Inst_DS__DS_MIN_RTN_I32
+
+ Inst_DS__DS_MIN_RTN_I32::~Inst_DS__DS_MIN_RTN_I32()
+ {
+ } // ~Inst_DS__DS_MIN_RTN_I32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (DATA < tmp) ? DATA : tmp (signed compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_MIN_RTN_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MAX_RTN_I32::Inst_DS__DS_MAX_RTN_I32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_max_rtn_i32")
+ {
+ } // Inst_DS__DS_MAX_RTN_I32
+
+ Inst_DS__DS_MAX_RTN_I32::~Inst_DS__DS_MAX_RTN_I32()
+ {
+ } // ~Inst_DS__DS_MAX_RTN_I32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (DATA > tmp) ? DATA : tmp (signed compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_MAX_RTN_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MIN_RTN_U32::Inst_DS__DS_MIN_RTN_U32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_min_rtn_u32")
+ {
+ } // Inst_DS__DS_MIN_RTN_U32
+
+ Inst_DS__DS_MIN_RTN_U32::~Inst_DS__DS_MIN_RTN_U32()
+ {
+ } // ~Inst_DS__DS_MIN_RTN_U32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (DATA < tmp) ? DATA : tmp (unsigned compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_MIN_RTN_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MAX_RTN_U32::Inst_DS__DS_MAX_RTN_U32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_max_rtn_u32")
+ {
+ } // Inst_DS__DS_MAX_RTN_U32
+
+ Inst_DS__DS_MAX_RTN_U32::~Inst_DS__DS_MAX_RTN_U32()
+ {
+ } // ~Inst_DS__DS_MAX_RTN_U32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (DATA > tmp) ? DATA : tmp (unsigned compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_MAX_RTN_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_AND_RTN_B32::Inst_DS__DS_AND_RTN_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_and_rtn_b32")
+ {
+ } // Inst_DS__DS_AND_RTN_B32
+
+ Inst_DS__DS_AND_RTN_B32::~Inst_DS__DS_AND_RTN_B32()
+ {
+ } // ~Inst_DS__DS_AND_RTN_B32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] &= DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_AND_RTN_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_OR_RTN_B32::Inst_DS__DS_OR_RTN_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_or_rtn_b32")
+ {
+ } // Inst_DS__DS_OR_RTN_B32
+
+ Inst_DS__DS_OR_RTN_B32::~Inst_DS__DS_OR_RTN_B32()
+ {
+ } // ~Inst_DS__DS_OR_RTN_B32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] |= DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_OR_RTN_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_XOR_RTN_B32::Inst_DS__DS_XOR_RTN_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_xor_rtn_b32")
+ {
+ } // Inst_DS__DS_XOR_RTN_B32
+
+ Inst_DS__DS_XOR_RTN_B32::~Inst_DS__DS_XOR_RTN_B32()
+ {
+ } // ~Inst_DS__DS_XOR_RTN_B32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] ^= DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_XOR_RTN_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MSKOR_RTN_B32::Inst_DS__DS_MSKOR_RTN_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_mskor_rtn_b32")
+ {
+ } // Inst_DS__DS_MSKOR_RTN_B32
+
+ Inst_DS__DS_MSKOR_RTN_B32::~Inst_DS__DS_MSKOR_RTN_B32()
+ {
+ } // ~Inst_DS__DS_MSKOR_RTN_B32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (MEM_ADDR[ADDR] & ~DATA) | DATA2;
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_MSKOR_RTN_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_WRXCHG_RTN_B32::Inst_DS__DS_WRXCHG_RTN_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_wrxchg_rtn_b32")
+ {
+ } // Inst_DS__DS_WRXCHG_RTN_B32
+
+ Inst_DS__DS_WRXCHG_RTN_B32::~Inst_DS__DS_WRXCHG_RTN_B32()
+ {
+ } // ~Inst_DS__DS_WRXCHG_RTN_B32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = DATA;
+ // RETURN_DATA = tmp.
+ // Write-exchange operation.
+ void
+ Inst_DS__DS_WRXCHG_RTN_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_WRXCHG2_RTN_B32::Inst_DS__DS_WRXCHG2_RTN_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_wrxchg2_rtn_b32")
+ {
+ } // Inst_DS__DS_WRXCHG2_RTN_B32
+
+ Inst_DS__DS_WRXCHG2_RTN_B32::~Inst_DS__DS_WRXCHG2_RTN_B32()
+ {
+ } // ~Inst_DS__DS_WRXCHG2_RTN_B32
+
+ // Write-exchange 2 separate dwords.
+ void
+ Inst_DS__DS_WRXCHG2_RTN_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_WRXCHG2ST64_RTN_B32::Inst_DS__DS_WRXCHG2ST64_RTN_B32(
+ InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_wrxchg2st64_rtn_b32")
+ {
+ } // Inst_DS__DS_WRXCHG2ST64_RTN_B32
+
+ Inst_DS__DS_WRXCHG2ST64_RTN_B32::~Inst_DS__DS_WRXCHG2ST64_RTN_B32()
+ {
+ } // ~Inst_DS__DS_WRXCHG2ST64_RTN_B32
+
+ // Write-exchange 2 separate dwords with a stride of 64 dwords.
+ void
+ Inst_DS__DS_WRXCHG2ST64_RTN_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_CMPST_RTN_B32::Inst_DS__DS_CMPST_RTN_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_cmpst_rtn_b32")
+ {
+ } // Inst_DS__DS_CMPST_RTN_B32
+
+ Inst_DS__DS_CMPST_RTN_B32::~Inst_DS__DS_CMPST_RTN_B32()
+ {
+ } // ~Inst_DS__DS_CMPST_RTN_B32
+
+ // tmp = MEM[ADDR];
+ // src = DATA2;
+ // cmp = DATA;
+ // MEM[ADDR] = (tmp == cmp) ? src : tmp;
+ // RETURN_DATA[0] = tmp.
+ // Compare and store.
+ void
+ Inst_DS__DS_CMPST_RTN_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_CMPST_RTN_F32::Inst_DS__DS_CMPST_RTN_F32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_cmpst_rtn_f32")
+ {
+ setFlag(F32);
+ } // Inst_DS__DS_CMPST_RTN_F32
+
+ Inst_DS__DS_CMPST_RTN_F32::~Inst_DS__DS_CMPST_RTN_F32()
+ {
+ } // ~Inst_DS__DS_CMPST_RTN_F32
+
+ // tmp = MEM[ADDR];
+ // src = DATA2;
+ // cmp = DATA;
+ // MEM[ADDR] = (tmp == cmp) ? src : tmp;
+ // RETURN_DATA[0] = tmp.
+ void
+ Inst_DS__DS_CMPST_RTN_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MIN_RTN_F32::Inst_DS__DS_MIN_RTN_F32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_min_rtn_f32")
+ {
+ setFlag(F32);
+ } // Inst_DS__DS_MIN_RTN_F32
+
+ Inst_DS__DS_MIN_RTN_F32::~Inst_DS__DS_MIN_RTN_F32()
+ {
+ } // ~Inst_DS__DS_MIN_RTN_F32
+
+ // tmp = MEM[ADDR];
+ // src = DATA;
+ // cmp = DATA2;
+ // MEM[ADDR] = (cmp < tmp) ? src : tmp.
+ void
+ Inst_DS__DS_MIN_RTN_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MAX_RTN_F32::Inst_DS__DS_MAX_RTN_F32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_max_rtn_f32")
+ {
+ setFlag(F32);
+ } // Inst_DS__DS_MAX_RTN_F32
+
+ Inst_DS__DS_MAX_RTN_F32::~Inst_DS__DS_MAX_RTN_F32()
+ {
+ } // ~Inst_DS__DS_MAX_RTN_F32
+
+ // tmp = MEM[ADDR];
+ // src = DATA;
+ // cmp = DATA2;
+ // MEM[ADDR] = (tmp > cmp) ? src : tmp.
+ void
+ Inst_DS__DS_MAX_RTN_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_WRAP_RTN_B32::Inst_DS__DS_WRAP_RTN_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_wrap_rtn_b32")
+ {
+ } // Inst_DS__DS_WRAP_RTN_B32
+
+ Inst_DS__DS_WRAP_RTN_B32::~Inst_DS__DS_WRAP_RTN_B32()
+ {
+ } // ~Inst_DS__DS_WRAP_RTN_B32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (tmp >= DATA) ? tmp - DATA : tmp + DATA2;
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_WRAP_RTN_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_ADD_RTN_F32::Inst_DS__DS_ADD_RTN_F32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_add_rtn_f32")
+ {
+ setFlag(F32);
+ } // Inst_DS__DS_ADD_RTN_F32
+
+ Inst_DS__DS_ADD_RTN_F32::~Inst_DS__DS_ADD_RTN_F32()
+ {
+ } // ~Inst_DS__DS_ADD_RTN_F32
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] += DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_ADD_RTN_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_DS__DS_READ_B32::Inst_DS__DS_READ_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_read_b32")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_DS__DS_READ_B32
+
+ Inst_DS__DS_READ_B32::~Inst_DS__DS_READ_B32()
+ {
+ } // ~Inst_DS__DS_READ_B32
+
+ // RETURN_DATA = MEM[ADDR].
+ // Dword read.
+ void
+ Inst_DS__DS_READ_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(
+ gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
+
+ wf->rdLmReqsInPipe--;
+ wf->outstandingReqsRdLm++;
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ }
+
+ void
+ Inst_DS__DS_READ_B32::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ Addr offset0 = instData.OFFSET0;
+ Addr offset1 = instData.OFFSET1;
+ Addr offset = (offset1 << 8) | offset0;
+
+ initMemRead<VecElemU32>(gpuDynInst, offset);
+ } // initiateAcc
+
+ void
+ Inst_DS__DS_READ_B32::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ VecOperandU32 vdst(gpuDynInst, extData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ vdst[lane] = (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane];
+ }
+ }
+
+ vdst.write();
+ } // completeAcc
+
+ Inst_DS__DS_READ2_B32::Inst_DS__DS_READ2_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_read2_b32")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_DS__DS_READ2_B32
+
+ Inst_DS__DS_READ2_B32::~Inst_DS__DS_READ2_B32()
+ {
+ } // ~Inst_DS__DS_READ2_B32
+
+ // RETURN_DATA[0] = MEM[ADDR_BASE + OFFSET0 * 4];
+ // RETURN_DATA[1] = MEM[ADDR_BASE + OFFSET1 * 4].
+ // Read 2 dwords.
+ void
+ Inst_DS__DS_READ2_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(
+ gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
+
+ wf->rdLmReqsInPipe--;
+ wf->outstandingReqsRdLm++;
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ }
+
+ void
+ Inst_DS__DS_READ2_B32::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ Addr offset0 = instData.OFFSET0 * 4;
+ Addr offset1 = instData.OFFSET1 * 4;
+
+ initDualMemRead<VecElemU32>(gpuDynInst, offset0, offset1);
+ } // initiateAcc
+
+ void
+ Inst_DS__DS_READ2_B32::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ VecOperandU32 vdst0(gpuDynInst, extData.VDST);
+ VecOperandU32 vdst1(gpuDynInst, extData.VDST + 1);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ vdst0[lane] = (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane * 2];
+ vdst1[lane] = (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane * 2 + 1];
+ }
+ }
+
+ vdst0.write();
+ vdst1.write();
+ } // completeAcc
+
+ Inst_DS__DS_READ2ST64_B32::Inst_DS__DS_READ2ST64_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_read2st64_b32")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_DS__DS_READ2ST64_B32
+
+ Inst_DS__DS_READ2ST64_B32::~Inst_DS__DS_READ2ST64_B32()
+ {
+ } // ~Inst_DS__DS_READ2ST64_B32
+
+ // RETURN_DATA[0] = MEM[ADDR_BASE + OFFSET0 * 4 * 64];
+ // RETURN_DATA[1] = MEM[ADDR_BASE + OFFSET1 * 4 * 64].
+ // Read 2 dwords.
+ void
+ Inst_DS__DS_READ2ST64_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(
+ gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
+
+ wf->rdLmReqsInPipe--;
+ wf->outstandingReqsRdLm++;
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ } // execute
+
+ void
+ Inst_DS__DS_READ2ST64_B32::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ Addr offset0 = (instData.OFFSET0 * 4 * 64);
+ Addr offset1 = (instData.OFFSET1 * 4 * 64);
+
+ initDualMemRead<VecElemU32>(gpuDynInst, offset0, offset1);
+ }
+
+ void
+ Inst_DS__DS_READ2ST64_B32::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ VecOperandU32 vdst0(gpuDynInst, extData.VDST);
+ VecOperandU32 vdst1(gpuDynInst, extData.VDST + 2);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ vdst0[lane] = (reinterpret_cast<VecElemU64*>(
+ gpuDynInst->d_data))[lane * 2];
+ vdst1[lane] = (reinterpret_cast<VecElemU64*>(
+ gpuDynInst->d_data))[lane * 2 + 1];
+ }
+ }
+
+ vdst0.write();
+ vdst1.write();
+ }
+ // --- Inst_DS__DS_READ_I8 class methods ---
+
+ Inst_DS__DS_READ_I8::Inst_DS__DS_READ_I8(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_read_i8")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_DS__DS_READ_I8
+
+ Inst_DS__DS_READ_I8::~Inst_DS__DS_READ_I8()
+ {
+ } // ~Inst_DS__DS_READ_I8
+
+ // RETURN_DATA = signext(MEM[ADDR][7:0]).
+ // Signed byte read.
+ void
+ Inst_DS__DS_READ_I8::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_READ_U8::Inst_DS__DS_READ_U8(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_read_u8")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_DS__DS_READ_U8
+
+ Inst_DS__DS_READ_U8::~Inst_DS__DS_READ_U8()
+ {
+ } // ~Inst_DS__DS_READ_U8
+
+ // RETURN_DATA = {24'h0,MEM[ADDR][7:0]}.
+ // Unsigned byte read.
+ void
+ Inst_DS__DS_READ_U8::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(
+ gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
+
+ wf->rdLmReqsInPipe--;
+ wf->outstandingReqsRdLm++;
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ } // execute
+
+ void
+ Inst_DS__DS_READ_U8::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ Addr offset0 = instData.OFFSET0;
+ Addr offset1 = instData.OFFSET1;
+ Addr offset = (offset1 << 8) | offset0;
+
+ initMemRead<VecElemU8>(gpuDynInst, offset);
+ } // initiateAcc
+
+ void
+ Inst_DS__DS_READ_U8::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ VecOperandU8 vdst(gpuDynInst, extData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ vdst[lane] = (reinterpret_cast<VecElemU8*>(
+ gpuDynInst->d_data))[lane];
+ }
+ }
+
+ vdst.write();
+ } // completeAcc
+ // --- Inst_DS__DS_READ_I16 class methods ---
+
+ Inst_DS__DS_READ_I16::Inst_DS__DS_READ_I16(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_read_i16")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_DS__DS_READ_I16
+
+ Inst_DS__DS_READ_I16::~Inst_DS__DS_READ_I16()
+ {
+ } // ~Inst_DS__DS_READ_I16
+
+ // RETURN_DATA = signext(MEM[ADDR][15:0]).
+ // Signed short read.
+ void
+ Inst_DS__DS_READ_I16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_READ_U16::Inst_DS__DS_READ_U16(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_read_u16")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_DS__DS_READ_U16
+
+ Inst_DS__DS_READ_U16::~Inst_DS__DS_READ_U16()
+ {
+ } // ~Inst_DS__DS_READ_U16
+
+ // RETURN_DATA = {16'h0,MEM[ADDR][15:0]}.
+ // Unsigned short read.
+ void
+ Inst_DS__DS_READ_U16::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(
+ gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
+
+ wf->rdLmReqsInPipe--;
+ wf->outstandingReqsRdLm++;
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ } // execute
+ void
+ Inst_DS__DS_READ_U16::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ Addr offset0 = instData.OFFSET0;
+ Addr offset1 = instData.OFFSET1;
+ Addr offset = (offset1 << 8) | offset0;
+
+ initMemRead<VecElemU16>(gpuDynInst, offset);
+ } // initiateAcc
+
+ void
+ Inst_DS__DS_READ_U16::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ VecOperandU16 vdst(gpuDynInst, extData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ vdst[lane] = (reinterpret_cast<VecElemU16*>(
+ gpuDynInst->d_data))[lane];
+ }
+ }
+
+ vdst.write();
+ } // completeAcc
+ // --- Inst_DS__DS_SWIZZLE_B32 class methods ---
+
+ Inst_DS__DS_SWIZZLE_B32::Inst_DS__DS_SWIZZLE_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_swizzle_b32")
+ {
+ } // Inst_DS__DS_SWIZZLE_B32
+
+ Inst_DS__DS_SWIZZLE_B32::~Inst_DS__DS_SWIZZLE_B32()
+ {
+ } // ~Inst_DS__DS_SWIZZLE_B32
+
+ // RETURN_DATA = swizzle(vgpr_data, offset1:offset0).
+ // Dword swizzle, no data is written to LDS memory;
+ void
+ Inst_DS__DS_SWIZZLE_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_PERMUTE_B32::Inst_DS__DS_PERMUTE_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_permute_b32")
+ {
+ } // Inst_DS__DS_PERMUTE_B32
+
+ Inst_DS__DS_PERMUTE_B32::~Inst_DS__DS_PERMUTE_B32()
+ {
+ } // ~Inst_DS__DS_PERMUTE_B32
+
+ // Forward permute.
+ void
+ Inst_DS__DS_PERMUTE_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_BPERMUTE_B32::Inst_DS__DS_BPERMUTE_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_bpermute_b32")
+ {
+ } // Inst_DS__DS_BPERMUTE_B32
+
+ Inst_DS__DS_BPERMUTE_B32::~Inst_DS__DS_BPERMUTE_B32()
+ {
+ } // ~Inst_DS__DS_BPERMUTE_B32
+
+ // Backward permute.
+ void
+ Inst_DS__DS_BPERMUTE_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_ADD_U64::Inst_DS__DS_ADD_U64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_add_u64")
+ {
+ } // Inst_DS__DS_ADD_U64
+
+ Inst_DS__DS_ADD_U64::~Inst_DS__DS_ADD_U64()
+ {
+ } // ~Inst_DS__DS_ADD_U64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] += DATA[0:1];
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_DS__DS_ADD_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_SUB_U64::Inst_DS__DS_SUB_U64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_sub_u64")
+ {
+ } // Inst_DS__DS_SUB_U64
+
+ Inst_DS__DS_SUB_U64::~Inst_DS__DS_SUB_U64()
+ {
+ } // ~Inst_DS__DS_SUB_U64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= DATA[0:1];
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_DS__DS_SUB_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_RSUB_U64::Inst_DS__DS_RSUB_U64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_rsub_u64")
+ {
+ } // Inst_DS__DS_RSUB_U64
+
+ Inst_DS__DS_RSUB_U64::~Inst_DS__DS_RSUB_U64()
+ {
+ } // ~Inst_DS__DS_RSUB_U64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = DATA - MEM[ADDR];
+ // RETURN_DATA = tmp.
+ // Subtraction with reversed operands.
+ void
+ Inst_DS__DS_RSUB_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_INC_U64::Inst_DS__DS_INC_U64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_inc_u64")
+ {
+ } // Inst_DS__DS_INC_U64
+
+ Inst_DS__DS_INC_U64::~Inst_DS__DS_INC_U64()
+ {
+ } // ~Inst_DS__DS_INC_U64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (tmp >= DATA[0:1]) ? 0 : tmp + 1 (unsigned compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_DS__DS_INC_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_DEC_U64::Inst_DS__DS_DEC_U64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_dec_u64")
+ {
+ } // Inst_DS__DS_DEC_U64
+
+ Inst_DS__DS_DEC_U64::~Inst_DS__DS_DEC_U64()
+ {
+ } // ~Inst_DS__DS_DEC_U64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (tmp == 0 || tmp > DATA[0:1]) ? DATA[0:1] : tmp - 1
+ // (unsigned compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_DS__DS_DEC_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MIN_I64::Inst_DS__DS_MIN_I64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_min_i64")
+ {
+ } // Inst_DS__DS_MIN_I64
+
+ Inst_DS__DS_MIN_I64::~Inst_DS__DS_MIN_I64()
+ {
+ } // ~Inst_DS__DS_MIN_I64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= (DATA[0:1] < tmp) ? DATA[0:1] : tmp (signed compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_DS__DS_MIN_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MAX_I64::Inst_DS__DS_MAX_I64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_max_i64")
+ {
+ } // Inst_DS__DS_MAX_I64
+
+ Inst_DS__DS_MAX_I64::~Inst_DS__DS_MAX_I64()
+ {
+ } // ~Inst_DS__DS_MAX_I64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= (DATA[0:1] > tmp) ? DATA[0:1] : tmp (signed compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_DS__DS_MAX_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MIN_U64::Inst_DS__DS_MIN_U64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_min_u64")
+ {
+ } // Inst_DS__DS_MIN_U64
+
+ Inst_DS__DS_MIN_U64::~Inst_DS__DS_MIN_U64()
+ {
+ } // ~Inst_DS__DS_MIN_U64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= (DATA[0:1] < tmp) ? DATA[0:1] : tmp (unsigned compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_DS__DS_MIN_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MAX_U64::Inst_DS__DS_MAX_U64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_max_u64")
+ {
+ } // Inst_DS__DS_MAX_U64
+
+ Inst_DS__DS_MAX_U64::~Inst_DS__DS_MAX_U64()
+ {
+ } // ~Inst_DS__DS_MAX_U64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= (DATA[0:1] > tmp) ? DATA[0:1] : tmp (unsigned compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_DS__DS_MAX_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_AND_B64::Inst_DS__DS_AND_B64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_and_b64")
+ {
+ } // Inst_DS__DS_AND_B64
+
+ Inst_DS__DS_AND_B64::~Inst_DS__DS_AND_B64()
+ {
+ } // ~Inst_DS__DS_AND_B64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] &= DATA[0:1];
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_DS__DS_AND_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_OR_B64::Inst_DS__DS_OR_B64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_or_b64")
+ {
+ } // Inst_DS__DS_OR_B64
+
+ Inst_DS__DS_OR_B64::~Inst_DS__DS_OR_B64()
+ {
+ } // ~Inst_DS__DS_OR_B64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] |= DATA[0:1];
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_DS__DS_OR_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_XOR_B64::Inst_DS__DS_XOR_B64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_xor_b64")
+ {
+ } // Inst_DS__DS_XOR_B64
+
+ Inst_DS__DS_XOR_B64::~Inst_DS__DS_XOR_B64()
+ {
+ } // ~Inst_DS__DS_XOR_B64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] ^= DATA[0:1];
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_DS__DS_XOR_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MSKOR_B64::Inst_DS__DS_MSKOR_B64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_mskor_b64")
+ {
+ } // Inst_DS__DS_MSKOR_B64
+
+ Inst_DS__DS_MSKOR_B64::~Inst_DS__DS_MSKOR_B64()
+ {
+ } // ~Inst_DS__DS_MSKOR_B64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (MEM_ADDR[ADDR] & ~DATA) | DATA2;
+ // RETURN_DATA = tmp.
+ void
+ Inst_DS__DS_MSKOR_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_WRITE_B64::Inst_DS__DS_WRITE_B64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_write_b64")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_DS__DS_WRITE_B64
+
+ Inst_DS__DS_WRITE_B64::~Inst_DS__DS_WRITE_B64()
+ {
+ } // ~Inst_DS__DS_WRITE_B64
+
+ // MEM[ADDR] = DATA.
+ // Write qword.
+ void
+ Inst_DS__DS_WRITE_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(
+ gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ ConstVecOperandU64 data(gpuDynInst, extData.DATA0);
+
+ addr.read();
+ data.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ (reinterpret_cast<VecElemU64*>(gpuDynInst->d_data))[lane]
+ = data[lane];
+ }
+ }
+
+ gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
+
+ wf->wrLmReqsInPipe--;
+ wf->outstandingReqsWrLm++;
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ }
+
+ void
+ Inst_DS__DS_WRITE_B64::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ Addr offset0 = instData.OFFSET0;
+ Addr offset1 = instData.OFFSET1;
+ Addr offset = (offset1 << 8) | offset0;
+
+ initMemWrite<VecElemU64>(gpuDynInst, offset);
+ } // initiateAcc
+
+ void
+ Inst_DS__DS_WRITE_B64::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_DS__DS_WRITE2_B64::Inst_DS__DS_WRITE2_B64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_write2_b64")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_DS__DS_WRITE2_B64
+
+ Inst_DS__DS_WRITE2_B64::~Inst_DS__DS_WRITE2_B64()
+ {
+ } // ~Inst_DS__DS_WRITE2_B64
+
+ // MEM[ADDR_BASE + OFFSET0 * 8] = DATA;
+ // MEM[ADDR_BASE + OFFSET1 * 8] = DATA2.
+ // Write 2 qwords.
+ void
+ Inst_DS__DS_WRITE2_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(
+ gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ ConstVecOperandU64 data0(gpuDynInst, extData.DATA0);
+ ConstVecOperandU64 data1(gpuDynInst, extData.DATA1);
+
+ addr.read();
+ data0.read();
+ data1.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ (reinterpret_cast<VecElemU64*>(
+ gpuDynInst->d_data))[lane * 2] = data0[lane];
+ (reinterpret_cast<VecElemU64*>(
+ gpuDynInst->d_data))[lane * 2 + 1] = data1[lane];
+ }
+ }
+
+ gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
+
+ wf->wrLmReqsInPipe--;
+ wf->outstandingReqsWrLm++;
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ }
+
+ void
+ Inst_DS__DS_WRITE2_B64::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ Addr offset0 = instData.OFFSET0 * 8;
+ Addr offset1 = instData.OFFSET1 * 8;
+
+ initDualMemWrite<VecElemU64>(gpuDynInst, offset0, offset1);
+ }
+
+ void
+ Inst_DS__DS_WRITE2_B64::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_DS__DS_WRITE2ST64_B64::Inst_DS__DS_WRITE2ST64_B64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_write2st64_b64")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_DS__DS_WRITE2ST64_B64
+
+ Inst_DS__DS_WRITE2ST64_B64::~Inst_DS__DS_WRITE2ST64_B64()
+ {
+ } // ~Inst_DS__DS_WRITE2ST64_B64
+
+ // MEM[ADDR_BASE + OFFSET0 * 8 * 64] = DATA;
+ // MEM[ADDR_BASE + OFFSET1 * 8 * 64] = DATA2;
+ // Write 2 qwords.
+ void
+ Inst_DS__DS_WRITE2ST64_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_CMPST_B64::Inst_DS__DS_CMPST_B64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_cmpst_b64")
+ {
+ } // Inst_DS__DS_CMPST_B64
+
+ Inst_DS__DS_CMPST_B64::~Inst_DS__DS_CMPST_B64()
+ {
+ } // ~Inst_DS__DS_CMPST_B64
+
+ // tmp = MEM[ADDR];
+ // src = DATA2;
+ // cmp = DATA;
+ // MEM[ADDR] = (tmp == cmp) ? src : tmp;
+ // RETURN_DATA[0] = tmp.
+ // Compare and store.
+ void
+ Inst_DS__DS_CMPST_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_CMPST_F64::Inst_DS__DS_CMPST_F64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_cmpst_f64")
+ {
+ setFlag(F64);
+ } // Inst_DS__DS_CMPST_F64
+
+ Inst_DS__DS_CMPST_F64::~Inst_DS__DS_CMPST_F64()
+ {
+ } // ~Inst_DS__DS_CMPST_F64
+
+ // tmp = MEM[ADDR];
+ // src = DATA2;
+ // cmp = DATA;
+ // MEM[ADDR] = (tmp == cmp) ? src : tmp;
+ // RETURN_DATA[0] = tmp.
+ void
+ Inst_DS__DS_CMPST_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MIN_F64::Inst_DS__DS_MIN_F64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_min_f64")
+ {
+ setFlag(F64);
+ } // Inst_DS__DS_MIN_F64
+
+ Inst_DS__DS_MIN_F64::~Inst_DS__DS_MIN_F64()
+ {
+ } // ~Inst_DS__DS_MIN_F64
+
+ // tmp = MEM[ADDR];
+ // src = DATA;
+ // cmp = DATA2;
+ // MEM[ADDR] = (cmp < tmp) ? src : tmp.
+ void
+ Inst_DS__DS_MIN_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MAX_F64::Inst_DS__DS_MAX_F64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_max_f64")
+ {
+ setFlag(F64);
+ } // Inst_DS__DS_MAX_F64
+
+ Inst_DS__DS_MAX_F64::~Inst_DS__DS_MAX_F64()
+ {
+ } // ~Inst_DS__DS_MAX_F64
+
+ // tmp = MEM[ADDR];
+ // src = DATA;
+ // cmp = DATA2;
+ // MEM[ADDR] = (tmp > cmp) ? src : tmp.
+ void
+ Inst_DS__DS_MAX_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_ADD_RTN_U64::Inst_DS__DS_ADD_RTN_U64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_add_rtn_u64")
+ {
+ } // Inst_DS__DS_ADD_RTN_U64
+
+ Inst_DS__DS_ADD_RTN_U64::~Inst_DS__DS_ADD_RTN_U64()
+ {
+ } // ~Inst_DS__DS_ADD_RTN_U64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] += DATA[0:1];
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_DS__DS_ADD_RTN_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_SUB_RTN_U64::Inst_DS__DS_SUB_RTN_U64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_sub_rtn_u64")
+ {
+ } // Inst_DS__DS_SUB_RTN_U64
+
+ Inst_DS__DS_SUB_RTN_U64::~Inst_DS__DS_SUB_RTN_U64()
+ {
+ } // ~Inst_DS__DS_SUB_RTN_U64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= DATA[0:1];
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_DS__DS_SUB_RTN_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_RSUB_RTN_U64::Inst_DS__DS_RSUB_RTN_U64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_rsub_rtn_u64")
+ {
+ } // Inst_DS__DS_RSUB_RTN_U64
+
+ Inst_DS__DS_RSUB_RTN_U64::~Inst_DS__DS_RSUB_RTN_U64()
+ {
+ } // ~Inst_DS__DS_RSUB_RTN_U64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = DATA - MEM[ADDR];
+ // RETURN_DATA = tmp.
+ // Subtraction with reversed operands.
+ void
+ Inst_DS__DS_RSUB_RTN_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_INC_RTN_U64::Inst_DS__DS_INC_RTN_U64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_inc_rtn_u64")
+ {
+ } // Inst_DS__DS_INC_RTN_U64
+
+ Inst_DS__DS_INC_RTN_U64::~Inst_DS__DS_INC_RTN_U64()
+ {
+ } // ~Inst_DS__DS_INC_RTN_U64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (tmp >= DATA[0:1]) ? 0 : tmp + 1 (unsigned compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_DS__DS_INC_RTN_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_DEC_RTN_U64::Inst_DS__DS_DEC_RTN_U64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_dec_rtn_u64")
+ {
+ } // Inst_DS__DS_DEC_RTN_U64
+
+ Inst_DS__DS_DEC_RTN_U64::~Inst_DS__DS_DEC_RTN_U64()
+ {
+ } // ~Inst_DS__DS_DEC_RTN_U64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (tmp == 0 || tmp > DATA[0:1]) ? DATA[0:1] : tmp - 1
+ // (unsigned compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_DS__DS_DEC_RTN_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MIN_RTN_I64::Inst_DS__DS_MIN_RTN_I64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_min_rtn_i64")
+ {
+ } // Inst_DS__DS_MIN_RTN_I64
+
+ Inst_DS__DS_MIN_RTN_I64::~Inst_DS__DS_MIN_RTN_I64()
+ {
+ } // ~Inst_DS__DS_MIN_RTN_I64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= (DATA[0:1] < tmp) ? DATA[0:1] : tmp (signed compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_DS__DS_MIN_RTN_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MAX_RTN_I64::Inst_DS__DS_MAX_RTN_I64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_max_rtn_i64")
+ {
+ } // Inst_DS__DS_MAX_RTN_I64
+
+ Inst_DS__DS_MAX_RTN_I64::~Inst_DS__DS_MAX_RTN_I64()
+ {
+ } // ~Inst_DS__DS_MAX_RTN_I64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= (DATA[0:1] > tmp) ? DATA[0:1] : tmp (signed compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_DS__DS_MAX_RTN_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MIN_RTN_U64::Inst_DS__DS_MIN_RTN_U64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_min_rtn_u64")
+ {
+ } // Inst_DS__DS_MIN_RTN_U64
+
+ Inst_DS__DS_MIN_RTN_U64::~Inst_DS__DS_MIN_RTN_U64()
+ {
+ } // ~Inst_DS__DS_MIN_RTN_U64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= (DATA[0:1] < tmp) ? DATA[0:1] : tmp (unsigned compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_DS__DS_MIN_RTN_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MAX_RTN_U64::Inst_DS__DS_MAX_RTN_U64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_max_rtn_u64")
+ {
+ } // Inst_DS__DS_MAX_RTN_U64
+
+ Inst_DS__DS_MAX_RTN_U64::~Inst_DS__DS_MAX_RTN_U64()
+ {
+ } // ~Inst_DS__DS_MAX_RTN_U64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= (DATA[0:1] > tmp) ? DATA[0:1] : tmp (unsigned compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_DS__DS_MAX_RTN_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_AND_RTN_B64::Inst_DS__DS_AND_RTN_B64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_and_rtn_b64")
+ {
+ } // Inst_DS__DS_AND_RTN_B64
+
+ Inst_DS__DS_AND_RTN_B64::~Inst_DS__DS_AND_RTN_B64()
+ {
+ } // ~Inst_DS__DS_AND_RTN_B64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] &= DATA[0:1];
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_DS__DS_AND_RTN_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_OR_RTN_B64::Inst_DS__DS_OR_RTN_B64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_or_rtn_b64")
+ {
+ } // Inst_DS__DS_OR_RTN_B64
+
+ Inst_DS__DS_OR_RTN_B64::~Inst_DS__DS_OR_RTN_B64()
+ {
+ } // ~Inst_DS__DS_OR_RTN_B64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] |= DATA[0:1];
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_DS__DS_OR_RTN_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_XOR_RTN_B64::Inst_DS__DS_XOR_RTN_B64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_xor_rtn_b64")
+ {
+ } // Inst_DS__DS_XOR_RTN_B64
+
+ Inst_DS__DS_XOR_RTN_B64::~Inst_DS__DS_XOR_RTN_B64()
+ {
+ } // ~Inst_DS__DS_XOR_RTN_B64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] ^= DATA[0:1];
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_DS__DS_XOR_RTN_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MSKOR_RTN_B64::Inst_DS__DS_MSKOR_RTN_B64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_mskor_rtn_b64")
+ {
+ } // Inst_DS__DS_MSKOR_RTN_B64
+
+ Inst_DS__DS_MSKOR_RTN_B64::~Inst_DS__DS_MSKOR_RTN_B64()
+ {
+ } // ~Inst_DS__DS_MSKOR_RTN_B64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (MEM_ADDR[ADDR] & ~DATA) | DATA2;
+ // RETURN_DATA = tmp.
+ // Masked dword OR, D0 contains the mask and D1 contains the new value.
+ void
+ Inst_DS__DS_MSKOR_RTN_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_WRXCHG_RTN_B64::Inst_DS__DS_WRXCHG_RTN_B64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_wrxchg_rtn_b64")
+ {
+ } // Inst_DS__DS_WRXCHG_RTN_B64
+
+ Inst_DS__DS_WRXCHG_RTN_B64::~Inst_DS__DS_WRXCHG_RTN_B64()
+ {
+ } // ~Inst_DS__DS_WRXCHG_RTN_B64
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = DATA;
+ // RETURN_DATA = tmp.
+ // Write-exchange operation.
+ void
+ Inst_DS__DS_WRXCHG_RTN_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_WRXCHG2_RTN_B64::Inst_DS__DS_WRXCHG2_RTN_B64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_wrxchg2_rtn_b64")
+ {
+ } // Inst_DS__DS_WRXCHG2_RTN_B64
+
+ Inst_DS__DS_WRXCHG2_RTN_B64::~Inst_DS__DS_WRXCHG2_RTN_B64()
+ {
+ } // ~Inst_DS__DS_WRXCHG2_RTN_B64
+
+ // Write-exchange 2 separate qwords.
+ void
+ Inst_DS__DS_WRXCHG2_RTN_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_WRXCHG2ST64_RTN_B64::Inst_DS__DS_WRXCHG2ST64_RTN_B64(
+ InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_wrxchg2st64_rtn_b64")
+ {
+ } // Inst_DS__DS_WRXCHG2ST64_RTN_B64
+
+ Inst_DS__DS_WRXCHG2ST64_RTN_B64::~Inst_DS__DS_WRXCHG2ST64_RTN_B64()
+ {
+ } // ~Inst_DS__DS_WRXCHG2ST64_RTN_B64
+
+ // Write-exchange 2 qwords with a stride of 64 qwords.
+ void
+ Inst_DS__DS_WRXCHG2ST64_RTN_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_CMPST_RTN_B64::Inst_DS__DS_CMPST_RTN_B64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_cmpst_rtn_b64")
+ {
+ } // Inst_DS__DS_CMPST_RTN_B64
+
+ Inst_DS__DS_CMPST_RTN_B64::~Inst_DS__DS_CMPST_RTN_B64()
+ {
+ } // ~Inst_DS__DS_CMPST_RTN_B64
+
+ // tmp = MEM[ADDR];
+ // src = DATA2;
+ // cmp = DATA;
+ // MEM[ADDR] = (tmp == cmp) ? src : tmp;
+ // RETURN_DATA[0] = tmp.
+ // Compare and store.
+ void
+ Inst_DS__DS_CMPST_RTN_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_CMPST_RTN_F64::Inst_DS__DS_CMPST_RTN_F64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_cmpst_rtn_f64")
+ {
+ setFlag(F64);
+ } // Inst_DS__DS_CMPST_RTN_F64
+
+ Inst_DS__DS_CMPST_RTN_F64::~Inst_DS__DS_CMPST_RTN_F64()
+ {
+ } // ~Inst_DS__DS_CMPST_RTN_F64
+
+ // tmp = MEM[ADDR];
+ // src = DATA2;
+ // cmp = DATA;
+ // MEM[ADDR] = (tmp == cmp) ? src : tmp;
+ // RETURN_DATA[0] = tmp.
+ void
+ Inst_DS__DS_CMPST_RTN_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MIN_RTN_F64::Inst_DS__DS_MIN_RTN_F64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_min_rtn_f64")
+ {
+ setFlag(F64);
+ } // Inst_DS__DS_MIN_RTN_F64
+
+ Inst_DS__DS_MIN_RTN_F64::~Inst_DS__DS_MIN_RTN_F64()
+ {
+ } // ~Inst_DS__DS_MIN_RTN_F64
+
+ // tmp = MEM[ADDR];
+ // src = DATA;
+ // cmp = DATA2;
+ // MEM[ADDR] = (cmp < tmp) ? src : tmp.
+ void
+ Inst_DS__DS_MIN_RTN_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MAX_RTN_F64::Inst_DS__DS_MAX_RTN_F64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_max_rtn_f64")
+ {
+ setFlag(F64);
+ } // Inst_DS__DS_MAX_RTN_F64
+
+ Inst_DS__DS_MAX_RTN_F64::~Inst_DS__DS_MAX_RTN_F64()
+ {
+ } // ~Inst_DS__DS_MAX_RTN_F64
+
+ // tmp = MEM[ADDR];
+ // src = DATA;
+ // cmp = DATA2;
+ // MEM[ADDR] = (tmp > cmp) ? src : tmp.
+ void
+ Inst_DS__DS_MAX_RTN_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_READ_B64::Inst_DS__DS_READ_B64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_read_b64")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_DS__DS_READ_B64
+
+ Inst_DS__DS_READ_B64::~Inst_DS__DS_READ_B64()
+ {
+ } // ~Inst_DS__DS_READ_B64
+
+ // RETURN_DATA = MEM[ADDR].
+ // Read 1 qword.
+ void
+ Inst_DS__DS_READ_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(
+ gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
+
+ wf->rdLmReqsInPipe--;
+ wf->outstandingReqsRdLm++;
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ }
+
+ void
+ Inst_DS__DS_READ_B64::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ Addr offset0 = instData.OFFSET0;
+ Addr offset1 = instData.OFFSET1;
+ Addr offset = (offset1 << 8) | offset0;
+
+ initMemRead<VecElemU64>(gpuDynInst, offset);
+ } // initiateAcc
+
+ void
+ Inst_DS__DS_READ_B64::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ VecOperandU64 vdst(gpuDynInst, extData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ vdst[lane] = (reinterpret_cast<VecElemU64*>(
+ gpuDynInst->d_data))[lane];
+ }
+ }
+
+ vdst.write();
+ } // completeAcc
+
+ Inst_DS__DS_READ2_B64::Inst_DS__DS_READ2_B64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_read2_b64")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_DS__DS_READ2_B64
+
+ Inst_DS__DS_READ2_B64::~Inst_DS__DS_READ2_B64()
+ {
+ } // ~Inst_DS__DS_READ2_B64
+
+ // RETURN_DATA[0] = MEM[ADDR_BASE + OFFSET0 * 8];
+ // RETURN_DATA[1] = MEM[ADDR_BASE + OFFSET1 * 8].
+ // Read 2 qwords.
+ void
+ Inst_DS__DS_READ2_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(
+ gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
+
+ wf->rdLmReqsInPipe--;
+ wf->outstandingReqsRdLm++;
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ }
+
+ void
+ Inst_DS__DS_READ2_B64::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ Addr offset0 = instData.OFFSET0 * 8;
+ Addr offset1 = instData.OFFSET1 * 8;
+
+ initDualMemRead<VecElemU64>(gpuDynInst, offset0, offset1);
+ } // initiateAcc
+
+ void
+ Inst_DS__DS_READ2_B64::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ VecOperandU64 vdst0(gpuDynInst, extData.VDST);
+ VecOperandU64 vdst1(gpuDynInst, extData.VDST + 2);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ vdst0[lane] = (reinterpret_cast<VecElemU64*>(
+ gpuDynInst->d_data))[lane * 2];
+ vdst1[lane] = (reinterpret_cast<VecElemU64*>(
+ gpuDynInst->d_data))[lane * 2 + 1];
+ }
+ }
+
+ vdst0.write();
+ vdst1.write();
+ } // completeAcc
+
+ Inst_DS__DS_READ2ST64_B64::Inst_DS__DS_READ2ST64_B64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_read2st64_b64")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_DS__DS_READ2ST64_B64
+
+ Inst_DS__DS_READ2ST64_B64::~Inst_DS__DS_READ2ST64_B64()
+ {
+ } // ~Inst_DS__DS_READ2ST64_B64
+
+ // RETURN_DATA[0] = MEM[ADDR_BASE + OFFSET0 * 8 * 64];
+ // RETURN_DATA[1] = MEM[ADDR_BASE + OFFSET1 * 8 * 64].
+ // Read 2 qwords.
+ void
+ Inst_DS__DS_READ2ST64_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(
+ gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
+
+ wf->rdLmReqsInPipe--;
+ wf->outstandingReqsRdLm++;
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ }
+
+ void
+ Inst_DS__DS_READ2ST64_B64::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ Addr offset0 = (instData.OFFSET0 * 8 * 64);
+ Addr offset1 = (instData.OFFSET1 * 8 * 64);
+
+ initDualMemRead<VecElemU64>(gpuDynInst, offset0, offset1);
+ }
+
+ void
+ Inst_DS__DS_READ2ST64_B64::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ VecOperandU64 vdst0(gpuDynInst, extData.VDST);
+ VecOperandU64 vdst1(gpuDynInst, extData.VDST + 2);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ vdst0[lane] = (reinterpret_cast<VecElemU64*>(
+ gpuDynInst->d_data))[lane * 2];
+ vdst1[lane] = (reinterpret_cast<VecElemU64*>(
+ gpuDynInst->d_data))[lane * 2 + 1];
+ }
+ }
+
+ vdst0.write();
+ vdst1.write();
+ }
+
+ Inst_DS__DS_CONDXCHG32_RTN_B64::Inst_DS__DS_CONDXCHG32_RTN_B64(
+ InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_condxchg32_rtn_b64")
+ {
+ } // Inst_DS__DS_CONDXCHG32_RTN_B64
+
+ Inst_DS__DS_CONDXCHG32_RTN_B64::~Inst_DS__DS_CONDXCHG32_RTN_B64()
+ {
+ } // ~Inst_DS__DS_CONDXCHG32_RTN_B64
+
+ // Conditional write exchange.
+ void
+ Inst_DS__DS_CONDXCHG32_RTN_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_ADD_SRC2_U32::Inst_DS__DS_ADD_SRC2_U32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_add_src2_u32")
+ {
+ } // Inst_DS__DS_ADD_SRC2_U32
+
+ Inst_DS__DS_ADD_SRC2_U32::~Inst_DS__DS_ADD_SRC2_U32()
+ {
+ } // ~Inst_DS__DS_ADD_SRC2_U32
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = MEM[A] + MEM[B].
+ void
+ Inst_DS__DS_ADD_SRC2_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_SUB_SRC2_U32::Inst_DS__DS_SUB_SRC2_U32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_sub_src2_u32")
+ {
+ } // Inst_DS__DS_SUB_SRC2_U32
+
+ Inst_DS__DS_SUB_SRC2_U32::~Inst_DS__DS_SUB_SRC2_U32()
+ {
+ } // ~Inst_DS__DS_SUB_SRC2_U32
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = MEM[A] - MEM[B].
+ void
+ Inst_DS__DS_SUB_SRC2_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_RSUB_SRC2_U32::Inst_DS__DS_RSUB_SRC2_U32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_rsub_src2_u32")
+ {
+ } // Inst_DS__DS_RSUB_SRC2_U32
+
+ Inst_DS__DS_RSUB_SRC2_U32::~Inst_DS__DS_RSUB_SRC2_U32()
+ {
+ } // ~Inst_DS__DS_RSUB_SRC2_U32
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = MEM[B] - MEM[A].
+ void
+ Inst_DS__DS_RSUB_SRC2_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_INC_SRC2_U32::Inst_DS__DS_INC_SRC2_U32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_inc_src2_u32")
+ {
+ } // Inst_DS__DS_INC_SRC2_U32
+
+ Inst_DS__DS_INC_SRC2_U32::~Inst_DS__DS_INC_SRC2_U32()
+ {
+ } // ~Inst_DS__DS_INC_SRC2_U32
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = (MEM[A] >= MEM[B] ? 0 : MEM[A] + 1).
+ void
+ Inst_DS__DS_INC_SRC2_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_DEC_SRC2_U32::Inst_DS__DS_DEC_SRC2_U32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_dec_src2_u32")
+ {
+ } // Inst_DS__DS_DEC_SRC2_U32
+
+ Inst_DS__DS_DEC_SRC2_U32::~Inst_DS__DS_DEC_SRC2_U32()
+ {
+ } // ~Inst_DS__DS_DEC_SRC2_U32
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = (MEM[A] == 0 || MEM[A] > MEM[B] ? MEM[B] : MEM[A] - 1).
+ // Uint decrement.
+ void
+ Inst_DS__DS_DEC_SRC2_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MIN_SRC2_I32::Inst_DS__DS_MIN_SRC2_I32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_min_src2_i32")
+ {
+ } // Inst_DS__DS_MIN_SRC2_I32
+
+ Inst_DS__DS_MIN_SRC2_I32::~Inst_DS__DS_MIN_SRC2_I32()
+ {
+ } // ~Inst_DS__DS_MIN_SRC2_I32
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = min(MEM[A], MEM[B]).
+ void
+ Inst_DS__DS_MIN_SRC2_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MAX_SRC2_I32::Inst_DS__DS_MAX_SRC2_I32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_max_src2_i32")
+ {
+ } // Inst_DS__DS_MAX_SRC2_I32
+
+ Inst_DS__DS_MAX_SRC2_I32::~Inst_DS__DS_MAX_SRC2_I32()
+ {
+ } // ~Inst_DS__DS_MAX_SRC2_I32
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = max(MEM[A], MEM[B]).
+ void
+ Inst_DS__DS_MAX_SRC2_I32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MIN_SRC2_U32::Inst_DS__DS_MIN_SRC2_U32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_min_src2_u32")
+ {
+ } // Inst_DS__DS_MIN_SRC2_U32
+
+ Inst_DS__DS_MIN_SRC2_U32::~Inst_DS__DS_MIN_SRC2_U32()
+ {
+ } // ~Inst_DS__DS_MIN_SRC2_U32
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = min(MEM[A], MEM[B]).
+ void
+ Inst_DS__DS_MIN_SRC2_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MAX_SRC2_U32::Inst_DS__DS_MAX_SRC2_U32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_max_src2_u32")
+ {
+ } // Inst_DS__DS_MAX_SRC2_U32
+
+ Inst_DS__DS_MAX_SRC2_U32::~Inst_DS__DS_MAX_SRC2_U32()
+ {
+ } // ~Inst_DS__DS_MAX_SRC2_U32
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = max(MEM[A], MEM[B]).
+ void
+ Inst_DS__DS_MAX_SRC2_U32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_AND_SRC2_B32::Inst_DS__DS_AND_SRC2_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_and_src2_b32")
+ {
+ } // Inst_DS__DS_AND_SRC2_B32
+
+ Inst_DS__DS_AND_SRC2_B32::~Inst_DS__DS_AND_SRC2_B32()
+ {
+ } // ~Inst_DS__DS_AND_SRC2_B32
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = MEM[A] & MEM[B].
+ void
+ Inst_DS__DS_AND_SRC2_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_OR_SRC2_B32::Inst_DS__DS_OR_SRC2_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_or_src2_b32")
+ {
+ } // Inst_DS__DS_OR_SRC2_B32
+
+ Inst_DS__DS_OR_SRC2_B32::~Inst_DS__DS_OR_SRC2_B32()
+ {
+ } // ~Inst_DS__DS_OR_SRC2_B32
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = MEM[A] | MEM[B].
+ void
+ Inst_DS__DS_OR_SRC2_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_XOR_SRC2_B32::Inst_DS__DS_XOR_SRC2_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_xor_src2_b32")
+ {
+ } // Inst_DS__DS_XOR_SRC2_B32
+
+ Inst_DS__DS_XOR_SRC2_B32::~Inst_DS__DS_XOR_SRC2_B32()
+ {
+ } // ~Inst_DS__DS_XOR_SRC2_B32
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = MEM[A] ^ MEM[B].
+ void
+ Inst_DS__DS_XOR_SRC2_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_WRITE_SRC2_B32::Inst_DS__DS_WRITE_SRC2_B32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_write_src2_b32")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_DS__DS_WRITE_SRC2_B32
+
+ Inst_DS__DS_WRITE_SRC2_B32::~Inst_DS__DS_WRITE_SRC2_B32()
+ {
+ } // ~Inst_DS__DS_WRITE_SRC2_B32
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = MEM[B].
+ // Write dword.
+ void
+ Inst_DS__DS_WRITE_SRC2_B32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MIN_SRC2_F32::Inst_DS__DS_MIN_SRC2_F32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_min_src2_f32")
+ {
+ setFlag(F32);
+ } // Inst_DS__DS_MIN_SRC2_F32
+
+ Inst_DS__DS_MIN_SRC2_F32::~Inst_DS__DS_MIN_SRC2_F32()
+ {
+ } // ~Inst_DS__DS_MIN_SRC2_F32
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = (MEM[B] < MEM[A]) ? MEM[B] : MEM[A].
+ void
+ Inst_DS__DS_MIN_SRC2_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MAX_SRC2_F32::Inst_DS__DS_MAX_SRC2_F32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_max_src2_f32")
+ {
+ setFlag(F32);
+ } // Inst_DS__DS_MAX_SRC2_F32
+
+ Inst_DS__DS_MAX_SRC2_F32::~Inst_DS__DS_MAX_SRC2_F32()
+ {
+ } // ~Inst_DS__DS_MAX_SRC2_F32
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = (MEM[B] > MEM[A]) ? MEM[B] : MEM[A].
+ void
+ Inst_DS__DS_MAX_SRC2_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_ADD_SRC2_F32::Inst_DS__DS_ADD_SRC2_F32(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_add_src2_f32")
+ {
+ setFlag(F32);
+ } // Inst_DS__DS_ADD_SRC2_F32
+
+ Inst_DS__DS_ADD_SRC2_F32::~Inst_DS__DS_ADD_SRC2_F32()
+ {
+ } // ~Inst_DS__DS_ADD_SRC2_F32
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = MEM[B] + MEM[A].
+ void
+ Inst_DS__DS_ADD_SRC2_F32::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_GWS_SEMA_RELEASE_ALL::Inst_DS__DS_GWS_SEMA_RELEASE_ALL(
+ InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_gws_sema_release_all")
+ {
+ } // Inst_DS__DS_GWS_SEMA_RELEASE_ALL
+
+ Inst_DS__DS_GWS_SEMA_RELEASE_ALL::~Inst_DS__DS_GWS_SEMA_RELEASE_ALL()
+ {
+ } // ~Inst_DS__DS_GWS_SEMA_RELEASE_ALL
+
+ void
+ Inst_DS__DS_GWS_SEMA_RELEASE_ALL::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_GWS_INIT::Inst_DS__DS_GWS_INIT(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_gws_init")
+ {
+ } // Inst_DS__DS_GWS_INIT
+
+ Inst_DS__DS_GWS_INIT::~Inst_DS__DS_GWS_INIT()
+ {
+ } // ~Inst_DS__DS_GWS_INIT
+
+ void
+ Inst_DS__DS_GWS_INIT::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_GWS_SEMA_V::Inst_DS__DS_GWS_SEMA_V(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_gws_sema_v")
+ {
+ } // Inst_DS__DS_GWS_SEMA_V
+
+ Inst_DS__DS_GWS_SEMA_V::~Inst_DS__DS_GWS_SEMA_V()
+ {
+ } // ~Inst_DS__DS_GWS_SEMA_V
+
+ void
+ Inst_DS__DS_GWS_SEMA_V::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_GWS_SEMA_BR::Inst_DS__DS_GWS_SEMA_BR(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_gws_sema_br")
+ {
+ } // Inst_DS__DS_GWS_SEMA_BR
+
+ Inst_DS__DS_GWS_SEMA_BR::~Inst_DS__DS_GWS_SEMA_BR()
+ {
+ } // ~Inst_DS__DS_GWS_SEMA_BR
+
+ void
+ Inst_DS__DS_GWS_SEMA_BR::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_GWS_SEMA_P::Inst_DS__DS_GWS_SEMA_P(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_gws_sema_p")
+ {
+ } // Inst_DS__DS_GWS_SEMA_P
+
+ Inst_DS__DS_GWS_SEMA_P::~Inst_DS__DS_GWS_SEMA_P()
+ {
+ } // ~Inst_DS__DS_GWS_SEMA_P
+
+ void
+ Inst_DS__DS_GWS_SEMA_P::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_GWS_BARRIER::Inst_DS__DS_GWS_BARRIER(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_gws_barrier")
+ {
+ } // Inst_DS__DS_GWS_BARRIER
+
+ Inst_DS__DS_GWS_BARRIER::~Inst_DS__DS_GWS_BARRIER()
+ {
+ } // ~Inst_DS__DS_GWS_BARRIER
+
+ void
+ Inst_DS__DS_GWS_BARRIER::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_CONSUME::Inst_DS__DS_CONSUME(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_consume")
+ {
+ } // Inst_DS__DS_CONSUME
+
+ Inst_DS__DS_CONSUME::~Inst_DS__DS_CONSUME()
+ {
+ } // ~Inst_DS__DS_CONSUME
+
+ void
+ Inst_DS__DS_CONSUME::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_APPEND::Inst_DS__DS_APPEND(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_append")
+ {
+ } // Inst_DS__DS_APPEND
+
+ Inst_DS__DS_APPEND::~Inst_DS__DS_APPEND()
+ {
+ } // ~Inst_DS__DS_APPEND
+
+ void
+ Inst_DS__DS_APPEND::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_ORDERED_COUNT::Inst_DS__DS_ORDERED_COUNT(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_ordered_count")
+ {
+ } // Inst_DS__DS_ORDERED_COUNT
+
+ Inst_DS__DS_ORDERED_COUNT::~Inst_DS__DS_ORDERED_COUNT()
+ {
+ } // ~Inst_DS__DS_ORDERED_COUNT
+
+ void
+ Inst_DS__DS_ORDERED_COUNT::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_ADD_SRC2_U64::Inst_DS__DS_ADD_SRC2_U64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_add_src2_u64")
+ {
+ } // Inst_DS__DS_ADD_SRC2_U64
+
+ Inst_DS__DS_ADD_SRC2_U64::~Inst_DS__DS_ADD_SRC2_U64()
+ {
+ } // ~Inst_DS__DS_ADD_SRC2_U64
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = MEM[A] + MEM[B].
+ void
+ Inst_DS__DS_ADD_SRC2_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_SUB_SRC2_U64::Inst_DS__DS_SUB_SRC2_U64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_sub_src2_u64")
+ {
+ } // Inst_DS__DS_SUB_SRC2_U64
+
+ Inst_DS__DS_SUB_SRC2_U64::~Inst_DS__DS_SUB_SRC2_U64()
+ {
+ } // ~Inst_DS__DS_SUB_SRC2_U64
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = MEM[A] - MEM[B].
+ void
+ Inst_DS__DS_SUB_SRC2_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_RSUB_SRC2_U64::Inst_DS__DS_RSUB_SRC2_U64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_rsub_src2_u64")
+ {
+ } // Inst_DS__DS_RSUB_SRC2_U64
+
+ Inst_DS__DS_RSUB_SRC2_U64::~Inst_DS__DS_RSUB_SRC2_U64()
+ {
+ } // ~Inst_DS__DS_RSUB_SRC2_U64
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = MEM[B] - MEM[A].
+ void
+ Inst_DS__DS_RSUB_SRC2_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_INC_SRC2_U64::Inst_DS__DS_INC_SRC2_U64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_inc_src2_u64")
+ {
+ } // Inst_DS__DS_INC_SRC2_U64
+
+ Inst_DS__DS_INC_SRC2_U64::~Inst_DS__DS_INC_SRC2_U64()
+ {
+ } // ~Inst_DS__DS_INC_SRC2_U64
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = (MEM[A] >= MEM[B] ? 0 : MEM[A] + 1).
+ void
+ Inst_DS__DS_INC_SRC2_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_DEC_SRC2_U64::Inst_DS__DS_DEC_SRC2_U64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_dec_src2_u64")
+ {
+ } // Inst_DS__DS_DEC_SRC2_U64
+
+ Inst_DS__DS_DEC_SRC2_U64::~Inst_DS__DS_DEC_SRC2_U64()
+ {
+ } // ~Inst_DS__DS_DEC_SRC2_U64
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = (MEM[A] == 0 || MEM[A] > MEM[B] ? MEM[B] : MEM[A] - 1).
+ // Uint decrement.
+ void
+ Inst_DS__DS_DEC_SRC2_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MIN_SRC2_I64::Inst_DS__DS_MIN_SRC2_I64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_min_src2_i64")
+ {
+ } // Inst_DS__DS_MIN_SRC2_I64
+
+ Inst_DS__DS_MIN_SRC2_I64::~Inst_DS__DS_MIN_SRC2_I64()
+ {
+ } // ~Inst_DS__DS_MIN_SRC2_I64
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = min(MEM[A], MEM[B]).
+ void
+ Inst_DS__DS_MIN_SRC2_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MAX_SRC2_I64::Inst_DS__DS_MAX_SRC2_I64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_max_src2_i64")
+ {
+ } // Inst_DS__DS_MAX_SRC2_I64
+
+ Inst_DS__DS_MAX_SRC2_I64::~Inst_DS__DS_MAX_SRC2_I64()
+ {
+ } // ~Inst_DS__DS_MAX_SRC2_I64
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = max(MEM[A], MEM[B]).
+ void
+ Inst_DS__DS_MAX_SRC2_I64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MIN_SRC2_U64::Inst_DS__DS_MIN_SRC2_U64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_min_src2_u64")
+ {
+ } // Inst_DS__DS_MIN_SRC2_U64
+
+ Inst_DS__DS_MIN_SRC2_U64::~Inst_DS__DS_MIN_SRC2_U64()
+ {
+ } // ~Inst_DS__DS_MIN_SRC2_U64
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = min(MEM[A], MEM[B]).
+ void
+ Inst_DS__DS_MIN_SRC2_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MAX_SRC2_U64::Inst_DS__DS_MAX_SRC2_U64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_max_src2_u64")
+ {
+ } // Inst_DS__DS_MAX_SRC2_U64
+
+ Inst_DS__DS_MAX_SRC2_U64::~Inst_DS__DS_MAX_SRC2_U64()
+ {
+ } // ~Inst_DS__DS_MAX_SRC2_U64
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = max(MEM[A], MEM[B]).
+ void
+ Inst_DS__DS_MAX_SRC2_U64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_AND_SRC2_B64::Inst_DS__DS_AND_SRC2_B64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_and_src2_b64")
+ {
+ } // Inst_DS__DS_AND_SRC2_B64
+
+ Inst_DS__DS_AND_SRC2_B64::~Inst_DS__DS_AND_SRC2_B64()
+ {
+ } // ~Inst_DS__DS_AND_SRC2_B64
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = MEM[A] & MEM[B].
+ void
+ Inst_DS__DS_AND_SRC2_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_OR_SRC2_B64::Inst_DS__DS_OR_SRC2_B64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_or_src2_b64")
+ {
+ } // Inst_DS__DS_OR_SRC2_B64
+
+ Inst_DS__DS_OR_SRC2_B64::~Inst_DS__DS_OR_SRC2_B64()
+ {
+ } // ~Inst_DS__DS_OR_SRC2_B64
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = MEM[A] | MEM[B].
+ void
+ Inst_DS__DS_OR_SRC2_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_XOR_SRC2_B64::Inst_DS__DS_XOR_SRC2_B64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_xor_src2_b64")
+ {
+ } // Inst_DS__DS_XOR_SRC2_B64
+
+ Inst_DS__DS_XOR_SRC2_B64::~Inst_DS__DS_XOR_SRC2_B64()
+ {
+ } // ~Inst_DS__DS_XOR_SRC2_B64
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = MEM[A] ^ MEM[B].
+ void
+ Inst_DS__DS_XOR_SRC2_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_WRITE_SRC2_B64::Inst_DS__DS_WRITE_SRC2_B64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_write_src2_b64")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_DS__DS_WRITE_SRC2_B64
+
+ Inst_DS__DS_WRITE_SRC2_B64::~Inst_DS__DS_WRITE_SRC2_B64()
+ {
+ } // ~Inst_DS__DS_WRITE_SRC2_B64
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = MEM[B].
+ // Write qword.
+ void
+ Inst_DS__DS_WRITE_SRC2_B64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MIN_SRC2_F64::Inst_DS__DS_MIN_SRC2_F64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_min_src2_f64")
+ {
+ setFlag(F64);
+ } // Inst_DS__DS_MIN_SRC2_F64
+
+ Inst_DS__DS_MIN_SRC2_F64::~Inst_DS__DS_MIN_SRC2_F64()
+ {
+ } // ~Inst_DS__DS_MIN_SRC2_F64
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = (MEM[B] < MEM[A]) ? MEM[B] : MEM[A].
+ void
+ Inst_DS__DS_MIN_SRC2_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_MAX_SRC2_F64::Inst_DS__DS_MAX_SRC2_F64(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_max_src2_f64")
+ {
+ setFlag(F64);
+ } // Inst_DS__DS_MAX_SRC2_F64
+
+ Inst_DS__DS_MAX_SRC2_F64::~Inst_DS__DS_MAX_SRC2_F64()
+ {
+ } // ~Inst_DS__DS_MAX_SRC2_F64
+
+ // A = ADDR_BASE;
+ // B = A + 4*(offset1[7] ? {A[31],A[31:17]} :
+ // {offset1[6],offset1[6:0],offset0});
+ // MEM[A] = (MEM[B] > MEM[A]) ? MEM[B] : MEM[A].
+ void
+ Inst_DS__DS_MAX_SRC2_F64::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_WRITE_B96::Inst_DS__DS_WRITE_B96(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_write_b96")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_DS__DS_WRITE_B96
+
+ Inst_DS__DS_WRITE_B96::~Inst_DS__DS_WRITE_B96()
+ {
+ } // ~Inst_DS__DS_WRITE_B96
+
+ // {MEM[ADDR + 8], MEM[ADDR + 4], MEM[ADDR]} = DATA[95:0].
+ // Tri-dword write.
+ void
+ Inst_DS__DS_WRITE_B96::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_WRITE_B128::Inst_DS__DS_WRITE_B128(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_write_b128")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_DS__DS_WRITE_B128
+
+ Inst_DS__DS_WRITE_B128::~Inst_DS__DS_WRITE_B128()
+ {
+ } // ~Inst_DS__DS_WRITE_B128
+
+ // {MEM[ADDR + 12], MEM[ADDR + 8], MEM[ADDR + 4], MEM[ADDR]} = DATA[127:0].
+ // Qword write.
+ void
+ Inst_DS__DS_WRITE_B128::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_READ_B96::Inst_DS__DS_READ_B96(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_read_b96")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_DS__DS_READ_B96
+
+ Inst_DS__DS_READ_B96::~Inst_DS__DS_READ_B96()
+ {
+ } // ~Inst_DS__DS_READ_B96
+
+ // Tri-dword read.
+ void
+ Inst_DS__DS_READ_B96::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_DS__DS_READ_B128::Inst_DS__DS_READ_B128(InFmt_DS *iFmt)
+ : Inst_DS(iFmt, "ds_read_b128")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_DS__DS_READ_B128
+
+ Inst_DS__DS_READ_B128::~Inst_DS__DS_READ_B128()
+ {
+ } // ~Inst_DS__DS_READ_B128
+
+ // Qword read.
+ void
+ Inst_DS__DS_READ_B128::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_X
+ ::Inst_MUBUF__BUFFER_LOAD_FORMAT_X(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_load_format_x")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_LOAD_FORMAT_X
+
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_X::~Inst_MUBUF__BUFFER_LOAD_FORMAT_X()
+ {
+ } // ~Inst_MUBUF__BUFFER_LOAD_FORMAT_X
+
+ // Untyped buffer load 1 dword with format conversion.
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_X::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_X::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_X::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_XY
+ ::Inst_MUBUF__BUFFER_LOAD_FORMAT_XY(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_load_format_xy")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_LOAD_FORMAT_XY
+
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_XY::~Inst_MUBUF__BUFFER_LOAD_FORMAT_XY()
+ {
+ } // ~Inst_MUBUF__BUFFER_LOAD_FORMAT_XY
+
+ // Untyped buffer load 2 dwords with format conversion.
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_XY::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_XY::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_XY::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ
+ ::Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_load_format_xyz")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ
+
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ::~Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ()
+ {
+ } // ~Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ
+
+ // Untyped buffer load 3 dwords with format conversion.
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW
+ ::Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_load_format_xyzw")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW
+
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW::~Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW()
+ {
+ } // ~Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW
+
+ // Untyped buffer load 4 dwords with format conversion.
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MUBUF__BUFFER_STORE_FORMAT_X
+ ::Inst_MUBUF__BUFFER_STORE_FORMAT_X(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_store_format_x")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_STORE_FORMAT_X
+
+ Inst_MUBUF__BUFFER_STORE_FORMAT_X::~Inst_MUBUF__BUFFER_STORE_FORMAT_X()
+ {
+ } // ~Inst_MUBUF__BUFFER_STORE_FORMAT_X
+
+ // Untyped buffer store 1 dword with format conversion.
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_X::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_X::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_X::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MUBUF__BUFFER_STORE_FORMAT_XY
+ ::Inst_MUBUF__BUFFER_STORE_FORMAT_XY(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_store_format_xy")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_STORE_FORMAT_XY
+
+ Inst_MUBUF__BUFFER_STORE_FORMAT_XY::~Inst_MUBUF__BUFFER_STORE_FORMAT_XY()
+ {
+ } // ~Inst_MUBUF__BUFFER_STORE_FORMAT_XY
+
+ // Untyped buffer store 2 dwords with format conversion.
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_XY::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_XY::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_XY::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ
+ ::Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_store_format_xyz")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ
+
+ Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ::~Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ()
+ {
+ } // ~Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ
+
+ // Untyped buffer store 3 dwords with format conversion.
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW
+ ::Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_store_format_xyzw")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW
+
+ Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW
+ ::~Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW()
+ {
+ } // ~Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW
+
+ // Untyped buffer store 4 dwords with format conversion.
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X
+ ::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_load_format_d16_x")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X
+
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X
+ ::~Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X()
+ {
+ } // ~Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X
+
+ // Untyped buffer load 1 dword with format conversion.
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
+ ::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_load_format_d16_xy")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
+
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
+ ::~Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY()
+ {
+ } // ~Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
+
+ // Untyped buffer load 2 dwords with format conversion.
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY::initiateAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY::completeAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
+ ::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_load_format_d16_xyz")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
+
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
+ ::~Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ()
+ {
+ } // ~Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
+
+ // Untyped buffer load 3 dwords with format conversion.
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ::initiateAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ::completeAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
+ ::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_load_format_d16_xyzw")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
+
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
+ ::~Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW()
+ {
+ } // ~Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
+
+ // Untyped buffer load 4 dwords with format conversion.
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW::initiateAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW::completeAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X
+ ::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_store_format_d16_x")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X
+
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X
+ ::~Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X()
+ {
+ } // ~Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X
+
+ // Untyped buffer store 1 dword with format conversion.
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X::initiateAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X::completeAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY
+ ::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_store_format_d16_xy")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY
+
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY
+ ::~Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY()
+ {
+ } // ~Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY
+
+ // Untyped buffer store 2 dwords with format conversion.
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY::initiateAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY::completeAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
+ ::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_store_format_d16_xyz")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
+
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
+ ::~Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ()
+ {
+ } // ~Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
+
+ // Untyped buffer store 3 dwords with format conversion.
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ::initiateAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ::completeAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
+ ::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_store_format_d16_xyzw")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
+
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
+ ::~Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW()
+ {
+ } // ~Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
+
+ // Untyped buffer store 4 dwords with format conversion.
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW::initiateAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW::completeAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MUBUF__BUFFER_LOAD_UBYTE
+ ::Inst_MUBUF__BUFFER_LOAD_UBYTE(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_load_ubyte")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ if (instData.LDS) {
+ setFlag(GroupSegment);
+ } else {
+ setFlag(GlobalSegment);
+ }
+ } // Inst_MUBUF__BUFFER_LOAD_UBYTE
+
+ Inst_MUBUF__BUFFER_LOAD_UBYTE::~Inst_MUBUF__BUFFER_LOAD_UBYTE()
+ {
+ } // ~Inst_MUBUF__BUFFER_LOAD_UBYTE
+
+ // Untyped buffer load unsigned byte (zero extend to VGPR destination).
+ void
+ Inst_MUBUF__BUFFER_LOAD_UBYTE::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ ConstVecOperandU32 addr0(gpuDynInst, extData.VADDR);
+ ConstVecOperandU32 addr1(gpuDynInst, extData.VADDR + 1);
+ ConstScalarOperandU128 rsrcDesc(gpuDynInst, extData.SRSRC * 4);
+ ConstScalarOperandU32 offset(gpuDynInst, extData.SOFFSET);
+
+ rsrcDesc.read();
+ offset.read();
+
+ int inst_offset = instData.OFFSET;
+
+ if (!instData.IDXEN && !instData.OFFEN) {
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr0, addr1, rsrcDesc, offset, inst_offset);
+ } else if (!instData.IDXEN && instData.OFFEN) {
+ addr0.read();
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr0, addr1, rsrcDesc, offset, inst_offset);
+ } else if (instData.IDXEN && !instData.OFFEN) {
+ addr0.read();
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr1, addr0, rsrcDesc, offset, inst_offset);
+ } else {
+ addr0.read();
+ addr1.read();
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr1, addr0, rsrcDesc, offset, inst_offset);
+ }
+
+ if (isLocalMem()) {
+ gpuDynInst->computeUnit()->localMemoryPipe.
+ issueRequest(gpuDynInst);
+ wf->rdLmReqsInPipe--;
+ wf->outstandingReqsRdLm++;
+ } else {
+ gpuDynInst->computeUnit()->globalMemoryPipe.
+ issueRequest(gpuDynInst);
+ wf->rdGmReqsInPipe--;
+ wf->outstandingReqsRdGm++;
+ }
+
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_UBYTE::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ initMemRead<VecElemU8>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_UBYTE::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ VecOperandU32 vdst(gpuDynInst, extData.VDATA);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ vdst[lane] = (VecElemU32)((reinterpret_cast<VecElemU8*>(
+ gpuDynInst->d_data))[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+
+ Inst_MUBUF__BUFFER_LOAD_SBYTE
+ ::Inst_MUBUF__BUFFER_LOAD_SBYTE(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_load_sbyte")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_LOAD_SBYTE
+
+ Inst_MUBUF__BUFFER_LOAD_SBYTE::~Inst_MUBUF__BUFFER_LOAD_SBYTE()
+ {
+ } // ~Inst_MUBUF__BUFFER_LOAD_SBYTE
+
+ // Untyped buffer load signed byte (sign extend to VGPR destination).
+ void
+ Inst_MUBUF__BUFFER_LOAD_SBYTE::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_SBYTE::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_SBYTE::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MUBUF__BUFFER_LOAD_USHORT
+ ::Inst_MUBUF__BUFFER_LOAD_USHORT(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_load_ushort")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ if (instData.LDS) {
+ setFlag(GroupSegment);
+ } else {
+ setFlag(GlobalSegment);
+ }
+ } // Inst_MUBUF__BUFFER_LOAD_USHORT
+
+ Inst_MUBUF__BUFFER_LOAD_USHORT::~Inst_MUBUF__BUFFER_LOAD_USHORT()
+ {
+ } // ~Inst_MUBUF__BUFFER_LOAD_USHORT
+
+ // Untyped buffer load unsigned short (zero extend to VGPR destination).
+ void
+ Inst_MUBUF__BUFFER_LOAD_USHORT::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ ConstVecOperandU32 addr0(gpuDynInst, extData.VADDR);
+ ConstVecOperandU32 addr1(gpuDynInst, extData.VADDR + 1);
+ ConstScalarOperandU128 rsrcDesc(gpuDynInst, extData.SRSRC * 4);
+ ConstScalarOperandU32 offset(gpuDynInst, extData.SOFFSET);
+
+ rsrcDesc.read();
+ offset.read();
+
+ int inst_offset = instData.OFFSET;
+
+ if (!instData.IDXEN && !instData.OFFEN) {
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr0, addr1, rsrcDesc, offset, inst_offset);
+ } else if (!instData.IDXEN && instData.OFFEN) {
+ addr0.read();
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr0, addr1, rsrcDesc, offset, inst_offset);
+ } else if (instData.IDXEN && !instData.OFFEN) {
+ addr0.read();
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr1, addr0, rsrcDesc, offset, inst_offset);
+ } else {
+ addr0.read();
+ addr1.read();
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr1, addr0, rsrcDesc, offset, inst_offset);
+ }
+
+ if (isLocalMem()) {
+ gpuDynInst->computeUnit()->localMemoryPipe
+ .issueRequest(gpuDynInst);
+ wf->rdLmReqsInPipe--;
+ wf->outstandingReqsRdLm++;
+ } else {
+ gpuDynInst->computeUnit()->globalMemoryPipe
+ .issueRequest(gpuDynInst);
+ wf->rdGmReqsInPipe--;
+ wf->outstandingReqsRdGm++;
+ }
+
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_USHORT::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ initMemRead<VecElemU16>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_USHORT::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ VecOperandU32 vdst(gpuDynInst, extData.VDATA);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ vdst[lane] = (VecElemU32)((reinterpret_cast<VecElemU16*>(
+ gpuDynInst->d_data))[lane]);
+ }
+ }
+
+ vdst.write();
+ }
+
+
+ Inst_MUBUF__BUFFER_LOAD_SSHORT
+ ::Inst_MUBUF__BUFFER_LOAD_SSHORT(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_load_sshort")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_LOAD_SSHORT
+
+ Inst_MUBUF__BUFFER_LOAD_SSHORT::~Inst_MUBUF__BUFFER_LOAD_SSHORT()
+ {
+ } // ~Inst_MUBUF__BUFFER_LOAD_SSHORT
+
+ // Untyped buffer load signed short (sign extend to VGPR destination).
+ void
+ Inst_MUBUF__BUFFER_LOAD_SSHORT::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_SSHORT::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_SSHORT::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MUBUF__BUFFER_LOAD_DWORD
+ ::Inst_MUBUF__BUFFER_LOAD_DWORD(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_load_dword")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ if (instData.LDS) {
+ setFlag(GroupSegment);
+ } else {
+ setFlag(GlobalSegment);
+ }
+ } // Inst_MUBUF__BUFFER_LOAD_DWORD
+
+ Inst_MUBUF__BUFFER_LOAD_DWORD::~Inst_MUBUF__BUFFER_LOAD_DWORD()
+ {
+ } // ~Inst_MUBUF__BUFFER_LOAD_DWORD
+
+ // Untyped buffer load dword.
+ void
+ Inst_MUBUF__BUFFER_LOAD_DWORD::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ ConstVecOperandU32 addr0(gpuDynInst, extData.VADDR);
+ ConstVecOperandU32 addr1(gpuDynInst, extData.VADDR + 1);
+ ConstScalarOperandU128 rsrcDesc(gpuDynInst, extData.SRSRC * 4);
+ ConstScalarOperandU32 offset(gpuDynInst, extData.SOFFSET);
+
+ rsrcDesc.read();
+ offset.read();
+
+ int inst_offset = instData.OFFSET;
+
+ if (!instData.IDXEN && !instData.OFFEN) {
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr0, addr1, rsrcDesc, offset, inst_offset);
+ } else if (!instData.IDXEN && instData.OFFEN) {
+ addr0.read();
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr0, addr1, rsrcDesc, offset, inst_offset);
+ } else if (instData.IDXEN && !instData.OFFEN) {
+ addr0.read();
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr1, addr0, rsrcDesc, offset, inst_offset);
+ } else {
+ addr0.read();
+ addr1.read();
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr1, addr0, rsrcDesc, offset, inst_offset);
+ }
+
+ if (isLocalMem()) {
+ gpuDynInst->computeUnit()->localMemoryPipe
+ .issueRequest(gpuDynInst);
+ wf->rdLmReqsInPipe--;
+ wf->outstandingReqsRdLm++;
+ } else {
+ gpuDynInst->computeUnit()->globalMemoryPipe
+ .issueRequest(gpuDynInst);
+ wf->rdGmReqsInPipe--;
+ wf->outstandingReqsRdGm++;
+ }
+
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_DWORD::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ initMemRead<VecElemU32>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_DWORD::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ VecOperandU32 vdst(gpuDynInst, extData.VDATA);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ vdst[lane] = (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane];
+ }
+ }
+
+ vdst.write();
+ } // completeAcc
+
+ Inst_MUBUF__BUFFER_LOAD_DWORDX2
+ ::Inst_MUBUF__BUFFER_LOAD_DWORDX2(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_load_dwordx2")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_LOAD_DWORDX2
+
+ Inst_MUBUF__BUFFER_LOAD_DWORDX2::~Inst_MUBUF__BUFFER_LOAD_DWORDX2()
+ {
+ } // ~Inst_MUBUF__BUFFER_LOAD_DWORDX2
+
+ // Untyped buffer load 2 dwords.
+ void
+ Inst_MUBUF__BUFFER_LOAD_DWORDX2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_DWORDX2::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_DWORDX2::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_MUBUF__BUFFER_LOAD_DWORDX3
+ ::Inst_MUBUF__BUFFER_LOAD_DWORDX3(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_load_dwordx3")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_LOAD_DWORDX3
+
+ Inst_MUBUF__BUFFER_LOAD_DWORDX3::~Inst_MUBUF__BUFFER_LOAD_DWORDX3()
+ {
+ } // ~Inst_MUBUF__BUFFER_LOAD_DWORDX3
+
+ // Untyped buffer load 3 dwords.
+ void
+ Inst_MUBUF__BUFFER_LOAD_DWORDX3::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_DWORDX3::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_DWORDX3::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_MUBUF__BUFFER_LOAD_DWORDX4
+ ::Inst_MUBUF__BUFFER_LOAD_DWORDX4(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_load_dwordx4")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_LOAD_DWORDX4
+
+ Inst_MUBUF__BUFFER_LOAD_DWORDX4::~Inst_MUBUF__BUFFER_LOAD_DWORDX4()
+ {
+ } // ~Inst_MUBUF__BUFFER_LOAD_DWORDX4
+
+ // Untyped buffer load 4 dwords.
+ void
+ Inst_MUBUF__BUFFER_LOAD_DWORDX4::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_DWORDX4::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_LOAD_DWORDX4::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_MUBUF__BUFFER_STORE_BYTE
+ ::Inst_MUBUF__BUFFER_STORE_BYTE(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_store_byte")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ if (instData.LDS) {
+ setFlag(GroupSegment);
+ } else {
+ setFlag(GlobalSegment);
+ }
+ } // Inst_MUBUF__BUFFER_STORE_BYTE
+
+ Inst_MUBUF__BUFFER_STORE_BYTE::~Inst_MUBUF__BUFFER_STORE_BYTE()
+ {
+ } // ~Inst_MUBUF__BUFFER_STORE_BYTE
+
+ // Untyped buffer store byte.
+ void
+ Inst_MUBUF__BUFFER_STORE_BYTE::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ ConstVecOperandU32 addr0(gpuDynInst, extData.VADDR);
+ ConstVecOperandU32 addr1(gpuDynInst, extData.VADDR + 1);
+ ConstScalarOperandU128 rsrcDesc(gpuDynInst, extData.SRSRC * 4);
+ ConstScalarOperandU32 offset(gpuDynInst, extData.SOFFSET);
+
+ rsrcDesc.read();
+ offset.read();
+
+ int inst_offset = instData.OFFSET;
+
+ if (!instData.IDXEN && !instData.OFFEN) {
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr0, addr1, rsrcDesc, offset, inst_offset);
+ } else if (!instData.IDXEN && instData.OFFEN) {
+ addr0.read();
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr0, addr1, rsrcDesc, offset, inst_offset);
+ } else if (instData.IDXEN && !instData.OFFEN) {
+ addr0.read();
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr1, addr0, rsrcDesc, offset, inst_offset);
+ } else {
+ addr0.read();
+ addr1.read();
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr1, addr0, rsrcDesc, offset, inst_offset);
+ }
+
+ if (isLocalMem()) {
+ gpuDynInst->computeUnit()->localMemoryPipe
+ .issueRequest(gpuDynInst);
+ wf->wrLmReqsInPipe--;
+ wf->outstandingReqsWrLm++;
+ } else {
+ gpuDynInst->computeUnit()->globalMemoryPipe
+ .issueRequest(gpuDynInst);
+ wf->wrGmReqsInPipe--;
+ wf->outstandingReqsWrGm++;
+ }
+
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_STORE_BYTE::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ ConstVecOperandI8 data(gpuDynInst, extData.VDATA);
+ data.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ (reinterpret_cast<VecElemI8*>(gpuDynInst->d_data))[lane]
+ = data[lane];
+ }
+ }
+
+ initMemWrite<VecElemI8>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_STORE_BYTE::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MUBUF__BUFFER_STORE_SHORT
+ ::Inst_MUBUF__BUFFER_STORE_SHORT(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_store_short")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ if (instData.LDS) {
+ setFlag(GroupSegment);
+ } else {
+ setFlag(GlobalSegment);
+ }
+ } // Inst_MUBUF__BUFFER_STORE_SHORT
+
+ Inst_MUBUF__BUFFER_STORE_SHORT::~Inst_MUBUF__BUFFER_STORE_SHORT()
+ {
+ } // ~Inst_MUBUF__BUFFER_STORE_SHORT
+
+ // Untyped buffer store short.
+ void
+ Inst_MUBUF__BUFFER_STORE_SHORT::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ ConstVecOperandU32 addr0(gpuDynInst, extData.VADDR);
+ ConstVecOperandU32 addr1(gpuDynInst, extData.VADDR + 1);
+ ConstScalarOperandU128 rsrcDesc(gpuDynInst, extData.SRSRC * 4);
+ ConstScalarOperandU32 offset(gpuDynInst, extData.SOFFSET);
+
+ rsrcDesc.read();
+ offset.read();
+
+ int inst_offset = instData.OFFSET;
+
+ if (!instData.IDXEN && !instData.OFFEN) {
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr0, addr1, rsrcDesc, offset, inst_offset);
+ } else if (!instData.IDXEN && instData.OFFEN) {
+ addr0.read();
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr0, addr1, rsrcDesc, offset, inst_offset);
+ } else if (instData.IDXEN && !instData.OFFEN) {
+ addr0.read();
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr1, addr0, rsrcDesc, offset, inst_offset);
+ } else {
+ addr0.read();
+ addr1.read();
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr1, addr0, rsrcDesc, offset, inst_offset);
+ }
+
+ if (isLocalMem()) {
+ gpuDynInst->computeUnit()->localMemoryPipe
+ .issueRequest(gpuDynInst);
+ wf->wrLmReqsInPipe--;
+ wf->outstandingReqsWrLm++;
+ } else {
+ gpuDynInst->computeUnit()->globalMemoryPipe
+ .issueRequest(gpuDynInst);
+ wf->wrGmReqsInPipe--;
+ wf->outstandingReqsWrGm++;
+ }
+
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_STORE_SHORT::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ ConstVecOperandI16 data(gpuDynInst, extData.VDATA);
+ data.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ (reinterpret_cast<VecElemI16*>(gpuDynInst->d_data))[lane]
+ = data[lane];
+ }
+ }
+
+ initMemWrite<VecElemI16>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_STORE_SHORT::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MUBUF__BUFFER_STORE_DWORD::
+ Inst_MUBUF__BUFFER_STORE_DWORD(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_store_dword")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ if (instData.LDS) {
+ setFlag(GroupSegment);
+ } else {
+ setFlag(GlobalSegment);
+ }
+ } // Inst_MUBUF__BUFFER_STORE_DWORD
+
+ Inst_MUBUF__BUFFER_STORE_DWORD::~Inst_MUBUF__BUFFER_STORE_DWORD()
+ {
+ } // ~Inst_MUBUF__BUFFER_STORE_DWORD
+
+ // Untyped buffer store dword.
+ void
+ Inst_MUBUF__BUFFER_STORE_DWORD::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ ConstVecOperandU32 addr0(gpuDynInst, extData.VADDR);
+ ConstVecOperandU32 addr1(gpuDynInst, extData.VADDR + 1);
+ ConstScalarOperandU128 rsrcDesc(gpuDynInst, extData.SRSRC * 4);
+ ConstScalarOperandU32 offset(gpuDynInst, extData.SOFFSET);
+
+ rsrcDesc.read();
+ offset.read();
+
+ int inst_offset = instData.OFFSET;
+
+ if (!instData.IDXEN && !instData.OFFEN) {
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr0, addr1, rsrcDesc, offset, inst_offset);
+ } else if (!instData.IDXEN && instData.OFFEN) {
+ addr0.read();
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr0, addr1, rsrcDesc, offset, inst_offset);
+ } else if (instData.IDXEN && !instData.OFFEN) {
+ addr0.read();
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr1, addr0, rsrcDesc, offset, inst_offset);
+ } else {
+ addr0.read();
+ addr1.read();
+ calcAddr<ConstVecOperandU32, ConstVecOperandU32,
+ ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
+ addr1, addr0, rsrcDesc, offset, inst_offset);
+ }
+
+ if (isLocalMem()) {
+ gpuDynInst->computeUnit()->localMemoryPipe
+ .issueRequest(gpuDynInst);
+ wf->wrLmReqsInPipe--;
+ wf->outstandingReqsWrLm++;
+ } else {
+ gpuDynInst->computeUnit()->globalMemoryPipe
+ .issueRequest(gpuDynInst);
+ wf->wrGmReqsInPipe--;
+ wf->outstandingReqsWrGm++;
+ }
+
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_STORE_DWORD::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ ConstVecOperandU32 data(gpuDynInst, extData.VDATA);
+ data.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ (reinterpret_cast<VecElemU32*>(gpuDynInst->d_data))[lane]
+ = data[lane];
+ }
+ }
+
+ initMemWrite<VecElemU32>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_STORE_DWORD::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_MUBUF__BUFFER_STORE_DWORDX2
+ ::Inst_MUBUF__BUFFER_STORE_DWORDX2(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_store_dwordx2")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_STORE_DWORDX2
+
+ Inst_MUBUF__BUFFER_STORE_DWORDX2::~Inst_MUBUF__BUFFER_STORE_DWORDX2()
+ {
+ } // ~Inst_MUBUF__BUFFER_STORE_DWORDX2
+
+ // Untyped buffer store 2 dwords.
+ void
+ Inst_MUBUF__BUFFER_STORE_DWORDX2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_STORE_DWORDX2::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_STORE_DWORDX2::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_MUBUF__BUFFER_STORE_DWORDX3
+ ::Inst_MUBUF__BUFFER_STORE_DWORDX3(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_store_dwordx3")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_STORE_DWORDX3
+
+ Inst_MUBUF__BUFFER_STORE_DWORDX3::~Inst_MUBUF__BUFFER_STORE_DWORDX3()
+ {
+ } // ~Inst_MUBUF__BUFFER_STORE_DWORDX3
+
+ // Untyped buffer store 3 dwords.
+ void
+ Inst_MUBUF__BUFFER_STORE_DWORDX3::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_STORE_DWORDX3::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_STORE_DWORDX3::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_MUBUF__BUFFER_STORE_DWORDX4
+ ::Inst_MUBUF__BUFFER_STORE_DWORDX4(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_store_dwordx4")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_STORE_DWORDX4
+
+ Inst_MUBUF__BUFFER_STORE_DWORDX4::~Inst_MUBUF__BUFFER_STORE_DWORDX4()
+ {
+ } // ~Inst_MUBUF__BUFFER_STORE_DWORDX4
+
+ // Untyped buffer store 4 dwords.
+ void
+ Inst_MUBUF__BUFFER_STORE_DWORDX4::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_STORE_DWORDX4::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_STORE_DWORDX4::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_MUBUF__BUFFER_STORE_LDS_DWORD
+ ::Inst_MUBUF__BUFFER_STORE_LDS_DWORD(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_store_lds_dword")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_STORE_LDS_DWORD
+
+ Inst_MUBUF__BUFFER_STORE_LDS_DWORD::~Inst_MUBUF__BUFFER_STORE_LDS_DWORD()
+ {
+ } // ~Inst_MUBUF__BUFFER_STORE_LDS_DWORD
+
+ // Store one DWORD from LDS memory to system memory without utilizing
+ // VGPRs.
+ void
+ Inst_MUBUF__BUFFER_STORE_LDS_DWORD::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_WBINVL1::Inst_MUBUF__BUFFER_WBINVL1(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_wbinvl1")
+ {
+ setFlag(MemoryRef);
+ setFlag(GPUStaticInst::MemSync);
+ setFlag(GlobalSegment);
+ setFlag(MemSync);
+ } // Inst_MUBUF__BUFFER_WBINVL1
+
+ Inst_MUBUF__BUFFER_WBINVL1::~Inst_MUBUF__BUFFER_WBINVL1()
+ {
+ } // ~Inst_MUBUF__BUFFER_WBINVL1
+
+ // Write back and invalidate the shader L1.
+ // Always returns ACK to shader.
+ void
+ Inst_MUBUF__BUFFER_WBINVL1::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
+ gpuDynInst->computeUnit()->globalMemoryPipe.
+ issueRequest(gpuDynInst);
+ wf->wrGmReqsInPipe--;
+ wf->rdGmReqsInPipe--;
+
+ wf->outstandingReqsWrGm++;
+ wf->outstandingReqsRdGm++;
+ } else {
+ fatal("Non global flat instructions not implemented yet.\n");
+ }
+
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ }
+
+ void
+ Inst_MUBUF__BUFFER_WBINVL1::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ injectGlobalMemFence(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_MUBUF__BUFFER_WBINVL1::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_MUBUF__BUFFER_WBINVL1_VOL
+ ::Inst_MUBUF__BUFFER_WBINVL1_VOL(InFmt_MUBUF*iFmt)
+ : Inst_MUBUF(iFmt, "buffer_wbinvl1_vol") {
+ /**
+ * This instruction is same as buffer_wbinvl1 instruction except this
+ * instruction only invalidate L1 shader line with MTYPE for system
+ * or group coherence. Since L1 do not differentiate between its cache
+ * lines, this instruction currently behaves (and implemented )
+ * exactly like buffer_wbinvl1 instruction.
+ */
+ setFlag(MemoryRef);
+ setFlag(GPUStaticInst::MemSync);
+ setFlag(GlobalSegment);
+ setFlag(MemSync);
+ } // Inst_MUBUF__BUFFER_WBINVL1_VOL
+
+ Inst_MUBUF__BUFFER_WBINVL1_VOL::~Inst_MUBUF__BUFFER_WBINVL1_VOL()
+ {
+ } // ~Inst_MUBUF__BUFFER_WBINVL1_VOL
+
+ // Write back and invalidate the shader L1 only for lines that are marked
+ // volatile. Always returns ACK to shader.
+ void
+ Inst_MUBUF__BUFFER_WBINVL1_VOL::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
+ gpuDynInst->computeUnit()->globalMemoryPipe.
+ issueRequest(gpuDynInst);
+ wf->wrGmReqsInPipe--;
+ wf->rdGmReqsInPipe--;
+
+ wf->outstandingReqsWrGm++;
+ wf->outstandingReqsRdGm++;
+ } else {
+ fatal("Non global flat instructions not implemented yet.\n");
+ }
+
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ }
+ void
+ Inst_MUBUF__BUFFER_WBINVL1_VOL::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ injectGlobalMemFence(gpuDynInst);
+ } // initiateAcc
+ void
+ Inst_MUBUF__BUFFER_WBINVL1_VOL::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_MUBUF__BUFFER_ATOMIC_SWAP
+ ::Inst_MUBUF__BUFFER_ATOMIC_SWAP(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_swap")
+ {
+ setFlag(AtomicExch);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ } // if
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_SWAP
+
+ Inst_MUBUF__BUFFER_ATOMIC_SWAP::~Inst_MUBUF__BUFFER_ATOMIC_SWAP()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_SWAP
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_SWAP::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP
+ ::Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_cmpswap")
+ {
+ setFlag(AtomicCAS);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP
+
+ Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP::~Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP
+
+ // tmp = MEM[ADDR];
+ // src = DATA[0];
+ // cmp = DATA[1];
+ // MEM[ADDR] = (tmp == cmp) ? src : tmp;
+ // RETURN_DATA[0] = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_ADD
+ ::Inst_MUBUF__BUFFER_ATOMIC_ADD(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_add")
+ {
+ setFlag(AtomicAdd);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ } // if
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_ADD
+
+ Inst_MUBUF__BUFFER_ATOMIC_ADD::~Inst_MUBUF__BUFFER_ATOMIC_ADD()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_ADD
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] += DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_ADD::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_SUB
+ ::Inst_MUBUF__BUFFER_ATOMIC_SUB(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_sub")
+ {
+ setFlag(AtomicSub);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_SUB
+
+ Inst_MUBUF__BUFFER_ATOMIC_SUB::~Inst_MUBUF__BUFFER_ATOMIC_SUB()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_SUB
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_SUB::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_SMIN
+ ::Inst_MUBUF__BUFFER_ATOMIC_SMIN(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_smin")
+ {
+ setFlag(AtomicMin);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_SMIN
+
+ Inst_MUBUF__BUFFER_ATOMIC_SMIN::~Inst_MUBUF__BUFFER_ATOMIC_SMIN()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_SMIN
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (DATA < tmp) ? DATA : tmp (signed compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_SMIN::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_UMIN
+ ::Inst_MUBUF__BUFFER_ATOMIC_UMIN(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_umin")
+ {
+ setFlag(AtomicMin);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_UMIN
+
+ Inst_MUBUF__BUFFER_ATOMIC_UMIN::~Inst_MUBUF__BUFFER_ATOMIC_UMIN()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_UMIN
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (DATA < tmp) ? DATA : tmp (unsigned compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_UMIN::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_SMAX
+ ::Inst_MUBUF__BUFFER_ATOMIC_SMAX(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_smax")
+ {
+ setFlag(AtomicMax);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_SMAX
+
+ Inst_MUBUF__BUFFER_ATOMIC_SMAX::~Inst_MUBUF__BUFFER_ATOMIC_SMAX()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_SMAX
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (DATA > tmp) ? DATA : tmp (signed compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_SMAX::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_UMAX
+ ::Inst_MUBUF__BUFFER_ATOMIC_UMAX(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_umax")
+ {
+ setFlag(AtomicMax);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ } // if
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_UMAX
+
+ Inst_MUBUF__BUFFER_ATOMIC_UMAX::~Inst_MUBUF__BUFFER_ATOMIC_UMAX()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_UMAX
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (DATA > tmp) ? DATA : tmp (unsigned compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_UMAX::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_AND
+ ::Inst_MUBUF__BUFFER_ATOMIC_AND(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_and")
+ {
+ setFlag(AtomicAnd);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_AND
+
+ Inst_MUBUF__BUFFER_ATOMIC_AND::~Inst_MUBUF__BUFFER_ATOMIC_AND()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_AND
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] &= DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_AND::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_OR
+ ::Inst_MUBUF__BUFFER_ATOMIC_OR(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_or")
+ {
+ setFlag(AtomicOr);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_OR
+
+ Inst_MUBUF__BUFFER_ATOMIC_OR::~Inst_MUBUF__BUFFER_ATOMIC_OR()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_OR
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] |= DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_OR::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_XOR
+ ::Inst_MUBUF__BUFFER_ATOMIC_XOR(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_xor")
+ {
+ setFlag(AtomicXor);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_XOR
+
+ Inst_MUBUF__BUFFER_ATOMIC_XOR::~Inst_MUBUF__BUFFER_ATOMIC_XOR()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_XOR
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] ^= DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_XOR::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_INC
+ ::Inst_MUBUF__BUFFER_ATOMIC_INC(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_inc")
+ {
+ setFlag(AtomicInc);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_INC
+
+ Inst_MUBUF__BUFFER_ATOMIC_INC::~Inst_MUBUF__BUFFER_ATOMIC_INC()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_INC
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (tmp >= DATA) ? 0 : tmp + 1 (unsigned compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_INC::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_DEC
+ ::Inst_MUBUF__BUFFER_ATOMIC_DEC(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_dec")
+ {
+ setFlag(AtomicDec);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_DEC
+
+ Inst_MUBUF__BUFFER_ATOMIC_DEC::~Inst_MUBUF__BUFFER_ATOMIC_DEC()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_DEC
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (tmp == 0 || tmp > DATA) ? DATA : tmp - 1
+ // (unsigned compare); RETURN_DATA = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_DEC::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2
+ ::Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_swap_x2")
+ {
+ setFlag(AtomicExch);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2
+
+ Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2::~Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = DATA[0:1];
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
+ ::Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_cmpswap_x2")
+ {
+ setFlag(AtomicCAS);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
+
+ Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
+ ::~Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
+
+ // tmp = MEM[ADDR];
+ // src = DATA[0:1];
+ // cmp = DATA[2:3];
+ // MEM[ADDR] = (tmp == cmp) ? src : tmp;
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_ADD_X2
+ ::Inst_MUBUF__BUFFER_ATOMIC_ADD_X2(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_add_x2")
+ {
+ setFlag(AtomicAdd);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_ADD_X2
+
+ Inst_MUBUF__BUFFER_ATOMIC_ADD_X2::~Inst_MUBUF__BUFFER_ATOMIC_ADD_X2()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_ADD_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] += DATA[0:1];
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_ADD_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_SUB_X2
+ ::Inst_MUBUF__BUFFER_ATOMIC_SUB_X2(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_sub_x2")
+ {
+ setFlag(AtomicSub);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_SUB_X2
+
+ Inst_MUBUF__BUFFER_ATOMIC_SUB_X2::~Inst_MUBUF__BUFFER_ATOMIC_SUB_X2()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_SUB_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= DATA[0:1];
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_SUB_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2
+ ::Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_smin_x2")
+ {
+ setFlag(AtomicMin);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2
+
+ Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2::~Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= (DATA[0:1] < tmp) ? DATA[0:1] : tmp (signed compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2
+ ::Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_umin_x2")
+ {
+ setFlag(AtomicMin);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2
+
+ Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2::~Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= (DATA[0:1] < tmp) ? DATA[0:1] : tmp (unsigned compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2
+ ::Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_smax_x2")
+ {
+ setFlag(AtomicMax);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2
+
+ Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2::~Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= (DATA[0:1] > tmp) ? DATA[0:1] : tmp (signed compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2
+ ::Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_umax_x2")
+ {
+ setFlag(AtomicMax);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2
+
+ Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2::~Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= (DATA[0:1] > tmp) ? DATA[0:1] : tmp (unsigned compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_AND_X2
+ ::Inst_MUBUF__BUFFER_ATOMIC_AND_X2(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_and_x2")
+ {
+ setFlag(AtomicAnd);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_AND_X2
+
+ Inst_MUBUF__BUFFER_ATOMIC_AND_X2::~Inst_MUBUF__BUFFER_ATOMIC_AND_X2()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_AND_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] &= DATA[0:1];
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_AND_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_OR_X2
+ ::Inst_MUBUF__BUFFER_ATOMIC_OR_X2(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_or_x2")
+ {
+ setFlag(AtomicOr);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_OR_X2
+
+ Inst_MUBUF__BUFFER_ATOMIC_OR_X2::~Inst_MUBUF__BUFFER_ATOMIC_OR_X2()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_OR_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] |= DATA[0:1];
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_OR_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_XOR_X2
+ ::Inst_MUBUF__BUFFER_ATOMIC_XOR_X2(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_xor_x2")
+ {
+ setFlag(AtomicXor);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_XOR_X2
+
+ Inst_MUBUF__BUFFER_ATOMIC_XOR_X2::~Inst_MUBUF__BUFFER_ATOMIC_XOR_X2()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_XOR_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] ^= DATA[0:1];
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_XOR_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_INC_X2
+ ::Inst_MUBUF__BUFFER_ATOMIC_INC_X2(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_inc_x2")
+ {
+ setFlag(AtomicInc);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_INC_X2
+
+ Inst_MUBUF__BUFFER_ATOMIC_INC_X2::~Inst_MUBUF__BUFFER_ATOMIC_INC_X2()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_INC_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (tmp >= DATA[0:1]) ? 0 : tmp + 1 (unsigned compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_INC_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MUBUF__BUFFER_ATOMIC_DEC_X2
+ ::Inst_MUBUF__BUFFER_ATOMIC_DEC_X2(InFmt_MUBUF *iFmt)
+ : Inst_MUBUF(iFmt, "buffer_atomic_dec_x2")
+ {
+ setFlag(AtomicDec);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MUBUF__BUFFER_ATOMIC_DEC_X2
+
+ Inst_MUBUF__BUFFER_ATOMIC_DEC_X2::~Inst_MUBUF__BUFFER_ATOMIC_DEC_X2()
+ {
+ } // ~Inst_MUBUF__BUFFER_ATOMIC_DEC_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (tmp == 0 || tmp > DATA[0:1]) ? DATA[0:1] : tmp - 1
+ // (unsigned compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_MUBUF__BUFFER_ATOMIC_DEC_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_X
+ ::Inst_MTBUF__TBUFFER_LOAD_FORMAT_X(InFmt_MTBUF *iFmt)
+ : Inst_MTBUF(iFmt, "tbuffer_load_format_x")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MTBUF__TBUFFER_LOAD_FORMAT_X
+
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_X::~Inst_MTBUF__TBUFFER_LOAD_FORMAT_X()
+ {
+ } // ~Inst_MTBUF__TBUFFER_LOAD_FORMAT_X
+
+ // Typed buffer load 1 dword with format conversion.
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_X::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_X::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_X::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY
+ ::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY(InFmt_MTBUF *iFmt)
+ : Inst_MTBUF(iFmt, "tbuffer_load_format_xy")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY
+
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY::~Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY()
+ {
+ } // ~Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY
+
+ // Typed buffer load 2 dwords with format conversion.
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
+ ::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ(InFmt_MTBUF *iFmt)
+ : Inst_MTBUF(iFmt, "tbuffer_load_format_xyz")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
+
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ::~Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ()
+ {
+ } // ~Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
+
+ // Typed buffer load 3 dwords with format conversion.
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
+ ::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW(InFmt_MTBUF *iFmt)
+ : Inst_MTBUF(iFmt, "tbuffer_load_format_xyzw")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
+
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
+ ::~Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW()
+ {
+ } // ~Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
+
+ // Typed buffer load 4 dwords with format conversion.
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_X
+ ::Inst_MTBUF__TBUFFER_STORE_FORMAT_X(InFmt_MTBUF *iFmt)
+ : Inst_MTBUF(iFmt, "tbuffer_store_format_x")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MTBUF__TBUFFER_STORE_FORMAT_X
+
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_X::~Inst_MTBUF__TBUFFER_STORE_FORMAT_X()
+ {
+ } // ~Inst_MTBUF__TBUFFER_STORE_FORMAT_X
+
+ // Typed buffer store 1 dword with format conversion.
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_X::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_X::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_X::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_XY
+ ::Inst_MTBUF__TBUFFER_STORE_FORMAT_XY(InFmt_MTBUF *iFmt)
+ : Inst_MTBUF(iFmt, "tbuffer_store_format_xy")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MTBUF__TBUFFER_STORE_FORMAT_XY
+
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_XY::~Inst_MTBUF__TBUFFER_STORE_FORMAT_XY()
+ {
+ } // ~Inst_MTBUF__TBUFFER_STORE_FORMAT_XY
+
+ // Typed buffer store 2 dwords with format conversion.
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_XY::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_XY::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_XY::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ
+ ::Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ(InFmt_MTBUF *iFmt)
+ : Inst_MTBUF(iFmt, "tbuffer_store_format_xyz")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ
+
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ
+ ::~Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ()
+ {
+ } // ~Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ
+
+ // Typed buffer store 3 dwords with format conversion.
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW
+ ::Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW(InFmt_MTBUF *iFmt)
+ : Inst_MTBUF(iFmt, "tbuffer_store_format_xyzw")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW
+
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW
+ ::~Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW()
+ {
+ } // ~Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW
+
+ // Typed buffer store 4 dwords with format conversion.
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW::initiateAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW::completeAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
+ ::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X(InFmt_MTBUF *iFmt)
+ : Inst_MTBUF(iFmt, "tbuffer_load_format_d16_x")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
+
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X::
+ ~Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X()
+ {
+ } // ~Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
+
+ // Typed buffer load 1 dword with format conversion.
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X::initiateAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X::completeAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
+ ::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY(InFmt_MTBUF *iFmt)
+ : Inst_MTBUF(iFmt, "tbuffer_load_format_d16_xy")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
+
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
+ ::~Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY()
+ {
+ } // ~Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
+
+ // Typed buffer load 2 dwords with format conversion.
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY::initiateAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY::completeAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
+ ::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ(
+ InFmt_MTBUF *iFmt)
+ : Inst_MTBUF(iFmt, "tbuffer_load_format_d16_xyz")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
+
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
+ ::~Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ()
+ {
+ } // ~Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
+
+ // Typed buffer load 3 dwords with format conversion.
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ::initiateAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ::completeAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
+ ::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW(
+ InFmt_MTBUF *iFmt)
+ : Inst_MTBUF(iFmt, "tbuffer_load_format_d16_xyzw")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
+
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
+ ::~Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW()
+ {
+ } // ~Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
+
+ // Typed buffer load 4 dwords with format conversion.
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW::initiateAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW::completeAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X
+ ::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X(InFmt_MTBUF *iFmt)
+ : Inst_MTBUF(iFmt, "tbuffer_store_format_d16_x")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X
+
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X
+ ::~Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X()
+ {
+ } // ~Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X
+
+ // Typed buffer store 1 dword with format conversion.
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X::initiateAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X::completeAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
+ ::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY(InFmt_MTBUF *iFmt)
+ : Inst_MTBUF(iFmt, "tbuffer_store_format_d16_xy")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
+
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
+ ::~Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY()
+ {
+ } // ~Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
+
+ // Typed buffer store 2 dwords with format conversion.
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY::initiateAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY::completeAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
+ ::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ(InFmt_MTBUF *iFmt)
+ : Inst_MTBUF(iFmt, "tbuffer_store_format_d16_xyz")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
+
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
+ ::~Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ()
+ {
+ } // ~Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
+
+ // Typed buffer store 3 dwords with format conversion.
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ::initiateAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ::completeAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
+ ::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW(InFmt_MTBUF *iFmt)
+ : Inst_MTBUF(iFmt, "tbuffer_store_format_d16_xyzw")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
+
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
+ ::~Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW()
+ {
+ } // ~Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
+
+ // Typed buffer store 4 dwords with format conversion.
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW::execute(
+ GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW::initiateAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW::completeAcc(
+ GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MIMG__IMAGE_LOAD::Inst_MIMG__IMAGE_LOAD(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_load")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_LOAD
+
+ Inst_MIMG__IMAGE_LOAD::~Inst_MIMG__IMAGE_LOAD()
+ {
+ } // ~Inst_MIMG__IMAGE_LOAD
+
+ // Image memory load with format conversion specified
+ void
+ Inst_MIMG__IMAGE_LOAD::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MIMG__IMAGE_LOAD::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MIMG__IMAGE_LOAD::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MIMG__IMAGE_LOAD_MIP::Inst_MIMG__IMAGE_LOAD_MIP(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_load_mip")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_LOAD_MIP
+
+ Inst_MIMG__IMAGE_LOAD_MIP::~Inst_MIMG__IMAGE_LOAD_MIP()
+ {
+ } // ~Inst_MIMG__IMAGE_LOAD_MIP
+
+ void
+ Inst_MIMG__IMAGE_LOAD_MIP::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MIMG__IMAGE_LOAD_MIP::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MIMG__IMAGE_LOAD_MIP::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MIMG__IMAGE_LOAD_PCK::Inst_MIMG__IMAGE_LOAD_PCK(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_load_pck")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_LOAD_PCK
+
+ Inst_MIMG__IMAGE_LOAD_PCK::~Inst_MIMG__IMAGE_LOAD_PCK()
+ {
+ } // ~Inst_MIMG__IMAGE_LOAD_PCK
+
+ void
+ Inst_MIMG__IMAGE_LOAD_PCK::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MIMG__IMAGE_LOAD_PCK::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MIMG__IMAGE_LOAD_PCK::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MIMG__IMAGE_LOAD_PCK_SGN::Inst_MIMG__IMAGE_LOAD_PCK_SGN(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_load_pck_sgn")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_LOAD_PCK_SGN
+
+ Inst_MIMG__IMAGE_LOAD_PCK_SGN::~Inst_MIMG__IMAGE_LOAD_PCK_SGN()
+ {
+ } // ~Inst_MIMG__IMAGE_LOAD_PCK_SGN
+
+ // Image memory load with with no format conversion and sign extension
+ void
+ Inst_MIMG__IMAGE_LOAD_PCK_SGN::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MIMG__IMAGE_LOAD_PCK_SGN::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MIMG__IMAGE_LOAD_PCK_SGN::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MIMG__IMAGE_LOAD_MIP_PCK::Inst_MIMG__IMAGE_LOAD_MIP_PCK(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_load_mip_pck")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_LOAD_MIP_PCK
+
+ Inst_MIMG__IMAGE_LOAD_MIP_PCK::~Inst_MIMG__IMAGE_LOAD_MIP_PCK()
+ {
+ } // ~Inst_MIMG__IMAGE_LOAD_MIP_PCK
+
+ // Image memory load with user-supplied mip level, no format conversion
+ void
+ Inst_MIMG__IMAGE_LOAD_MIP_PCK::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MIMG__IMAGE_LOAD_MIP_PCK::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MIMG__IMAGE_LOAD_MIP_PCK::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN::Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_load_mip_pck_sgn")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN
+
+ Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN::~Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN()
+ {
+ } // ~Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN
+
+ // Image memory load with user-supplied mip level, no format conversion.
+ void
+ Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MIMG__IMAGE_STORE::Inst_MIMG__IMAGE_STORE(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_store")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_STORE
+
+ Inst_MIMG__IMAGE_STORE::~Inst_MIMG__IMAGE_STORE()
+ {
+ } // ~Inst_MIMG__IMAGE_STORE
+
+ // Image memory store with format conversion specified
+ void
+ Inst_MIMG__IMAGE_STORE::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MIMG__IMAGE_STORE::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MIMG__IMAGE_STORE::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MIMG__IMAGE_STORE_MIP::Inst_MIMG__IMAGE_STORE_MIP(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_store_mip")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_STORE_MIP
+
+ Inst_MIMG__IMAGE_STORE_MIP::~Inst_MIMG__IMAGE_STORE_MIP()
+ {
+ } // ~Inst_MIMG__IMAGE_STORE_MIP
+
+ void
+ Inst_MIMG__IMAGE_STORE_MIP::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MIMG__IMAGE_STORE_MIP::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MIMG__IMAGE_STORE_MIP::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MIMG__IMAGE_STORE_PCK::Inst_MIMG__IMAGE_STORE_PCK(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_store_pck")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_STORE_PCK
+
+ Inst_MIMG__IMAGE_STORE_PCK::~Inst_MIMG__IMAGE_STORE_PCK()
+ {
+ } // ~Inst_MIMG__IMAGE_STORE_PCK
+
+ // Image memory store of packed data without format conversion.
+ void
+ Inst_MIMG__IMAGE_STORE_PCK::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MIMG__IMAGE_STORE_PCK::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MIMG__IMAGE_STORE_PCK::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MIMG__IMAGE_STORE_MIP_PCK::Inst_MIMG__IMAGE_STORE_MIP_PCK(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_store_mip_pck")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_STORE_MIP_PCK
+
+ Inst_MIMG__IMAGE_STORE_MIP_PCK::~Inst_MIMG__IMAGE_STORE_MIP_PCK()
+ {
+ } // ~Inst_MIMG__IMAGE_STORE_MIP_PCK
+
+ // Image memory store of packed data without format conversion
+ void
+ Inst_MIMG__IMAGE_STORE_MIP_PCK::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_MIMG__IMAGE_STORE_MIP_PCK::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_MIMG__IMAGE_STORE_MIP_PCK::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_MIMG__IMAGE_GET_RESINFO::Inst_MIMG__IMAGE_GET_RESINFO(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_get_resinfo")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GET_RESINFO
+
+ Inst_MIMG__IMAGE_GET_RESINFO::~Inst_MIMG__IMAGE_GET_RESINFO()
+ {
+ } // ~Inst_MIMG__IMAGE_GET_RESINFO
+
+ void
+ Inst_MIMG__IMAGE_GET_RESINFO::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_ATOMIC_SWAP::Inst_MIMG__IMAGE_ATOMIC_SWAP(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_atomic_swap")
+ {
+ setFlag(AtomicExch);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_ATOMIC_SWAP
+
+ Inst_MIMG__IMAGE_ATOMIC_SWAP::~Inst_MIMG__IMAGE_ATOMIC_SWAP()
+ {
+ } // ~Inst_MIMG__IMAGE_ATOMIC_SWAP
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_MIMG__IMAGE_ATOMIC_SWAP::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_ATOMIC_CMPSWAP::Inst_MIMG__IMAGE_ATOMIC_CMPSWAP(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_atomic_cmpswap")
+ {
+ setFlag(AtomicCAS);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_ATOMIC_CMPSWAP
+
+ Inst_MIMG__IMAGE_ATOMIC_CMPSWAP::~Inst_MIMG__IMAGE_ATOMIC_CMPSWAP()
+ {
+ } // ~Inst_MIMG__IMAGE_ATOMIC_CMPSWAP
+
+ // tmp = MEM[ADDR];
+ // src = DATA[0];
+ // cmp = DATA[1];
+ // MEM[ADDR] = (tmp == cmp) ? src : tmp;
+ // RETURN_DATA[0] = tmp.
+ void
+ Inst_MIMG__IMAGE_ATOMIC_CMPSWAP::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_ATOMIC_ADD::Inst_MIMG__IMAGE_ATOMIC_ADD(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_atomic_add")
+ {
+ setFlag(AtomicAdd);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_ATOMIC_ADD
+
+ Inst_MIMG__IMAGE_ATOMIC_ADD::~Inst_MIMG__IMAGE_ATOMIC_ADD()
+ {
+ } // ~Inst_MIMG__IMAGE_ATOMIC_ADD
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] += DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_MIMG__IMAGE_ATOMIC_ADD::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_ATOMIC_SUB::Inst_MIMG__IMAGE_ATOMIC_SUB(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_atomic_sub")
+ {
+ setFlag(AtomicSub);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_ATOMIC_SUB
+
+ Inst_MIMG__IMAGE_ATOMIC_SUB::~Inst_MIMG__IMAGE_ATOMIC_SUB()
+ {
+ } // ~Inst_MIMG__IMAGE_ATOMIC_SUB
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_MIMG__IMAGE_ATOMIC_SUB::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_ATOMIC_SMIN::Inst_MIMG__IMAGE_ATOMIC_SMIN(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_atomic_smin")
+ {
+ setFlag(AtomicMin);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_ATOMIC_SMIN
+
+ Inst_MIMG__IMAGE_ATOMIC_SMIN::~Inst_MIMG__IMAGE_ATOMIC_SMIN()
+ {
+ } // ~Inst_MIMG__IMAGE_ATOMIC_SMIN
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (DATA < tmp) ? DATA : tmp (signed compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_MIMG__IMAGE_ATOMIC_SMIN::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_ATOMIC_UMIN::Inst_MIMG__IMAGE_ATOMIC_UMIN(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_atomic_umin")
+ {
+ setFlag(AtomicMin);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_ATOMIC_UMIN
+
+ Inst_MIMG__IMAGE_ATOMIC_UMIN::~Inst_MIMG__IMAGE_ATOMIC_UMIN()
+ {
+ } // ~Inst_MIMG__IMAGE_ATOMIC_UMIN
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (DATA < tmp) ? DATA : tmp (unsigned compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_MIMG__IMAGE_ATOMIC_UMIN::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_ATOMIC_SMAX::Inst_MIMG__IMAGE_ATOMIC_SMAX(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_atomic_smax")
+ {
+ setFlag(AtomicMax);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_ATOMIC_SMAX
+
+ Inst_MIMG__IMAGE_ATOMIC_SMAX::~Inst_MIMG__IMAGE_ATOMIC_SMAX()
+ {
+ } // ~Inst_MIMG__IMAGE_ATOMIC_SMAX
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (DATA > tmp) ? DATA : tmp (signed compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_MIMG__IMAGE_ATOMIC_SMAX::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_ATOMIC_UMAX::Inst_MIMG__IMAGE_ATOMIC_UMAX(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_atomic_umax")
+ {
+ setFlag(AtomicMax);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_ATOMIC_UMAX
+
+ Inst_MIMG__IMAGE_ATOMIC_UMAX::~Inst_MIMG__IMAGE_ATOMIC_UMAX()
+ {
+ } // ~Inst_MIMG__IMAGE_ATOMIC_UMAX
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (DATA > tmp) ? DATA : tmp (unsigned compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_MIMG__IMAGE_ATOMIC_UMAX::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_ATOMIC_AND::Inst_MIMG__IMAGE_ATOMIC_AND(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_atomic_and")
+ {
+ setFlag(AtomicAnd);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_ATOMIC_AND
+
+ Inst_MIMG__IMAGE_ATOMIC_AND::~Inst_MIMG__IMAGE_ATOMIC_AND()
+ {
+ } // ~Inst_MIMG__IMAGE_ATOMIC_AND
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] &= DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_MIMG__IMAGE_ATOMIC_AND::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_ATOMIC_OR::Inst_MIMG__IMAGE_ATOMIC_OR(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_atomic_or")
+ {
+ setFlag(AtomicOr);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_ATOMIC_OR
+
+ Inst_MIMG__IMAGE_ATOMIC_OR::~Inst_MIMG__IMAGE_ATOMIC_OR()
+ {
+ } // ~Inst_MIMG__IMAGE_ATOMIC_OR
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] |= DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_MIMG__IMAGE_ATOMIC_OR::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_ATOMIC_XOR::Inst_MIMG__IMAGE_ATOMIC_XOR(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_atomic_xor")
+ {
+ setFlag(AtomicXor);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_ATOMIC_XOR
+
+ Inst_MIMG__IMAGE_ATOMIC_XOR::~Inst_MIMG__IMAGE_ATOMIC_XOR()
+ {
+ } // ~Inst_MIMG__IMAGE_ATOMIC_XOR
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] ^= DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_MIMG__IMAGE_ATOMIC_XOR::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_ATOMIC_INC::Inst_MIMG__IMAGE_ATOMIC_INC(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_atomic_inc")
+ {
+ setFlag(AtomicInc);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_ATOMIC_INC
+
+ Inst_MIMG__IMAGE_ATOMIC_INC::~Inst_MIMG__IMAGE_ATOMIC_INC()
+ {
+ } // ~Inst_MIMG__IMAGE_ATOMIC_INC
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (tmp >= DATA) ? 0 : tmp + 1 (unsigned compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_MIMG__IMAGE_ATOMIC_INC::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_ATOMIC_DEC::Inst_MIMG__IMAGE_ATOMIC_DEC(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_atomic_dec")
+ {
+ setFlag(AtomicDec);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_ATOMIC_DEC
+
+ Inst_MIMG__IMAGE_ATOMIC_DEC::~Inst_MIMG__IMAGE_ATOMIC_DEC()
+ {
+ } // ~Inst_MIMG__IMAGE_ATOMIC_DEC
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (tmp == 0 || tmp > DATA) ? DATA : tmp - 1
+ // (unsigned compare); RETURN_DATA = tmp.
+ void
+ Inst_MIMG__IMAGE_ATOMIC_DEC::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE::Inst_MIMG__IMAGE_SAMPLE(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE
+
+ Inst_MIMG__IMAGE_SAMPLE::~Inst_MIMG__IMAGE_SAMPLE()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_CL::Inst_MIMG__IMAGE_SAMPLE_CL(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_cl")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_CL
+
+ Inst_MIMG__IMAGE_SAMPLE_CL::~Inst_MIMG__IMAGE_SAMPLE_CL()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_CL
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_CL::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_D::Inst_MIMG__IMAGE_SAMPLE_D(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_d")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_D
+
+ Inst_MIMG__IMAGE_SAMPLE_D::~Inst_MIMG__IMAGE_SAMPLE_D()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_D
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_D::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_D_CL::Inst_MIMG__IMAGE_SAMPLE_D_CL(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_d_cl")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_D_CL
+
+ Inst_MIMG__IMAGE_SAMPLE_D_CL::~Inst_MIMG__IMAGE_SAMPLE_D_CL()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_D_CL
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_D_CL::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_L::Inst_MIMG__IMAGE_SAMPLE_L(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_l")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_L
+
+ Inst_MIMG__IMAGE_SAMPLE_L::~Inst_MIMG__IMAGE_SAMPLE_L()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_L
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_L::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_B::Inst_MIMG__IMAGE_SAMPLE_B(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_b")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_B
+
+ Inst_MIMG__IMAGE_SAMPLE_B::~Inst_MIMG__IMAGE_SAMPLE_B()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_B
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_B::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_B_CL::Inst_MIMG__IMAGE_SAMPLE_B_CL(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_b_cl")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_B_CL
+
+ Inst_MIMG__IMAGE_SAMPLE_B_CL::~Inst_MIMG__IMAGE_SAMPLE_B_CL()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_B_CL
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_B_CL::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_LZ::Inst_MIMG__IMAGE_SAMPLE_LZ(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_lz")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_LZ
+
+ Inst_MIMG__IMAGE_SAMPLE_LZ::~Inst_MIMG__IMAGE_SAMPLE_LZ()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_LZ
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_LZ::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_C::Inst_MIMG__IMAGE_SAMPLE_C(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_c")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_C
+
+ Inst_MIMG__IMAGE_SAMPLE_C::~Inst_MIMG__IMAGE_SAMPLE_C()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_C
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_C::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_C_CL::Inst_MIMG__IMAGE_SAMPLE_C_CL(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_c_cl")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_C_CL
+
+ Inst_MIMG__IMAGE_SAMPLE_C_CL::~Inst_MIMG__IMAGE_SAMPLE_C_CL()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_C_CL
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_C_CL::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_C_D::Inst_MIMG__IMAGE_SAMPLE_C_D(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_c_d")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_C_D
+
+ Inst_MIMG__IMAGE_SAMPLE_C_D::~Inst_MIMG__IMAGE_SAMPLE_C_D()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_C_D
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_C_D::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_C_D_CL::Inst_MIMG__IMAGE_SAMPLE_C_D_CL(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_c_d_cl")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_C_D_CL
+
+ Inst_MIMG__IMAGE_SAMPLE_C_D_CL::~Inst_MIMG__IMAGE_SAMPLE_C_D_CL()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_C_D_CL
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_C_D_CL::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_C_L::Inst_MIMG__IMAGE_SAMPLE_C_L(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_c_l")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_C_L
+
+ Inst_MIMG__IMAGE_SAMPLE_C_L::~Inst_MIMG__IMAGE_SAMPLE_C_L()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_C_L
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_C_L::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_C_B::Inst_MIMG__IMAGE_SAMPLE_C_B(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_c_b")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_C_B
+
+ Inst_MIMG__IMAGE_SAMPLE_C_B::~Inst_MIMG__IMAGE_SAMPLE_C_B()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_C_B
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_C_B::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_C_B_CL::Inst_MIMG__IMAGE_SAMPLE_C_B_CL(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_c_b_cl")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_C_B_CL
+
+ Inst_MIMG__IMAGE_SAMPLE_C_B_CL::~Inst_MIMG__IMAGE_SAMPLE_C_B_CL()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_C_B_CL
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_C_B_CL::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_C_LZ::Inst_MIMG__IMAGE_SAMPLE_C_LZ(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_c_lz")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_C_LZ
+
+ Inst_MIMG__IMAGE_SAMPLE_C_LZ::~Inst_MIMG__IMAGE_SAMPLE_C_LZ()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_C_LZ
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_C_LZ::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_O::Inst_MIMG__IMAGE_SAMPLE_O(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_O
+
+ Inst_MIMG__IMAGE_SAMPLE_O::~Inst_MIMG__IMAGE_SAMPLE_O()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_O
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_CL_O::Inst_MIMG__IMAGE_SAMPLE_CL_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_cl_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_CL_O
+
+ Inst_MIMG__IMAGE_SAMPLE_CL_O::~Inst_MIMG__IMAGE_SAMPLE_CL_O()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_CL_O
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_CL_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_D_O::Inst_MIMG__IMAGE_SAMPLE_D_O(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_d_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_D_O
+
+ Inst_MIMG__IMAGE_SAMPLE_D_O::~Inst_MIMG__IMAGE_SAMPLE_D_O()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_D_O
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_D_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_D_CL_O::Inst_MIMG__IMAGE_SAMPLE_D_CL_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_d_cl_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_D_CL_O
+
+ Inst_MIMG__IMAGE_SAMPLE_D_CL_O::~Inst_MIMG__IMAGE_SAMPLE_D_CL_O()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_D_CL_O
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_D_CL_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_L_O::Inst_MIMG__IMAGE_SAMPLE_L_O(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_l_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_L_O
+
+ Inst_MIMG__IMAGE_SAMPLE_L_O::~Inst_MIMG__IMAGE_SAMPLE_L_O()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_L_O
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_L_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_B_O::Inst_MIMG__IMAGE_SAMPLE_B_O(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_b_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_B_O
+
+ Inst_MIMG__IMAGE_SAMPLE_B_O::~Inst_MIMG__IMAGE_SAMPLE_B_O()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_B_O
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_B_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_B_CL_O::Inst_MIMG__IMAGE_SAMPLE_B_CL_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_b_cl_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_B_CL_O
+
+ Inst_MIMG__IMAGE_SAMPLE_B_CL_O::~Inst_MIMG__IMAGE_SAMPLE_B_CL_O()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_B_CL_O
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_B_CL_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_LZ_O::Inst_MIMG__IMAGE_SAMPLE_LZ_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_lz_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_LZ_O
+
+ Inst_MIMG__IMAGE_SAMPLE_LZ_O::~Inst_MIMG__IMAGE_SAMPLE_LZ_O()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_LZ_O
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_LZ_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_C_O::Inst_MIMG__IMAGE_SAMPLE_C_O(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_c_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_C_O
+
+ Inst_MIMG__IMAGE_SAMPLE_C_O::~Inst_MIMG__IMAGE_SAMPLE_C_O()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_C_O
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_C_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_C_CL_O::Inst_MIMG__IMAGE_SAMPLE_C_CL_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_c_cl_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_C_CL_O
+
+ Inst_MIMG__IMAGE_SAMPLE_C_CL_O::~Inst_MIMG__IMAGE_SAMPLE_C_CL_O()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_C_CL_O
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_C_CL_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_C_D_O::Inst_MIMG__IMAGE_SAMPLE_C_D_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_c_d_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_C_D_O
+
+ Inst_MIMG__IMAGE_SAMPLE_C_D_O::~Inst_MIMG__IMAGE_SAMPLE_C_D_O()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_C_D_O
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_C_D_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O::Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_c_d_cl_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O
+
+ Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O::~Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_C_L_O::Inst_MIMG__IMAGE_SAMPLE_C_L_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_c_l_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_C_L_O
+
+ Inst_MIMG__IMAGE_SAMPLE_C_L_O::~Inst_MIMG__IMAGE_SAMPLE_C_L_O()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_C_L_O
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_C_L_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_C_B_O::Inst_MIMG__IMAGE_SAMPLE_C_B_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_c_b_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_C_B_O
+
+ Inst_MIMG__IMAGE_SAMPLE_C_B_O::~Inst_MIMG__IMAGE_SAMPLE_C_B_O()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_C_B_O
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_C_B_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O::Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_c_b_cl_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O
+
+ Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O::~Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_C_LZ_O::Inst_MIMG__IMAGE_SAMPLE_C_LZ_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_c_lz_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_C_LZ_O
+
+ Inst_MIMG__IMAGE_SAMPLE_C_LZ_O::~Inst_MIMG__IMAGE_SAMPLE_C_LZ_O()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_C_LZ_O
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_C_LZ_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4::Inst_MIMG__IMAGE_GATHER4(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4
+
+ Inst_MIMG__IMAGE_GATHER4::~Inst_MIMG__IMAGE_GATHER4()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4
+
+ void
+ Inst_MIMG__IMAGE_GATHER4::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_CL::Inst_MIMG__IMAGE_GATHER4_CL(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_cl")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_CL
+
+ Inst_MIMG__IMAGE_GATHER4_CL::~Inst_MIMG__IMAGE_GATHER4_CL()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_CL
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_CL::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_L::Inst_MIMG__IMAGE_GATHER4_L(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_l")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_L
+
+ Inst_MIMG__IMAGE_GATHER4_L::~Inst_MIMG__IMAGE_GATHER4_L()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_L
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_L::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_B::Inst_MIMG__IMAGE_GATHER4_B(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_b")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_B
+
+ Inst_MIMG__IMAGE_GATHER4_B::~Inst_MIMG__IMAGE_GATHER4_B()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_B
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_B::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_B_CL::Inst_MIMG__IMAGE_GATHER4_B_CL(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_b_cl")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_B_CL
+
+ Inst_MIMG__IMAGE_GATHER4_B_CL::~Inst_MIMG__IMAGE_GATHER4_B_CL()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_B_CL
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_B_CL::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_LZ::Inst_MIMG__IMAGE_GATHER4_LZ(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_lz")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_LZ
+
+ Inst_MIMG__IMAGE_GATHER4_LZ::~Inst_MIMG__IMAGE_GATHER4_LZ()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_LZ
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_LZ::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_C::Inst_MIMG__IMAGE_GATHER4_C(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_c")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_C
+
+ Inst_MIMG__IMAGE_GATHER4_C::~Inst_MIMG__IMAGE_GATHER4_C()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_C
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_C::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_C_CL::Inst_MIMG__IMAGE_GATHER4_C_CL(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_c_cl")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_C_CL
+
+ Inst_MIMG__IMAGE_GATHER4_C_CL::~Inst_MIMG__IMAGE_GATHER4_C_CL()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_C_CL
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_C_CL::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_C_L::Inst_MIMG__IMAGE_GATHER4_C_L(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_c_l")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_C_L
+
+ Inst_MIMG__IMAGE_GATHER4_C_L::~Inst_MIMG__IMAGE_GATHER4_C_L()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_C_L
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_C_L::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_C_B::Inst_MIMG__IMAGE_GATHER4_C_B(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_c_b")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_C_B
+
+ Inst_MIMG__IMAGE_GATHER4_C_B::~Inst_MIMG__IMAGE_GATHER4_C_B()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_C_B
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_C_B::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_C_B_CL::Inst_MIMG__IMAGE_GATHER4_C_B_CL(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_c_b_cl")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_C_B_CL
+
+ Inst_MIMG__IMAGE_GATHER4_C_B_CL::~Inst_MIMG__IMAGE_GATHER4_C_B_CL()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_C_B_CL
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_C_B_CL::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_C_LZ::Inst_MIMG__IMAGE_GATHER4_C_LZ(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_c_lz")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_C_LZ
+
+ Inst_MIMG__IMAGE_GATHER4_C_LZ::~Inst_MIMG__IMAGE_GATHER4_C_LZ()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_C_LZ
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_C_LZ::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_O::Inst_MIMG__IMAGE_GATHER4_O(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_O
+
+ Inst_MIMG__IMAGE_GATHER4_O::~Inst_MIMG__IMAGE_GATHER4_O()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_O
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_CL_O::Inst_MIMG__IMAGE_GATHER4_CL_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_cl_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_CL_O
+
+ Inst_MIMG__IMAGE_GATHER4_CL_O::~Inst_MIMG__IMAGE_GATHER4_CL_O()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_CL_O
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_CL_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_L_O::Inst_MIMG__IMAGE_GATHER4_L_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_l_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_L_O
+
+ Inst_MIMG__IMAGE_GATHER4_L_O::~Inst_MIMG__IMAGE_GATHER4_L_O()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_L_O
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_L_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_B_O::Inst_MIMG__IMAGE_GATHER4_B_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_b_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_B_O
+
+ Inst_MIMG__IMAGE_GATHER4_B_O::~Inst_MIMG__IMAGE_GATHER4_B_O()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_B_O
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_B_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_B_CL_O::Inst_MIMG__IMAGE_GATHER4_B_CL_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_b_cl_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_B_CL_O
+
+ Inst_MIMG__IMAGE_GATHER4_B_CL_O::~Inst_MIMG__IMAGE_GATHER4_B_CL_O()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_B_CL_O
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_B_CL_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_LZ_O::Inst_MIMG__IMAGE_GATHER4_LZ_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_lz_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_LZ_O
+
+ Inst_MIMG__IMAGE_GATHER4_LZ_O::~Inst_MIMG__IMAGE_GATHER4_LZ_O()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_LZ_O
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_LZ_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_C_O::Inst_MIMG__IMAGE_GATHER4_C_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_c_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_C_O
+
+ Inst_MIMG__IMAGE_GATHER4_C_O::~Inst_MIMG__IMAGE_GATHER4_C_O()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_C_O
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_C_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_C_CL_O::Inst_MIMG__IMAGE_GATHER4_C_CL_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_c_cl_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_C_CL_O
+
+ Inst_MIMG__IMAGE_GATHER4_C_CL_O::~Inst_MIMG__IMAGE_GATHER4_C_CL_O()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_C_CL_O
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_C_CL_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_C_L_O::Inst_MIMG__IMAGE_GATHER4_C_L_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_c_l_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_C_L_O
+
+ Inst_MIMG__IMAGE_GATHER4_C_L_O::~Inst_MIMG__IMAGE_GATHER4_C_L_O()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_C_L_O
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_C_L_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_C_B_O::Inst_MIMG__IMAGE_GATHER4_C_B_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_c_b_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_C_B_O
+
+ Inst_MIMG__IMAGE_GATHER4_C_B_O::~Inst_MIMG__IMAGE_GATHER4_C_B_O()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_C_B_O
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_C_B_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_C_B_CL_O::Inst_MIMG__IMAGE_GATHER4_C_B_CL_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_c_b_cl_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_C_B_CL_O
+
+ Inst_MIMG__IMAGE_GATHER4_C_B_CL_O::~Inst_MIMG__IMAGE_GATHER4_C_B_CL_O()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_C_B_CL_O
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_C_B_CL_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GATHER4_C_LZ_O::Inst_MIMG__IMAGE_GATHER4_C_LZ_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_gather4_c_lz_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GATHER4_C_LZ_O
+
+ Inst_MIMG__IMAGE_GATHER4_C_LZ_O::~Inst_MIMG__IMAGE_GATHER4_C_LZ_O()
+ {
+ } // ~Inst_MIMG__IMAGE_GATHER4_C_LZ_O
+
+ void
+ Inst_MIMG__IMAGE_GATHER4_C_LZ_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_GET_LOD::Inst_MIMG__IMAGE_GET_LOD(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_get_lod")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_GET_LOD
+
+ Inst_MIMG__IMAGE_GET_LOD::~Inst_MIMG__IMAGE_GET_LOD()
+ {
+ } // ~Inst_MIMG__IMAGE_GET_LOD
+
+ void
+ Inst_MIMG__IMAGE_GET_LOD::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_CD::Inst_MIMG__IMAGE_SAMPLE_CD(InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_cd")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_CD
+
+ Inst_MIMG__IMAGE_SAMPLE_CD::~Inst_MIMG__IMAGE_SAMPLE_CD()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_CD
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_CD::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_CD_CL::Inst_MIMG__IMAGE_SAMPLE_CD_CL(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_cd_cl")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_CD_CL
+
+ Inst_MIMG__IMAGE_SAMPLE_CD_CL::~Inst_MIMG__IMAGE_SAMPLE_CD_CL()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_CD_CL
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_CD_CL::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_C_CD::Inst_MIMG__IMAGE_SAMPLE_C_CD(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_c_cd")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_C_CD
+
+ Inst_MIMG__IMAGE_SAMPLE_C_CD::~Inst_MIMG__IMAGE_SAMPLE_C_CD()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_C_CD
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_C_CD::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_C_CD_CL::Inst_MIMG__IMAGE_SAMPLE_C_CD_CL(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_c_cd_cl")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_C_CD_CL
+
+ Inst_MIMG__IMAGE_SAMPLE_C_CD_CL::~Inst_MIMG__IMAGE_SAMPLE_C_CD_CL()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_C_CD_CL
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_C_CD_CL::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_CD_O::Inst_MIMG__IMAGE_SAMPLE_CD_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_cd_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_CD_O
+
+ Inst_MIMG__IMAGE_SAMPLE_CD_O::~Inst_MIMG__IMAGE_SAMPLE_CD_O()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_CD_O
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_CD_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_CD_CL_O::Inst_MIMG__IMAGE_SAMPLE_CD_CL_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_cd_cl_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_CD_CL_O
+
+ Inst_MIMG__IMAGE_SAMPLE_CD_CL_O::~Inst_MIMG__IMAGE_SAMPLE_CD_CL_O()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_CD_CL_O
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_CD_CL_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_C_CD_O::Inst_MIMG__IMAGE_SAMPLE_C_CD_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_c_cd_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_C_CD_O
+
+ Inst_MIMG__IMAGE_SAMPLE_C_CD_O::~Inst_MIMG__IMAGE_SAMPLE_C_CD_O()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_C_CD_O
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_C_CD_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O::Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O(
+ InFmt_MIMG *iFmt)
+ : Inst_MIMG(iFmt, "image_sample_c_cd_cl_o")
+ {
+ setFlag(GlobalSegment);
+ } // Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O
+
+ Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O::~Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O()
+ {
+ } // ~Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O
+
+ void
+ Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_EXP__EXP::Inst_EXP__EXP(InFmt_EXP *iFmt)
+ : Inst_EXP(iFmt, "exp")
+ {
+ } // Inst_EXP__EXP
+
+ Inst_EXP__EXP::~Inst_EXP__EXP()
+ {
+ } // ~Inst_EXP__EXP
+
+ void
+ Inst_EXP__EXP::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_FLAT__FLAT_LOAD_UBYTE::Inst_FLAT__FLAT_LOAD_UBYTE(InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_load_ubyte")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_FLAT__FLAT_LOAD_UBYTE
+
+ Inst_FLAT__FLAT_LOAD_UBYTE::~Inst_FLAT__FLAT_LOAD_UBYTE()
+ {
+ } // ~Inst_FLAT__FLAT_LOAD_UBYTE
+
+ // Untyped buffer load unsigned byte (zero extend to VGPR destination).
+ void
+ Inst_FLAT__FLAT_LOAD_UBYTE::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ if (wf->execMask().none()) {
+ wf->rdGmReqsInPipe--;
+ wf->rdLmReqsInPipe--;
+ return;
+ }
+
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = gpuDynInst->wavefront()->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
+ gpuDynInst->computeUnit()->globalMemoryPipe
+ .issueRequest(gpuDynInst);
+ wf->rdGmReqsInPipe--;
+ wf->outstandingReqsRdGm++;
+ } else {
+ fatal("Non global flat instructions not implemented yet.\n");
+ }
+
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ } // execute
+
+ void
+ Inst_FLAT__FLAT_LOAD_UBYTE::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ initMemRead<VecElemU8>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_FLAT__FLAT_LOAD_UBYTE::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ VecOperandU32 vdst(gpuDynInst, extData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ vdst[lane] = (VecElemU32)((reinterpret_cast<VecElemU8*>(
+ gpuDynInst->d_data))[lane]);
+ }
+ }
+ vdst.write();
+ } // execute
+ // --- Inst_FLAT__FLAT_LOAD_SBYTE class methods ---
+
+ Inst_FLAT__FLAT_LOAD_SBYTE::Inst_FLAT__FLAT_LOAD_SBYTE(InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_load_sbyte")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_FLAT__FLAT_LOAD_SBYTE
+
+ Inst_FLAT__FLAT_LOAD_SBYTE::~Inst_FLAT__FLAT_LOAD_SBYTE()
+ {
+ } // ~Inst_FLAT__FLAT_LOAD_SBYTE
+
+ // Untyped buffer load signed byte (sign extend to VGPR destination).
+ void
+ Inst_FLAT__FLAT_LOAD_SBYTE::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_FLAT__FLAT_LOAD_SBYTE::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_FLAT__FLAT_LOAD_SBYTE::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_FLAT__FLAT_LOAD_USHORT::Inst_FLAT__FLAT_LOAD_USHORT(InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_load_ushort")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_FLAT__FLAT_LOAD_USHORT
+
+ Inst_FLAT__FLAT_LOAD_USHORT::~Inst_FLAT__FLAT_LOAD_USHORT()
+ {
+ } // ~Inst_FLAT__FLAT_LOAD_USHORT
+
+ // Untyped buffer load unsigned short (zero extend to VGPR destination).
+ void
+ Inst_FLAT__FLAT_LOAD_USHORT::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ if (wf->execMask().none()) {
+ wf->rdGmReqsInPipe--;
+ wf->rdLmReqsInPipe--;
+ return;
+ }
+
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = gpuDynInst->wavefront()->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
+ gpuDynInst->computeUnit()->globalMemoryPipe
+ .issueRequest(gpuDynInst);
+ wf->rdGmReqsInPipe--;
+ wf->outstandingReqsRdGm++;
+ } else {
+ fatal("Non global flat instructions not implemented yet.\n");
+ }
+
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ }
+
+ void
+ Inst_FLAT__FLAT_LOAD_USHORT::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ initMemRead<VecElemU16>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_FLAT__FLAT_LOAD_USHORT::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ VecOperandU32 vdst(gpuDynInst, extData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ vdst[lane] = (VecElemU32)((reinterpret_cast<VecElemU16*>(
+ gpuDynInst->d_data))[lane]);
+ }
+ }
+ vdst.write();
+ }
+
+
+ Inst_FLAT__FLAT_LOAD_SSHORT::Inst_FLAT__FLAT_LOAD_SSHORT(InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_load_sshort")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_FLAT__FLAT_LOAD_SSHORT
+
+ Inst_FLAT__FLAT_LOAD_SSHORT::~Inst_FLAT__FLAT_LOAD_SSHORT()
+ {
+ } // ~Inst_FLAT__FLAT_LOAD_SSHORT
+
+ // Untyped buffer load signed short (sign extend to VGPR destination).
+ void
+ Inst_FLAT__FLAT_LOAD_SSHORT::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ void
+ Inst_FLAT__FLAT_LOAD_SSHORT::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // initiateAcc
+
+ void
+ Inst_FLAT__FLAT_LOAD_SSHORT::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_FLAT__FLAT_LOAD_DWORD::Inst_FLAT__FLAT_LOAD_DWORD(InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_load_dword")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_FLAT__FLAT_LOAD_DWORD
+
+ Inst_FLAT__FLAT_LOAD_DWORD::~Inst_FLAT__FLAT_LOAD_DWORD()
+ {
+ } // ~Inst_FLAT__FLAT_LOAD_DWORD
+
+ // Untyped buffer load dword.
+ void
+ Inst_FLAT__FLAT_LOAD_DWORD::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ if (wf->execMask().none()) {
+ wf->rdGmReqsInPipe--;
+ wf->rdLmReqsInPipe--;
+ return;
+ }
+
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = gpuDynInst->wavefront()->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
+ gpuDynInst->computeUnit()->globalMemoryPipe
+ .issueRequest(gpuDynInst);
+ wf->rdGmReqsInPipe--;
+ wf->outstandingReqsRdGm++;
+ } else {
+ fatal("Non global flat instructions not implemented yet.\n");
+ }
+
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ }
+
+ void
+ Inst_FLAT__FLAT_LOAD_DWORD::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ initMemRead<VecElemU32>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_FLAT__FLAT_LOAD_DWORD::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ VecOperandU32 vdst(gpuDynInst, extData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ vdst[lane] = (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane];
+ }
+ }
+ vdst.write();
+ } // completeAcc
+
+ Inst_FLAT__FLAT_LOAD_DWORDX2::Inst_FLAT__FLAT_LOAD_DWORDX2(
+ InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_load_dwordx2")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_FLAT__FLAT_LOAD_DWORDX2
+
+ Inst_FLAT__FLAT_LOAD_DWORDX2::~Inst_FLAT__FLAT_LOAD_DWORDX2()
+ {
+ } // ~Inst_FLAT__FLAT_LOAD_DWORDX2
+
+ // Untyped buffer load 2 dwords.
+ void
+ Inst_FLAT__FLAT_LOAD_DWORDX2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ if (wf->execMask().none()) {
+ wf->rdGmReqsInPipe--;
+ wf->rdLmReqsInPipe--;
+ return;
+ }
+
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = gpuDynInst->wavefront()->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
+ gpuDynInst->computeUnit()->globalMemoryPipe
+ .issueRequest(gpuDynInst);
+ wf->rdGmReqsInPipe--;
+ wf->outstandingReqsRdGm++;
+ } else {
+ fatal("Non global flat instructions not implemented yet.\n");
+ }
+
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ }
+
+ void
+ Inst_FLAT__FLAT_LOAD_DWORDX2::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ initMemRead<VecElemU64>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_FLAT__FLAT_LOAD_DWORDX2::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ VecOperandU64 vdst(gpuDynInst, extData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ vdst[lane] = (reinterpret_cast<VecElemU64*>(
+ gpuDynInst->d_data))[lane];
+ }
+ }
+ vdst.write();
+ } // completeAcc
+
+ Inst_FLAT__FLAT_LOAD_DWORDX3::Inst_FLAT__FLAT_LOAD_DWORDX3(
+ InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_load_dwordx3")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_FLAT__FLAT_LOAD_DWORDX3
+
+ Inst_FLAT__FLAT_LOAD_DWORDX3::~Inst_FLAT__FLAT_LOAD_DWORDX3()
+ {
+ } // ~Inst_FLAT__FLAT_LOAD_DWORDX3
+
+ // Untyped buffer load 3 dwords.
+ void
+ Inst_FLAT__FLAT_LOAD_DWORDX3::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ if (wf->execMask().none()) {
+ wf->rdGmReqsInPipe--;
+ wf->rdLmReqsInPipe--;
+ return;
+ }
+
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
+ gpuDynInst->computeUnit()->globalMemoryPipe
+ .issueRequest(gpuDynInst);
+ wf->rdGmReqsInPipe--;
+ wf->outstandingReqsRdGm++;
+ } else {
+ fatal("Non global flat instructions not implemented yet.\n");
+ }
+
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ }
+
+ void
+ Inst_FLAT__FLAT_LOAD_DWORDX3::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ initMemRead<3>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_FLAT__FLAT_LOAD_DWORDX3::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ VecOperandU32 vdst0(gpuDynInst, extData.VDST);
+ VecOperandU32 vdst1(gpuDynInst, extData.VDST + 1);
+ VecOperandU32 vdst2(gpuDynInst, extData.VDST + 2);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ vdst0[lane] = (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane * 3];
+ vdst1[lane] = (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane * 3 + 1];
+ vdst2[lane] = (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane * 3 + 2];
+ }
+ }
+
+ vdst0.write();
+ vdst1.write();
+ vdst2.write();
+ } // completeAcc
+
+ Inst_FLAT__FLAT_LOAD_DWORDX4::Inst_FLAT__FLAT_LOAD_DWORDX4(
+ InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_load_dwordx4")
+ {
+ setFlag(MemoryRef);
+ setFlag(Load);
+ } // Inst_FLAT__FLAT_LOAD_DWORDX4
+
+ Inst_FLAT__FLAT_LOAD_DWORDX4::~Inst_FLAT__FLAT_LOAD_DWORDX4()
+ {
+ } // ~Inst_FLAT__FLAT_LOAD_DWORDX4
+
+ // Untyped buffer load 4 dwords.
+ void
+ Inst_FLAT__FLAT_LOAD_DWORDX4::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ if (wf->execMask().none()) {
+ wf->rdGmReqsInPipe--;
+ wf->rdLmReqsInPipe--;
+ }
+
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
+ gpuDynInst->computeUnit()->globalMemoryPipe
+ .issueRequest(gpuDynInst);
+ wf->rdGmReqsInPipe--;
+ wf->outstandingReqsRdGm++;
+ } else {
+ fatal("Non global flat instructions not implemented yet.\n");
+ }
+
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ }
+
+ void
+ Inst_FLAT__FLAT_LOAD_DWORDX4::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ initMemRead<4>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_FLAT__FLAT_LOAD_DWORDX4::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ VecOperandU32 vdst0(gpuDynInst, extData.VDST);
+ VecOperandU32 vdst1(gpuDynInst, extData.VDST + 1);
+ VecOperandU32 vdst2(gpuDynInst, extData.VDST + 2);
+ VecOperandU32 vdst3(gpuDynInst, extData.VDST + 3);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ vdst0[lane] = (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane * 4];
+ vdst1[lane] = (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane * 4 + 1];
+ vdst2[lane] = (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane * 4 + 2];
+ vdst3[lane] = (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane * 4 + 3];
+ }
+ }
+
+ vdst0.write();
+ vdst1.write();
+ vdst2.write();
+ vdst3.write();
+ } // completeAcc
+
+ Inst_FLAT__FLAT_STORE_BYTE::Inst_FLAT__FLAT_STORE_BYTE(InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_store_byte")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_FLAT__FLAT_STORE_BYTE
+
+ Inst_FLAT__FLAT_STORE_BYTE::~Inst_FLAT__FLAT_STORE_BYTE()
+ {
+ } // ~Inst_FLAT__FLAT_STORE_BYTE
+
+ // Untyped buffer store byte.
+ void
+ Inst_FLAT__FLAT_STORE_BYTE::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ if (wf->execMask().none()) {
+ wf->wrGmReqsInPipe--;
+ wf->wrLmReqsInPipe--;
+ return;
+ }
+
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
+ gpuDynInst->computeUnit()->globalMemoryPipe
+ .issueRequest(gpuDynInst);
+ wf->wrGmReqsInPipe--;
+ wf->outstandingReqsWrGm++;
+ } else {
+ fatal("Non global flat instructions not implemented yet.\n");
+ }
+
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ } // execute
+
+ void
+ Inst_FLAT__FLAT_STORE_BYTE::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ ConstVecOperandU8 data(gpuDynInst, extData.DATA);
+ data.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ (reinterpret_cast<VecElemU8*>(gpuDynInst->d_data))[lane]
+ = data[lane];
+ }
+ }
+
+ initMemWrite<VecElemU8>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_FLAT__FLAT_STORE_BYTE::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ }
+
+ Inst_FLAT__FLAT_STORE_SHORT::Inst_FLAT__FLAT_STORE_SHORT(InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_store_short")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_FLAT__FLAT_STORE_SHORT
+
+ Inst_FLAT__FLAT_STORE_SHORT::~Inst_FLAT__FLAT_STORE_SHORT()
+ {
+ } // ~Inst_FLAT__FLAT_STORE_SHORT
+
+ // Untyped buffer store short.
+ void
+ Inst_FLAT__FLAT_STORE_SHORT::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ if (wf->execMask().none()) {
+ wf->wrGmReqsInPipe--;
+ wf->wrLmReqsInPipe--;
+ return;
+ }
+
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
+ gpuDynInst->computeUnit()->globalMemoryPipe
+ .issueRequest(gpuDynInst);
+ wf->wrGmReqsInPipe--;
+ wf->outstandingReqsWrGm++;
+ } else {
+ fatal("Non global flat instructions not implemented yet.\n");
+ }
+
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ }
+
+ void
+ Inst_FLAT__FLAT_STORE_SHORT::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ ConstVecOperandU16 data(gpuDynInst, extData.DATA);
+
+ data.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ (reinterpret_cast<VecElemU16*>(gpuDynInst->d_data))[lane]
+ = data[lane];
+ }
+ }
+
+ initMemWrite<VecElemU16>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_FLAT__FLAT_STORE_SHORT::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_FLAT__FLAT_STORE_DWORD::Inst_FLAT__FLAT_STORE_DWORD(InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_store_dword")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_FLAT__FLAT_STORE_DWORD
+
+ Inst_FLAT__FLAT_STORE_DWORD::~Inst_FLAT__FLAT_STORE_DWORD()
+ {
+ } // ~Inst_FLAT__FLAT_STORE_DWORD
+
+ // Untyped buffer store dword.
+ void
+ Inst_FLAT__FLAT_STORE_DWORD::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ if (wf->execMask().none()) {
+ wf->wrGmReqsInPipe--;
+ wf->wrLmReqsInPipe--;
+ return;
+ }
+
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
+ gpuDynInst->computeUnit()->globalMemoryPipe
+ .issueRequest(gpuDynInst);
+ wf->wrGmReqsInPipe--;
+ wf->outstandingReqsWrGm++;
+ } else {
+ fatal("Non global flat instructions not implemented yet.\n");
+ }
+
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ }
+
+ void
+ Inst_FLAT__FLAT_STORE_DWORD::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ ConstVecOperandU32 data(gpuDynInst, extData.DATA);
+ data.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ (reinterpret_cast<VecElemU32*>(gpuDynInst->d_data))[lane]
+ = data[lane];
+ }
+ }
+
+ initMemWrite<VecElemU32>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_FLAT__FLAT_STORE_DWORD::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_FLAT__FLAT_STORE_DWORDX2::Inst_FLAT__FLAT_STORE_DWORDX2(
+ InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_store_dwordx2")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_FLAT__FLAT_STORE_DWORDX2
+
+ Inst_FLAT__FLAT_STORE_DWORDX2::~Inst_FLAT__FLAT_STORE_DWORDX2()
+ {
+ } // ~Inst_FLAT__FLAT_STORE_DWORDX2
+
+ // Untyped buffer store 2 dwords.
+ void
+ Inst_FLAT__FLAT_STORE_DWORDX2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ if (wf->execMask().none()) {
+ wf->wrGmReqsInPipe--;
+ wf->wrLmReqsInPipe--;
+ return;
+ }
+
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
+ gpuDynInst->computeUnit()->globalMemoryPipe
+ .issueRequest(gpuDynInst);
+ wf->wrGmReqsInPipe--;
+ wf->outstandingReqsWrGm++;
+ } else {
+ fatal("Non global flat instructions not implemented yet.\n");
+ }
+
+ wf->outstandingReqs++;
+ wf->validateRequestCounters();
+ }
+
+ void
+ Inst_FLAT__FLAT_STORE_DWORDX2::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ ConstVecOperandU64 data(gpuDynInst, extData.DATA);
+ data.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ (reinterpret_cast<VecElemU64*>(gpuDynInst->d_data))[lane]
+ = data[lane];
+ }
+ }
+
+ initMemWrite<VecElemU64>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_FLAT__FLAT_STORE_DWORDX2::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_FLAT__FLAT_STORE_DWORDX3::Inst_FLAT__FLAT_STORE_DWORDX3(
+ InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_store_dwordx3")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_FLAT__FLAT_STORE_DWORDX3
+
+ Inst_FLAT__FLAT_STORE_DWORDX3::~Inst_FLAT__FLAT_STORE_DWORDX3()
+ {
+ } // ~Inst_FLAT__FLAT_STORE_DWORDX3
+
+ // Untyped buffer store 3 dwords.
+ void
+ Inst_FLAT__FLAT_STORE_DWORDX3::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ if (wf->execMask().none()) {
+ wf->wrGmReqsInPipe--;
+ wf->wrLmReqsInPipe--;
+ return;
+ }
+
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
+ gpuDynInst->computeUnit()->globalMemoryPipe
+ .issueRequest(gpuDynInst);
+ wf->wrGmReqsInPipe--;
+ wf->outstandingReqsWrGm++;
+ } else {
+ fatal("Non global flat instructions not implemented yet.\n");
+ }
+
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ }
+
+ void
+ Inst_FLAT__FLAT_STORE_DWORDX3::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ ConstVecOperandU32 data0(gpuDynInst, extData.DATA);
+ ConstVecOperandU32 data1(gpuDynInst, extData.DATA + 1);
+ ConstVecOperandU32 data2(gpuDynInst, extData.DATA + 2);
+
+ data0.read();
+ data1.read();
+ data2.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane * 3] = data0[lane];
+ (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane * 3 + 1] = data1[lane];
+ (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane * 3 + 2] = data2[lane];
+ }
+ }
+
+ initMemWrite<3>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_FLAT__FLAT_STORE_DWORDX3::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_FLAT__FLAT_STORE_DWORDX4::Inst_FLAT__FLAT_STORE_DWORDX4(
+ InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_store_dwordx4")
+ {
+ setFlag(MemoryRef);
+ setFlag(Store);
+ } // Inst_FLAT__FLAT_STORE_DWORDX4
+
+ Inst_FLAT__FLAT_STORE_DWORDX4::~Inst_FLAT__FLAT_STORE_DWORDX4()
+ {
+ } // ~Inst_FLAT__FLAT_STORE_DWORDX4
+
+ // Untyped buffer store 4 dwords.
+ void
+ Inst_FLAT__FLAT_STORE_DWORDX4::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ if (wf->execMask().none()) {
+ wf->wrGmReqsInPipe--;
+ wf->wrLmReqsInPipe--;
+ return;
+ }
+
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
+ gpuDynInst->computeUnit()->globalMemoryPipe
+ .issueRequest(gpuDynInst);
+ wf->wrGmReqsInPipe--;
+ wf->outstandingReqsWrGm++;
+ } else {
+ fatal("Non global flat instructions not implemented yet.\n");
+ }
+
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ }
+
+ void
+ Inst_FLAT__FLAT_STORE_DWORDX4::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ ConstVecOperandU32 data0(gpuDynInst, extData.DATA);
+ ConstVecOperandU32 data1(gpuDynInst, extData.DATA + 1);
+ ConstVecOperandU32 data2(gpuDynInst, extData.DATA + 2);
+ ConstVecOperandU32 data3(gpuDynInst, extData.DATA + 3);
+
+ data0.read();
+ data1.read();
+ data2.read();
+ data3.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane * 4] = data0[lane];
+ (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane * 4 + 1] = data1[lane];
+ (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane * 4 + 2] = data2[lane];
+ (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane * 4 + 3] = data3[lane];
+ }
+ }
+
+ initMemWrite<4>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_FLAT__FLAT_STORE_DWORDX4::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
+
+ Inst_FLAT__FLAT_ATOMIC_SWAP::Inst_FLAT__FLAT_ATOMIC_SWAP(InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_swap")
+ {
+ setFlag(AtomicExch);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ } // if
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_SWAP
+
+ Inst_FLAT__FLAT_ATOMIC_SWAP::~Inst_FLAT__FLAT_ATOMIC_SWAP()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_SWAP
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_SWAP::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_FLAT__FLAT_ATOMIC_CMPSWAP
+ ::Inst_FLAT__FLAT_ATOMIC_CMPSWAP(InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_cmpswap")
+ {
+ setFlag(AtomicCAS);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ } // if
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_CMPSWAP
+
+ Inst_FLAT__FLAT_ATOMIC_CMPSWAP::~Inst_FLAT__FLAT_ATOMIC_CMPSWAP()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_CMPSWAP
+
+ // tmp = MEM[ADDR];
+ // src = DATA[0];
+ // cmp = DATA[1];
+ // MEM[ADDR] = (tmp == cmp) ? src : tmp;
+ // RETURN_DATA[0] = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_CMPSWAP::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ if (wf->execMask().none()) {
+ wf->wrGmReqsInPipe--;
+ wf->rdGmReqsInPipe--;
+ return;
+ }
+
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ if (gpuDynInst->executedAs() == Enums::SC_GLOBAL ||
+ gpuDynInst->executedAs() == Enums::SC_PRIVATE) {
+ /**
+ * TODO: If you encounter this panic, just remove this panic
+ * and restart the simulation. It should just work fine but
+ * this is to warn user that this path is never tested although
+ * all the necessary logic is implemented
+ */
+ panic_if(gpuDynInst->executedAs() == Enums::SC_PRIVATE,
+ "Flats to private aperture not tested yet\n");
+ gpuDynInst->computeUnit()->globalMemoryPipe.
+ issueRequest(gpuDynInst);
+ wf->wrGmReqsInPipe--;
+ wf->outstandingReqsWrGm++;
+ wf->rdGmReqsInPipe--;
+ wf->outstandingReqsRdGm++;
+ } else {
+ fatal("Non global flat instructions not implemented yet.\n");
+ }
+
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ }
+
+ void
+ Inst_FLAT__FLAT_ATOMIC_CMPSWAP::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ ConstVecOperandU32 data(gpuDynInst, extData.DATA);
+ ConstVecOperandU32 cmp(gpuDynInst, extData.DATA + 1);
+
+ data.read();
+ cmp.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ (reinterpret_cast<VecElemU32*>(gpuDynInst->x_data))[lane]
+ = data[lane];
+ (reinterpret_cast<VecElemU32*>(gpuDynInst->a_data))[lane]
+ = cmp[lane];
+ }
+ }
+
+ initAtomicAccess<VecElemU32>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_FLAT__FLAT_ATOMIC_CMPSWAP::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ if (isAtomicRet()) {
+ VecOperandU32 vdst(gpuDynInst, extData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ vdst[lane] = (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane];
+ }
+ }
+
+ vdst.write();
+ }
+ } // completeAcc
+
+ Inst_FLAT__FLAT_ATOMIC_ADD::Inst_FLAT__FLAT_ATOMIC_ADD(InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_add")
+ {
+ setFlag(AtomicAdd);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ } // if
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_ADD
+
+ Inst_FLAT__FLAT_ATOMIC_ADD::~Inst_FLAT__FLAT_ATOMIC_ADD()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_ADD
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] += DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_ADD::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ if (wf->execMask().none()) {
+ wf->wrGmReqsInPipe--;
+ wf->rdGmReqsInPipe--;
+ return;
+ }
+
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
+ gpuDynInst->computeUnit()->globalMemoryPipe.
+ issueRequest(gpuDynInst);
+ wf->wrGmReqsInPipe--;
+ wf->outstandingReqsWrGm++;
+ wf->rdGmReqsInPipe--;
+ wf->outstandingReqsRdGm++;
+ } else {
+ fatal("Non global flat instructions not implemented yet.\n");
+ }
+
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ }
+
+ void
+ Inst_FLAT__FLAT_ATOMIC_ADD::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ ConstVecOperandU32 data(gpuDynInst, extData.DATA);
+
+ data.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ (reinterpret_cast<VecElemU32*>(gpuDynInst->a_data))[lane]
+ = data[lane];
+ }
+ }
+
+ initAtomicAccess<VecElemU32>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_FLAT__FLAT_ATOMIC_ADD::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ if (isAtomicRet()) {
+ VecOperandU32 vdst(gpuDynInst, extData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ vdst[lane] = (reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane];
+ }
+ }
+
+ vdst.write();
+ }
+ } // completeAcc
+
+ Inst_FLAT__FLAT_ATOMIC_SUB::Inst_FLAT__FLAT_ATOMIC_SUB(InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_sub")
+ {
+ setFlag(AtomicSub);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ } // if
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_SUB
+
+ Inst_FLAT__FLAT_ATOMIC_SUB::~Inst_FLAT__FLAT_ATOMIC_SUB()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_SUB
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_SUB::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_FLAT__FLAT_ATOMIC_SMIN::Inst_FLAT__FLAT_ATOMIC_SMIN(InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_smin")
+ {
+ setFlag(AtomicMin);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_SMIN
+
+ Inst_FLAT__FLAT_ATOMIC_SMIN::~Inst_FLAT__FLAT_ATOMIC_SMIN()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_SMIN
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (DATA < tmp) ? DATA : tmp (signed compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_SMIN::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_FLAT__FLAT_ATOMIC_UMIN::Inst_FLAT__FLAT_ATOMIC_UMIN(InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_umin")
+ {
+ setFlag(AtomicMin);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_UMIN
+
+ Inst_FLAT__FLAT_ATOMIC_UMIN::~Inst_FLAT__FLAT_ATOMIC_UMIN()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_UMIN
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (DATA < tmp) ? DATA : tmp (unsigned compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_UMIN::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_FLAT__FLAT_ATOMIC_SMAX::Inst_FLAT__FLAT_ATOMIC_SMAX(InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_smax")
+ {
+ setFlag(AtomicMax);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_SMAX
+
+ Inst_FLAT__FLAT_ATOMIC_SMAX::~Inst_FLAT__FLAT_ATOMIC_SMAX()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_SMAX
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (DATA > tmp) ? DATA : tmp (signed compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_SMAX::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_FLAT__FLAT_ATOMIC_UMAX::Inst_FLAT__FLAT_ATOMIC_UMAX(InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_umax")
+ {
+ setFlag(AtomicMax);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_UMAX
+
+ Inst_FLAT__FLAT_ATOMIC_UMAX::~Inst_FLAT__FLAT_ATOMIC_UMAX()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_UMAX
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (DATA > tmp) ? DATA : tmp (unsigned compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_UMAX::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_FLAT__FLAT_ATOMIC_AND::Inst_FLAT__FLAT_ATOMIC_AND(InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_and")
+ {
+ setFlag(AtomicAnd);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_AND
+
+ Inst_FLAT__FLAT_ATOMIC_AND::~Inst_FLAT__FLAT_ATOMIC_AND()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_AND
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] &= DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_AND::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_FLAT__FLAT_ATOMIC_OR::Inst_FLAT__FLAT_ATOMIC_OR(InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_or")
+ {
+ setFlag(AtomicOr);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_OR
+
+ Inst_FLAT__FLAT_ATOMIC_OR::~Inst_FLAT__FLAT_ATOMIC_OR()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_OR
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] |= DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_OR::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_FLAT__FLAT_ATOMIC_XOR::Inst_FLAT__FLAT_ATOMIC_XOR(InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_xor")
+ {
+ setFlag(AtomicXor);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_XOR
+
+ Inst_FLAT__FLAT_ATOMIC_XOR::~Inst_FLAT__FLAT_ATOMIC_XOR()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_XOR
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] ^= DATA;
+ // RETURN_DATA = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_XOR::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_FLAT__FLAT_ATOMIC_INC::Inst_FLAT__FLAT_ATOMIC_INC(InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_inc")
+ {
+ setFlag(AtomicInc);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_INC
+
+ Inst_FLAT__FLAT_ATOMIC_INC::~Inst_FLAT__FLAT_ATOMIC_INC()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_INC
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (tmp >= DATA) ? 0 : tmp + 1 (unsigned compare);
+ // RETURN_DATA = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_INC::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_FLAT__FLAT_ATOMIC_DEC::Inst_FLAT__FLAT_ATOMIC_DEC(InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_dec")
+ {
+ setFlag(AtomicDec);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_DEC
+
+ Inst_FLAT__FLAT_ATOMIC_DEC::~Inst_FLAT__FLAT_ATOMIC_DEC()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_DEC
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (tmp == 0 || tmp > DATA) ? DATA : tmp - 1
+ // (unsigned compare); RETURN_DATA = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_DEC::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_FLAT__FLAT_ATOMIC_SWAP_X2::Inst_FLAT__FLAT_ATOMIC_SWAP_X2(
+ InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_swap_x2")
+ {
+ setFlag(AtomicExch);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_SWAP_X2
+
+ Inst_FLAT__FLAT_ATOMIC_SWAP_X2::~Inst_FLAT__FLAT_ATOMIC_SWAP_X2()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_SWAP_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = DATA[0:1];
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_SWAP_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2::Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2(
+ InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_cmpswap_x2")
+ {
+ setFlag(AtomicCAS);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2
+
+ Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2::~Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2
+
+ // tmp = MEM[ADDR];
+ // src = DATA[0:1];
+ // cmp = DATA[2:3];
+ // MEM[ADDR] = (tmp == cmp) ? src : tmp;
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ if (wf->execMask().none()) {
+ wf->wrGmReqsInPipe--;
+ wf->rdGmReqsInPipe--;
+ return;
+ }
+
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ if (gpuDynInst->executedAs() == Enums::SC_GLOBAL ||
+ gpuDynInst->executedAs() == Enums::SC_PRIVATE) {
+ /**
+ * TODO: If you encounter this panic, just remove this panic
+ * and restart the simulation. It should just work fine but
+ * this is to warn user that this path is never tested although
+ * all the necessary logic is implemented
+ */
+ panic_if(gpuDynInst->executedAs() == Enums::SC_PRIVATE,
+ "Flats to private aperture not tested yet\n");
+ gpuDynInst->computeUnit()->globalMemoryPipe.
+ issueRequest(gpuDynInst);
+ wf->wrGmReqsInPipe--;
+ wf->outstandingReqsWrGm++;
+ wf->rdGmReqsInPipe--;
+ wf->outstandingReqsRdGm++;
+ } else {
+ fatal("Non global flat instructions not implemented yet.\n");
+ }
+
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ }
+
+ void
+ Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ ConstVecOperandU64 data(gpuDynInst, extData.DATA);
+ ConstVecOperandU64 cmp(gpuDynInst, extData.DATA + 2);
+
+ data.read();
+ cmp.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ (reinterpret_cast<VecElemU64*>(gpuDynInst->x_data))[lane]
+ = data[lane];
+ (reinterpret_cast<VecElemU64*>(gpuDynInst->a_data))[lane]
+ = cmp[lane];
+ }
+ }
+
+ initAtomicAccess<VecElemU64>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ if (isAtomicRet()) {
+ VecOperandU64 vdst(gpuDynInst, extData.VDST);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ vdst[lane] = (reinterpret_cast<VecElemU64*>(
+ gpuDynInst->d_data))[lane];
+ }
+ }
+
+ vdst.write();
+ }
+ } // completeAcc
+
+ Inst_FLAT__FLAT_ATOMIC_ADD_X2::Inst_FLAT__FLAT_ATOMIC_ADD_X2(
+ InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_add_x2")
+ {
+ setFlag(AtomicAdd);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_ADD_X2
+
+ Inst_FLAT__FLAT_ATOMIC_ADD_X2::~Inst_FLAT__FLAT_ATOMIC_ADD_X2()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_ADD_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] += DATA[0:1];
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_ADD_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ if (wf->execMask().none()) {
+ wf->wrGmReqsInPipe--;
+ wf->rdGmReqsInPipe--;
+ return;
+ }
+
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->exec_mask = wf->execMask();
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
+
+ addr.read();
+
+ calcAddr(gpuDynInst, addr);
+ if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
+ gpuDynInst->computeUnit()->globalMemoryPipe.
+ issueRequest(gpuDynInst);
+ wf->wrGmReqsInPipe--;
+ wf->outstandingReqsWrGm++;
+ wf->rdGmReqsInPipe--;
+ wf->outstandingReqsRdGm++;
+ } else {
+ fatal("Non global flat instructions not implemented yet.\n");
+ }
+
+ gpuDynInst->wavefront()->outstandingReqs++;
+ gpuDynInst->wavefront()->validateRequestCounters();
+ }
+
+ void
+ Inst_FLAT__FLAT_ATOMIC_ADD_X2::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ ConstVecOperandU64 data(gpuDynInst, extData.DATA);
+
+ data.read();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ (reinterpret_cast<VecElemU64*>(gpuDynInst->a_data))[lane]
+ = data[lane];
+ }
+ }
+
+ initAtomicAccess<VecElemU64>(gpuDynInst);
+ } // initiateAcc
+
+ void
+ Inst_FLAT__FLAT_ATOMIC_ADD_X2::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ if (isAtomicRet()) {
+ VecOperandU64 vdst(gpuDynInst, extData.VDST);
+
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ vdst[lane] = (reinterpret_cast<VecElemU64*>(
+ gpuDynInst->d_data))[lane];
+ }
+ }
+
+ vdst.write();
+ }
+ } // completeAcc
+
+ Inst_FLAT__FLAT_ATOMIC_SUB_X2::Inst_FLAT__FLAT_ATOMIC_SUB_X2(
+ InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_sub_x2")
+ {
+ setFlag(AtomicSub);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_SUB_X2
+
+ Inst_FLAT__FLAT_ATOMIC_SUB_X2::~Inst_FLAT__FLAT_ATOMIC_SUB_X2()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_SUB_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= DATA[0:1];
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_SUB_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_FLAT__FLAT_ATOMIC_SMIN_X2::Inst_FLAT__FLAT_ATOMIC_SMIN_X2(
+ InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_smin_x2")
+ {
+ setFlag(AtomicMin);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_SMIN_X2
+
+ Inst_FLAT__FLAT_ATOMIC_SMIN_X2::~Inst_FLAT__FLAT_ATOMIC_SMIN_X2()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_SMIN_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= (DATA[0:1] < tmp) ? DATA[0:1] : tmp (signed compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_SMIN_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_FLAT__FLAT_ATOMIC_UMIN_X2::Inst_FLAT__FLAT_ATOMIC_UMIN_X2(
+ InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_umin_x2")
+ {
+ setFlag(AtomicMin);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_UMIN_X2
+
+ Inst_FLAT__FLAT_ATOMIC_UMIN_X2::~Inst_FLAT__FLAT_ATOMIC_UMIN_X2()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_UMIN_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= (DATA[0:1] < tmp) ? DATA[0:1] : tmp (unsigned compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_UMIN_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_FLAT__FLAT_ATOMIC_SMAX_X2::Inst_FLAT__FLAT_ATOMIC_SMAX_X2(
+ InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_smax_x2")
+ {
+ setFlag(AtomicMax);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_SMAX_X2
+
+ Inst_FLAT__FLAT_ATOMIC_SMAX_X2::~Inst_FLAT__FLAT_ATOMIC_SMAX_X2()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_SMAX_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= (DATA[0:1] > tmp) ? DATA[0:1] : tmp (signed compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_SMAX_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_FLAT__FLAT_ATOMIC_UMAX_X2::Inst_FLAT__FLAT_ATOMIC_UMAX_X2(
+ InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_umax_x2")
+ {
+ setFlag(AtomicMax);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_UMAX_X2
+
+ Inst_FLAT__FLAT_ATOMIC_UMAX_X2::~Inst_FLAT__FLAT_ATOMIC_UMAX_X2()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_UMAX_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] -= (DATA[0:1] > tmp) ? DATA[0:1] : tmp (unsigned compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_UMAX_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_FLAT__FLAT_ATOMIC_AND_X2::Inst_FLAT__FLAT_ATOMIC_AND_X2(
+ InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_and_x2")
+ {
+ setFlag(AtomicAnd);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_AND_X2
+
+ Inst_FLAT__FLAT_ATOMIC_AND_X2::~Inst_FLAT__FLAT_ATOMIC_AND_X2()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_AND_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] &= DATA[0:1];
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_AND_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_FLAT__FLAT_ATOMIC_OR_X2::Inst_FLAT__FLAT_ATOMIC_OR_X2(
+ InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_or_x2")
+ {
+ setFlag(AtomicOr);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_OR_X2
+
+ Inst_FLAT__FLAT_ATOMIC_OR_X2::~Inst_FLAT__FLAT_ATOMIC_OR_X2()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_OR_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] |= DATA[0:1];
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_OR_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_FLAT__FLAT_ATOMIC_XOR_X2::Inst_FLAT__FLAT_ATOMIC_XOR_X2(
+ InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_xor_x2")
+ {
+ setFlag(AtomicXor);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_XOR_X2
+
+ Inst_FLAT__FLAT_ATOMIC_XOR_X2::~Inst_FLAT__FLAT_ATOMIC_XOR_X2()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_XOR_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] ^= DATA[0:1];
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_XOR_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_FLAT__FLAT_ATOMIC_INC_X2::Inst_FLAT__FLAT_ATOMIC_INC_X2(
+ InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_inc_x2")
+ {
+ setFlag(AtomicInc);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_INC_X2
+
+ Inst_FLAT__FLAT_ATOMIC_INC_X2::~Inst_FLAT__FLAT_ATOMIC_INC_X2()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_INC_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (tmp >= DATA[0:1]) ? 0 : tmp + 1 (unsigned compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_INC_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+
+ Inst_FLAT__FLAT_ATOMIC_DEC_X2::Inst_FLAT__FLAT_ATOMIC_DEC_X2(
+ InFmt_FLAT *iFmt)
+ : Inst_FLAT(iFmt, "flat_atomic_dec_x2")
+ {
+ setFlag(AtomicDec);
+ if (instData.GLC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+ setFlag(MemoryRef);
+ } // Inst_FLAT__FLAT_ATOMIC_DEC_X2
+
+ Inst_FLAT__FLAT_ATOMIC_DEC_X2::~Inst_FLAT__FLAT_ATOMIC_DEC_X2()
+ {
+ } // ~Inst_FLAT__FLAT_ATOMIC_DEC_X2
+
+ // tmp = MEM[ADDR];
+ // MEM[ADDR] = (tmp == 0 || tmp > DATA[0:1]) ? DATA[0:1] : tmp - 1
+ // (unsigned compare);
+ // RETURN_DATA[0:1] = tmp.
+ void
+ Inst_FLAT__FLAT_ATOMIC_DEC_X2::execute(GPUDynInstPtr gpuDynInst)
+ {
+ panicUnimplemented();
+ }
+} // namespace Gcn3ISA
diff --git a/src/arch/gcn3/insts/instructions.hh b/src/arch/gcn3/insts/instructions.hh
new file mode 100644
index 0000000..ff0cfea
--- /dev/null
+++ b/src/arch/gcn3/insts/instructions.hh
@@ -0,0 +1,81655 @@
+/*
+ * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * For use for simulation and test purposes only
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Anthony Gutierrez
+ */
+
+#ifndef __ARCH_GCN3_INSTS_INSTRUCTIONS_HH__
+#define __ARCH_GCN3_INSTS_INSTRUCTIONS_HH__
+
+#include "arch/gcn3/gpu_decoder.hh"
+#include "arch/gcn3/insts/gpu_static_inst.hh"
+#include "arch/gcn3/insts/op_encodings.hh"
+#include "debug/GCN3.hh"
+
+namespace Gcn3ISA
+{
+ class Inst_SOP2__S_ADD_U32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_ADD_U32(InFmt_SOP2*);
+ ~Inst_SOP2__S_ADD_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_ADD_U32
+
+ class Inst_SOP2__S_SUB_U32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_SUB_U32(InFmt_SOP2*);
+ ~Inst_SOP2__S_SUB_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_SUB_U32
+
+ class Inst_SOP2__S_ADD_I32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_ADD_I32(InFmt_SOP2*);
+ ~Inst_SOP2__S_ADD_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_ADD_I32
+
+ class Inst_SOP2__S_SUB_I32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_SUB_I32(InFmt_SOP2*);
+ ~Inst_SOP2__S_SUB_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_SUB_I32
+
+ class Inst_SOP2__S_ADDC_U32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_ADDC_U32(InFmt_SOP2*);
+ ~Inst_SOP2__S_ADDC_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_ADDC_U32
+
+ class Inst_SOP2__S_SUBB_U32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_SUBB_U32(InFmt_SOP2*);
+ ~Inst_SOP2__S_SUBB_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_SUBB_U32
+
+ class Inst_SOP2__S_MIN_I32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_MIN_I32(InFmt_SOP2*);
+ ~Inst_SOP2__S_MIN_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_MIN_I32
+
+ class Inst_SOP2__S_MIN_U32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_MIN_U32(InFmt_SOP2*);
+ ~Inst_SOP2__S_MIN_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_MIN_U32
+
+ class Inst_SOP2__S_MAX_I32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_MAX_I32(InFmt_SOP2*);
+ ~Inst_SOP2__S_MAX_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_MAX_I32
+
+ class Inst_SOP2__S_MAX_U32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_MAX_U32(InFmt_SOP2*);
+ ~Inst_SOP2__S_MAX_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_MAX_U32
+
+ class Inst_SOP2__S_CSELECT_B32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_CSELECT_B32(InFmt_SOP2*);
+ ~Inst_SOP2__S_CSELECT_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_CSELECT_B32
+
+ class Inst_SOP2__S_CSELECT_B64 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_CSELECT_B64(InFmt_SOP2*);
+ ~Inst_SOP2__S_CSELECT_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 8;
+ case 1: //ssrc_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_CSELECT_B64
+
+ class Inst_SOP2__S_AND_B32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_AND_B32(InFmt_SOP2*);
+ ~Inst_SOP2__S_AND_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_AND_B32
+
+ class Inst_SOP2__S_AND_B64 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_AND_B64(InFmt_SOP2*);
+ ~Inst_SOP2__S_AND_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 8;
+ case 1: //ssrc_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_AND_B64
+
+ class Inst_SOP2__S_OR_B32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_OR_B32(InFmt_SOP2*);
+ ~Inst_SOP2__S_OR_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_OR_B32
+
+ class Inst_SOP2__S_OR_B64 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_OR_B64(InFmt_SOP2*);
+ ~Inst_SOP2__S_OR_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 8;
+ case 1: //ssrc_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_OR_B64
+
+ class Inst_SOP2__S_XOR_B32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_XOR_B32(InFmt_SOP2*);
+ ~Inst_SOP2__S_XOR_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_XOR_B32
+
+ class Inst_SOP2__S_XOR_B64 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_XOR_B64(InFmt_SOP2*);
+ ~Inst_SOP2__S_XOR_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 8;
+ case 1: //ssrc_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_XOR_B64
+
+ class Inst_SOP2__S_ANDN2_B32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_ANDN2_B32(InFmt_SOP2*);
+ ~Inst_SOP2__S_ANDN2_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_ANDN2_B32
+
+ class Inst_SOP2__S_ANDN2_B64 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_ANDN2_B64(InFmt_SOP2*);
+ ~Inst_SOP2__S_ANDN2_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 8;
+ case 1: //ssrc_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_ANDN2_B64
+
+ class Inst_SOP2__S_ORN2_B32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_ORN2_B32(InFmt_SOP2*);
+ ~Inst_SOP2__S_ORN2_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_ORN2_B32
+
+ class Inst_SOP2__S_ORN2_B64 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_ORN2_B64(InFmt_SOP2*);
+ ~Inst_SOP2__S_ORN2_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 8;
+ case 1: //ssrc_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_ORN2_B64
+
+ class Inst_SOP2__S_NAND_B32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_NAND_B32(InFmt_SOP2*);
+ ~Inst_SOP2__S_NAND_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_NAND_B32
+
+ class Inst_SOP2__S_NAND_B64 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_NAND_B64(InFmt_SOP2*);
+ ~Inst_SOP2__S_NAND_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 8;
+ case 1: //ssrc_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_NAND_B64
+
+ class Inst_SOP2__S_NOR_B32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_NOR_B32(InFmt_SOP2*);
+ ~Inst_SOP2__S_NOR_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_NOR_B32
+
+ class Inst_SOP2__S_NOR_B64 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_NOR_B64(InFmt_SOP2*);
+ ~Inst_SOP2__S_NOR_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 8;
+ case 1: //ssrc_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_NOR_B64
+
+ class Inst_SOP2__S_XNOR_B32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_XNOR_B32(InFmt_SOP2*);
+ ~Inst_SOP2__S_XNOR_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_XNOR_B32
+
+ class Inst_SOP2__S_XNOR_B64 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_XNOR_B64(InFmt_SOP2*);
+ ~Inst_SOP2__S_XNOR_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 8;
+ case 1: //ssrc_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_XNOR_B64
+
+ class Inst_SOP2__S_LSHL_B32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_LSHL_B32(InFmt_SOP2*);
+ ~Inst_SOP2__S_LSHL_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_LSHL_B32
+
+ class Inst_SOP2__S_LSHL_B64 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_LSHL_B64(InFmt_SOP2*);
+ ~Inst_SOP2__S_LSHL_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 8;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_LSHL_B64
+
+ class Inst_SOP2__S_LSHR_B32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_LSHR_B32(InFmt_SOP2*);
+ ~Inst_SOP2__S_LSHR_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_LSHR_B32
+
+ class Inst_SOP2__S_LSHR_B64 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_LSHR_B64(InFmt_SOP2*);
+ ~Inst_SOP2__S_LSHR_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 8;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_LSHR_B64
+
+ class Inst_SOP2__S_ASHR_I32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_ASHR_I32(InFmt_SOP2*);
+ ~Inst_SOP2__S_ASHR_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_ASHR_I32
+
+ class Inst_SOP2__S_ASHR_I64 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_ASHR_I64(InFmt_SOP2*);
+ ~Inst_SOP2__S_ASHR_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 8;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_ASHR_I64
+
+ class Inst_SOP2__S_BFM_B32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_BFM_B32(InFmt_SOP2*);
+ ~Inst_SOP2__S_BFM_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_BFM_B32
+
+ class Inst_SOP2__S_BFM_B64 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_BFM_B64(InFmt_SOP2*);
+ ~Inst_SOP2__S_BFM_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_BFM_B64
+
+ class Inst_SOP2__S_MUL_I32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_MUL_I32(InFmt_SOP2*);
+ ~Inst_SOP2__S_MUL_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_MUL_I32
+
+ class Inst_SOP2__S_BFE_U32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_BFE_U32(InFmt_SOP2*);
+ ~Inst_SOP2__S_BFE_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_BFE_U32
+
+ class Inst_SOP2__S_BFE_I32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_BFE_I32(InFmt_SOP2*);
+ ~Inst_SOP2__S_BFE_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_BFE_I32
+
+ class Inst_SOP2__S_BFE_U64 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_BFE_U64(InFmt_SOP2*);
+ ~Inst_SOP2__S_BFE_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 8;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_BFE_U64
+
+ class Inst_SOP2__S_BFE_I64 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_BFE_I64(InFmt_SOP2*);
+ ~Inst_SOP2__S_BFE_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 8;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_BFE_I64
+
+ class Inst_SOP2__S_CBRANCH_G_FORK : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_CBRANCH_G_FORK(InFmt_SOP2*);
+ ~Inst_SOP2__S_CBRANCH_G_FORK();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 8;
+ case 1: //ssrc_1
+ return 8;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_CBRANCH_G_FORK
+
+ class Inst_SOP2__S_ABSDIFF_I32 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_ABSDIFF_I32(InFmt_SOP2*);
+ ~Inst_SOP2__S_ABSDIFF_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_ABSDIFF_I32
+
+ class Inst_SOP2__S_RFE_RESTORE_B64 : public Inst_SOP2
+ {
+ public:
+ Inst_SOP2__S_RFE_RESTORE_B64(InFmt_SOP2*);
+ ~Inst_SOP2__S_RFE_RESTORE_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 8;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP2__S_RFE_RESTORE_B64
+
+ class Inst_SOPK__S_MOVK_I32 : public Inst_SOPK
+ {
+ public:
+ Inst_SOPK__S_MOVK_I32(InFmt_SOPK*);
+ ~Inst_SOPK__S_MOVK_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPK__S_MOVK_I32
+
+ class Inst_SOPK__S_CMOVK_I32 : public Inst_SOPK
+ {
+ public:
+ Inst_SOPK__S_CMOVK_I32(InFmt_SOPK*);
+ ~Inst_SOPK__S_CMOVK_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPK__S_CMOVK_I32
+
+ class Inst_SOPK__S_CMPK_EQ_I32 : public Inst_SOPK
+ {
+ public:
+ Inst_SOPK__S_CMPK_EQ_I32(InFmt_SOPK*);
+ ~Inst_SOPK__S_CMPK_EQ_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPK__S_CMPK_EQ_I32
+
+ class Inst_SOPK__S_CMPK_LG_I32 : public Inst_SOPK
+ {
+ public:
+ Inst_SOPK__S_CMPK_LG_I32(InFmt_SOPK*);
+ ~Inst_SOPK__S_CMPK_LG_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPK__S_CMPK_LG_I32
+
+ class Inst_SOPK__S_CMPK_GT_I32 : public Inst_SOPK
+ {
+ public:
+ Inst_SOPK__S_CMPK_GT_I32(InFmt_SOPK*);
+ ~Inst_SOPK__S_CMPK_GT_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPK__S_CMPK_GT_I32
+
+ class Inst_SOPK__S_CMPK_GE_I32 : public Inst_SOPK
+ {
+ public:
+ Inst_SOPK__S_CMPK_GE_I32(InFmt_SOPK*);
+ ~Inst_SOPK__S_CMPK_GE_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPK__S_CMPK_GE_I32
+
+ class Inst_SOPK__S_CMPK_LT_I32 : public Inst_SOPK
+ {
+ public:
+ Inst_SOPK__S_CMPK_LT_I32(InFmt_SOPK*);
+ ~Inst_SOPK__S_CMPK_LT_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPK__S_CMPK_LT_I32
+
+ class Inst_SOPK__S_CMPK_LE_I32 : public Inst_SOPK
+ {
+ public:
+ Inst_SOPK__S_CMPK_LE_I32(InFmt_SOPK*);
+ ~Inst_SOPK__S_CMPK_LE_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPK__S_CMPK_LE_I32
+
+ class Inst_SOPK__S_CMPK_EQ_U32 : public Inst_SOPK
+ {
+ public:
+ Inst_SOPK__S_CMPK_EQ_U32(InFmt_SOPK*);
+ ~Inst_SOPK__S_CMPK_EQ_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPK__S_CMPK_EQ_U32
+
+ class Inst_SOPK__S_CMPK_LG_U32 : public Inst_SOPK
+ {
+ public:
+ Inst_SOPK__S_CMPK_LG_U32(InFmt_SOPK*);
+ ~Inst_SOPK__S_CMPK_LG_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPK__S_CMPK_LG_U32
+
+ class Inst_SOPK__S_CMPK_GT_U32 : public Inst_SOPK
+ {
+ public:
+ Inst_SOPK__S_CMPK_GT_U32(InFmt_SOPK*);
+ ~Inst_SOPK__S_CMPK_GT_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPK__S_CMPK_GT_U32
+
+ class Inst_SOPK__S_CMPK_GE_U32 : public Inst_SOPK
+ {
+ public:
+ Inst_SOPK__S_CMPK_GE_U32(InFmt_SOPK*);
+ ~Inst_SOPK__S_CMPK_GE_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPK__S_CMPK_GE_U32
+
+ class Inst_SOPK__S_CMPK_LT_U32 : public Inst_SOPK
+ {
+ public:
+ Inst_SOPK__S_CMPK_LT_U32(InFmt_SOPK*);
+ ~Inst_SOPK__S_CMPK_LT_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPK__S_CMPK_LT_U32
+
+ class Inst_SOPK__S_CMPK_LE_U32 : public Inst_SOPK
+ {
+ public:
+ Inst_SOPK__S_CMPK_LE_U32(InFmt_SOPK*);
+ ~Inst_SOPK__S_CMPK_LE_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPK__S_CMPK_LE_U32
+
+ class Inst_SOPK__S_ADDK_I32 : public Inst_SOPK
+ {
+ public:
+ Inst_SOPK__S_ADDK_I32(InFmt_SOPK*);
+ ~Inst_SOPK__S_ADDK_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPK__S_ADDK_I32
+
+ class Inst_SOPK__S_MULK_I32 : public Inst_SOPK
+ {
+ public:
+ Inst_SOPK__S_MULK_I32(InFmt_SOPK*);
+ ~Inst_SOPK__S_MULK_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPK__S_MULK_I32
+
+ class Inst_SOPK__S_CBRANCH_I_FORK : public Inst_SOPK
+ {
+ public:
+ Inst_SOPK__S_CBRANCH_I_FORK(InFmt_SOPK*);
+ ~Inst_SOPK__S_CBRANCH_I_FORK();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sdst
+ return 8;
+ case 1: //
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sdst
+ return true;
+ case 1: //
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sdst
+ return false;
+ case 1: //
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPK__S_CBRANCH_I_FORK
+
+ class Inst_SOPK__S_GETREG_B32 : public Inst_SOPK
+ {
+ public:
+ Inst_SOPK__S_GETREG_B32(InFmt_SOPK*);
+ ~Inst_SOPK__S_GETREG_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPK__S_GETREG_B32
+
+ class Inst_SOPK__S_SETREG_B32 : public Inst_SOPK
+ {
+ public:
+ Inst_SOPK__S_SETREG_B32(InFmt_SOPK*);
+ ~Inst_SOPK__S_SETREG_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPK__S_SETREG_B32
+
+ class Inst_SOPK__S_SETREG_IMM32_B32 : public Inst_SOPK
+ {
+ public:
+ Inst_SOPK__S_SETREG_IMM32_B32(InFmt_SOPK*);
+ ~Inst_SOPK__S_SETREG_IMM32_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm32
+ return 4;
+ case 1: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm32
+ return true;
+ case 1: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm32
+ return false;
+ case 1: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPK__S_SETREG_IMM32_B32
+
+ class Inst_SOP1__S_MOV_B32 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_MOV_B32(InFmt_SOP1*);
+ ~Inst_SOP1__S_MOV_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_MOV_B32
+
+ class Inst_SOP1__S_MOV_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_MOV_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_MOV_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_MOV_B64
+
+ class Inst_SOP1__S_CMOV_B32 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_CMOV_B32(InFmt_SOP1*);
+ ~Inst_SOP1__S_CMOV_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_CMOV_B32
+
+ class Inst_SOP1__S_CMOV_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_CMOV_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_CMOV_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_CMOV_B64
+
+ class Inst_SOP1__S_NOT_B32 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_NOT_B32(InFmt_SOP1*);
+ ~Inst_SOP1__S_NOT_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_NOT_B32
+
+ class Inst_SOP1__S_NOT_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_NOT_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_NOT_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_NOT_B64
+
+ class Inst_SOP1__S_WQM_B32 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_WQM_B32(InFmt_SOP1*);
+ ~Inst_SOP1__S_WQM_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_WQM_B32
+
+ class Inst_SOP1__S_WQM_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_WQM_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_WQM_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_WQM_B64
+
+ class Inst_SOP1__S_BREV_B32 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_BREV_B32(InFmt_SOP1*);
+ ~Inst_SOP1__S_BREV_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_BREV_B32
+
+ class Inst_SOP1__S_BREV_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_BREV_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_BREV_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_BREV_B64
+
+ class Inst_SOP1__S_BCNT0_I32_B32 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_BCNT0_I32_B32(InFmt_SOP1*);
+ ~Inst_SOP1__S_BCNT0_I32_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_BCNT0_I32_B32
+
+ class Inst_SOP1__S_BCNT0_I32_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_BCNT0_I32_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_BCNT0_I32_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_BCNT0_I32_B64
+
+ class Inst_SOP1__S_BCNT1_I32_B32 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_BCNT1_I32_B32(InFmt_SOP1*);
+ ~Inst_SOP1__S_BCNT1_I32_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_BCNT1_I32_B32
+
+ class Inst_SOP1__S_BCNT1_I32_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_BCNT1_I32_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_BCNT1_I32_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_BCNT1_I32_B64
+
+ class Inst_SOP1__S_FF0_I32_B32 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_FF0_I32_B32(InFmt_SOP1*);
+ ~Inst_SOP1__S_FF0_I32_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_FF0_I32_B32
+
+ class Inst_SOP1__S_FF0_I32_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_FF0_I32_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_FF0_I32_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_FF0_I32_B64
+
+ class Inst_SOP1__S_FF1_I32_B32 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_FF1_I32_B32(InFmt_SOP1*);
+ ~Inst_SOP1__S_FF1_I32_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_FF1_I32_B32
+
+ class Inst_SOP1__S_FF1_I32_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_FF1_I32_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_FF1_I32_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_FF1_I32_B64
+
+ class Inst_SOP1__S_FLBIT_I32_B32 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_FLBIT_I32_B32(InFmt_SOP1*);
+ ~Inst_SOP1__S_FLBIT_I32_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_FLBIT_I32_B32
+
+ class Inst_SOP1__S_FLBIT_I32_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_FLBIT_I32_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_FLBIT_I32_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_FLBIT_I32_B64
+
+ class Inst_SOP1__S_FLBIT_I32 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_FLBIT_I32(InFmt_SOP1*);
+ ~Inst_SOP1__S_FLBIT_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_FLBIT_I32
+
+ class Inst_SOP1__S_FLBIT_I32_I64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_FLBIT_I32_I64(InFmt_SOP1*);
+ ~Inst_SOP1__S_FLBIT_I32_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_FLBIT_I32_I64
+
+ class Inst_SOP1__S_SEXT_I32_I8 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_SEXT_I32_I8(InFmt_SOP1*);
+ ~Inst_SOP1__S_SEXT_I32_I8();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_SEXT_I32_I8
+
+ class Inst_SOP1__S_SEXT_I32_I16 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_SEXT_I32_I16(InFmt_SOP1*);
+ ~Inst_SOP1__S_SEXT_I32_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_SEXT_I32_I16
+
+ class Inst_SOP1__S_BITSET0_B32 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_BITSET0_B32(InFmt_SOP1*);
+ ~Inst_SOP1__S_BITSET0_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_BITSET0_B32
+
+ class Inst_SOP1__S_BITSET0_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_BITSET0_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_BITSET0_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_BITSET0_B64
+
+ class Inst_SOP1__S_BITSET1_B32 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_BITSET1_B32(InFmt_SOP1*);
+ ~Inst_SOP1__S_BITSET1_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_BITSET1_B32
+
+ class Inst_SOP1__S_BITSET1_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_BITSET1_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_BITSET1_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_BITSET1_B64
+
+ class Inst_SOP1__S_GETPC_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_GETPC_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_GETPC_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_GETPC_B64
+
+ class Inst_SOP1__S_SETPC_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_SETPC_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_SETPC_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_SETPC_B64
+
+ class Inst_SOP1__S_SWAPPC_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_SWAPPC_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_SWAPPC_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_SWAPPC_B64
+
+ class Inst_SOP1__S_RFE_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_RFE_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_RFE_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_RFE_B64
+
+ class Inst_SOP1__S_AND_SAVEEXEC_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_AND_SAVEEXEC_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_AND_SAVEEXEC_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_AND_SAVEEXEC_B64
+
+ class Inst_SOP1__S_OR_SAVEEXEC_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_OR_SAVEEXEC_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_OR_SAVEEXEC_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_OR_SAVEEXEC_B64
+
+ class Inst_SOP1__S_XOR_SAVEEXEC_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_XOR_SAVEEXEC_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_XOR_SAVEEXEC_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_XOR_SAVEEXEC_B64
+
+ class Inst_SOP1__S_ANDN2_SAVEEXEC_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_ANDN2_SAVEEXEC_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_ANDN2_SAVEEXEC_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_ANDN2_SAVEEXEC_B64
+
+ class Inst_SOP1__S_ORN2_SAVEEXEC_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_ORN2_SAVEEXEC_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_ORN2_SAVEEXEC_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_ORN2_SAVEEXEC_B64
+
+ class Inst_SOP1__S_NAND_SAVEEXEC_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_NAND_SAVEEXEC_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_NAND_SAVEEXEC_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_NAND_SAVEEXEC_B64
+
+ class Inst_SOP1__S_NOR_SAVEEXEC_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_NOR_SAVEEXEC_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_NOR_SAVEEXEC_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_NOR_SAVEEXEC_B64
+
+ class Inst_SOP1__S_XNOR_SAVEEXEC_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_XNOR_SAVEEXEC_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_XNOR_SAVEEXEC_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_XNOR_SAVEEXEC_B64
+
+ class Inst_SOP1__S_QUADMASK_B32 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_QUADMASK_B32(InFmt_SOP1*);
+ ~Inst_SOP1__S_QUADMASK_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_QUADMASK_B32
+
+ class Inst_SOP1__S_QUADMASK_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_QUADMASK_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_QUADMASK_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_QUADMASK_B64
+
+ class Inst_SOP1__S_MOVRELS_B32 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_MOVRELS_B32(InFmt_SOP1*);
+ ~Inst_SOP1__S_MOVRELS_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_MOVRELS_B32
+
+ class Inst_SOP1__S_MOVRELS_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_MOVRELS_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_MOVRELS_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sdst
+ return 8;
+ case 1: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sdst
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sdst
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_MOVRELS_B64
+
+ class Inst_SOP1__S_MOVRELD_B32 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_MOVRELD_B32(InFmt_SOP1*);
+ ~Inst_SOP1__S_MOVRELD_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_MOVRELD_B32
+
+ class Inst_SOP1__S_MOVRELD_B64 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_MOVRELD_B64(InFmt_SOP1*);
+ ~Inst_SOP1__S_MOVRELD_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 8;
+ case 1: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_MOVRELD_B64
+
+ class Inst_SOP1__S_CBRANCH_JOIN : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_CBRANCH_JOIN(InFmt_SOP1*);
+ ~Inst_SOP1__S_CBRANCH_JOIN();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_CBRANCH_JOIN
+
+ class Inst_SOP1__S_ABS_I32 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_ABS_I32(InFmt_SOP1*);
+ ~Inst_SOP1__S_ABS_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_ABS_I32
+
+ class Inst_SOP1__S_MOV_FED_B32 : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_MOV_FED_B32(InFmt_SOP1*);
+ ~Inst_SOP1__S_MOV_FED_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_MOV_FED_B32
+
+ class Inst_SOP1__S_SET_GPR_IDX_IDX : public Inst_SOP1
+ {
+ public:
+ Inst_SOP1__S_SET_GPR_IDX_IDX(InFmt_SOP1*);
+ ~Inst_SOP1__S_SET_GPR_IDX_IDX();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOP1__S_SET_GPR_IDX_IDX
+
+ class Inst_SOPC__S_CMP_EQ_I32 : public Inst_SOPC
+ {
+ public:
+ Inst_SOPC__S_CMP_EQ_I32(InFmt_SOPC*);
+ ~Inst_SOPC__S_CMP_EQ_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPC__S_CMP_EQ_I32
+
+ class Inst_SOPC__S_CMP_LG_I32 : public Inst_SOPC
+ {
+ public:
+ Inst_SOPC__S_CMP_LG_I32(InFmt_SOPC*);
+ ~Inst_SOPC__S_CMP_LG_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPC__S_CMP_LG_I32
+
+ class Inst_SOPC__S_CMP_GT_I32 : public Inst_SOPC
+ {
+ public:
+ Inst_SOPC__S_CMP_GT_I32(InFmt_SOPC*);
+ ~Inst_SOPC__S_CMP_GT_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPC__S_CMP_GT_I32
+
+ class Inst_SOPC__S_CMP_GE_I32 : public Inst_SOPC
+ {
+ public:
+ Inst_SOPC__S_CMP_GE_I32(InFmt_SOPC*);
+ ~Inst_SOPC__S_CMP_GE_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPC__S_CMP_GE_I32
+
+ class Inst_SOPC__S_CMP_LT_I32 : public Inst_SOPC
+ {
+ public:
+ Inst_SOPC__S_CMP_LT_I32(InFmt_SOPC*);
+ ~Inst_SOPC__S_CMP_LT_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPC__S_CMP_LT_I32
+
+ class Inst_SOPC__S_CMP_LE_I32 : public Inst_SOPC
+ {
+ public:
+ Inst_SOPC__S_CMP_LE_I32(InFmt_SOPC*);
+ ~Inst_SOPC__S_CMP_LE_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPC__S_CMP_LE_I32
+
+ class Inst_SOPC__S_CMP_EQ_U32 : public Inst_SOPC
+ {
+ public:
+ Inst_SOPC__S_CMP_EQ_U32(InFmt_SOPC*);
+ ~Inst_SOPC__S_CMP_EQ_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPC__S_CMP_EQ_U32
+
+ class Inst_SOPC__S_CMP_LG_U32 : public Inst_SOPC
+ {
+ public:
+ Inst_SOPC__S_CMP_LG_U32(InFmt_SOPC*);
+ ~Inst_SOPC__S_CMP_LG_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPC__S_CMP_LG_U32
+
+ class Inst_SOPC__S_CMP_GT_U32 : public Inst_SOPC
+ {
+ public:
+ Inst_SOPC__S_CMP_GT_U32(InFmt_SOPC*);
+ ~Inst_SOPC__S_CMP_GT_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPC__S_CMP_GT_U32
+
+ class Inst_SOPC__S_CMP_GE_U32 : public Inst_SOPC
+ {
+ public:
+ Inst_SOPC__S_CMP_GE_U32(InFmt_SOPC*);
+ ~Inst_SOPC__S_CMP_GE_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPC__S_CMP_GE_U32
+
+ class Inst_SOPC__S_CMP_LT_U32 : public Inst_SOPC
+ {
+ public:
+ Inst_SOPC__S_CMP_LT_U32(InFmt_SOPC*);
+ ~Inst_SOPC__S_CMP_LT_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPC__S_CMP_LT_U32
+
+ class Inst_SOPC__S_CMP_LE_U32 : public Inst_SOPC
+ {
+ public:
+ Inst_SOPC__S_CMP_LE_U32(InFmt_SOPC*);
+ ~Inst_SOPC__S_CMP_LE_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPC__S_CMP_LE_U32
+
+ class Inst_SOPC__S_BITCMP0_B32 : public Inst_SOPC
+ {
+ public:
+ Inst_SOPC__S_BITCMP0_B32(InFmt_SOPC*);
+ ~Inst_SOPC__S_BITCMP0_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPC__S_BITCMP0_B32
+
+ class Inst_SOPC__S_BITCMP1_B32 : public Inst_SOPC
+ {
+ public:
+ Inst_SOPC__S_BITCMP1_B32(InFmt_SOPC*);
+ ~Inst_SOPC__S_BITCMP1_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPC__S_BITCMP1_B32
+
+ class Inst_SOPC__S_BITCMP0_B64 : public Inst_SOPC
+ {
+ public:
+ Inst_SOPC__S_BITCMP0_B64(InFmt_SOPC*);
+ ~Inst_SOPC__S_BITCMP0_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 8;
+ case 1: //ssrc_1
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPC__S_BITCMP0_B64
+
+ class Inst_SOPC__S_BITCMP1_B64 : public Inst_SOPC
+ {
+ public:
+ Inst_SOPC__S_BITCMP1_B64(InFmt_SOPC*);
+ ~Inst_SOPC__S_BITCMP1_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 8;
+ case 1: //ssrc_1
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPC__S_BITCMP1_B64
+
+ class Inst_SOPC__S_SETVSKIP : public Inst_SOPC
+ {
+ public:
+ Inst_SOPC__S_SETVSKIP(InFmt_SOPC*);
+ ~Inst_SOPC__S_SETVSKIP();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPC__S_SETVSKIP
+
+ class Inst_SOPC__S_SET_GPR_IDX_ON : public Inst_SOPC
+ {
+ public:
+ Inst_SOPC__S_SET_GPR_IDX_ON(InFmt_SOPC*);
+ ~Inst_SOPC__S_SET_GPR_IDX_ON();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //simm4
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //simm4
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //simm4
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPC__S_SET_GPR_IDX_ON
+
+ class Inst_SOPC__S_CMP_EQ_U64 : public Inst_SOPC
+ {
+ public:
+ Inst_SOPC__S_CMP_EQ_U64(InFmt_SOPC*);
+ ~Inst_SOPC__S_CMP_EQ_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 8;
+ case 1: //ssrc_1
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPC__S_CMP_EQ_U64
+
+ class Inst_SOPC__S_CMP_LG_U64 : public Inst_SOPC
+ {
+ public:
+ Inst_SOPC__S_CMP_LG_U64(InFmt_SOPC*);
+ ~Inst_SOPC__S_CMP_LG_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 8;
+ case 1: //ssrc_1
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPC__S_CMP_LG_U64
+
+ class Inst_SOPP__S_NOP : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_NOP(InFmt_SOPP*);
+ ~Inst_SOPP__S_NOP();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_NOP
+
+ class Inst_SOPP__S_ENDPGM : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_ENDPGM(InFmt_SOPP*);
+ ~Inst_SOPP__S_ENDPGM();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_ENDPGM
+
+ class Inst_SOPP__S_BRANCH : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_BRANCH(InFmt_SOPP*);
+ ~Inst_SOPP__S_BRANCH();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_BRANCH
+
+ class Inst_SOPP__S_WAKEUP : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_WAKEUP(InFmt_SOPP*);
+ ~Inst_SOPP__S_WAKEUP();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_WAKEUP
+
+ class Inst_SOPP__S_CBRANCH_SCC0 : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_CBRANCH_SCC0(InFmt_SOPP*);
+ ~Inst_SOPP__S_CBRANCH_SCC0();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_CBRANCH_SCC0
+
+ class Inst_SOPP__S_CBRANCH_SCC1 : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_CBRANCH_SCC1(InFmt_SOPP*);
+ ~Inst_SOPP__S_CBRANCH_SCC1();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_CBRANCH_SCC1
+
+ class Inst_SOPP__S_CBRANCH_VCCZ : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_CBRANCH_VCCZ(InFmt_SOPP*);
+ ~Inst_SOPP__S_CBRANCH_VCCZ();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return 2;
+ case 1:
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return true;
+ case 1:
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return false;
+ case 1:
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_CBRANCH_VCCZ
+
+ class Inst_SOPP__S_CBRANCH_VCCNZ : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_CBRANCH_VCCNZ(InFmt_SOPP*);
+ ~Inst_SOPP__S_CBRANCH_VCCNZ();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return 2;
+ case 1:
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return true;
+ case 1:
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return false;
+ case 1:
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_CBRANCH_VCCNZ
+
+ class Inst_SOPP__S_CBRANCH_EXECZ : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_CBRANCH_EXECZ(InFmt_SOPP*);
+ ~Inst_SOPP__S_CBRANCH_EXECZ();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_CBRANCH_EXECZ
+
+ class Inst_SOPP__S_CBRANCH_EXECNZ : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_CBRANCH_EXECNZ(InFmt_SOPP*);
+ ~Inst_SOPP__S_CBRANCH_EXECNZ();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_CBRANCH_EXECNZ
+
+ class Inst_SOPP__S_BARRIER : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_BARRIER(InFmt_SOPP*);
+ ~Inst_SOPP__S_BARRIER();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_BARRIER
+
+ class Inst_SOPP__S_SETKILL : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_SETKILL(InFmt_SOPP*);
+ ~Inst_SOPP__S_SETKILL();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_SETKILL
+
+ class Inst_SOPP__S_WAITCNT : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_WAITCNT(InFmt_SOPP*);
+ ~Inst_SOPP__S_WAITCNT();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_WAITCNT
+
+ class Inst_SOPP__S_SETHALT : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_SETHALT(InFmt_SOPP*);
+ ~Inst_SOPP__S_SETHALT();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_SETHALT
+
+ class Inst_SOPP__S_SLEEP : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_SLEEP(InFmt_SOPP*);
+ ~Inst_SOPP__S_SLEEP();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_SLEEP
+
+ class Inst_SOPP__S_SETPRIO : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_SETPRIO(InFmt_SOPP*);
+ ~Inst_SOPP__S_SETPRIO();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_SETPRIO
+
+ class Inst_SOPP__S_SENDMSG : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_SENDMSG(InFmt_SOPP*);
+ ~Inst_SOPP__S_SENDMSG();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_SENDMSG
+
+ class Inst_SOPP__S_SENDMSGHALT : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_SENDMSGHALT(InFmt_SOPP*);
+ ~Inst_SOPP__S_SENDMSGHALT();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_SENDMSGHALT
+
+ class Inst_SOPP__S_TRAP : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_TRAP(InFmt_SOPP*);
+ ~Inst_SOPP__S_TRAP();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_TRAP
+
+ class Inst_SOPP__S_ICACHE_INV : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_ICACHE_INV(InFmt_SOPP*);
+ ~Inst_SOPP__S_ICACHE_INV();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_ICACHE_INV
+
+ class Inst_SOPP__S_INCPERFLEVEL : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_INCPERFLEVEL(InFmt_SOPP*);
+ ~Inst_SOPP__S_INCPERFLEVEL();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_INCPERFLEVEL
+
+ class Inst_SOPP__S_DECPERFLEVEL : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_DECPERFLEVEL(InFmt_SOPP*);
+ ~Inst_SOPP__S_DECPERFLEVEL();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_DECPERFLEVEL
+
+ class Inst_SOPP__S_TTRACEDATA : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_TTRACEDATA(InFmt_SOPP*);
+ ~Inst_SOPP__S_TTRACEDATA();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_TTRACEDATA
+
+ class Inst_SOPP__S_CBRANCH_CDBGSYS : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_CBRANCH_CDBGSYS(InFmt_SOPP*);
+ ~Inst_SOPP__S_CBRANCH_CDBGSYS();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_CBRANCH_CDBGSYS
+
+ class Inst_SOPP__S_CBRANCH_CDBGUSER : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_CBRANCH_CDBGUSER(InFmt_SOPP*);
+ ~Inst_SOPP__S_CBRANCH_CDBGUSER();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_CBRANCH_CDBGUSER
+
+ class Inst_SOPP__S_CBRANCH_CDBGSYS_OR_USER : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_CBRANCH_CDBGSYS_OR_USER(InFmt_SOPP*);
+ ~Inst_SOPP__S_CBRANCH_CDBGSYS_OR_USER();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_CBRANCH_CDBGSYS_OR_USER
+
+ class Inst_SOPP__S_CBRANCH_CDBGSYS_AND_USER : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_CBRANCH_CDBGSYS_AND_USER(InFmt_SOPP*);
+ ~Inst_SOPP__S_CBRANCH_CDBGSYS_AND_USER();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //label
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_CBRANCH_CDBGSYS_AND_USER
+
+ class Inst_SOPP__S_ENDPGM_SAVED : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_ENDPGM_SAVED(InFmt_SOPP*);
+ ~Inst_SOPP__S_ENDPGM_SAVED();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_ENDPGM_SAVED
+
+ class Inst_SOPP__S_SET_GPR_IDX_OFF : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_SET_GPR_IDX_OFF(InFmt_SOPP*);
+ ~Inst_SOPP__S_SET_GPR_IDX_OFF();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_SET_GPR_IDX_OFF
+
+ class Inst_SOPP__S_SET_GPR_IDX_MODE : public Inst_SOPP
+ {
+ public:
+ Inst_SOPP__S_SET_GPR_IDX_MODE(InFmt_SOPP*);
+ ~Inst_SOPP__S_SET_GPR_IDX_MODE();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //simm16
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SOPP__S_SET_GPR_IDX_MODE
+
+ class Inst_SMEM__S_LOAD_DWORD : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_LOAD_DWORD(InFmt_SMEM*);
+ ~Inst_SMEM__S_LOAD_DWORD();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return 8;
+ case 1: //offset
+ return 4;
+ case 2: //sgpr_dst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return true;
+ case 1: //offset
+ return true;
+ case 2: //sgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return false;
+ case 1: //offset
+ return false;
+ case 2: //sgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_LOAD_DWORD
+
+ class Inst_SMEM__S_LOAD_DWORDX2 : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_LOAD_DWORDX2(InFmt_SMEM*);
+ ~Inst_SMEM__S_LOAD_DWORDX2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return 8;
+ case 1: //offset
+ return 4;
+ case 2: //sgpr_dst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return true;
+ case 1: //offset
+ return true;
+ case 2: //sgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return false;
+ case 1: //offset
+ return false;
+ case 2: //sgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_LOAD_DWORDX2
+
+ class Inst_SMEM__S_LOAD_DWORDX4 : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_LOAD_DWORDX4(InFmt_SMEM*);
+ ~Inst_SMEM__S_LOAD_DWORDX4();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return 8;
+ case 1: //offset
+ return 4;
+ case 2: //sgpr_dst
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return true;
+ case 1: //offset
+ return true;
+ case 2: //sgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return false;
+ case 1: //offset
+ return false;
+ case 2: //sgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_LOAD_DWORDX4
+
+ class Inst_SMEM__S_LOAD_DWORDX8 : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_LOAD_DWORDX8(InFmt_SMEM*);
+ ~Inst_SMEM__S_LOAD_DWORDX8();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return 8;
+ case 1: //offset
+ return 4;
+ case 2: //sgpr_dst
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return true;
+ case 1: //offset
+ return true;
+ case 2: //sgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return false;
+ case 1: //offset
+ return false;
+ case 2: //sgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_LOAD_DWORDX8
+
+ class Inst_SMEM__S_LOAD_DWORDX16 : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_LOAD_DWORDX16(InFmt_SMEM*);
+ ~Inst_SMEM__S_LOAD_DWORDX16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return 8;
+ case 1: //offset
+ return 4;
+ case 2: //sgpr_dst
+ return 64;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return true;
+ case 1: //offset
+ return true;
+ case 2: //sgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return false;
+ case 1: //offset
+ return false;
+ case 2: //sgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_LOAD_DWORDX16
+
+ class Inst_SMEM__S_BUFFER_LOAD_DWORD : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_BUFFER_LOAD_DWORD(InFmt_SMEM*);
+ ~Inst_SMEM__S_BUFFER_LOAD_DWORD();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return 16;
+ case 1: //offset
+ return 4;
+ case 2: //sgpr_dst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return true;
+ case 1: //offset
+ return true;
+ case 2: //sgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return false;
+ case 1: //offset
+ return false;
+ case 2: //sgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_BUFFER_LOAD_DWORD
+
+ class Inst_SMEM__S_BUFFER_LOAD_DWORDX2 : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX2(InFmt_SMEM*);
+ ~Inst_SMEM__S_BUFFER_LOAD_DWORDX2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return 16;
+ case 1: //offset
+ return 4;
+ case 2: //sgpr_dst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return true;
+ case 1: //offset
+ return true;
+ case 2: //sgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return false;
+ case 1: //offset
+ return false;
+ case 2: //sgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_BUFFER_LOAD_DWORDX2
+
+ class Inst_SMEM__S_BUFFER_LOAD_DWORDX4 : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX4(InFmt_SMEM*);
+ ~Inst_SMEM__S_BUFFER_LOAD_DWORDX4();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return 16;
+ case 1: //offset
+ return 4;
+ case 2: //sgpr_dst
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return true;
+ case 1: //offset
+ return true;
+ case 2: //sgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return false;
+ case 1: //offset
+ return false;
+ case 2: //sgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_BUFFER_LOAD_DWORDX4
+
+ class Inst_SMEM__S_BUFFER_LOAD_DWORDX8 : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX8(InFmt_SMEM*);
+ ~Inst_SMEM__S_BUFFER_LOAD_DWORDX8();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return 16;
+ case 1: //offset
+ return 4;
+ case 2: //sgpr_dst
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return true;
+ case 1: //offset
+ return true;
+ case 2: //sgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return false;
+ case 1: //offset
+ return false;
+ case 2: //sgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_BUFFER_LOAD_DWORDX8
+
+ class Inst_SMEM__S_BUFFER_LOAD_DWORDX16 : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_BUFFER_LOAD_DWORDX16(InFmt_SMEM*);
+ ~Inst_SMEM__S_BUFFER_LOAD_DWORDX16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return 16;
+ case 1: //offset
+ return 4;
+ case 2: //sgpr_dst
+ return 64;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return true;
+ case 1: //offset
+ return true;
+ case 2: //sgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_base
+ return false;
+ case 1: //offset
+ return false;
+ case 2: //sgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_BUFFER_LOAD_DWORDX16
+
+ class Inst_SMEM__S_STORE_DWORD : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_STORE_DWORD(InFmt_SMEM*);
+ ~Inst_SMEM__S_STORE_DWORD();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_data
+ return 4;
+ case 1: //sgpr_base
+ return 8;
+ case 2: //offset
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_data
+ return true;
+ case 1: //sgpr_base
+ return true;
+ case 2: //offset
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_data
+ return false;
+ case 1: //sgpr_base
+ return false;
+ case 2: //offset
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_STORE_DWORD
+
+ class Inst_SMEM__S_STORE_DWORDX2 : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_STORE_DWORDX2(InFmt_SMEM*);
+ ~Inst_SMEM__S_STORE_DWORDX2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_data
+ return 8;
+ case 1: //sgpr_base
+ return 8;
+ case 2: //offset
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_data
+ return true;
+ case 1: //sgpr_base
+ return true;
+ case 2: //offset
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_data
+ return false;
+ case 1: //sgpr_base
+ return false;
+ case 2: //offset
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_STORE_DWORDX2
+
+ class Inst_SMEM__S_STORE_DWORDX4 : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_STORE_DWORDX4(InFmt_SMEM*);
+ ~Inst_SMEM__S_STORE_DWORDX4();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_data
+ return 16;
+ case 1: //sgpr_base
+ return 8;
+ case 2: //offset
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_data
+ return true;
+ case 1: //sgpr_base
+ return true;
+ case 2: //offset
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_data
+ return false;
+ case 1: //sgpr_base
+ return false;
+ case 2: //offset
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_STORE_DWORDX4
+
+ class Inst_SMEM__S_BUFFER_STORE_DWORD : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_BUFFER_STORE_DWORD(InFmt_SMEM*);
+ ~Inst_SMEM__S_BUFFER_STORE_DWORD();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_data
+ return 4;
+ case 1: //sgpr_base
+ return 16;
+ case 2: //offset
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_data
+ return true;
+ case 1: //sgpr_base
+ return true;
+ case 2: //offset
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_data
+ return false;
+ case 1: //sgpr_base
+ return false;
+ case 2: //offset
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_BUFFER_STORE_DWORD
+
+ class Inst_SMEM__S_BUFFER_STORE_DWORDX2 : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_BUFFER_STORE_DWORDX2(InFmt_SMEM*);
+ ~Inst_SMEM__S_BUFFER_STORE_DWORDX2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_data
+ return 8;
+ case 1: //sgpr_base
+ return 16;
+ case 2: //offset
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_data
+ return true;
+ case 1: //sgpr_base
+ return true;
+ case 2: //offset
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_data
+ return false;
+ case 1: //sgpr_base
+ return false;
+ case 2: //offset
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_BUFFER_STORE_DWORDX2
+
+ class Inst_SMEM__S_BUFFER_STORE_DWORDX4 : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_BUFFER_STORE_DWORDX4(InFmt_SMEM*);
+ ~Inst_SMEM__S_BUFFER_STORE_DWORDX4();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_data
+ return 16;
+ case 1: //sgpr_base
+ return 16;
+ case 2: //offset
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_data
+ return true;
+ case 1: //sgpr_base
+ return true;
+ case 2: //offset
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_data
+ return false;
+ case 1: //sgpr_base
+ return false;
+ case 2: //offset
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_BUFFER_STORE_DWORDX4
+
+ class Inst_SMEM__S_DCACHE_INV : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_DCACHE_INV(InFmt_SMEM*);
+ ~Inst_SMEM__S_DCACHE_INV();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_DCACHE_INV
+
+ class Inst_SMEM__S_DCACHE_WB : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_DCACHE_WB(InFmt_SMEM*);
+ ~Inst_SMEM__S_DCACHE_WB();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_DCACHE_WB
+
+ class Inst_SMEM__S_DCACHE_INV_VOL : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_DCACHE_INV_VOL(InFmt_SMEM*);
+ ~Inst_SMEM__S_DCACHE_INV_VOL();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_DCACHE_INV_VOL
+
+ class Inst_SMEM__S_DCACHE_WB_VOL : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_DCACHE_WB_VOL(InFmt_SMEM*);
+ ~Inst_SMEM__S_DCACHE_WB_VOL();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_DCACHE_WB_VOL
+
+ class Inst_SMEM__S_MEMTIME : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_MEMTIME(InFmt_SMEM*);
+ ~Inst_SMEM__S_MEMTIME();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_dst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_MEMTIME
+
+ class Inst_SMEM__S_MEMREALTIME : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_MEMREALTIME(InFmt_SMEM*);
+ ~Inst_SMEM__S_MEMREALTIME();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_dst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_MEMREALTIME
+
+ class Inst_SMEM__S_ATC_PROBE : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_ATC_PROBE(InFmt_SMEM*);
+ ~Inst_SMEM__S_ATC_PROBE();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //perm_rwx
+ return 32;
+ case 1: //sgpr_base
+ return 8;
+ case 2: //offset
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //perm_rwx
+ return true;
+ case 1: //sgpr_base
+ return true;
+ case 2: //offset
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //perm_rwx
+ return false;
+ case 1: //sgpr_base
+ return false;
+ case 2: //offset
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_ATC_PROBE
+
+ class Inst_SMEM__S_ATC_PROBE_BUFFER : public Inst_SMEM
+ {
+ public:
+ Inst_SMEM__S_ATC_PROBE_BUFFER(InFmt_SMEM*);
+ ~Inst_SMEM__S_ATC_PROBE_BUFFER();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //perm_rwx
+ return 32;
+ case 1: //sgpr_base
+ return 16;
+ case 2: //offset
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //perm_rwx
+ return true;
+ case 1: //sgpr_base
+ return true;
+ case 2: //offset
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //perm_rwx
+ return false;
+ case 1: //sgpr_base
+ return false;
+ case 2: //offset
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_SMEM__S_ATC_PROBE_BUFFER
+
+ class Inst_VOP2__V_CNDMASK_B32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_CNDMASK_B32(InFmt_VOP2*);
+ ~Inst_VOP2__V_CNDMASK_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_CNDMASK_B32
+
+ class Inst_VOP2__V_ADD_F32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_ADD_F32(InFmt_VOP2*);
+ ~Inst_VOP2__V_ADD_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_ADD_F32
+
+ class Inst_VOP2__V_SUB_F32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_SUB_F32(InFmt_VOP2*);
+ ~Inst_VOP2__V_SUB_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_SUB_F32
+
+ class Inst_VOP2__V_SUBREV_F32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_SUBREV_F32(InFmt_VOP2*);
+ ~Inst_VOP2__V_SUBREV_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_SUBREV_F32
+
+ class Inst_VOP2__V_MUL_LEGACY_F32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MUL_LEGACY_F32(InFmt_VOP2*);
+ ~Inst_VOP2__V_MUL_LEGACY_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MUL_LEGACY_F32
+
+ class Inst_VOP2__V_MUL_F32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MUL_F32(InFmt_VOP2*);
+ ~Inst_VOP2__V_MUL_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MUL_F32
+
+ class Inst_VOP2__V_MUL_I32_I24 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MUL_I32_I24(InFmt_VOP2*);
+ ~Inst_VOP2__V_MUL_I32_I24();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MUL_I32_I24
+
+ class Inst_VOP2__V_MUL_HI_I32_I24 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MUL_HI_I32_I24(InFmt_VOP2*);
+ ~Inst_VOP2__V_MUL_HI_I32_I24();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MUL_HI_I32_I24
+
+ class Inst_VOP2__V_MUL_U32_U24 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MUL_U32_U24(InFmt_VOP2*);
+ ~Inst_VOP2__V_MUL_U32_U24();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MUL_U32_U24
+
+ class Inst_VOP2__V_MUL_HI_U32_U24 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MUL_HI_U32_U24(InFmt_VOP2*);
+ ~Inst_VOP2__V_MUL_HI_U32_U24();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MUL_HI_U32_U24
+
+ class Inst_VOP2__V_MIN_F32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MIN_F32(InFmt_VOP2*);
+ ~Inst_VOP2__V_MIN_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MIN_F32
+
+ class Inst_VOP2__V_MAX_F32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MAX_F32(InFmt_VOP2*);
+ ~Inst_VOP2__V_MAX_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MAX_F32
+
+ class Inst_VOP2__V_MIN_I32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MIN_I32(InFmt_VOP2*);
+ ~Inst_VOP2__V_MIN_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MIN_I32
+
+ class Inst_VOP2__V_MAX_I32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MAX_I32(InFmt_VOP2*);
+ ~Inst_VOP2__V_MAX_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MAX_I32
+
+ class Inst_VOP2__V_MIN_U32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MIN_U32(InFmt_VOP2*);
+ ~Inst_VOP2__V_MIN_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MIN_U32
+
+ class Inst_VOP2__V_MAX_U32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MAX_U32(InFmt_VOP2*);
+ ~Inst_VOP2__V_MAX_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MAX_U32
+
+ class Inst_VOP2__V_LSHRREV_B32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_LSHRREV_B32(InFmt_VOP2*);
+ ~Inst_VOP2__V_LSHRREV_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_LSHRREV_B32
+
+ class Inst_VOP2__V_ASHRREV_I32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_ASHRREV_I32(InFmt_VOP2*);
+ ~Inst_VOP2__V_ASHRREV_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_ASHRREV_I32
+
+ class Inst_VOP2__V_LSHLREV_B32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_LSHLREV_B32(InFmt_VOP2*);
+ ~Inst_VOP2__V_LSHLREV_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_LSHLREV_B32
+
+ class Inst_VOP2__V_AND_B32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_AND_B32(InFmt_VOP2*);
+ ~Inst_VOP2__V_AND_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_AND_B32
+
+ class Inst_VOP2__V_OR_B32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_OR_B32(InFmt_VOP2*);
+ ~Inst_VOP2__V_OR_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_OR_B32
+
+ class Inst_VOP2__V_XOR_B32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_XOR_B32(InFmt_VOP2*);
+ ~Inst_VOP2__V_XOR_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_XOR_B32
+
+ class Inst_VOP2__V_MAC_F32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MAC_F32(InFmt_VOP2*);
+ ~Inst_VOP2__V_MAC_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MAC_F32
+
+ class Inst_VOP2__V_MADMK_F32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MADMK_F32(InFmt_VOP2*);
+ ~Inst_VOP2__V_MADMK_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MADMK_F32
+
+ class Inst_VOP2__V_MADAK_F32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MADAK_F32(InFmt_VOP2*);
+ ~Inst_VOP2__V_MADAK_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MADAK_F32
+
+ class Inst_VOP2__V_ADD_U32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_ADD_U32(InFmt_VOP2*);
+ ~Inst_VOP2__V_ADD_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 2; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ case 3: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ case 3: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ case 3: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_ADD_U32
+
+ class Inst_VOP2__V_SUB_U32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_SUB_U32(InFmt_VOP2*);
+ ~Inst_VOP2__V_SUB_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 2; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ case 3: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ case 3: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ case 3: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_SUB_U32
+
+ class Inst_VOP2__V_SUBREV_U32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_SUBREV_U32(InFmt_VOP2*);
+ ~Inst_VOP2__V_SUBREV_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 2; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ case 3: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ case 3: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ case 3: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_SUBREV_U32
+
+ class Inst_VOP2__V_ADDC_U32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_ADDC_U32(InFmt_VOP2*);
+ ~Inst_VOP2__V_ADDC_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 2; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ case 3: //vdst
+ return 4;
+ case 4: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return true;
+ case 3: //vdst
+ return false;
+ case 4: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return false;
+ case 3: //vdst
+ return true;
+ case 4: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_ADDC_U32
+
+ class Inst_VOP2__V_SUBB_U32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_SUBB_U32(InFmt_VOP2*);
+ ~Inst_VOP2__V_SUBB_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 2; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ case 3: //vdst
+ return 4;
+ case 4: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return true;
+ case 3: //vdst
+ return false;
+ case 4: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return false;
+ case 3: //vdst
+ return true;
+ case 4: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_SUBB_U32
+
+ class Inst_VOP2__V_SUBBREV_U32 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_SUBBREV_U32(InFmt_VOP2*);
+ ~Inst_VOP2__V_SUBBREV_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 2; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ case 3: //vdst
+ return 4;
+ case 4: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return true;
+ case 3: //vdst
+ return false;
+ case 4: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return false;
+ case 3: //vdst
+ return true;
+ case 4: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_SUBBREV_U32
+
+ class Inst_VOP2__V_ADD_F16 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_ADD_F16(InFmt_VOP2*);
+ ~Inst_VOP2__V_ADD_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_ADD_F16
+
+ class Inst_VOP2__V_SUB_F16 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_SUB_F16(InFmt_VOP2*);
+ ~Inst_VOP2__V_SUB_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_SUB_F16
+
+ class Inst_VOP2__V_SUBREV_F16 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_SUBREV_F16(InFmt_VOP2*);
+ ~Inst_VOP2__V_SUBREV_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_SUBREV_F16
+
+ class Inst_VOP2__V_MUL_F16 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MUL_F16(InFmt_VOP2*);
+ ~Inst_VOP2__V_MUL_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MUL_F16
+
+ class Inst_VOP2__V_MAC_F16 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MAC_F16(InFmt_VOP2*);
+ ~Inst_VOP2__V_MAC_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MAC_F16
+
+ class Inst_VOP2__V_MADMK_F16 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MADMK_F16(InFmt_VOP2*);
+ ~Inst_VOP2__V_MADMK_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //src_2
+ return 2;
+ case 3: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MADMK_F16
+
+ class Inst_VOP2__V_MADAK_F16 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MADAK_F16(InFmt_VOP2*);
+ ~Inst_VOP2__V_MADAK_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //src_2
+ return 2;
+ case 3: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MADAK_F16
+
+ class Inst_VOP2__V_ADD_U16 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_ADD_U16(InFmt_VOP2*);
+ ~Inst_VOP2__V_ADD_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_ADD_U16
+
+ class Inst_VOP2__V_SUB_U16 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_SUB_U16(InFmt_VOP2*);
+ ~Inst_VOP2__V_SUB_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_SUB_U16
+
+ class Inst_VOP2__V_SUBREV_U16 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_SUBREV_U16(InFmt_VOP2*);
+ ~Inst_VOP2__V_SUBREV_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_SUBREV_U16
+
+ class Inst_VOP2__V_MUL_LO_U16 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MUL_LO_U16(InFmt_VOP2*);
+ ~Inst_VOP2__V_MUL_LO_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MUL_LO_U16
+
+ class Inst_VOP2__V_LSHLREV_B16 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_LSHLREV_B16(InFmt_VOP2*);
+ ~Inst_VOP2__V_LSHLREV_B16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_LSHLREV_B16
+
+ class Inst_VOP2__V_LSHRREV_B16 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_LSHRREV_B16(InFmt_VOP2*);
+ ~Inst_VOP2__V_LSHRREV_B16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_LSHRREV_B16
+
+ class Inst_VOP2__V_ASHRREV_I16 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_ASHRREV_I16(InFmt_VOP2*);
+ ~Inst_VOP2__V_ASHRREV_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_ASHRREV_I16
+
+ class Inst_VOP2__V_MAX_F16 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MAX_F16(InFmt_VOP2*);
+ ~Inst_VOP2__V_MAX_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MAX_F16
+
+ class Inst_VOP2__V_MIN_F16 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MIN_F16(InFmt_VOP2*);
+ ~Inst_VOP2__V_MIN_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MIN_F16
+
+ class Inst_VOP2__V_MAX_U16 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MAX_U16(InFmt_VOP2*);
+ ~Inst_VOP2__V_MAX_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MAX_U16
+
+ class Inst_VOP2__V_MAX_I16 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MAX_I16(InFmt_VOP2*);
+ ~Inst_VOP2__V_MAX_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MAX_I16
+
+ class Inst_VOP2__V_MIN_U16 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MIN_U16(InFmt_VOP2*);
+ ~Inst_VOP2__V_MIN_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MIN_U16
+
+ class Inst_VOP2__V_MIN_I16 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_MIN_I16(InFmt_VOP2*);
+ ~Inst_VOP2__V_MIN_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_MIN_I16
+
+ class Inst_VOP2__V_LDEXP_F16 : public Inst_VOP2
+ {
+ public:
+ Inst_VOP2__V_LDEXP_F16(InFmt_VOP2*);
+ ~Inst_VOP2__V_LDEXP_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP2__V_LDEXP_F16
+
+ class Inst_VOP1__V_NOP : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_NOP(InFmt_VOP1*);
+ ~Inst_VOP1__V_NOP();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_NOP
+
+ class Inst_VOP1__V_MOV_B32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_MOV_B32(InFmt_VOP1*);
+ ~Inst_VOP1__V_MOV_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_MOV_B32
+
+ class Inst_VOP1__V_READFIRSTLANE_B32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_READFIRSTLANE_B32(InFmt_VOP1*);
+ ~Inst_VOP1__V_READFIRSTLANE_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vsrc
+ return 4;
+ case 1: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vsrc
+ return true;
+ case 1: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vsrc
+ return false;
+ case 1: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_READFIRSTLANE_B32
+
+ class Inst_VOP1__V_CVT_I32_F64 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_I32_F64(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_I32_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_I32_F64
+
+ class Inst_VOP1__V_CVT_F64_I32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_F64_I32(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_F64_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_F64_I32
+
+ class Inst_VOP1__V_CVT_F32_I32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_F32_I32(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_F32_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_F32_I32
+
+ class Inst_VOP1__V_CVT_F32_U32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_F32_U32(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_F32_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_F32_U32
+
+ class Inst_VOP1__V_CVT_U32_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_U32_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_U32_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_U32_F32
+
+ class Inst_VOP1__V_CVT_I32_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_I32_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_I32_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_I32_F32
+
+ class Inst_VOP1__V_MOV_FED_B32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_MOV_FED_B32(InFmt_VOP1*);
+ ~Inst_VOP1__V_MOV_FED_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_MOV_FED_B32
+
+ class Inst_VOP1__V_CVT_F16_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_F16_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_F16_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_F16_F32
+
+ class Inst_VOP1__V_CVT_F32_F16 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_F32_F16(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_F32_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_F32_F16
+
+ class Inst_VOP1__V_CVT_RPI_I32_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_RPI_I32_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_RPI_I32_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_RPI_I32_F32
+
+ class Inst_VOP1__V_CVT_FLR_I32_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_FLR_I32_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_FLR_I32_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_FLR_I32_F32
+
+ class Inst_VOP1__V_CVT_OFF_F32_I4 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_OFF_F32_I4(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_OFF_F32_I4();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_OFF_F32_I4
+
+ class Inst_VOP1__V_CVT_F32_F64 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_F32_F64(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_F32_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_F32_F64
+
+ class Inst_VOP1__V_CVT_F64_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_F64_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_F64_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_F64_F32
+
+ class Inst_VOP1__V_CVT_F32_UBYTE0 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_F32_UBYTE0(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_F32_UBYTE0();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_F32_UBYTE0
+
+ class Inst_VOP1__V_CVT_F32_UBYTE1 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_F32_UBYTE1(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_F32_UBYTE1();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_F32_UBYTE1
+
+ class Inst_VOP1__V_CVT_F32_UBYTE2 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_F32_UBYTE2(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_F32_UBYTE2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_F32_UBYTE2
+
+ class Inst_VOP1__V_CVT_F32_UBYTE3 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_F32_UBYTE3(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_F32_UBYTE3();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_F32_UBYTE3
+
+ class Inst_VOP1__V_CVT_U32_F64 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_U32_F64(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_U32_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_U32_F64
+
+ class Inst_VOP1__V_CVT_F64_U32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_F64_U32(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_F64_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_F64_U32
+
+ class Inst_VOP1__V_TRUNC_F64 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_TRUNC_F64(InFmt_VOP1*);
+ ~Inst_VOP1__V_TRUNC_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_TRUNC_F64
+
+ class Inst_VOP1__V_CEIL_F64 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CEIL_F64(InFmt_VOP1*);
+ ~Inst_VOP1__V_CEIL_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CEIL_F64
+
+ class Inst_VOP1__V_RNDNE_F64 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_RNDNE_F64(InFmt_VOP1*);
+ ~Inst_VOP1__V_RNDNE_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_RNDNE_F64
+
+ class Inst_VOP1__V_FLOOR_F64 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_FLOOR_F64(InFmt_VOP1*);
+ ~Inst_VOP1__V_FLOOR_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_FLOOR_F64
+
+ class Inst_VOP1__V_FRACT_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_FRACT_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_FRACT_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_FRACT_F32
+
+ class Inst_VOP1__V_TRUNC_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_TRUNC_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_TRUNC_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_TRUNC_F32
+
+ class Inst_VOP1__V_CEIL_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CEIL_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_CEIL_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CEIL_F32
+
+ class Inst_VOP1__V_RNDNE_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_RNDNE_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_RNDNE_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_RNDNE_F32
+
+ class Inst_VOP1__V_FLOOR_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_FLOOR_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_FLOOR_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_FLOOR_F32
+
+ class Inst_VOP1__V_EXP_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_EXP_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_EXP_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_EXP_F32
+
+ class Inst_VOP1__V_LOG_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_LOG_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_LOG_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_LOG_F32
+
+ class Inst_VOP1__V_RCP_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_RCP_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_RCP_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_RCP_F32
+
+ class Inst_VOP1__V_RCP_IFLAG_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_RCP_IFLAG_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_RCP_IFLAG_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_RCP_IFLAG_F32
+
+ class Inst_VOP1__V_RSQ_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_RSQ_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_RSQ_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_RSQ_F32
+
+ class Inst_VOP1__V_RCP_F64 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_RCP_F64(InFmt_VOP1*);
+ ~Inst_VOP1__V_RCP_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_RCP_F64
+
+ class Inst_VOP1__V_RSQ_F64 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_RSQ_F64(InFmt_VOP1*);
+ ~Inst_VOP1__V_RSQ_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_RSQ_F64
+
+ class Inst_VOP1__V_SQRT_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_SQRT_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_SQRT_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_SQRT_F32
+
+ class Inst_VOP1__V_SQRT_F64 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_SQRT_F64(InFmt_VOP1*);
+ ~Inst_VOP1__V_SQRT_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_SQRT_F64
+
+ class Inst_VOP1__V_SIN_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_SIN_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_SIN_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_SIN_F32
+
+ class Inst_VOP1__V_COS_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_COS_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_COS_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_COS_F32
+
+ class Inst_VOP1__V_NOT_B32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_NOT_B32(InFmt_VOP1*);
+ ~Inst_VOP1__V_NOT_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_NOT_B32
+
+ class Inst_VOP1__V_BFREV_B32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_BFREV_B32(InFmt_VOP1*);
+ ~Inst_VOP1__V_BFREV_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_BFREV_B32
+
+ class Inst_VOP1__V_FFBH_U32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_FFBH_U32(InFmt_VOP1*);
+ ~Inst_VOP1__V_FFBH_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_FFBH_U32
+
+ class Inst_VOP1__V_FFBL_B32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_FFBL_B32(InFmt_VOP1*);
+ ~Inst_VOP1__V_FFBL_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_FFBL_B32
+
+ class Inst_VOP1__V_FFBH_I32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_FFBH_I32(InFmt_VOP1*);
+ ~Inst_VOP1__V_FFBH_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_FFBH_I32
+
+ class Inst_VOP1__V_FREXP_EXP_I32_F64 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_FREXP_EXP_I32_F64(InFmt_VOP1*);
+ ~Inst_VOP1__V_FREXP_EXP_I32_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_FREXP_EXP_I32_F64
+
+ class Inst_VOP1__V_FREXP_MANT_F64 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_FREXP_MANT_F64(InFmt_VOP1*);
+ ~Inst_VOP1__V_FREXP_MANT_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_FREXP_MANT_F64
+
+ class Inst_VOP1__V_FRACT_F64 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_FRACT_F64(InFmt_VOP1*);
+ ~Inst_VOP1__V_FRACT_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_FRACT_F64
+
+ class Inst_VOP1__V_FREXP_EXP_I32_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_FREXP_EXP_I32_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_FREXP_EXP_I32_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_FREXP_EXP_I32_F32
+
+ class Inst_VOP1__V_FREXP_MANT_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_FREXP_MANT_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_FREXP_MANT_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_FREXP_MANT_F32
+
+ class Inst_VOP1__V_CLREXCP : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CLREXCP(InFmt_VOP1*);
+ ~Inst_VOP1__V_CLREXCP();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CLREXCP
+
+ class Inst_VOP1__V_CVT_F16_U16 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_F16_U16(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_F16_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_F16_U16
+
+ class Inst_VOP1__V_CVT_F16_I16 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_F16_I16(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_F16_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_F16_I16
+
+ class Inst_VOP1__V_CVT_U16_F16 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_U16_F16(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_U16_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_U16_F16
+
+ class Inst_VOP1__V_CVT_I16_F16 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CVT_I16_F16(InFmt_VOP1*);
+ ~Inst_VOP1__V_CVT_I16_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CVT_I16_F16
+
+ class Inst_VOP1__V_RCP_F16 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_RCP_F16(InFmt_VOP1*);
+ ~Inst_VOP1__V_RCP_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_RCP_F16
+
+ class Inst_VOP1__V_SQRT_F16 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_SQRT_F16(InFmt_VOP1*);
+ ~Inst_VOP1__V_SQRT_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_SQRT_F16
+
+ class Inst_VOP1__V_RSQ_F16 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_RSQ_F16(InFmt_VOP1*);
+ ~Inst_VOP1__V_RSQ_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_RSQ_F16
+
+ class Inst_VOP1__V_LOG_F16 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_LOG_F16(InFmt_VOP1*);
+ ~Inst_VOP1__V_LOG_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_LOG_F16
+
+ class Inst_VOP1__V_EXP_F16 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_EXP_F16(InFmt_VOP1*);
+ ~Inst_VOP1__V_EXP_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_EXP_F16
+
+ class Inst_VOP1__V_FREXP_MANT_F16 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_FREXP_MANT_F16(InFmt_VOP1*);
+ ~Inst_VOP1__V_FREXP_MANT_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_FREXP_MANT_F16
+
+ class Inst_VOP1__V_FREXP_EXP_I16_F16 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_FREXP_EXP_I16_F16(InFmt_VOP1*);
+ ~Inst_VOP1__V_FREXP_EXP_I16_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_FREXP_EXP_I16_F16
+
+ class Inst_VOP1__V_FLOOR_F16 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_FLOOR_F16(InFmt_VOP1*);
+ ~Inst_VOP1__V_FLOOR_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_FLOOR_F16
+
+ class Inst_VOP1__V_CEIL_F16 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_CEIL_F16(InFmt_VOP1*);
+ ~Inst_VOP1__V_CEIL_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_CEIL_F16
+
+ class Inst_VOP1__V_TRUNC_F16 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_TRUNC_F16(InFmt_VOP1*);
+ ~Inst_VOP1__V_TRUNC_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_TRUNC_F16
+
+ class Inst_VOP1__V_RNDNE_F16 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_RNDNE_F16(InFmt_VOP1*);
+ ~Inst_VOP1__V_RNDNE_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_RNDNE_F16
+
+ class Inst_VOP1__V_FRACT_F16 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_FRACT_F16(InFmt_VOP1*);
+ ~Inst_VOP1__V_FRACT_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_FRACT_F16
+
+ class Inst_VOP1__V_SIN_F16 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_SIN_F16(InFmt_VOP1*);
+ ~Inst_VOP1__V_SIN_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_SIN_F16
+
+ class Inst_VOP1__V_COS_F16 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_COS_F16(InFmt_VOP1*);
+ ~Inst_VOP1__V_COS_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_COS_F16
+
+ class Inst_VOP1__V_EXP_LEGACY_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_EXP_LEGACY_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_EXP_LEGACY_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_EXP_LEGACY_F32
+
+ class Inst_VOP1__V_LOG_LEGACY_F32 : public Inst_VOP1
+ {
+ public:
+ Inst_VOP1__V_LOG_LEGACY_F32(InFmt_VOP1*);
+ ~Inst_VOP1__V_LOG_LEGACY_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP1__V_LOG_LEGACY_F32
+
+ class Inst_VOPC__V_CMP_CLASS_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_CLASS_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_CLASS_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_CLASS_F32
+
+ class Inst_VOPC__V_CMPX_CLASS_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_CLASS_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_CLASS_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_CLASS_F32
+
+ class Inst_VOPC__V_CMP_CLASS_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_CLASS_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_CLASS_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: // vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_CLASS_F64
+
+ class Inst_VOPC__V_CMPX_CLASS_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_CLASS_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_CLASS_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_CLASS_F64
+
+ class Inst_VOPC__V_CMP_CLASS_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_CLASS_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_CLASS_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_CLASS_F16
+
+ class Inst_VOPC__V_CMPX_CLASS_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_CLASS_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_CLASS_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_CLASS_F16
+
+ class Inst_VOPC__V_CMP_F_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_F_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_F_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_F_F16
+
+ class Inst_VOPC__V_CMP_LT_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_LT_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_LT_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_LT_F16
+
+ class Inst_VOPC__V_CMP_EQ_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_EQ_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_EQ_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_EQ_F16
+
+ class Inst_VOPC__V_CMP_LE_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_LE_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_LE_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_LE_F16
+
+ class Inst_VOPC__V_CMP_GT_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_GT_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_GT_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_GT_F16
+
+ class Inst_VOPC__V_CMP_LG_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_LG_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_LG_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_LG_F16
+
+ class Inst_VOPC__V_CMP_GE_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_GE_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_GE_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_GE_F16
+
+ class Inst_VOPC__V_CMP_O_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_O_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_O_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_O_F16
+
+ class Inst_VOPC__V_CMP_U_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_U_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_U_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_U_F16
+
+ class Inst_VOPC__V_CMP_NGE_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NGE_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NGE_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NGE_F16
+
+ class Inst_VOPC__V_CMP_NLG_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NLG_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NLG_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NLG_F16
+
+ class Inst_VOPC__V_CMP_NGT_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NGT_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NGT_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NGT_F16
+
+ class Inst_VOPC__V_CMP_NLE_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NLE_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NLE_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NLE_F16
+
+ class Inst_VOPC__V_CMP_NEQ_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NEQ_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NEQ_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NEQ_F16
+
+ class Inst_VOPC__V_CMP_NLT_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NLT_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NLT_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NLT_F16
+
+ class Inst_VOPC__V_CMP_TRU_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_TRU_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_TRU_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_TRU_F16
+
+ class Inst_VOPC__V_CMPX_F_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_F_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_F_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_F_F16
+
+ class Inst_VOPC__V_CMPX_LT_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_LT_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_LT_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_LT_F16
+
+ class Inst_VOPC__V_CMPX_EQ_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_EQ_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_EQ_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_EQ_F16
+
+ class Inst_VOPC__V_CMPX_LE_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_LE_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_LE_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_LE_F16
+
+ class Inst_VOPC__V_CMPX_GT_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_GT_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_GT_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_GT_F16
+
+ class Inst_VOPC__V_CMPX_LG_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_LG_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_LG_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_LG_F16
+
+ class Inst_VOPC__V_CMPX_GE_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_GE_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_GE_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_GE_F16
+
+ class Inst_VOPC__V_CMPX_O_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_O_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_O_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_O_F16
+
+ class Inst_VOPC__V_CMPX_U_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_U_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_U_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_U_F16
+
+ class Inst_VOPC__V_CMPX_NGE_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NGE_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NGE_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NGE_F16
+
+ class Inst_VOPC__V_CMPX_NLG_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NLG_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NLG_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NLG_F16
+
+ class Inst_VOPC__V_CMPX_NGT_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NGT_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NGT_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NGT_F16
+
+ class Inst_VOPC__V_CMPX_NLE_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NLE_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NLE_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NLE_F16
+
+ class Inst_VOPC__V_CMPX_NEQ_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NEQ_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NEQ_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NEQ_F16
+
+ class Inst_VOPC__V_CMPX_NLT_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NLT_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NLT_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NLT_F16
+
+ class Inst_VOPC__V_CMPX_TRU_F16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_TRU_F16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_TRU_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_TRU_F16
+
+ class Inst_VOPC__V_CMP_F_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_F_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_F_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_F_F32
+
+ class Inst_VOPC__V_CMP_LT_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_LT_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_LT_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_LT_F32
+
+ class Inst_VOPC__V_CMP_EQ_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_EQ_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_EQ_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_EQ_F32
+
+ class Inst_VOPC__V_CMP_LE_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_LE_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_LE_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_LE_F32
+
+ class Inst_VOPC__V_CMP_GT_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_GT_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_GT_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_GT_F32
+
+ class Inst_VOPC__V_CMP_LG_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_LG_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_LG_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_LG_F32
+
+ class Inst_VOPC__V_CMP_GE_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_GE_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_GE_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_GE_F32
+
+ class Inst_VOPC__V_CMP_O_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_O_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_O_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_O_F32
+
+ class Inst_VOPC__V_CMP_U_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_U_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_U_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_U_F32
+
+ class Inst_VOPC__V_CMP_NGE_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NGE_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NGE_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NGE_F32
+
+ class Inst_VOPC__V_CMP_NLG_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NLG_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NLG_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NLG_F32
+
+ class Inst_VOPC__V_CMP_NGT_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NGT_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NGT_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NGT_F32
+
+ class Inst_VOPC__V_CMP_NLE_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NLE_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NLE_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NLE_F32
+
+ class Inst_VOPC__V_CMP_NEQ_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NEQ_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NEQ_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NEQ_F32
+
+ class Inst_VOPC__V_CMP_NLT_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NLT_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NLT_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NLT_F32
+
+ class Inst_VOPC__V_CMP_TRU_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_TRU_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_TRU_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_TRU_F32
+
+ class Inst_VOPC__V_CMPX_F_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_F_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_F_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_F_F32
+
+ class Inst_VOPC__V_CMPX_LT_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_LT_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_LT_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_LT_F32
+
+ class Inst_VOPC__V_CMPX_EQ_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_EQ_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_EQ_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_EQ_F32
+
+ class Inst_VOPC__V_CMPX_LE_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_LE_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_LE_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_LE_F32
+
+ class Inst_VOPC__V_CMPX_GT_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_GT_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_GT_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_GT_F32
+
+ class Inst_VOPC__V_CMPX_LG_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_LG_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_LG_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_LG_F32
+
+ class Inst_VOPC__V_CMPX_GE_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_GE_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_GE_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_GE_F32
+
+ class Inst_VOPC__V_CMPX_O_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_O_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_O_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_O_F32
+
+ class Inst_VOPC__V_CMPX_U_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_U_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_U_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_U_F32
+
+ class Inst_VOPC__V_CMPX_NGE_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NGE_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NGE_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NGE_F32
+
+ class Inst_VOPC__V_CMPX_NLG_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NLG_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NLG_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NLG_F32
+
+ class Inst_VOPC__V_CMPX_NGT_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NGT_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NGT_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NGT_F32
+
+ class Inst_VOPC__V_CMPX_NLE_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NLE_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NLE_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NLE_F32
+
+ class Inst_VOPC__V_CMPX_NEQ_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NEQ_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NEQ_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NEQ_F32
+
+ class Inst_VOPC__V_CMPX_NLT_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NLT_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NLT_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NLT_F32
+
+ class Inst_VOPC__V_CMPX_TRU_F32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_TRU_F32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_TRU_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_TRU_F32
+
+ class Inst_VOPC__V_CMP_F_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_F_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_F_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_F_F64
+
+ class Inst_VOPC__V_CMP_LT_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_LT_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_LT_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_LT_F64
+
+ class Inst_VOPC__V_CMP_EQ_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_EQ_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_EQ_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_EQ_F64
+
+ class Inst_VOPC__V_CMP_LE_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_LE_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_LE_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_LE_F64
+
+ class Inst_VOPC__V_CMP_GT_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_GT_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_GT_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_GT_F64
+
+ class Inst_VOPC__V_CMP_LG_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_LG_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_LG_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_LG_F64
+
+ class Inst_VOPC__V_CMP_GE_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_GE_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_GE_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_GE_F64
+
+ class Inst_VOPC__V_CMP_O_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_O_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_O_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_O_F64
+
+ class Inst_VOPC__V_CMP_U_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_U_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_U_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_U_F64
+
+ class Inst_VOPC__V_CMP_NGE_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NGE_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NGE_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NGE_F64
+
+ class Inst_VOPC__V_CMP_NLG_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NLG_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NLG_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NLG_F64
+
+ class Inst_VOPC__V_CMP_NGT_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NGT_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NGT_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NGT_F64
+
+ class Inst_VOPC__V_CMP_NLE_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NLE_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NLE_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NLE_F64
+
+ class Inst_VOPC__V_CMP_NEQ_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NEQ_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NEQ_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NEQ_F64
+
+ class Inst_VOPC__V_CMP_NLT_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NLT_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NLT_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NLT_F64
+
+ class Inst_VOPC__V_CMP_TRU_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_TRU_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_TRU_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_TRU_F64
+
+ class Inst_VOPC__V_CMPX_F_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_F_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_F_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_F_F64
+
+ class Inst_VOPC__V_CMPX_LT_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_LT_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_LT_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_LT_F64
+
+ class Inst_VOPC__V_CMPX_EQ_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_EQ_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_EQ_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_EQ_F64
+
+ class Inst_VOPC__V_CMPX_LE_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_LE_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_LE_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_LE_F64
+
+ class Inst_VOPC__V_CMPX_GT_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_GT_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_GT_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_GT_F64
+
+ class Inst_VOPC__V_CMPX_LG_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_LG_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_LG_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_LG_F64
+
+ class Inst_VOPC__V_CMPX_GE_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_GE_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_GE_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_GE_F64
+
+ class Inst_VOPC__V_CMPX_O_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_O_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_O_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_O_F64
+
+ class Inst_VOPC__V_CMPX_U_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_U_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_U_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_U_F64
+
+ class Inst_VOPC__V_CMPX_NGE_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NGE_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NGE_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NGE_F64
+
+ class Inst_VOPC__V_CMPX_NLG_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NLG_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NLG_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NLG_F64
+
+ class Inst_VOPC__V_CMPX_NGT_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NGT_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NGT_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NGT_F64
+
+ class Inst_VOPC__V_CMPX_NLE_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NLE_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NLE_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NLE_F64
+
+ class Inst_VOPC__V_CMPX_NEQ_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NEQ_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NEQ_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NEQ_F64
+
+ class Inst_VOPC__V_CMPX_NLT_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NLT_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NLT_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NLT_F64
+
+ class Inst_VOPC__V_CMPX_TRU_F64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_TRU_F64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_TRU_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_TRU_F64
+
+ class Inst_VOPC__V_CMP_F_I16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_F_I16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_F_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_F_I16
+
+ class Inst_VOPC__V_CMP_LT_I16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_LT_I16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_LT_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_LT_I16
+
+ class Inst_VOPC__V_CMP_EQ_I16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_EQ_I16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_EQ_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_EQ_I16
+
+ class Inst_VOPC__V_CMP_LE_I16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_LE_I16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_LE_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_LE_I16
+
+ class Inst_VOPC__V_CMP_GT_I16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_GT_I16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_GT_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_GT_I16
+
+ class Inst_VOPC__V_CMP_NE_I16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NE_I16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NE_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NE_I16
+
+ class Inst_VOPC__V_CMP_GE_I16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_GE_I16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_GE_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_GE_I16
+
+ class Inst_VOPC__V_CMP_T_I16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_T_I16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_T_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_T_I16
+
+ class Inst_VOPC__V_CMP_F_U16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_F_U16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_F_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_F_U16
+
+ class Inst_VOPC__V_CMP_LT_U16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_LT_U16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_LT_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_LT_U16
+
+ class Inst_VOPC__V_CMP_EQ_U16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_EQ_U16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_EQ_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_EQ_U16
+
+ class Inst_VOPC__V_CMP_LE_U16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_LE_U16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_LE_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_LE_U16
+
+ class Inst_VOPC__V_CMP_GT_U16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_GT_U16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_GT_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_GT_U16
+
+ class Inst_VOPC__V_CMP_NE_U16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NE_U16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NE_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NE_U16
+
+ class Inst_VOPC__V_CMP_GE_U16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_GE_U16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_GE_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_GE_U16
+
+ class Inst_VOPC__V_CMP_T_U16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_T_U16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_T_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_T_U16
+
+ class Inst_VOPC__V_CMPX_F_I16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_F_I16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_F_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_F_I16
+
+ class Inst_VOPC__V_CMPX_LT_I16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_LT_I16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_LT_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_LT_I16
+
+ class Inst_VOPC__V_CMPX_EQ_I16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_EQ_I16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_EQ_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_EQ_I16
+
+ class Inst_VOPC__V_CMPX_LE_I16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_LE_I16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_LE_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_LE_I16
+
+ class Inst_VOPC__V_CMPX_GT_I16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_GT_I16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_GT_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_GT_I16
+
+ class Inst_VOPC__V_CMPX_NE_I16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NE_I16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NE_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NE_I16
+
+ class Inst_VOPC__V_CMPX_GE_I16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_GE_I16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_GE_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_GE_I16
+
+ class Inst_VOPC__V_CMPX_T_I16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_T_I16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_T_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_T_I16
+
+ class Inst_VOPC__V_CMPX_F_U16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_F_U16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_F_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_F_U16
+
+ class Inst_VOPC__V_CMPX_LT_U16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_LT_U16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_LT_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_LT_U16
+
+ class Inst_VOPC__V_CMPX_EQ_U16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_EQ_U16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_EQ_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_EQ_U16
+
+ class Inst_VOPC__V_CMPX_LE_U16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_LE_U16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_LE_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_LE_U16
+
+ class Inst_VOPC__V_CMPX_GT_U16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_GT_U16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_GT_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_GT_U16
+
+ class Inst_VOPC__V_CMPX_NE_U16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NE_U16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NE_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NE_U16
+
+ class Inst_VOPC__V_CMPX_GE_U16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_GE_U16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_GE_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_GE_U16
+
+ class Inst_VOPC__V_CMPX_T_U16 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_T_U16(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_T_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_T_U16
+
+ class Inst_VOPC__V_CMP_F_I32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_F_I32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_F_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_F_I32
+
+ class Inst_VOPC__V_CMP_LT_I32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_LT_I32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_LT_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_LT_I32
+
+ class Inst_VOPC__V_CMP_EQ_I32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_EQ_I32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_EQ_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_EQ_I32
+
+ class Inst_VOPC__V_CMP_LE_I32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_LE_I32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_LE_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_LE_I32
+
+ class Inst_VOPC__V_CMP_GT_I32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_GT_I32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_GT_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_GT_I32
+
+ class Inst_VOPC__V_CMP_NE_I32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NE_I32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NE_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NE_I32
+
+ class Inst_VOPC__V_CMP_GE_I32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_GE_I32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_GE_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_GE_I32
+
+ class Inst_VOPC__V_CMP_T_I32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_T_I32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_T_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_T_I32
+
+ class Inst_VOPC__V_CMP_F_U32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_F_U32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_F_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_F_U32
+
+ class Inst_VOPC__V_CMP_LT_U32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_LT_U32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_LT_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_LT_U32
+
+ class Inst_VOPC__V_CMP_EQ_U32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_EQ_U32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_EQ_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_EQ_U32
+
+ class Inst_VOPC__V_CMP_LE_U32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_LE_U32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_LE_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_LE_U32
+
+ class Inst_VOPC__V_CMP_GT_U32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_GT_U32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_GT_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_GT_U32
+
+ class Inst_VOPC__V_CMP_NE_U32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NE_U32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NE_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NE_U32
+
+ class Inst_VOPC__V_CMP_GE_U32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_GE_U32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_GE_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_GE_U32
+
+ class Inst_VOPC__V_CMP_T_U32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_T_U32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_T_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_T_U32
+
+ class Inst_VOPC__V_CMPX_F_I32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_F_I32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_F_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_F_I32
+
+ class Inst_VOPC__V_CMPX_LT_I32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_LT_I32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_LT_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_LT_I32
+
+ class Inst_VOPC__V_CMPX_EQ_I32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_EQ_I32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_EQ_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_EQ_I32
+
+ class Inst_VOPC__V_CMPX_LE_I32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_LE_I32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_LE_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_LE_I32
+
+ class Inst_VOPC__V_CMPX_GT_I32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_GT_I32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_GT_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_GT_I32
+
+ class Inst_VOPC__V_CMPX_NE_I32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NE_I32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NE_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NE_I32
+
+ class Inst_VOPC__V_CMPX_GE_I32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_GE_I32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_GE_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_GE_I32
+
+ class Inst_VOPC__V_CMPX_T_I32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_T_I32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_T_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_T_I32
+
+ class Inst_VOPC__V_CMPX_F_U32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_F_U32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_F_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_F_U32
+
+ class Inst_VOPC__V_CMPX_LT_U32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_LT_U32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_LT_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_LT_U32
+
+ class Inst_VOPC__V_CMPX_EQ_U32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_EQ_U32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_EQ_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_EQ_U32
+
+ class Inst_VOPC__V_CMPX_LE_U32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_LE_U32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_LE_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_LE_U32
+
+ class Inst_VOPC__V_CMPX_GT_U32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_GT_U32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_GT_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_GT_U32
+
+ class Inst_VOPC__V_CMPX_NE_U32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NE_U32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NE_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NE_U32
+
+ class Inst_VOPC__V_CMPX_GE_U32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_GE_U32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_GE_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_GE_U32
+
+ class Inst_VOPC__V_CMPX_T_U32 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_T_U32(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_T_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_T_U32
+
+ class Inst_VOPC__V_CMP_F_I64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_F_I64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_F_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_F_I64
+
+ class Inst_VOPC__V_CMP_LT_I64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_LT_I64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_LT_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_LT_I64
+
+ class Inst_VOPC__V_CMP_EQ_I64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_EQ_I64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_EQ_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_EQ_I64
+
+ class Inst_VOPC__V_CMP_LE_I64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_LE_I64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_LE_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_LE_I64
+
+ class Inst_VOPC__V_CMP_GT_I64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_GT_I64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_GT_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_GT_I64
+
+ class Inst_VOPC__V_CMP_NE_I64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NE_I64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NE_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NE_I64
+
+ class Inst_VOPC__V_CMP_GE_I64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_GE_I64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_GE_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_GE_I64
+
+ class Inst_VOPC__V_CMP_T_I64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_T_I64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_T_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_T_I64
+
+ class Inst_VOPC__V_CMP_F_U64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_F_U64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_F_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_F_U64
+
+ class Inst_VOPC__V_CMP_LT_U64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_LT_U64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_LT_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_LT_U64
+
+ class Inst_VOPC__V_CMP_EQ_U64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_EQ_U64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_EQ_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_EQ_U64
+
+ class Inst_VOPC__V_CMP_LE_U64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_LE_U64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_LE_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_LE_U64
+
+ class Inst_VOPC__V_CMP_GT_U64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_GT_U64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_GT_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_GT_U64
+
+ class Inst_VOPC__V_CMP_NE_U64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_NE_U64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_NE_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_NE_U64
+
+ class Inst_VOPC__V_CMP_GE_U64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_GE_U64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_GE_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_GE_U64
+
+ class Inst_VOPC__V_CMP_T_U64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMP_T_U64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMP_T_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMP_T_U64
+
+ class Inst_VOPC__V_CMPX_F_I64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_F_I64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_F_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_F_I64
+
+ class Inst_VOPC__V_CMPX_LT_I64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_LT_I64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_LT_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_LT_I64
+
+ class Inst_VOPC__V_CMPX_EQ_I64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_EQ_I64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_EQ_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_EQ_I64
+
+ class Inst_VOPC__V_CMPX_LE_I64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_LE_I64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_LE_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_LE_I64
+
+ class Inst_VOPC__V_CMPX_GT_I64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_GT_I64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_GT_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_GT_I64
+
+ class Inst_VOPC__V_CMPX_NE_I64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NE_I64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NE_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NE_I64
+
+ class Inst_VOPC__V_CMPX_GE_I64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_GE_I64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_GE_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_GE_I64
+
+ class Inst_VOPC__V_CMPX_T_I64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_T_I64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_T_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_T_I64
+
+ class Inst_VOPC__V_CMPX_F_U64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_F_U64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_F_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_F_U64
+
+ class Inst_VOPC__V_CMPX_LT_U64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_LT_U64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_LT_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_LT_U64
+
+ class Inst_VOPC__V_CMPX_EQ_U64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_EQ_U64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_EQ_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_EQ_U64
+
+ class Inst_VOPC__V_CMPX_LE_U64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_LE_U64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_LE_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_LE_U64
+
+ class Inst_VOPC__V_CMPX_GT_U64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_GT_U64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_GT_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_GT_U64
+
+ class Inst_VOPC__V_CMPX_NE_U64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_NE_U64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_NE_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_NE_U64
+
+ class Inst_VOPC__V_CMPX_GE_U64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_GE_U64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_GE_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_GE_U64
+
+ class Inst_VOPC__V_CMPX_T_U64 : public Inst_VOPC
+ {
+ public:
+ Inst_VOPC__V_CMPX_T_U64(InFmt_VOPC*);
+ ~Inst_VOPC__V_CMPX_T_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOPC__V_CMPX_T_U64
+
+ class Inst_VINTRP__V_INTERP_P1_F32 : public Inst_VINTRP
+ {
+ public:
+ Inst_VINTRP__V_INTERP_P1_F32(InFmt_VINTRP*);
+ ~Inst_VINTRP__V_INTERP_P1_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_ij
+ return 4;
+ case 1: //attr
+ return 16;
+ case 2: //vgpr_dst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_ij
+ return true;
+ case 1: //attr
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_ij
+ return false;
+ case 1: //attr
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VINTRP__V_INTERP_P1_F32
+
+ class Inst_VINTRP__V_INTERP_P2_F32 : public Inst_VINTRP
+ {
+ public:
+ Inst_VINTRP__V_INTERP_P2_F32(InFmt_VINTRP*);
+ ~Inst_VINTRP__V_INTERP_P2_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_ij
+ return 4;
+ case 1: //attr
+ return 16;
+ case 2: //vgpr_dst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_ij
+ return true;
+ case 1: //attr
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_ij
+ return false;
+ case 1: //attr
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VINTRP__V_INTERP_P2_F32
+
+ class Inst_VINTRP__V_INTERP_MOV_F32 : public Inst_VINTRP
+ {
+ public:
+ Inst_VINTRP__V_INTERP_MOV_F32(InFmt_VINTRP*);
+ ~Inst_VINTRP__V_INTERP_MOV_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //param
+ return 4;
+ case 1: //attr
+ return 16;
+ case 2: //vgpr_dst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //param
+ return true;
+ case 1: //attr
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //param
+ return false;
+ case 1: //attr
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VINTRP__V_INTERP_MOV_F32
+
+ class Inst_VOP3__V_CMP_CLASS_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_CLASS_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_CLASS_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_CLASS_F32
+
+ class Inst_VOP3__V_CMPX_CLASS_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_CLASS_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_CLASS_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_CLASS_F32
+
+ class Inst_VOP3__V_CMP_CLASS_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_CLASS_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_CLASS_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_CLASS_F64
+
+ class Inst_VOP3__V_CMPX_CLASS_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_CLASS_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_CLASS_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_CLASS_F64
+
+ class Inst_VOP3__V_CMP_CLASS_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_CLASS_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_CLASS_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_CLASS_F16
+
+ class Inst_VOP3__V_CMPX_CLASS_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_CLASS_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_CLASS_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_CLASS_F16
+
+ class Inst_VOP3__V_CMP_F_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_F_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_F_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_F_F16
+
+ class Inst_VOP3__V_CMP_LT_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_LT_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_LT_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_LT_F16
+
+ class Inst_VOP3__V_CMP_EQ_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_EQ_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_EQ_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_EQ_F16
+
+ class Inst_VOP3__V_CMP_LE_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_LE_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_LE_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_LE_F16
+
+ class Inst_VOP3__V_CMP_GT_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_GT_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_GT_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_GT_F16
+
+ class Inst_VOP3__V_CMP_LG_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_LG_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_LG_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_LG_F16
+
+ class Inst_VOP3__V_CMP_GE_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_GE_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_GE_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_GE_F16
+
+ class Inst_VOP3__V_CMP_O_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_O_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_O_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_O_F16
+
+ class Inst_VOP3__V_CMP_U_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_U_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_U_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_U_F16
+
+ class Inst_VOP3__V_CMP_NGE_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NGE_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NGE_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NGE_F16
+
+ class Inst_VOP3__V_CMP_NLG_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NLG_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NLG_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NLG_F16
+
+ class Inst_VOP3__V_CMP_NGT_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NGT_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NGT_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NGT_F16
+
+ class Inst_VOP3__V_CMP_NLE_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NLE_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NLE_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NLE_F16
+
+ class Inst_VOP3__V_CMP_NEQ_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NEQ_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NEQ_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NEQ_F16
+
+ class Inst_VOP3__V_CMP_NLT_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NLT_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NLT_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NLT_F16
+
+ class Inst_VOP3__V_CMP_TRU_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_TRU_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_TRU_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_TRU_F16
+
+ class Inst_VOP3__V_CMPX_F_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_F_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_F_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_F_F16
+
+ class Inst_VOP3__V_CMPX_LT_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_LT_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_LT_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_LT_F16
+
+ class Inst_VOP3__V_CMPX_EQ_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_EQ_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_EQ_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_EQ_F16
+
+ class Inst_VOP3__V_CMPX_LE_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_LE_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_LE_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_LE_F16
+
+ class Inst_VOP3__V_CMPX_GT_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_GT_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_GT_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_GT_F16
+
+ class Inst_VOP3__V_CMPX_LG_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_LG_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_LG_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_LG_F16
+
+ class Inst_VOP3__V_CMPX_GE_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_GE_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_GE_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_GE_F16
+
+ class Inst_VOP3__V_CMPX_O_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_O_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_O_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_O_F16
+
+ class Inst_VOP3__V_CMPX_U_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_U_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_U_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_U_F16
+
+ class Inst_VOP3__V_CMPX_NGE_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NGE_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NGE_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NGE_F16
+
+ class Inst_VOP3__V_CMPX_NLG_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NLG_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NLG_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NLG_F16
+
+ class Inst_VOP3__V_CMPX_NGT_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NGT_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NGT_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NGT_F16
+
+ class Inst_VOP3__V_CMPX_NLE_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NLE_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NLE_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NLE_F16
+
+ class Inst_VOP3__V_CMPX_NEQ_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NEQ_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NEQ_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NEQ_F16
+
+ class Inst_VOP3__V_CMPX_NLT_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NLT_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NLT_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NLT_F16
+
+ class Inst_VOP3__V_CMPX_TRU_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_TRU_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_TRU_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_TRU_F16
+
+ class Inst_VOP3__V_CMP_F_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_F_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_F_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_F_F32
+
+ class Inst_VOP3__V_CMP_LT_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_LT_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_LT_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_LT_F32
+
+ class Inst_VOP3__V_CMP_EQ_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_EQ_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_EQ_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_EQ_F32
+
+ class Inst_VOP3__V_CMP_LE_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_LE_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_LE_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_LE_F32
+
+ class Inst_VOP3__V_CMP_GT_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_GT_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_GT_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_GT_F32
+
+ class Inst_VOP3__V_CMP_LG_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_LG_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_LG_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_LG_F32
+
+ class Inst_VOP3__V_CMP_GE_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_GE_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_GE_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_GE_F32
+
+ class Inst_VOP3__V_CMP_O_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_O_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_O_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_O_F32
+
+ class Inst_VOP3__V_CMP_U_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_U_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_U_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_U_F32
+
+ class Inst_VOP3__V_CMP_NGE_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NGE_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NGE_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NGE_F32
+
+ class Inst_VOP3__V_CMP_NLG_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NLG_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NLG_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NLG_F32
+
+ class Inst_VOP3__V_CMP_NGT_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NGT_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NGT_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NGT_F32
+
+ class Inst_VOP3__V_CMP_NLE_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NLE_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NLE_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NLE_F32
+
+ class Inst_VOP3__V_CMP_NEQ_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NEQ_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NEQ_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NEQ_F32
+
+ class Inst_VOP3__V_CMP_NLT_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NLT_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NLT_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NLT_F32
+
+ class Inst_VOP3__V_CMP_TRU_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_TRU_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_TRU_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_TRU_F32
+
+ class Inst_VOP3__V_CMPX_F_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_F_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_F_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_F_F32
+
+ class Inst_VOP3__V_CMPX_LT_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_LT_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_LT_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_LT_F32
+
+ class Inst_VOP3__V_CMPX_EQ_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_EQ_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_EQ_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_EQ_F32
+
+ class Inst_VOP3__V_CMPX_LE_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_LE_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_LE_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_LE_F32
+
+ class Inst_VOP3__V_CMPX_GT_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_GT_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_GT_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_GT_F32
+
+ class Inst_VOP3__V_CMPX_LG_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_LG_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_LG_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_LG_F32
+
+ class Inst_VOP3__V_CMPX_GE_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_GE_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_GE_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_GE_F32
+
+ class Inst_VOP3__V_CMPX_O_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_O_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_O_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_O_F32
+
+ class Inst_VOP3__V_CMPX_U_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_U_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_U_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_U_F32
+
+ class Inst_VOP3__V_CMPX_NGE_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NGE_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NGE_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NGE_F32
+
+ class Inst_VOP3__V_CMPX_NLG_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NLG_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NLG_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NLG_F32
+
+ class Inst_VOP3__V_CMPX_NGT_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NGT_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NGT_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NGT_F32
+
+ class Inst_VOP3__V_CMPX_NLE_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NLE_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NLE_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NLE_F32
+
+ class Inst_VOP3__V_CMPX_NEQ_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NEQ_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NEQ_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NEQ_F32
+
+ class Inst_VOP3__V_CMPX_NLT_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NLT_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NLT_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NLT_F32
+
+ class Inst_VOP3__V_CMPX_TRU_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_TRU_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_TRU_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_TRU_F32
+
+ class Inst_VOP3__V_CMP_F_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_F_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_F_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_F_F64
+
+ class Inst_VOP3__V_CMP_LT_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_LT_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_LT_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_LT_F64
+
+ class Inst_VOP3__V_CMP_EQ_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_EQ_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_EQ_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_EQ_F64
+
+ class Inst_VOP3__V_CMP_LE_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_LE_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_LE_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_LE_F64
+
+ class Inst_VOP3__V_CMP_GT_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_GT_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_GT_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_GT_F64
+
+ class Inst_VOP3__V_CMP_LG_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_LG_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_LG_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_LG_F64
+
+ class Inst_VOP3__V_CMP_GE_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_GE_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_GE_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_GE_F64
+
+ class Inst_VOP3__V_CMP_O_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_O_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_O_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_O_F64
+
+ class Inst_VOP3__V_CMP_U_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_U_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_U_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_U_F64
+
+ class Inst_VOP3__V_CMP_NGE_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NGE_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NGE_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NGE_F64
+
+ class Inst_VOP3__V_CMP_NLG_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NLG_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NLG_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NLG_F64
+
+ class Inst_VOP3__V_CMP_NGT_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NGT_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NGT_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NGT_F64
+
+ class Inst_VOP3__V_CMP_NLE_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NLE_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NLE_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NLE_F64
+
+ class Inst_VOP3__V_CMP_NEQ_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NEQ_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NEQ_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NEQ_F64
+
+ class Inst_VOP3__V_CMP_NLT_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NLT_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NLT_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NLT_F64
+
+ class Inst_VOP3__V_CMP_TRU_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_TRU_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_TRU_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_TRU_F64
+
+ class Inst_VOP3__V_CMPX_F_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_F_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_F_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_F_F64
+
+ class Inst_VOP3__V_CMPX_LT_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_LT_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_LT_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_LT_F64
+
+ class Inst_VOP3__V_CMPX_EQ_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_EQ_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_EQ_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_EQ_F64
+
+ class Inst_VOP3__V_CMPX_LE_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_LE_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_LE_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_LE_F64
+
+ class Inst_VOP3__V_CMPX_GT_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_GT_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_GT_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_GT_F64
+
+ class Inst_VOP3__V_CMPX_LG_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_LG_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_LG_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_LG_F64
+
+ class Inst_VOP3__V_CMPX_GE_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_GE_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_GE_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_GE_F64
+
+ class Inst_VOP3__V_CMPX_O_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_O_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_O_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_O_F64
+
+ class Inst_VOP3__V_CMPX_U_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_U_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_U_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_U_F64
+
+ class Inst_VOP3__V_CMPX_NGE_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NGE_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NGE_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NGE_F64
+
+ class Inst_VOP3__V_CMPX_NLG_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NLG_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NLG_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NLG_F64
+
+ class Inst_VOP3__V_CMPX_NGT_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NGT_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NGT_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NGT_F64
+
+ class Inst_VOP3__V_CMPX_NLE_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NLE_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NLE_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NLE_F64
+
+ class Inst_VOP3__V_CMPX_NEQ_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NEQ_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NEQ_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NEQ_F64
+
+ class Inst_VOP3__V_CMPX_NLT_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NLT_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NLT_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NLT_F64
+
+ class Inst_VOP3__V_CMPX_TRU_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_TRU_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_TRU_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_TRU_F64
+
+ class Inst_VOP3__V_CMP_F_I16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_F_I16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_F_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_F_I16
+
+ class Inst_VOP3__V_CMP_LT_I16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_LT_I16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_LT_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_LT_I16
+
+ class Inst_VOP3__V_CMP_EQ_I16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_EQ_I16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_EQ_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_EQ_I16
+
+ class Inst_VOP3__V_CMP_LE_I16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_LE_I16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_LE_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_LE_I16
+
+ class Inst_VOP3__V_CMP_GT_I16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_GT_I16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_GT_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_GT_I16
+
+ class Inst_VOP3__V_CMP_NE_I16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NE_I16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NE_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NE_I16
+
+ class Inst_VOP3__V_CMP_GE_I16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_GE_I16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_GE_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_GE_I16
+
+ class Inst_VOP3__V_CMP_T_I16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_T_I16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_T_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_T_I16
+
+ class Inst_VOP3__V_CMP_F_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_F_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_F_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_F_U16
+
+ class Inst_VOP3__V_CMP_LT_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_LT_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_LT_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_LT_U16
+
+ class Inst_VOP3__V_CMP_EQ_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_EQ_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_EQ_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_EQ_U16
+
+ class Inst_VOP3__V_CMP_LE_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_LE_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_LE_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_LE_U16
+
+ class Inst_VOP3__V_CMP_GT_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_GT_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_GT_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_GT_U16
+
+ class Inst_VOP3__V_CMP_NE_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NE_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NE_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NE_U16
+
+ class Inst_VOP3__V_CMP_GE_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_GE_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_GE_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_GE_U16
+
+ class Inst_VOP3__V_CMP_T_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_T_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_T_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_T_U16
+
+ class Inst_VOP3__V_CMPX_F_I16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_F_I16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_F_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_F_I16
+
+ class Inst_VOP3__V_CMPX_LT_I16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_LT_I16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_LT_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_LT_I16
+
+ class Inst_VOP3__V_CMPX_EQ_I16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_EQ_I16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_EQ_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_EQ_I16
+
+ class Inst_VOP3__V_CMPX_LE_I16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_LE_I16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_LE_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_LE_I16
+
+ class Inst_VOP3__V_CMPX_GT_I16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_GT_I16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_GT_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_GT_I16
+
+ class Inst_VOP3__V_CMPX_NE_I16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NE_I16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NE_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NE_I16
+
+ class Inst_VOP3__V_CMPX_GE_I16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_GE_I16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_GE_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_GE_I16
+
+ class Inst_VOP3__V_CMPX_T_I16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_T_I16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_T_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_T_I16
+
+ class Inst_VOP3__V_CMPX_F_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_F_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_F_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_F_U16
+
+ class Inst_VOP3__V_CMPX_LT_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_LT_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_LT_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_LT_U16
+
+ class Inst_VOP3__V_CMPX_EQ_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_EQ_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_EQ_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_EQ_U16
+
+ class Inst_VOP3__V_CMPX_LE_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_LE_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_LE_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_LE_U16
+
+ class Inst_VOP3__V_CMPX_GT_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_GT_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_GT_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_GT_U16
+
+ class Inst_VOP3__V_CMPX_NE_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NE_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NE_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NE_U16
+
+ class Inst_VOP3__V_CMPX_GE_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_GE_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_GE_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_GE_U16
+
+ class Inst_VOP3__V_CMPX_T_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_T_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_T_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_T_U16
+
+ class Inst_VOP3__V_CMP_F_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_F_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_F_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_F_I32
+
+ class Inst_VOP3__V_CMP_LT_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_LT_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_LT_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_LT_I32
+
+ class Inst_VOP3__V_CMP_EQ_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_EQ_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_EQ_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_EQ_I32
+
+ class Inst_VOP3__V_CMP_LE_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_LE_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_LE_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_LE_I32
+
+ class Inst_VOP3__V_CMP_GT_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_GT_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_GT_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_GT_I32
+
+ class Inst_VOP3__V_CMP_NE_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NE_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NE_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NE_I32
+
+ class Inst_VOP3__V_CMP_GE_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_GE_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_GE_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_GE_I32
+
+ class Inst_VOP3__V_CMP_T_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_T_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_T_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_T_I32
+
+ class Inst_VOP3__V_CMP_F_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_F_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_F_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_F_U32
+
+ class Inst_VOP3__V_CMP_LT_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_LT_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_LT_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_LT_U32
+
+ class Inst_VOP3__V_CMP_EQ_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_EQ_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_EQ_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_EQ_U32
+
+ class Inst_VOP3__V_CMP_LE_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_LE_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_LE_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_LE_U32
+
+ class Inst_VOP3__V_CMP_GT_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_GT_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_GT_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_GT_U32
+
+ class Inst_VOP3__V_CMP_NE_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NE_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NE_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NE_U32
+
+ class Inst_VOP3__V_CMP_GE_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_GE_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_GE_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_GE_U32
+
+ class Inst_VOP3__V_CMP_T_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_T_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_T_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_T_U32
+
+ class Inst_VOP3__V_CMPX_F_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_F_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_F_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_F_I32
+
+ class Inst_VOP3__V_CMPX_LT_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_LT_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_LT_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_LT_I32
+
+ class Inst_VOP3__V_CMPX_EQ_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_EQ_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_EQ_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_EQ_I32
+
+ class Inst_VOP3__V_CMPX_LE_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_LE_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_LE_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_LE_I32
+
+ class Inst_VOP3__V_CMPX_GT_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_GT_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_GT_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_GT_I32
+
+ class Inst_VOP3__V_CMPX_NE_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NE_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NE_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NE_I32
+
+ class Inst_VOP3__V_CMPX_GE_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_GE_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_GE_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_GE_I32
+
+ class Inst_VOP3__V_CMPX_T_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_T_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_T_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_T_I32
+
+ class Inst_VOP3__V_CMPX_F_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_F_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_F_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_F_U32
+
+ class Inst_VOP3__V_CMPX_LT_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_LT_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_LT_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_LT_U32
+
+ class Inst_VOP3__V_CMPX_EQ_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_EQ_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_EQ_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_EQ_U32
+
+ class Inst_VOP3__V_CMPX_LE_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_LE_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_LE_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_LE_U32
+
+ class Inst_VOP3__V_CMPX_GT_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_GT_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_GT_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_GT_U32
+
+ class Inst_VOP3__V_CMPX_NE_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NE_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NE_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NE_U32
+
+ class Inst_VOP3__V_CMPX_GE_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_GE_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_GE_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_GE_U32
+
+ class Inst_VOP3__V_CMPX_T_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_T_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_T_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_T_U32
+
+ class Inst_VOP3__V_CMP_F_I64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_F_I64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_F_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_F_I64
+
+ class Inst_VOP3__V_CMP_LT_I64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_LT_I64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_LT_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_LT_I64
+
+ class Inst_VOP3__V_CMP_EQ_I64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_EQ_I64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_EQ_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_EQ_I64
+
+ class Inst_VOP3__V_CMP_LE_I64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_LE_I64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_LE_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_LE_I64
+
+ class Inst_VOP3__V_CMP_GT_I64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_GT_I64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_GT_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_GT_I64
+
+ class Inst_VOP3__V_CMP_NE_I64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NE_I64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NE_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NE_I64
+
+ class Inst_VOP3__V_CMP_GE_I64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_GE_I64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_GE_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_GE_I64
+
+ class Inst_VOP3__V_CMP_T_I64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_T_I64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_T_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_T_I64
+
+ class Inst_VOP3__V_CMP_F_U64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_F_U64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_F_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_F_U64
+
+ class Inst_VOP3__V_CMP_LT_U64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_LT_U64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_LT_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_LT_U64
+
+ class Inst_VOP3__V_CMP_EQ_U64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_EQ_U64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_EQ_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_EQ_U64
+
+ class Inst_VOP3__V_CMP_LE_U64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_LE_U64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_LE_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_LE_U64
+
+ class Inst_VOP3__V_CMP_GT_U64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_GT_U64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_GT_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_GT_U64
+
+ class Inst_VOP3__V_CMP_NE_U64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_NE_U64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_NE_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_NE_U64
+
+ class Inst_VOP3__V_CMP_GE_U64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_GE_U64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_GE_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_GE_U64
+
+ class Inst_VOP3__V_CMP_T_U64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMP_T_U64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMP_T_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMP_T_U64
+
+ class Inst_VOP3__V_CMPX_F_I64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_F_I64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_F_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_F_I64
+
+ class Inst_VOP3__V_CMPX_LT_I64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_LT_I64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_LT_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_LT_I64
+
+ class Inst_VOP3__V_CMPX_EQ_I64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_EQ_I64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_EQ_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_EQ_I64
+
+ class Inst_VOP3__V_CMPX_LE_I64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_LE_I64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_LE_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_LE_I64
+
+ class Inst_VOP3__V_CMPX_GT_I64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_GT_I64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_GT_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_GT_I64
+
+ class Inst_VOP3__V_CMPX_NE_I64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NE_I64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NE_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NE_I64
+
+ class Inst_VOP3__V_CMPX_GE_I64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_GE_I64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_GE_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_GE_I64
+
+ class Inst_VOP3__V_CMPX_T_I64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_T_I64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_T_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_T_I64
+
+ class Inst_VOP3__V_CMPX_F_U64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_F_U64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_F_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_F_U64
+
+ class Inst_VOP3__V_CMPX_LT_U64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_LT_U64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_LT_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_LT_U64
+
+ class Inst_VOP3__V_CMPX_EQ_U64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_EQ_U64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_EQ_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_EQ_U64
+
+ class Inst_VOP3__V_CMPX_LE_U64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_LE_U64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_LE_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_LE_U64
+
+ class Inst_VOP3__V_CMPX_GT_U64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_GT_U64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_GT_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_GT_U64
+
+ class Inst_VOP3__V_CMPX_NE_U64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_NE_U64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_NE_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_NE_U64
+
+ class Inst_VOP3__V_CMPX_GE_U64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_GE_U64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_GE_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_GE_U64
+
+ class Inst_VOP3__V_CMPX_T_U64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CMPX_T_U64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CMPX_T_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //sdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CMPX_T_U64
+
+ class Inst_VOP3__V_CNDMASK_B32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CNDMASK_B32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CNDMASK_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //carryin
+ return 8;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //carryin
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //carryin
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CNDMASK_B32
+
+ class Inst_VOP3__V_ADD_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_ADD_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_ADD_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_ADD_F32
+
+ class Inst_VOP3__V_SUB_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_SUB_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_SUB_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_SUB_F32
+
+ class Inst_VOP3__V_SUBREV_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_SUBREV_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_SUBREV_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_SUBREV_F32
+
+ class Inst_VOP3__V_MUL_LEGACY_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MUL_LEGACY_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MUL_LEGACY_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MUL_LEGACY_F32
+
+ class Inst_VOP3__V_MUL_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MUL_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MUL_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MUL_F32
+
+ class Inst_VOP3__V_MUL_I32_I24 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MUL_I32_I24(InFmt_VOP3*);
+ ~Inst_VOP3__V_MUL_I32_I24();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MUL_I32_I24
+
+ class Inst_VOP3__V_MUL_HI_I32_I24 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MUL_HI_I32_I24(InFmt_VOP3*);
+ ~Inst_VOP3__V_MUL_HI_I32_I24();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MUL_HI_I32_I24
+
+ class Inst_VOP3__V_MUL_U32_U24 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MUL_U32_U24(InFmt_VOP3*);
+ ~Inst_VOP3__V_MUL_U32_U24();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MUL_U32_U24
+
+ class Inst_VOP3__V_MUL_HI_U32_U24 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MUL_HI_U32_U24(InFmt_VOP3*);
+ ~Inst_VOP3__V_MUL_HI_U32_U24();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MUL_HI_U32_U24
+
+ class Inst_VOP3__V_MIN_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MIN_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MIN_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MIN_F32
+
+ class Inst_VOP3__V_MAX_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MAX_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MAX_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MAX_F32
+
+ class Inst_VOP3__V_MIN_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MIN_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MIN_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MIN_I32
+
+ class Inst_VOP3__V_MAX_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MAX_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MAX_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MAX_I32
+
+ class Inst_VOP3__V_MIN_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MIN_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MIN_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MIN_U32
+
+ class Inst_VOP3__V_MAX_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MAX_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MAX_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MAX_U32
+
+ class Inst_VOP3__V_LSHRREV_B32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_LSHRREV_B32(InFmt_VOP3*);
+ ~Inst_VOP3__V_LSHRREV_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_LSHRREV_B32
+
+ class Inst_VOP3__V_ASHRREV_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_ASHRREV_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_ASHRREV_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_ASHRREV_I32
+
+ class Inst_VOP3__V_LSHLREV_B32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_LSHLREV_B32(InFmt_VOP3*);
+ ~Inst_VOP3__V_LSHLREV_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_LSHLREV_B32
+
+ class Inst_VOP3__V_AND_B32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_AND_B32(InFmt_VOP3*);
+ ~Inst_VOP3__V_AND_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_AND_B32
+
+ class Inst_VOP3__V_OR_B32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_OR_B32(InFmt_VOP3*);
+ ~Inst_VOP3__V_OR_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_OR_B32
+
+ class Inst_VOP3__V_XOR_B32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_XOR_B32(InFmt_VOP3*);
+ ~Inst_VOP3__V_XOR_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_XOR_B32
+
+ class Inst_VOP3__V_MAC_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MAC_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MAC_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MAC_F32
+
+ class Inst_VOP3__V_ADD_U32 : public Inst_VOP3_SDST_ENC
+ {
+ public:
+ Inst_VOP3__V_ADD_U32(InFmt_VOP3_SDST_ENC*);
+ ~Inst_VOP3__V_ADD_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 2; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ case 3: //carryout
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ case 3: //carryout
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ case 3: //carryout
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_ADD_U32
+
+ class Inst_VOP3__V_SUB_U32 : public Inst_VOP3_SDST_ENC
+ {
+ public:
+ Inst_VOP3__V_SUB_U32(InFmt_VOP3_SDST_ENC*);
+ ~Inst_VOP3__V_SUB_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 2; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ case 3: //carryout
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ case 3: //carryout
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ case 3: //carryout
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_SUB_U32
+
+ class Inst_VOP3__V_SUBREV_U32 : public Inst_VOP3_SDST_ENC
+ {
+ public:
+ Inst_VOP3__V_SUBREV_U32(InFmt_VOP3_SDST_ENC*);
+ ~Inst_VOP3__V_SUBREV_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 2; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ case 3: //carryout
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ case 3: //carryout
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ case 3: //carryout
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_SUBREV_U32
+
+ class Inst_VOP3__V_ADDC_U32 : public Inst_VOP3_SDST_ENC
+ {
+ public:
+ Inst_VOP3__V_ADDC_U32(InFmt_VOP3_SDST_ENC*);
+ ~Inst_VOP3__V_ADDC_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 2; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //carryin
+ return 8;
+ case 3: //vdst
+ return 4;
+ case 4: //carryout
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //carryin
+ return true;
+ case 3: //vdst
+ return false;
+ case 4: //carryout
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //carryin
+ return false;
+ case 3: //vdst
+ return true;
+ case 4: //carryout
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_ADDC_U32
+
+ class Inst_VOP3__V_SUBB_U32 : public Inst_VOP3_SDST_ENC
+ {
+ public:
+ Inst_VOP3__V_SUBB_U32(InFmt_VOP3_SDST_ENC*);
+ ~Inst_VOP3__V_SUBB_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 2; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //carryin
+ return 8;
+ case 3: //vdst
+ return 4;
+ case 4: //carryout
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //carryin
+ return true;
+ case 3: //vdst
+ return false;
+ case 4: //carryout
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //carryin
+ return false;
+ case 3: //vdst
+ return true;
+ case 4: //carryout
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_SUBB_U32
+
+ class Inst_VOP3__V_SUBBREV_U32 : public Inst_VOP3_SDST_ENC
+ {
+ public:
+ Inst_VOP3__V_SUBBREV_U32(InFmt_VOP3_SDST_ENC*);
+ ~Inst_VOP3__V_SUBBREV_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 2; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //carryin
+ return 8;
+ case 3: //vdst
+ return 4;
+ case 4: //carryout
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //carryin
+ return true;
+ case 3: //vdst
+ return false;
+ case 4: //carryout
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //carryin
+ return false;
+ case 3: //vdst
+ return true;
+ case 4: //carryout
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_SUBBREV_U32
+
+ class Inst_VOP3__V_ADD_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_ADD_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_ADD_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_ADD_F16
+
+ class Inst_VOP3__V_SUB_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_SUB_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_SUB_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_SUB_F16
+
+ class Inst_VOP3__V_SUBREV_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_SUBREV_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_SUBREV_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_SUBREV_F16
+
+ class Inst_VOP3__V_MUL_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MUL_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_MUL_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MUL_F16
+
+ class Inst_VOP3__V_MAC_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MAC_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_MAC_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MAC_F16
+
+ class Inst_VOP3__V_ADD_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_ADD_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_ADD_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_ADD_U16
+
+ class Inst_VOP3__V_SUB_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_SUB_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_SUB_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_SUB_U16
+
+ class Inst_VOP3__V_SUBREV_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_SUBREV_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_SUBREV_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_SUBREV_U16
+
+ class Inst_VOP3__V_MUL_LO_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MUL_LO_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_MUL_LO_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MUL_LO_U16
+
+ class Inst_VOP3__V_LSHLREV_B16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_LSHLREV_B16(InFmt_VOP3*);
+ ~Inst_VOP3__V_LSHLREV_B16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_LSHLREV_B16
+
+ class Inst_VOP3__V_LSHRREV_B16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_LSHRREV_B16(InFmt_VOP3*);
+ ~Inst_VOP3__V_LSHRREV_B16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_LSHRREV_B16
+
+ class Inst_VOP3__V_ASHRREV_I16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_ASHRREV_I16(InFmt_VOP3*);
+ ~Inst_VOP3__V_ASHRREV_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_ASHRREV_I16
+
+ class Inst_VOP3__V_MAX_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MAX_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_MAX_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MAX_F16
+
+ class Inst_VOP3__V_MIN_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MIN_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_MIN_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MIN_F16
+
+ class Inst_VOP3__V_MAX_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MAX_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_MAX_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MAX_U16
+
+ class Inst_VOP3__V_MAX_I16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MAX_I16(InFmt_VOP3*);
+ ~Inst_VOP3__V_MAX_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MAX_I16
+
+ class Inst_VOP3__V_MIN_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MIN_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_MIN_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MIN_U16
+
+ class Inst_VOP3__V_MIN_I16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MIN_I16(InFmt_VOP3*);
+ ~Inst_VOP3__V_MIN_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MIN_I16
+
+ class Inst_VOP3__V_LDEXP_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_LDEXP_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_LDEXP_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_LDEXP_F16
+
+ class Inst_VOP3__V_NOP : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_NOP(InFmt_VOP3*);
+ ~Inst_VOP3__V_NOP();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_NOP
+
+ class Inst_VOP3__V_MOV_B32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MOV_B32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MOV_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MOV_B32
+
+ class Inst_VOP3__V_CVT_I32_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_I32_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_I32_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_I32_F64
+
+ class Inst_VOP3__V_CVT_F64_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_F64_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_F64_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_F64_I32
+
+ class Inst_VOP3__V_CVT_F32_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_F32_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_F32_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_F32_I32
+
+ class Inst_VOP3__V_CVT_F32_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_F32_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_F32_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_F32_U32
+
+ class Inst_VOP3__V_CVT_U32_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_U32_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_U32_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_U32_F32
+
+ class Inst_VOP3__V_CVT_I32_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_I32_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_I32_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_I32_F32
+
+ class Inst_VOP3__V_MOV_FED_B32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MOV_FED_B32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MOV_FED_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MOV_FED_B32
+
+ class Inst_VOP3__V_CVT_F16_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_F16_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_F16_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_F16_F32
+
+ class Inst_VOP3__V_CVT_F32_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_F32_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_F32_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_F32_F16
+
+ class Inst_VOP3__V_CVT_RPI_I32_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_RPI_I32_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_RPI_I32_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_RPI_I32_F32
+
+ class Inst_VOP3__V_CVT_FLR_I32_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_FLR_I32_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_FLR_I32_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_FLR_I32_F32
+
+ class Inst_VOP3__V_CVT_OFF_F32_I4 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_OFF_F32_I4(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_OFF_F32_I4();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_OFF_F32_I4
+
+ class Inst_VOP3__V_CVT_F32_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_F32_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_F32_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_F32_F64
+
+ class Inst_VOP3__V_CVT_F64_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_F64_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_F64_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_F64_F32
+
+ class Inst_VOP3__V_CVT_F32_UBYTE0 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_F32_UBYTE0(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_F32_UBYTE0();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_F32_UBYTE0
+
+ class Inst_VOP3__V_CVT_F32_UBYTE1 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_F32_UBYTE1(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_F32_UBYTE1();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_F32_UBYTE1
+
+ class Inst_VOP3__V_CVT_F32_UBYTE2 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_F32_UBYTE2(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_F32_UBYTE2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_F32_UBYTE2
+
+ class Inst_VOP3__V_CVT_F32_UBYTE3 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_F32_UBYTE3(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_F32_UBYTE3();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_F32_UBYTE3
+
+ class Inst_VOP3__V_CVT_U32_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_U32_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_U32_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_U32_F64
+
+ class Inst_VOP3__V_CVT_F64_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_F64_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_F64_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_F64_U32
+
+ class Inst_VOP3__V_TRUNC_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_TRUNC_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_TRUNC_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_TRUNC_F64
+
+ class Inst_VOP3__V_CEIL_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CEIL_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_CEIL_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CEIL_F64
+
+ class Inst_VOP3__V_RNDNE_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_RNDNE_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_RNDNE_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_RNDNE_F64
+
+ class Inst_VOP3__V_FLOOR_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_FLOOR_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_FLOOR_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_FLOOR_F64
+
+ class Inst_VOP3__V_FRACT_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_FRACT_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_FRACT_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_FRACT_F32
+
+ class Inst_VOP3__V_TRUNC_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_TRUNC_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_TRUNC_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_TRUNC_F32
+
+ class Inst_VOP3__V_CEIL_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CEIL_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CEIL_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CEIL_F32
+
+ class Inst_VOP3__V_RNDNE_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_RNDNE_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_RNDNE_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_RNDNE_F32
+
+ class Inst_VOP3__V_FLOOR_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_FLOOR_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_FLOOR_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_FLOOR_F32
+
+ class Inst_VOP3__V_EXP_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_EXP_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_EXP_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_EXP_F32
+
+ class Inst_VOP3__V_LOG_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_LOG_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_LOG_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_LOG_F32
+
+ class Inst_VOP3__V_RCP_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_RCP_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_RCP_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_RCP_F32
+
+ class Inst_VOP3__V_RCP_IFLAG_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_RCP_IFLAG_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_RCP_IFLAG_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_RCP_IFLAG_F32
+
+ class Inst_VOP3__V_RSQ_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_RSQ_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_RSQ_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_RSQ_F32
+
+ class Inst_VOP3__V_RCP_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_RCP_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_RCP_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_RCP_F64
+
+ class Inst_VOP3__V_RSQ_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_RSQ_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_RSQ_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_RSQ_F64
+
+ class Inst_VOP3__V_SQRT_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_SQRT_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_SQRT_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_SQRT_F32
+
+ class Inst_VOP3__V_SQRT_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_SQRT_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_SQRT_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_SQRT_F64
+
+ class Inst_VOP3__V_SIN_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_SIN_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_SIN_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_SIN_F32
+
+ class Inst_VOP3__V_COS_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_COS_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_COS_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_COS_F32
+
+ class Inst_VOP3__V_NOT_B32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_NOT_B32(InFmt_VOP3*);
+ ~Inst_VOP3__V_NOT_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_NOT_B32
+
+ class Inst_VOP3__V_BFREV_B32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_BFREV_B32(InFmt_VOP3*);
+ ~Inst_VOP3__V_BFREV_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_BFREV_B32
+
+ class Inst_VOP3__V_FFBH_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_FFBH_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_FFBH_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_FFBH_U32
+
+ class Inst_VOP3__V_FFBL_B32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_FFBL_B32(InFmt_VOP3*);
+ ~Inst_VOP3__V_FFBL_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_FFBL_B32
+
+ class Inst_VOP3__V_FFBH_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_FFBH_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_FFBH_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_FFBH_I32
+
+ class Inst_VOP3__V_FREXP_EXP_I32_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_FREXP_EXP_I32_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_FREXP_EXP_I32_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_FREXP_EXP_I32_F64
+
+ class Inst_VOP3__V_FREXP_MANT_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_FREXP_MANT_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_FREXP_MANT_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_FREXP_MANT_F64
+
+ class Inst_VOP3__V_FRACT_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_FRACT_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_FRACT_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 8;
+ case 1: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_FRACT_F64
+
+ class Inst_VOP3__V_FREXP_EXP_I32_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_FREXP_EXP_I32_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_FREXP_EXP_I32_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_FREXP_EXP_I32_F32
+
+ class Inst_VOP3__V_FREXP_MANT_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_FREXP_MANT_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_FREXP_MANT_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_FREXP_MANT_F32
+
+ class Inst_VOP3__V_CLREXCP : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CLREXCP(InFmt_VOP3*);
+ ~Inst_VOP3__V_CLREXCP();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CLREXCP
+
+ class Inst_VOP3__V_CVT_F16_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_F16_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_F16_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_F16_U16
+
+ class Inst_VOP3__V_CVT_F16_I16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_F16_I16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_F16_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_F16_I16
+
+ class Inst_VOP3__V_CVT_U16_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_U16_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_U16_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_U16_F16
+
+ class Inst_VOP3__V_CVT_I16_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_I16_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_I16_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_I16_F16
+
+ class Inst_VOP3__V_RCP_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_RCP_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_RCP_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_RCP_F16
+
+ class Inst_VOP3__V_SQRT_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_SQRT_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_SQRT_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_SQRT_F16
+
+ class Inst_VOP3__V_RSQ_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_RSQ_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_RSQ_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_RSQ_F16
+
+ class Inst_VOP3__V_LOG_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_LOG_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_LOG_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_LOG_F16
+
+ class Inst_VOP3__V_EXP_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_EXP_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_EXP_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_EXP_F16
+
+ class Inst_VOP3__V_FREXP_MANT_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_FREXP_MANT_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_FREXP_MANT_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_FREXP_MANT_F16
+
+ class Inst_VOP3__V_FREXP_EXP_I16_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_FREXP_EXP_I16_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_FREXP_EXP_I16_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_FREXP_EXP_I16_F16
+
+ class Inst_VOP3__V_FLOOR_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_FLOOR_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_FLOOR_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_FLOOR_F16
+
+ class Inst_VOP3__V_CEIL_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CEIL_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_CEIL_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CEIL_F16
+
+ class Inst_VOP3__V_TRUNC_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_TRUNC_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_TRUNC_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_TRUNC_F16
+
+ class Inst_VOP3__V_RNDNE_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_RNDNE_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_RNDNE_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_RNDNE_F16
+
+ class Inst_VOP3__V_FRACT_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_FRACT_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_FRACT_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_FRACT_F16
+
+ class Inst_VOP3__V_SIN_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_SIN_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_SIN_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_SIN_F16
+
+ class Inst_VOP3__V_COS_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_COS_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_COS_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 2;
+ case 1: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_COS_F16
+
+ class Inst_VOP3__V_EXP_LEGACY_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_EXP_LEGACY_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_EXP_LEGACY_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_EXP_LEGACY_F32
+
+ class Inst_VOP3__V_LOG_LEGACY_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_LOG_LEGACY_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_LOG_LEGACY_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return 4;
+ case 1: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return true;
+ case 1: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src
+ return false;
+ case 1: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_LOG_LEGACY_F32
+
+ class Inst_VOP3__V_MAD_LEGACY_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MAD_LEGACY_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MAD_LEGACY_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MAD_LEGACY_F32
+
+ class Inst_VOP3__V_MAD_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MAD_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MAD_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MAD_F32
+
+ class Inst_VOP3__V_MAD_I32_I24 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MAD_I32_I24(InFmt_VOP3*);
+ ~Inst_VOP3__V_MAD_I32_I24();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MAD_I32_I24
+
+ class Inst_VOP3__V_MAD_U32_U24 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MAD_U32_U24(InFmt_VOP3*);
+ ~Inst_VOP3__V_MAD_U32_U24();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MAD_U32_U24
+
+ class Inst_VOP3__V_CUBEID_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CUBEID_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CUBEID_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CUBEID_F32
+
+ class Inst_VOP3__V_CUBESC_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CUBESC_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CUBESC_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CUBESC_F32
+
+ class Inst_VOP3__V_CUBETC_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CUBETC_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CUBETC_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CUBETC_F32
+
+ class Inst_VOP3__V_CUBEMA_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CUBEMA_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CUBEMA_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CUBEMA_F32
+
+ class Inst_VOP3__V_BFE_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_BFE_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_BFE_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_BFE_U32
+
+ class Inst_VOP3__V_BFE_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_BFE_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_BFE_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_BFE_I32
+
+ class Inst_VOP3__V_BFI_B32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_BFI_B32(InFmt_VOP3*);
+ ~Inst_VOP3__V_BFI_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_BFI_B32
+
+ class Inst_VOP3__V_FMA_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_FMA_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_FMA_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_FMA_F32
+
+ class Inst_VOP3__V_FMA_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_FMA_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_FMA_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //src_2
+ return 8;
+ case 3: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_FMA_F64
+
+ class Inst_VOP3__V_LERP_U8 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_LERP_U8(InFmt_VOP3*);
+ ~Inst_VOP3__V_LERP_U8();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_LERP_U8
+
+ class Inst_VOP3__V_ALIGNBIT_B32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_ALIGNBIT_B32(InFmt_VOP3*);
+ ~Inst_VOP3__V_ALIGNBIT_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_ALIGNBIT_B32
+
+ class Inst_VOP3__V_ALIGNBYTE_B32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_ALIGNBYTE_B32(InFmt_VOP3*);
+ ~Inst_VOP3__V_ALIGNBYTE_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_ALIGNBYTE_B32
+
+ class Inst_VOP3__V_MIN3_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MIN3_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MIN3_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MIN3_F32
+
+ class Inst_VOP3__V_MIN3_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MIN3_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MIN3_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MIN3_I32
+
+ class Inst_VOP3__V_MIN3_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MIN3_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MIN3_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MIN3_U32
+
+ class Inst_VOP3__V_MAX3_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MAX3_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MAX3_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MAX3_F32
+
+ class Inst_VOP3__V_MAX3_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MAX3_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MAX3_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MAX3_I32
+
+ class Inst_VOP3__V_MAX3_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MAX3_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MAX3_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MAX3_U32
+
+ class Inst_VOP3__V_MED3_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MED3_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MED3_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MED3_F32
+
+ class Inst_VOP3__V_MED3_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MED3_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MED3_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MED3_I32
+
+ class Inst_VOP3__V_MED3_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MED3_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MED3_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MED3_U32
+
+ class Inst_VOP3__V_SAD_U8 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_SAD_U8(InFmt_VOP3*);
+ ~Inst_VOP3__V_SAD_U8();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_SAD_U8
+
+ class Inst_VOP3__V_SAD_HI_U8 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_SAD_HI_U8(InFmt_VOP3*);
+ ~Inst_VOP3__V_SAD_HI_U8();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_SAD_HI_U8
+
+ class Inst_VOP3__V_SAD_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_SAD_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_SAD_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_SAD_U16
+
+ class Inst_VOP3__V_SAD_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_SAD_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_SAD_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_SAD_U32
+
+ class Inst_VOP3__V_CVT_PK_U8_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_PK_U8_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_PK_U8_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_PK_U8_F32
+
+ class Inst_VOP3__V_DIV_FIXUP_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_DIV_FIXUP_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_DIV_FIXUP_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_DIV_FIXUP_F32
+
+ class Inst_VOP3__V_DIV_FIXUP_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_DIV_FIXUP_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_DIV_FIXUP_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //src_2
+ return 8;
+ case 3: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_DIV_FIXUP_F64
+
+ class Inst_VOP3__V_DIV_SCALE_F32 : public Inst_VOP3_SDST_ENC
+ {
+ public:
+ Inst_VOP3__V_DIV_SCALE_F32(InFmt_VOP3_SDST_ENC*);
+ ~Inst_VOP3__V_DIV_SCALE_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 2; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ case 4: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ case 4: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ case 4: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_DIV_SCALE_F32
+
+ class Inst_VOP3__V_DIV_SCALE_F64 : public Inst_VOP3_SDST_ENC
+ {
+ public:
+ Inst_VOP3__V_DIV_SCALE_F64(InFmt_VOP3_SDST_ENC*);
+ ~Inst_VOP3__V_DIV_SCALE_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 2; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //src_2
+ return 8;
+ case 3: //vdst
+ return 8;
+ case 4: //vcc
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ case 4: //vcc
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ case 4: //vcc
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_DIV_SCALE_F64
+
+ class Inst_VOP3__V_DIV_FMAS_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_DIV_FMAS_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_DIV_FMAS_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3:
+ return 8;
+ case 4: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3:
+ return true;
+ case 4: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3:
+ return false;
+ case 4: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_DIV_FMAS_F32
+
+ class Inst_VOP3__V_DIV_FMAS_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_DIV_FMAS_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_DIV_FMAS_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //src_2
+ return 8;
+ case 3: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_DIV_FMAS_F64
+
+ class Inst_VOP3__V_MSAD_U8 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MSAD_U8(InFmt_VOP3*);
+ ~Inst_VOP3__V_MSAD_U8();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MSAD_U8
+
+ class Inst_VOP3__V_QSAD_PK_U16_U8 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_QSAD_PK_U16_U8(InFmt_VOP3*);
+ ~Inst_VOP3__V_QSAD_PK_U16_U8();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 8;
+ case 3: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_QSAD_PK_U16_U8
+
+ class Inst_VOP3__V_MQSAD_PK_U16_U8 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MQSAD_PK_U16_U8(InFmt_VOP3*);
+ ~Inst_VOP3__V_MQSAD_PK_U16_U8();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 8;
+ case 3: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MQSAD_PK_U16_U8
+
+ class Inst_VOP3__V_MQSAD_U32_U8 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MQSAD_U32_U8(InFmt_VOP3*);
+ ~Inst_VOP3__V_MQSAD_U32_U8();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 16;
+ case 3: //vdst
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MQSAD_U32_U8
+
+ class Inst_VOP3__V_MAD_U64_U32 : public Inst_VOP3_SDST_ENC
+ {
+ public:
+ Inst_VOP3__V_MAD_U64_U32(InFmt_VOP3_SDST_ENC*);
+ ~Inst_VOP3__V_MAD_U64_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 2; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ case 4: //carryout
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ case 4: //carryout
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ case 4: //carryout
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MAD_U64_U32
+
+ class Inst_VOP3__V_MAD_I64_I32 : public Inst_VOP3_SDST_ENC
+ {
+ public:
+ Inst_VOP3__V_MAD_I64_I32(InFmt_VOP3_SDST_ENC*);
+ ~Inst_VOP3__V_MAD_I64_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 2; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ case 4: //carryout
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ case 4: //carryout
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ case 4: //carryout
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MAD_I64_I32
+
+ class Inst_VOP3__V_MAD_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MAD_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_MAD_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //src_2
+ return 2;
+ case 3: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MAD_F16
+
+ class Inst_VOP3__V_MAD_U16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MAD_U16(InFmt_VOP3*);
+ ~Inst_VOP3__V_MAD_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //src_2
+ return 2;
+ case 3: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MAD_U16
+
+ class Inst_VOP3__V_MAD_I16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MAD_I16(InFmt_VOP3*);
+ ~Inst_VOP3__V_MAD_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //src_2
+ return 2;
+ case 3: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MAD_I16
+
+ class Inst_VOP3__V_PERM_B32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_PERM_B32(InFmt_VOP3*);
+ ~Inst_VOP3__V_PERM_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //src_2
+ return 4;
+ case 3: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ // From the GCN3 ISA SPEC:
+ // byte permute(byte in[8], byte sel) {
+ // if (sel>=13) then return 0xff;
+ // elsif (sel==12) then return 0x00;
+ // elsif (sel==11) then return in[7][7] * 0xff;
+ // elsif (sel==10) then return in[5][7] * 0xff;
+ // elsif (sel==9) then return in[3][7] * 0xff;
+ // elsif (sel==8) then return in[1][7] * 0xff;
+ // else return in[sel];
+ // }
+ // NOTE: I interpret the in[x][7] notation to mean "the high order
+ // bit of byte x".
+ uint8_t
+ permute(uint64_t in_dword2x, uint32_t sel)
+ {
+ assert (sel < 256);
+ uint8_t *in = reinterpret_cast<uint8_t*>(&in_dword2x);
+ DPRINTF(GCN3, "in_dword2x = 0x%08x\n", in_dword2x);
+ DPRINTF(GCN3, "Selecting %x using index %d\n", in[sel], sel);
+ if (sel >= 13) return 0xFF;
+ else if (sel == 12) return 0;
+ else if (sel == 11) return (in[7] & 0x80) ? 0xFF : 0;
+ else if (sel == 10) return (in[5] & 0x80) ? 0xFF : 0;
+ else if (sel == 9) return (in[3] & 0x80) ? 0xFF : 0;
+ else if (sel == 8) return (in[1] & 0x80) ? 0xFF : 0;
+ else return in[sel];
+ }
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_PERM_B32
+
+ class Inst_VOP3__V_FMA_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_FMA_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_FMA_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //src_2
+ return 2;
+ case 3: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_FMA_F16
+
+ class Inst_VOP3__V_DIV_FIXUP_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_DIV_FIXUP_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_DIV_FIXUP_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 2;
+ case 1: //src_1
+ return 2;
+ case 2: //src_2
+ return 2;
+ case 3: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //src_2
+ return true;
+ case 3: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //src_2
+ return false;
+ case 3: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_DIV_FIXUP_F16
+
+ class Inst_VOP3__V_CVT_PKACCUM_U8_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_PKACCUM_U8_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_PKACCUM_U8_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_PKACCUM_U8_F32
+
+ class Inst_VOP3__V_INTERP_P1_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_INTERP_P1_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_INTERP_P1_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_ij
+ return 4;
+ case 1: //attr
+ return 32;
+ case 2: //vgpr_dst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_ij
+ return true;
+ case 1: //attr
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_ij
+ return false;
+ case 1: //attr
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_INTERP_P1_F32
+
+ class Inst_VOP3__V_INTERP_P2_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_INTERP_P2_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_INTERP_P2_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_ij
+ return 4;
+ case 1: //attr
+ return 32;
+ case 2: //vgpr_dst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_ij
+ return true;
+ case 1: //attr
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_ij
+ return false;
+ case 1: //attr
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_INTERP_P2_F32
+
+ class Inst_VOP3__V_INTERP_MOV_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_INTERP_MOV_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_INTERP_MOV_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //param
+ return 4;
+ case 1: //attr
+ return 32;
+ case 2: //vgpr_dst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //param
+ return true;
+ case 1: //attr
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //param
+ return false;
+ case 1: //attr
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_INTERP_MOV_F32
+
+ class Inst_VOP3__V_INTERP_P1LL_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_INTERP_P1LL_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_INTERP_P1LL_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_ij
+ return 4;
+ case 1: //attr
+ return 2;
+ case 2: //vgpr_dst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_ij
+ return true;
+ case 1: //attr
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_ij
+ return false;
+ case 1: //attr
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_INTERP_P1LL_F16
+
+ class Inst_VOP3__V_INTERP_P1LV_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_INTERP_P1LV_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_INTERP_P1LV_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_ij
+ return 4;
+ case 1: //attr
+ return 2;
+ case 2: //vgpr_add
+ return 2;
+ case 3: //vgpr_dst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_ij
+ return true;
+ case 1: //attr
+ return true;
+ case 2: //vgpr_add
+ return true;
+ case 3: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_ij
+ return false;
+ case 1: //attr
+ return false;
+ case 2: //vgpr_add
+ return false;
+ case 3: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_INTERP_P1LV_F16
+
+ class Inst_VOP3__V_INTERP_P2_F16 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_INTERP_P2_F16(InFmt_VOP3*);
+ ~Inst_VOP3__V_INTERP_P2_F16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_ij
+ return 4;
+ case 1: //attr
+ return 2;
+ case 2: //vgpr_add
+ return 4;
+ case 3: //vgpr_dst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_ij
+ return true;
+ case 1: //attr
+ return true;
+ case 2: //vgpr_add
+ return true;
+ case 3: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_ij
+ return false;
+ case 1: //attr
+ return false;
+ case 2: //vgpr_add
+ return false;
+ case 3: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_INTERP_P2_F16
+
+ class Inst_VOP3__V_ADD_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_ADD_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_ADD_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_ADD_F64
+
+ class Inst_VOP3__V_MUL_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MUL_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_MUL_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MUL_F64
+
+ class Inst_VOP3__V_MIN_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MIN_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_MIN_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MIN_F64
+
+ class Inst_VOP3__V_MAX_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MAX_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_MAX_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 8;
+ case 2: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MAX_F64
+
+ class Inst_VOP3__V_LDEXP_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_LDEXP_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_LDEXP_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_LDEXP_F64
+
+ class Inst_VOP3__V_MUL_LO_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MUL_LO_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MUL_LO_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MUL_LO_U32
+
+ class Inst_VOP3__V_MUL_HI_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MUL_HI_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MUL_HI_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MUL_HI_U32
+
+ class Inst_VOP3__V_MUL_HI_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MUL_HI_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MUL_HI_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MUL_HI_I32
+
+ class Inst_VOP3__V_LDEXP_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_LDEXP_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_LDEXP_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_LDEXP_F32
+
+ class Inst_VOP3__V_READLANE_B32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_READLANE_B32(InFmt_VOP3*);
+ ~Inst_VOP3__V_READLANE_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vsrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //sdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vsrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //sdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vsrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //sdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_READLANE_B32
+
+ class Inst_VOP3__V_WRITELANE_B32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_WRITELANE_B32(InFmt_VOP3*);
+ ~Inst_VOP3__V_WRITELANE_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return 4;
+ case 1: //ssrc_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return true;
+ case 1: //ssrc_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //ssrc_0
+ return false;
+ case 1: //ssrc_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_WRITELANE_B32
+
+ class Inst_VOP3__V_BCNT_U32_B32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_BCNT_U32_B32(InFmt_VOP3*);
+ ~Inst_VOP3__V_BCNT_U32_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_BCNT_U32_B32
+
+ class Inst_VOP3__V_MBCNT_LO_U32_B32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MBCNT_LO_U32_B32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MBCNT_LO_U32_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MBCNT_LO_U32_B32
+
+ class Inst_VOP3__V_MBCNT_HI_U32_B32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_MBCNT_HI_U32_B32(InFmt_VOP3*);
+ ~Inst_VOP3__V_MBCNT_HI_U32_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_MBCNT_HI_U32_B32
+
+ class Inst_VOP3__V_LSHLREV_B64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_LSHLREV_B64(InFmt_VOP3*);
+ ~Inst_VOP3__V_LSHLREV_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 8;
+ case 2: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_LSHLREV_B64
+
+ class Inst_VOP3__V_LSHRREV_B64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_LSHRREV_B64(InFmt_VOP3*);
+ ~Inst_VOP3__V_LSHRREV_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 8;
+ case 2: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_LSHRREV_B64
+
+ class Inst_VOP3__V_ASHRREV_I64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_ASHRREV_I64(InFmt_VOP3*);
+ ~Inst_VOP3__V_ASHRREV_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 8;
+ case 2: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_ASHRREV_I64
+
+ class Inst_VOP3__V_TRIG_PREOP_F64 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_TRIG_PREOP_F64(InFmt_VOP3*);
+ ~Inst_VOP3__V_TRIG_PREOP_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 8;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_TRIG_PREOP_F64
+
+ class Inst_VOP3__V_BFM_B32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_BFM_B32(InFmt_VOP3*);
+ ~Inst_VOP3__V_BFM_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_BFM_B32
+
+ class Inst_VOP3__V_CVT_PKNORM_I16_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_PKNORM_I16_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_PKNORM_I16_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_PKNORM_I16_F32
+
+ class Inst_VOP3__V_CVT_PKNORM_U16_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_PKNORM_U16_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_PKNORM_U16_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_PKNORM_U16_F32
+
+ class Inst_VOP3__V_CVT_PKRTZ_F16_F32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_PKRTZ_F16_F32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_PKRTZ_F16_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_PKRTZ_F16_F32
+
+ class Inst_VOP3__V_CVT_PK_U16_U32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_PK_U16_U32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_PK_U16_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_PK_U16_U32
+
+ class Inst_VOP3__V_CVT_PK_I16_I32 : public Inst_VOP3
+ {
+ public:
+ Inst_VOP3__V_CVT_PK_I16_I32(InFmt_VOP3*);
+ ~Inst_VOP3__V_CVT_PK_I16_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return 4;
+ case 1: //src_1
+ return 4;
+ case 2: //vdst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return true;
+ case 1: //src_1
+ return true;
+ case 2: //vdst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //src_0
+ return false;
+ case 1: //src_1
+ return false;
+ case 2: //vdst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_VOP3__V_CVT_PK_I16_I32
+
+ class Inst_DS__DS_ADD_U32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_ADD_U32(InFmt_DS*);
+ ~Inst_DS__DS_ADD_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_ADD_U32
+
+ class Inst_DS__DS_SUB_U32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_SUB_U32(InFmt_DS*);
+ ~Inst_DS__DS_SUB_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_SUB_U32
+
+ class Inst_DS__DS_RSUB_U32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_RSUB_U32(InFmt_DS*);
+ ~Inst_DS__DS_RSUB_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_RSUB_U32
+
+ class Inst_DS__DS_INC_U32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_INC_U32(InFmt_DS*);
+ ~Inst_DS__DS_INC_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_INC_U32
+
+ class Inst_DS__DS_DEC_U32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_DEC_U32(InFmt_DS*);
+ ~Inst_DS__DS_DEC_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_DEC_U32
+
+ class Inst_DS__DS_MIN_I32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MIN_I32(InFmt_DS*);
+ ~Inst_DS__DS_MIN_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MIN_I32
+
+ class Inst_DS__DS_MAX_I32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MAX_I32(InFmt_DS*);
+ ~Inst_DS__DS_MAX_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MAX_I32
+
+ class Inst_DS__DS_MIN_U32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MIN_U32(InFmt_DS*);
+ ~Inst_DS__DS_MIN_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MIN_U32
+
+ class Inst_DS__DS_MAX_U32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MAX_U32(InFmt_DS*);
+ ~Inst_DS__DS_MAX_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MAX_U32
+
+ class Inst_DS__DS_AND_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_AND_B32(InFmt_DS*);
+ ~Inst_DS__DS_AND_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_AND_B32
+
+ class Inst_DS__DS_OR_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_OR_B32(InFmt_DS*);
+ ~Inst_DS__DS_OR_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_OR_B32
+
+ class Inst_DS__DS_XOR_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_XOR_B32(InFmt_DS*);
+ ~Inst_DS__DS_XOR_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_XOR_B32
+
+ class Inst_DS__DS_MSKOR_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MSKOR_B32(InFmt_DS*);
+ ~Inst_DS__DS_MSKOR_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d1
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MSKOR_B32
+
+ class Inst_DS__DS_WRITE_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_WRITE_B32(InFmt_DS*);
+ ~Inst_DS__DS_WRITE_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_WRITE_B32
+
+ class Inst_DS__DS_WRITE2_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_WRITE2_B32(InFmt_DS*);
+ ~Inst_DS__DS_WRITE2_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ case 2: //vgpr_d1
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_d1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_d1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_WRITE2_B32
+
+ class Inst_DS__DS_WRITE2ST64_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_WRITE2ST64_B32(InFmt_DS*);
+ ~Inst_DS__DS_WRITE2ST64_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ case 2: //vgpr_d1
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_d1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_d1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_WRITE2ST64_B32
+
+ class Inst_DS__DS_CMPST_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_CMPST_B32(InFmt_DS*);
+ ~Inst_DS__DS_CMPST_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d1
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_CMPST_B32
+
+ class Inst_DS__DS_CMPST_F32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_CMPST_F32(InFmt_DS*);
+ ~Inst_DS__DS_CMPST_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d1
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_CMPST_F32
+
+ class Inst_DS__DS_MIN_F32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MIN_F32(InFmt_DS*);
+ ~Inst_DS__DS_MIN_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MIN_F32
+
+ class Inst_DS__DS_MAX_F32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MAX_F32(InFmt_DS*);
+ ~Inst_DS__DS_MAX_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MAX_F32
+
+ class Inst_DS__DS_NOP : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_NOP(InFmt_DS*);
+ ~Inst_DS__DS_NOP();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_NOP
+
+ class Inst_DS__DS_ADD_F32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_ADD_F32(InFmt_DS*);
+ ~Inst_DS__DS_ADD_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_ADD_F32
+
+ class Inst_DS__DS_WRITE_B8 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_WRITE_B8(InFmt_DS*);
+ ~Inst_DS__DS_WRITE_B8();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 1;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_WRITE_B8
+
+ class Inst_DS__DS_WRITE_B16 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_WRITE_B16(InFmt_DS*);
+ ~Inst_DS__DS_WRITE_B16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_WRITE_B16
+
+ class Inst_DS__DS_ADD_RTN_U32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_ADD_RTN_U32(InFmt_DS*);
+ ~Inst_DS__DS_ADD_RTN_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_ADD_RTN_U32
+
+ class Inst_DS__DS_SUB_RTN_U32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_SUB_RTN_U32(InFmt_DS*);
+ ~Inst_DS__DS_SUB_RTN_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_SUB_RTN_U32
+
+ class Inst_DS__DS_RSUB_RTN_U32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_RSUB_RTN_U32(InFmt_DS*);
+ ~Inst_DS__DS_RSUB_RTN_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_RSUB_RTN_U32
+
+ class Inst_DS__DS_INC_RTN_U32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_INC_RTN_U32(InFmt_DS*);
+ ~Inst_DS__DS_INC_RTN_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_INC_RTN_U32
+
+ class Inst_DS__DS_DEC_RTN_U32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_DEC_RTN_U32(InFmt_DS*);
+ ~Inst_DS__DS_DEC_RTN_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_DEC_RTN_U32
+
+ class Inst_DS__DS_MIN_RTN_I32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MIN_RTN_I32(InFmt_DS*);
+ ~Inst_DS__DS_MIN_RTN_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MIN_RTN_I32
+
+ class Inst_DS__DS_MAX_RTN_I32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MAX_RTN_I32(InFmt_DS*);
+ ~Inst_DS__DS_MAX_RTN_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MAX_RTN_I32
+
+ class Inst_DS__DS_MIN_RTN_U32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MIN_RTN_U32(InFmt_DS*);
+ ~Inst_DS__DS_MIN_RTN_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MIN_RTN_U32
+
+ class Inst_DS__DS_MAX_RTN_U32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MAX_RTN_U32(InFmt_DS*);
+ ~Inst_DS__DS_MAX_RTN_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MAX_RTN_U32
+
+ class Inst_DS__DS_AND_RTN_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_AND_RTN_B32(InFmt_DS*);
+ ~Inst_DS__DS_AND_RTN_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_AND_RTN_B32
+
+ class Inst_DS__DS_OR_RTN_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_OR_RTN_B32(InFmt_DS*);
+ ~Inst_DS__DS_OR_RTN_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_OR_RTN_B32
+
+ class Inst_DS__DS_XOR_RTN_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_XOR_RTN_B32(InFmt_DS*);
+ ~Inst_DS__DS_XOR_RTN_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_XOR_RTN_B32
+
+ class Inst_DS__DS_MSKOR_RTN_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MSKOR_RTN_B32(InFmt_DS*);
+ ~Inst_DS__DS_MSKOR_RTN_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d1
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d1
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d1
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MSKOR_RTN_B32
+
+ class Inst_DS__DS_WRXCHG_RTN_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_WRXCHG_RTN_B32(InFmt_DS*);
+ ~Inst_DS__DS_WRXCHG_RTN_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_WRXCHG_RTN_B32
+
+ class Inst_DS__DS_WRXCHG2_RTN_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_WRXCHG2_RTN_B32(InFmt_DS*);
+ ~Inst_DS__DS_WRXCHG2_RTN_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d1
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d1
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d1
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_WRXCHG2_RTN_B32
+
+ class Inst_DS__DS_WRXCHG2ST64_RTN_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_WRXCHG2ST64_RTN_B32(InFmt_DS*);
+ ~Inst_DS__DS_WRXCHG2ST64_RTN_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d1
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d1
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d1
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_WRXCHG2ST64_RTN_B32
+
+ class Inst_DS__DS_CMPST_RTN_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_CMPST_RTN_B32(InFmt_DS*);
+ ~Inst_DS__DS_CMPST_RTN_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d1
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d1
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d1
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_CMPST_RTN_B32
+
+ class Inst_DS__DS_CMPST_RTN_F32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_CMPST_RTN_F32(InFmt_DS*);
+ ~Inst_DS__DS_CMPST_RTN_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d1
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d1
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d1
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_CMPST_RTN_F32
+
+ class Inst_DS__DS_MIN_RTN_F32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MIN_RTN_F32(InFmt_DS*);
+ ~Inst_DS__DS_MIN_RTN_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MIN_RTN_F32
+
+ class Inst_DS__DS_MAX_RTN_F32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MAX_RTN_F32(InFmt_DS*);
+ ~Inst_DS__DS_MAX_RTN_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MAX_RTN_F32
+
+ class Inst_DS__DS_WRAP_RTN_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_WRAP_RTN_B32(InFmt_DS*);
+ ~Inst_DS__DS_WRAP_RTN_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d1
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d1
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d1
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_WRAP_RTN_B32
+
+ class Inst_DS__DS_ADD_RTN_F32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_ADD_RTN_F32(InFmt_DS*);
+ ~Inst_DS__DS_ADD_RTN_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_ADD_RTN_F32
+
+ class Inst_DS__DS_READ_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_READ_B32(InFmt_DS*);
+ ~Inst_DS__DS_READ_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_READ_B32
+
+ class Inst_DS__DS_READ2_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_READ2_B32(InFmt_DS*);
+ ~Inst_DS__DS_READ2_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_READ2_B32
+
+ class Inst_DS__DS_READ2ST64_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_READ2ST64_B32(InFmt_DS*);
+ ~Inst_DS__DS_READ2ST64_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_READ2ST64_B32
+
+ class Inst_DS__DS_READ_I8 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_READ_I8(InFmt_DS*);
+ ~Inst_DS__DS_READ_I8();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_rtn
+ return 1;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_READ_I8
+
+ class Inst_DS__DS_READ_U8 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_READ_U8(InFmt_DS*);
+ ~Inst_DS__DS_READ_U8();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_rtn
+ return 1;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_READ_U8
+
+ class Inst_DS__DS_READ_I16 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_READ_I16(InFmt_DS*);
+ ~Inst_DS__DS_READ_I16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_rtn
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_READ_I16
+
+ class Inst_DS__DS_READ_U16 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_READ_U16(InFmt_DS*);
+ ~Inst_DS__DS_READ_U16();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_rtn
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_READ_U16
+
+ class Inst_DS__DS_SWIZZLE_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_SWIZZLE_B32(InFmt_DS*);
+ ~Inst_DS__DS_SWIZZLE_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_SWIZZLE_B32
+
+ class Inst_DS__DS_PERMUTE_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_PERMUTE_B32(InFmt_DS*);
+ ~Inst_DS__DS_PERMUTE_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_PERMUTE_B32
+
+ class Inst_DS__DS_BPERMUTE_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_BPERMUTE_B32(InFmt_DS*);
+ ~Inst_DS__DS_BPERMUTE_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ case 2: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_BPERMUTE_B32
+
+ class Inst_DS__DS_ADD_U64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_ADD_U64(InFmt_DS*);
+ ~Inst_DS__DS_ADD_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_ADD_U64
+
+ class Inst_DS__DS_SUB_U64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_SUB_U64(InFmt_DS*);
+ ~Inst_DS__DS_SUB_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_SUB_U64
+
+ class Inst_DS__DS_RSUB_U64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_RSUB_U64(InFmt_DS*);
+ ~Inst_DS__DS_RSUB_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_RSUB_U64
+
+ class Inst_DS__DS_INC_U64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_INC_U64(InFmt_DS*);
+ ~Inst_DS__DS_INC_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_INC_U64
+
+ class Inst_DS__DS_DEC_U64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_DEC_U64(InFmt_DS*);
+ ~Inst_DS__DS_DEC_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_DEC_U64
+
+ class Inst_DS__DS_MIN_I64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MIN_I64(InFmt_DS*);
+ ~Inst_DS__DS_MIN_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MIN_I64
+
+ class Inst_DS__DS_MAX_I64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MAX_I64(InFmt_DS*);
+ ~Inst_DS__DS_MAX_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MAX_I64
+
+ class Inst_DS__DS_MIN_U64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MIN_U64(InFmt_DS*);
+ ~Inst_DS__DS_MIN_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MIN_U64
+
+ class Inst_DS__DS_MAX_U64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MAX_U64(InFmt_DS*);
+ ~Inst_DS__DS_MAX_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MAX_U64
+
+ class Inst_DS__DS_AND_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_AND_B64(InFmt_DS*);
+ ~Inst_DS__DS_AND_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_AND_B64
+
+ class Inst_DS__DS_OR_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_OR_B64(InFmt_DS*);
+ ~Inst_DS__DS_OR_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_OR_B64
+
+ class Inst_DS__DS_XOR_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_XOR_B64(InFmt_DS*);
+ ~Inst_DS__DS_XOR_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_XOR_B64
+
+ class Inst_DS__DS_MSKOR_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MSKOR_B64(InFmt_DS*);
+ ~Inst_DS__DS_MSKOR_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d1
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MSKOR_B64
+
+ class Inst_DS__DS_WRITE_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_WRITE_B64(InFmt_DS*);
+ ~Inst_DS__DS_WRITE_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_WRITE_B64
+
+ class Inst_DS__DS_WRITE2_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_WRITE2_B64(InFmt_DS*);
+ ~Inst_DS__DS_WRITE2_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ case 2: //vgpr_d1
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_d1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_d1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_WRITE2_B64
+
+ class Inst_DS__DS_WRITE2ST64_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_WRITE2ST64_B64(InFmt_DS*);
+ ~Inst_DS__DS_WRITE2ST64_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d1
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_WRITE2ST64_B64
+
+ class Inst_DS__DS_CMPST_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_CMPST_B64(InFmt_DS*);
+ ~Inst_DS__DS_CMPST_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d1
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_CMPST_B64
+
+ class Inst_DS__DS_CMPST_F64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_CMPST_F64(InFmt_DS*);
+ ~Inst_DS__DS_CMPST_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d1
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d1
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d1
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_CMPST_F64
+
+ class Inst_DS__DS_MIN_F64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MIN_F64(InFmt_DS*);
+ ~Inst_DS__DS_MIN_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MIN_F64
+
+ class Inst_DS__DS_MAX_F64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MAX_F64(InFmt_DS*);
+ ~Inst_DS__DS_MAX_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MAX_F64
+
+ class Inst_DS__DS_ADD_RTN_U64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_ADD_RTN_U64(InFmt_DS*);
+ ~Inst_DS__DS_ADD_RTN_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ case 2: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_ADD_RTN_U64
+
+ class Inst_DS__DS_SUB_RTN_U64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_SUB_RTN_U64(InFmt_DS*);
+ ~Inst_DS__DS_SUB_RTN_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ case 2: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_SUB_RTN_U64
+
+ class Inst_DS__DS_RSUB_RTN_U64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_RSUB_RTN_U64(InFmt_DS*);
+ ~Inst_DS__DS_RSUB_RTN_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ case 2: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_RSUB_RTN_U64
+
+ class Inst_DS__DS_INC_RTN_U64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_INC_RTN_U64(InFmt_DS*);
+ ~Inst_DS__DS_INC_RTN_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ case 2: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_INC_RTN_U64
+
+ class Inst_DS__DS_DEC_RTN_U64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_DEC_RTN_U64(InFmt_DS*);
+ ~Inst_DS__DS_DEC_RTN_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ case 2: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_DEC_RTN_U64
+
+ class Inst_DS__DS_MIN_RTN_I64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MIN_RTN_I64(InFmt_DS*);
+ ~Inst_DS__DS_MIN_RTN_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ case 2: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MIN_RTN_I64
+
+ class Inst_DS__DS_MAX_RTN_I64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MAX_RTN_I64(InFmt_DS*);
+ ~Inst_DS__DS_MAX_RTN_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ case 2: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MAX_RTN_I64
+
+ class Inst_DS__DS_MIN_RTN_U64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MIN_RTN_U64(InFmt_DS*);
+ ~Inst_DS__DS_MIN_RTN_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ case 2: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MIN_RTN_U64
+
+ class Inst_DS__DS_MAX_RTN_U64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MAX_RTN_U64(InFmt_DS*);
+ ~Inst_DS__DS_MAX_RTN_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ case 2: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MAX_RTN_U64
+
+ class Inst_DS__DS_AND_RTN_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_AND_RTN_B64(InFmt_DS*);
+ ~Inst_DS__DS_AND_RTN_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ case 2: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_AND_RTN_B64
+
+ class Inst_DS__DS_OR_RTN_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_OR_RTN_B64(InFmt_DS*);
+ ~Inst_DS__DS_OR_RTN_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ case 2: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_OR_RTN_B64
+
+ class Inst_DS__DS_XOR_RTN_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_XOR_RTN_B64(InFmt_DS*);
+ ~Inst_DS__DS_XOR_RTN_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ case 2: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_XOR_RTN_B64
+
+ class Inst_DS__DS_MSKOR_RTN_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MSKOR_RTN_B64(InFmt_DS*);
+ ~Inst_DS__DS_MSKOR_RTN_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d1
+ return 8;
+ case 2: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d1
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d1
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MSKOR_RTN_B64
+
+ class Inst_DS__DS_WRXCHG_RTN_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_WRXCHG_RTN_B64(InFmt_DS*);
+ ~Inst_DS__DS_WRXCHG_RTN_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ case 2: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_WRXCHG_RTN_B64
+
+ class Inst_DS__DS_WRXCHG2_RTN_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_WRXCHG2_RTN_B64(InFmt_DS*);
+ ~Inst_DS__DS_WRXCHG2_RTN_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d1
+ return 8;
+ case 2: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d1
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d1
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_WRXCHG2_RTN_B64
+
+ class Inst_DS__DS_WRXCHG2ST64_RTN_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_WRXCHG2ST64_RTN_B64(InFmt_DS*);
+ ~Inst_DS__DS_WRXCHG2ST64_RTN_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d1
+ return 8;
+ case 2: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d1
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d1
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_WRXCHG2ST64_RTN_B64
+
+ class Inst_DS__DS_CMPST_RTN_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_CMPST_RTN_B64(InFmt_DS*);
+ ~Inst_DS__DS_CMPST_RTN_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d1
+ return 8;
+ case 2: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d1
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d1
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_CMPST_RTN_B64
+
+ class Inst_DS__DS_CMPST_RTN_F64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_CMPST_RTN_F64(InFmt_DS*);
+ ~Inst_DS__DS_CMPST_RTN_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d1
+ return 8;
+ case 2: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d1
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d1
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_CMPST_RTN_F64
+
+ class Inst_DS__DS_MIN_RTN_F64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MIN_RTN_F64(InFmt_DS*);
+ ~Inst_DS__DS_MIN_RTN_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ case 2: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MIN_RTN_F64
+
+ class Inst_DS__DS_MAX_RTN_F64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MAX_RTN_F64(InFmt_DS*);
+ ~Inst_DS__DS_MAX_RTN_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ case 2: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MAX_RTN_F64
+
+ class Inst_DS__DS_READ_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_READ_B64(InFmt_DS*);
+ ~Inst_DS__DS_READ_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_READ_B64
+
+ class Inst_DS__DS_READ2_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_READ2_B64(InFmt_DS*);
+ ~Inst_DS__DS_READ2_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_rtn
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_READ2_B64
+
+ class Inst_DS__DS_READ2ST64_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_READ2ST64_B64(InFmt_DS*);
+ ~Inst_DS__DS_READ2ST64_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_READ2ST64_B64
+
+ class Inst_DS__DS_CONDXCHG32_RTN_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_CONDXCHG32_RTN_B64(InFmt_DS*);
+ ~Inst_DS__DS_CONDXCHG32_RTN_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 8;
+ case 2: //vgpr_rtn
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ case 2: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ case 2: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_CONDXCHG32_RTN_B64
+
+ class Inst_DS__DS_ADD_SRC2_U32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_ADD_SRC2_U32(InFmt_DS*);
+ ~Inst_DS__DS_ADD_SRC2_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_ADD_SRC2_U32
+
+ class Inst_DS__DS_SUB_SRC2_U32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_SUB_SRC2_U32(InFmt_DS*);
+ ~Inst_DS__DS_SUB_SRC2_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_SUB_SRC2_U32
+
+ class Inst_DS__DS_RSUB_SRC2_U32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_RSUB_SRC2_U32(InFmt_DS*);
+ ~Inst_DS__DS_RSUB_SRC2_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_RSUB_SRC2_U32
+
+ class Inst_DS__DS_INC_SRC2_U32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_INC_SRC2_U32(InFmt_DS*);
+ ~Inst_DS__DS_INC_SRC2_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_INC_SRC2_U32
+
+ class Inst_DS__DS_DEC_SRC2_U32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_DEC_SRC2_U32(InFmt_DS*);
+ ~Inst_DS__DS_DEC_SRC2_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_DEC_SRC2_U32
+
+ class Inst_DS__DS_MIN_SRC2_I32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MIN_SRC2_I32(InFmt_DS*);
+ ~Inst_DS__DS_MIN_SRC2_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MIN_SRC2_I32
+
+ class Inst_DS__DS_MAX_SRC2_I32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MAX_SRC2_I32(InFmt_DS*);
+ ~Inst_DS__DS_MAX_SRC2_I32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MAX_SRC2_I32
+
+ class Inst_DS__DS_MIN_SRC2_U32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MIN_SRC2_U32(InFmt_DS*);
+ ~Inst_DS__DS_MIN_SRC2_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MIN_SRC2_U32
+
+ class Inst_DS__DS_MAX_SRC2_U32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MAX_SRC2_U32(InFmt_DS*);
+ ~Inst_DS__DS_MAX_SRC2_U32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MAX_SRC2_U32
+
+ class Inst_DS__DS_AND_SRC2_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_AND_SRC2_B32(InFmt_DS*);
+ ~Inst_DS__DS_AND_SRC2_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_AND_SRC2_B32
+
+ class Inst_DS__DS_OR_SRC2_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_OR_SRC2_B32(InFmt_DS*);
+ ~Inst_DS__DS_OR_SRC2_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_OR_SRC2_B32
+
+ class Inst_DS__DS_XOR_SRC2_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_XOR_SRC2_B32(InFmt_DS*);
+ ~Inst_DS__DS_XOR_SRC2_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_XOR_SRC2_B32
+
+ class Inst_DS__DS_WRITE_SRC2_B32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_WRITE_SRC2_B32(InFmt_DS*);
+ ~Inst_DS__DS_WRITE_SRC2_B32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_WRITE_SRC2_B32
+
+ class Inst_DS__DS_MIN_SRC2_F32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MIN_SRC2_F32(InFmt_DS*);
+ ~Inst_DS__DS_MIN_SRC2_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MIN_SRC2_F32
+
+ class Inst_DS__DS_MAX_SRC2_F32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MAX_SRC2_F32(InFmt_DS*);
+ ~Inst_DS__DS_MAX_SRC2_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MAX_SRC2_F32
+
+ class Inst_DS__DS_ADD_SRC2_F32 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_ADD_SRC2_F32(InFmt_DS*);
+ ~Inst_DS__DS_ADD_SRC2_F32();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_ADD_SRC2_F32
+
+ class Inst_DS__DS_GWS_SEMA_RELEASE_ALL : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_GWS_SEMA_RELEASE_ALL(InFmt_DS*);
+ ~Inst_DS__DS_GWS_SEMA_RELEASE_ALL();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_GWS_SEMA_RELEASE_ALL
+
+ class Inst_DS__DS_GWS_INIT : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_GWS_INIT(InFmt_DS*);
+ ~Inst_DS__DS_GWS_INIT();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d0
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d0
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d0
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_GWS_INIT
+
+ class Inst_DS__DS_GWS_SEMA_V : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_GWS_SEMA_V(InFmt_DS*);
+ ~Inst_DS__DS_GWS_SEMA_V();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_GWS_SEMA_V
+
+ class Inst_DS__DS_GWS_SEMA_BR : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_GWS_SEMA_BR(InFmt_DS*);
+ ~Inst_DS__DS_GWS_SEMA_BR();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d0
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d0
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d0
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_GWS_SEMA_BR
+
+ class Inst_DS__DS_GWS_SEMA_P : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_GWS_SEMA_P(InFmt_DS*);
+ ~Inst_DS__DS_GWS_SEMA_P();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_GWS_SEMA_P
+
+ class Inst_DS__DS_GWS_BARRIER : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_GWS_BARRIER(InFmt_DS*);
+ ~Inst_DS__DS_GWS_BARRIER();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d0
+ return 4;
+ case 1: //vgpr_d0
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d0
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d0
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_GWS_BARRIER
+
+ class Inst_DS__DS_CONSUME : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_CONSUME(InFmt_DS*);
+ ~Inst_DS__DS_CONSUME();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_CONSUME
+
+ class Inst_DS__DS_APPEND : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_APPEND(InFmt_DS*);
+ ~Inst_DS__DS_APPEND();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_APPEND
+
+ class Inst_DS__DS_ORDERED_COUNT : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_ORDERED_COUNT(InFmt_DS*);
+ ~Inst_DS__DS_ORDERED_COUNT();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_rtn
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_ORDERED_COUNT
+
+ class Inst_DS__DS_ADD_SRC2_U64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_ADD_SRC2_U64(InFmt_DS*);
+ ~Inst_DS__DS_ADD_SRC2_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_ADD_SRC2_U64
+
+ class Inst_DS__DS_SUB_SRC2_U64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_SUB_SRC2_U64(InFmt_DS*);
+ ~Inst_DS__DS_SUB_SRC2_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_SUB_SRC2_U64
+
+ class Inst_DS__DS_RSUB_SRC2_U64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_RSUB_SRC2_U64(InFmt_DS*);
+ ~Inst_DS__DS_RSUB_SRC2_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_RSUB_SRC2_U64
+
+ class Inst_DS__DS_INC_SRC2_U64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_INC_SRC2_U64(InFmt_DS*);
+ ~Inst_DS__DS_INC_SRC2_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_INC_SRC2_U64
+
+ class Inst_DS__DS_DEC_SRC2_U64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_DEC_SRC2_U64(InFmt_DS*);
+ ~Inst_DS__DS_DEC_SRC2_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_DEC_SRC2_U64
+
+ class Inst_DS__DS_MIN_SRC2_I64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MIN_SRC2_I64(InFmt_DS*);
+ ~Inst_DS__DS_MIN_SRC2_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MIN_SRC2_I64
+
+ class Inst_DS__DS_MAX_SRC2_I64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MAX_SRC2_I64(InFmt_DS*);
+ ~Inst_DS__DS_MAX_SRC2_I64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MAX_SRC2_I64
+
+ class Inst_DS__DS_MIN_SRC2_U64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MIN_SRC2_U64(InFmt_DS*);
+ ~Inst_DS__DS_MIN_SRC2_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MIN_SRC2_U64
+
+ class Inst_DS__DS_MAX_SRC2_U64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MAX_SRC2_U64(InFmt_DS*);
+ ~Inst_DS__DS_MAX_SRC2_U64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MAX_SRC2_U64
+
+ class Inst_DS__DS_AND_SRC2_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_AND_SRC2_B64(InFmt_DS*);
+ ~Inst_DS__DS_AND_SRC2_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_AND_SRC2_B64
+
+ class Inst_DS__DS_OR_SRC2_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_OR_SRC2_B64(InFmt_DS*);
+ ~Inst_DS__DS_OR_SRC2_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_OR_SRC2_B64
+
+ class Inst_DS__DS_XOR_SRC2_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_XOR_SRC2_B64(InFmt_DS*);
+ ~Inst_DS__DS_XOR_SRC2_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_XOR_SRC2_B64
+
+ class Inst_DS__DS_WRITE_SRC2_B64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_WRITE_SRC2_B64(InFmt_DS*);
+ ~Inst_DS__DS_WRITE_SRC2_B64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_WRITE_SRC2_B64
+
+ class Inst_DS__DS_MIN_SRC2_F64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MIN_SRC2_F64(InFmt_DS*);
+ ~Inst_DS__DS_MIN_SRC2_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MIN_SRC2_F64
+
+ class Inst_DS__DS_MAX_SRC2_F64 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_MAX_SRC2_F64(InFmt_DS*);
+ ~Inst_DS__DS_MAX_SRC2_F64();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_MAX_SRC2_F64
+
+ class Inst_DS__DS_WRITE_B96 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_WRITE_B96(InFmt_DS*);
+ ~Inst_DS__DS_WRITE_B96();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 12;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_WRITE_B96
+
+ class Inst_DS__DS_WRITE_B128 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_WRITE_B128(InFmt_DS*);
+ ~Inst_DS__DS_WRITE_B128();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_d0
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_d0
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_d0
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_WRITE_B128
+
+ class Inst_DS__DS_READ_B96 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_READ_B96(InFmt_DS*);
+ ~Inst_DS__DS_READ_B96();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_rtn
+ return 12;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_READ_B96
+
+ class Inst_DS__DS_READ_B128 : public Inst_DS
+ {
+ public:
+ Inst_DS__DS_READ_B128(InFmt_DS*);
+ ~Inst_DS__DS_READ_B128();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //vgpr_rtn
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //vgpr_rtn
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //vgpr_rtn
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_DS__DS_READ_B128
+
+ class Inst_MUBUF__BUFFER_LOAD_FORMAT_X : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_X(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_LOAD_FORMAT_X();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 4;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_LOAD_FORMAT_X
+
+ class Inst_MUBUF__BUFFER_LOAD_FORMAT_XY : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_XY(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_LOAD_FORMAT_XY();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 4;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_LOAD_FORMAT_XY
+
+ class Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 4;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 12;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ
+
+ class Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 4;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW
+
+ class Inst_MUBUF__BUFFER_STORE_FORMAT_X : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_STORE_FORMAT_X(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_STORE_FORMAT_X();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return 4;
+ case 1: //vgpr_a
+ return 8;
+ case 2: //sgpr_r
+ return 4;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_STORE_FORMAT_X
+
+ class Inst_MUBUF__BUFFER_STORE_FORMAT_XY : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_STORE_FORMAT_XY(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_STORE_FORMAT_XY();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return 8;
+ case 1: //vgpr_a
+ return 8;
+ case 2: //sgpr_r
+ return 4;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_STORE_FORMAT_XY
+
+ class Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return 12;
+ case 1: //vgpr_a
+ return 8;
+ case 2: //sgpr_r
+ return 4;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ
+
+ class Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return 16;
+ case 1: //vgpr_a
+ return 8;
+ case 2: //sgpr_r
+ return 4;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW
+
+ class Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 4;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X
+
+ class Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 4;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
+
+ class Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 4;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 12;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
+
+ class Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 4;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
+
+ class Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return 4;
+ case 1: //vgpr_a
+ return 8;
+ case 2: //sgpr_r
+ return 4;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X
+
+ class Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return 8;
+ case 1: //vgpr_a
+ return 8;
+ case 2: //sgpr_r
+ return 4;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY
+
+ class Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return 12;
+ case 1: //vgpr_a
+ return 8;
+ case 2: //sgpr_r
+ return 4;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
+
+ class Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return 16;
+ case 1: //vgpr_a
+ return 8;
+ case 2: //sgpr_r
+ return 4;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
+
+ class Inst_MUBUF__BUFFER_LOAD_UBYTE : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_LOAD_UBYTE(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_LOAD_UBYTE();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return 4;
+ case 1: //vgpr_a
+ if (instData.OFFEN && instData.IDXEN) {
+ // if we need an idx and offset from a
+ // VGPR, we'll read VGPR[VADDR] and
+ // VGPR[VADDR + 1], otherwise we just
+ // read VGPR[VADDR]
+ return 8;
+ } else {
+ return 4;
+ }
+ case 2: //sgpr_r
+ return 16;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return false;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return true;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_LOAD_UBYTE
+
+ class Inst_MUBUF__BUFFER_LOAD_SBYTE : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_LOAD_SBYTE(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_LOAD_SBYTE();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_LOAD_SBYTE
+
+ class Inst_MUBUF__BUFFER_LOAD_USHORT : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_LOAD_USHORT(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_LOAD_USHORT();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_LOAD_USHORT
+
+ class Inst_MUBUF__BUFFER_LOAD_SSHORT : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_LOAD_SSHORT(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_LOAD_SSHORT();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_LOAD_SSHORT
+
+ class Inst_MUBUF__BUFFER_LOAD_DWORD : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_LOAD_DWORD(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_LOAD_DWORD();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_LOAD_DWORD
+
+ class Inst_MUBUF__BUFFER_LOAD_DWORDX2 : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_LOAD_DWORDX2(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_LOAD_DWORDX2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_LOAD_DWORDX2
+
+ class Inst_MUBUF__BUFFER_LOAD_DWORDX3 : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_LOAD_DWORDX3(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_LOAD_DWORDX3();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 12;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_LOAD_DWORDX3
+
+ class Inst_MUBUF__BUFFER_LOAD_DWORDX4 : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_LOAD_DWORDX4(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_LOAD_DWORDX4();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_LOAD_DWORDX4
+
+ class Inst_MUBUF__BUFFER_STORE_BYTE : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_STORE_BYTE(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_STORE_BYTE();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return 4;
+ case 1: //vgpr_a
+ if (instData.OFFEN && instData.IDXEN) {
+ // if we need an idx and offset from a
+ // VGPR, we'll read VGPR[VADDR] and
+ // VGPR[VADDR + 1], otherwise we just
+ // read VGPR[VADDR]
+ return 8;
+ } else {
+ return 4;
+ }
+ case 2: //sgpr_r
+ return 16;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_STORE_BYTE
+
+ class Inst_MUBUF__BUFFER_STORE_SHORT : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_STORE_SHORT(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_STORE_SHORT();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return 4;
+ case 1: //vgpr_a
+ return 8;
+ case 2: //sgpr_r
+ return 16;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_STORE_SHORT
+
+ class Inst_MUBUF__BUFFER_STORE_DWORD : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_STORE_DWORD(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_STORE_DWORD();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return 4;
+ case 1: //vgpr_a
+ return 8;
+ case 2: //sgpr_r
+ return 16;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_STORE_DWORD
+
+ class Inst_MUBUF__BUFFER_STORE_DWORDX2 : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_STORE_DWORDX2(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_STORE_DWORDX2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return 8;
+ case 1: //vgpr_a
+ return 8;
+ case 2: //sgpr_r
+ return 16;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_STORE_DWORDX2
+
+ class Inst_MUBUF__BUFFER_STORE_DWORDX3 : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_STORE_DWORDX3(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_STORE_DWORDX3();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return 12;
+ case 1: //vgpr_a
+ return 8;
+ case 2: //sgpr_r
+ return 16;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_STORE_DWORDX3
+
+ class Inst_MUBUF__BUFFER_STORE_DWORDX4 : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_STORE_DWORDX4(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_STORE_DWORDX4();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return 16;
+ case 1: //vgpr_a
+ return 8;
+ case 2: //sgpr_r
+ return 16;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_s
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_STORE_DWORDX4
+
+ class Inst_MUBUF__BUFFER_STORE_LDS_DWORD : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_STORE_LDS_DWORD(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_STORE_LDS_DWORD();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_r
+ return 16;
+ case 1: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_r
+ return true;
+ case 1: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //sgpr_r
+ return false;
+ case 1: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_STORE_LDS_DWORD
+
+ class Inst_MUBUF__BUFFER_WBINVL1 : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_WBINVL1(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_WBINVL1();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_WBINVL1
+
+ class Inst_MUBUF__BUFFER_WBINVL1_VOL : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_WBINVL1_VOL(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_WBINVL1_VOL();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 0; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_WBINVL1_VOL
+
+ class Inst_MUBUF__BUFFER_ATOMIC_SWAP : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_SWAP(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_SWAP();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_SWAP
+
+ class Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP
+
+ class Inst_MUBUF__BUFFER_ATOMIC_ADD : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_ADD(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_ADD();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_ADD
+
+ class Inst_MUBUF__BUFFER_ATOMIC_SUB : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_SUB(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_SUB();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_SUB
+
+ class Inst_MUBUF__BUFFER_ATOMIC_SMIN : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_SMIN(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_SMIN();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_SMIN
+
+ class Inst_MUBUF__BUFFER_ATOMIC_UMIN : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_UMIN(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_UMIN();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_UMIN
+
+ class Inst_MUBUF__BUFFER_ATOMIC_SMAX : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_SMAX(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_SMAX();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_SMAX
+
+ class Inst_MUBUF__BUFFER_ATOMIC_UMAX : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_UMAX(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_UMAX();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_UMAX
+
+ class Inst_MUBUF__BUFFER_ATOMIC_AND : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_AND(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_AND();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_AND
+
+ class Inst_MUBUF__BUFFER_ATOMIC_OR : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_OR(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_OR();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_OR
+
+ class Inst_MUBUF__BUFFER_ATOMIC_XOR : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_XOR(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_XOR();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_XOR
+
+ class Inst_MUBUF__BUFFER_ATOMIC_INC : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_INC(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_INC();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_INC
+
+ class Inst_MUBUF__BUFFER_ATOMIC_DEC : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_DEC(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_DEC();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_DEC
+
+ class Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2 : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2
+
+ class Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2 : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
+
+ class Inst_MUBUF__BUFFER_ATOMIC_ADD_X2 : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_ADD_X2(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_ADD_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_ADD_X2
+
+ class Inst_MUBUF__BUFFER_ATOMIC_SUB_X2 : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_SUB_X2(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_SUB_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_SUB_X2
+
+ class Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2 : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2
+
+ class Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2 : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2
+
+ class Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2 : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2
+
+ class Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2 : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2
+
+ class Inst_MUBUF__BUFFER_ATOMIC_AND_X2 : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_AND_X2(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_AND_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_AND_X2
+
+ class Inst_MUBUF__BUFFER_ATOMIC_OR_X2 : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_OR_X2(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_OR_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_OR_X2
+
+ class Inst_MUBUF__BUFFER_ATOMIC_XOR_X2 : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_XOR_X2(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_XOR_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_XOR_X2
+
+ class Inst_MUBUF__BUFFER_ATOMIC_INC_X2 : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_INC_X2(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_INC_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_INC_X2
+
+ class Inst_MUBUF__BUFFER_ATOMIC_DEC_X2 : public Inst_MUBUF
+ {
+ public:
+ Inst_MUBUF__BUFFER_ATOMIC_DEC_X2(InFmt_MUBUF*);
+ ~Inst_MUBUF__BUFFER_ATOMIC_DEC_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 16;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MUBUF__BUFFER_ATOMIC_DEC_X2
+
+ class Inst_MTBUF__TBUFFER_LOAD_FORMAT_X : public Inst_MTBUF
+ {
+ public:
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_X(InFmt_MTBUF*);
+ ~Inst_MTBUF__TBUFFER_LOAD_FORMAT_X();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 4;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MTBUF__TBUFFER_LOAD_FORMAT_X
+
+ class Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY : public Inst_MTBUF
+ {
+ public:
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY(InFmt_MTBUF*);
+ ~Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 4;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY
+
+ class Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ : public Inst_MTBUF
+ {
+ public:
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ(InFmt_MTBUF*);
+ ~Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 4;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 12;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
+
+ class Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW : public Inst_MTBUF
+ {
+ public:
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW(InFmt_MTBUF*);
+ ~Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 4;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
+
+ class Inst_MTBUF__TBUFFER_STORE_FORMAT_X : public Inst_MTBUF
+ {
+ public:
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_X(InFmt_MTBUF*);
+ ~Inst_MTBUF__TBUFFER_STORE_FORMAT_X();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return 32;
+ case 1: //vgpr_a
+ return 8;
+ case 2: //sgpr_r
+ return 4;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MTBUF__TBUFFER_STORE_FORMAT_X
+
+ class Inst_MTBUF__TBUFFER_STORE_FORMAT_XY : public Inst_MTBUF
+ {
+ public:
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_XY(InFmt_MTBUF*);
+ ~Inst_MTBUF__TBUFFER_STORE_FORMAT_XY();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return 8;
+ case 1: //vgpr_a
+ return 8;
+ case 2: //sgpr_r
+ return 4;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MTBUF__TBUFFER_STORE_FORMAT_XY
+
+ class Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ : public Inst_MTBUF
+ {
+ public:
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ(InFmt_MTBUF*);
+ ~Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return 12;
+ case 1: //vgpr_a
+ return 8;
+ case 2: //sgpr_r
+ return 4;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ
+
+ class Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW : public Inst_MTBUF
+ {
+ public:
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW(InFmt_MTBUF*);
+ ~Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return 16;
+ case 1: //vgpr_a
+ return 8;
+ case 2: //sgpr_r
+ return 4;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW
+
+ class Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X : public Inst_MTBUF
+ {
+ public:
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X(InFmt_MTBUF*);
+ ~Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 4;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
+
+ class Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY : public Inst_MTBUF
+ {
+ public:
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY(InFmt_MTBUF*);
+ ~Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 4;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
+
+ class Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ : public Inst_MTBUF
+ {
+ public:
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ(InFmt_MTBUF*);
+ ~Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 4;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 12;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
+
+ class Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW : public Inst_MTBUF
+ {
+ public:
+ Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW(InFmt_MTBUF*);
+ ~Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 8;
+ case 1: //sgpr_r
+ return 4;
+ case 2: //sgpr_o
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_o
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_o
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
+
+ class Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X : public Inst_MTBUF
+ {
+ public:
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X(InFmt_MTBUF*);
+ ~Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return 32;
+ case 1: //vgpr_a
+ return 8;
+ case 2: //sgpr_r
+ return 4;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X
+
+ class Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY : public Inst_MTBUF
+ {
+ public:
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY(InFmt_MTBUF*);
+ ~Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return 8;
+ case 1: //vgpr_a
+ return 8;
+ case 2: //sgpr_r
+ return 4;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
+
+ class Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ : public Inst_MTBUF
+ {
+ public:
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ(InFmt_MTBUF*);
+ ~Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return 12;
+ case 1: //vgpr_a
+ return 8;
+ case 2: //sgpr_r
+ return 4;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
+
+ class Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW : public Inst_MTBUF
+ {
+ public:
+ Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW(InFmt_MTBUF*);
+ ~Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return 16;
+ case 1: //vgpr_a
+ return 8;
+ case 2: //sgpr_r
+ return 4;
+ case 3: //sgpr_o
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ case 3: //sgpr_o
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ case 3: //sgpr_o
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
+
+ class Inst_MIMG__IMAGE_LOAD : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_LOAD(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_LOAD();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 16;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_LOAD
+
+ class Inst_MIMG__IMAGE_LOAD_MIP : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_LOAD_MIP(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_LOAD_MIP();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 16;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_LOAD_MIP
+
+ class Inst_MIMG__IMAGE_LOAD_PCK : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_LOAD_PCK(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_LOAD_PCK();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 16;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_LOAD_PCK
+
+ class Inst_MIMG__IMAGE_LOAD_PCK_SGN : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_LOAD_PCK_SGN(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_LOAD_PCK_SGN();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 16;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_LOAD_PCK_SGN
+
+ class Inst_MIMG__IMAGE_LOAD_MIP_PCK : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_LOAD_MIP_PCK(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_LOAD_MIP_PCK();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 16;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_LOAD_MIP_PCK
+
+ class Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 16;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN
+
+ class Inst_MIMG__IMAGE_STORE : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_STORE(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_STORE();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return 16;
+ case 1: //vgpr_a
+ return 16;
+ case 2: //sgpr_r
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_STORE
+
+ class Inst_MIMG__IMAGE_STORE_MIP : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_STORE_MIP(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_STORE_MIP();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return 16;
+ case 1: //vgpr_a
+ return 16;
+ case 2: //sgpr_r
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_STORE_MIP
+
+ class Inst_MIMG__IMAGE_STORE_PCK : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_STORE_PCK(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_STORE_PCK();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return 16;
+ case 1: //vgpr_a
+ return 16;
+ case 2: //sgpr_r
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_STORE_PCK
+
+ class Inst_MIMG__IMAGE_STORE_MIP_PCK : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_STORE_MIP_PCK(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_STORE_MIP_PCK();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return 16;
+ case 1: //vgpr_a
+ return 16;
+ case 2: //sgpr_r
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return true;
+ case 1: //vgpr_a
+ return true;
+ case 2: //sgpr_r
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_d
+ return false;
+ case 1: //vgpr_a
+ return false;
+ case 2: //sgpr_r
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_STORE_MIP_PCK
+
+ class Inst_MIMG__IMAGE_GET_RESINFO : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GET_RESINFO(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GET_RESINFO();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 16;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GET_RESINFO
+
+ class Inst_MIMG__IMAGE_ATOMIC_SWAP : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_ATOMIC_SWAP(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_ATOMIC_SWAP();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 32;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_ATOMIC_SWAP
+
+ class Inst_MIMG__IMAGE_ATOMIC_CMPSWAP : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_ATOMIC_CMPSWAP(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_ATOMIC_CMPSWAP();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 32;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_ATOMIC_CMPSWAP
+
+ class Inst_MIMG__IMAGE_ATOMIC_ADD : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_ATOMIC_ADD(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_ATOMIC_ADD();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 32;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_ATOMIC_ADD
+
+ class Inst_MIMG__IMAGE_ATOMIC_SUB : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_ATOMIC_SUB(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_ATOMIC_SUB();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 32;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_ATOMIC_SUB
+
+ class Inst_MIMG__IMAGE_ATOMIC_SMIN : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_ATOMIC_SMIN(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_ATOMIC_SMIN();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 32;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_ATOMIC_SMIN
+
+ class Inst_MIMG__IMAGE_ATOMIC_UMIN : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_ATOMIC_UMIN(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_ATOMIC_UMIN();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 32;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_ATOMIC_UMIN
+
+ class Inst_MIMG__IMAGE_ATOMIC_SMAX : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_ATOMIC_SMAX(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_ATOMIC_SMAX();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 32;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_ATOMIC_SMAX
+
+ class Inst_MIMG__IMAGE_ATOMIC_UMAX : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_ATOMIC_UMAX(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_ATOMIC_UMAX();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 32;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_ATOMIC_UMAX
+
+ class Inst_MIMG__IMAGE_ATOMIC_AND : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_ATOMIC_AND(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_ATOMIC_AND();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 32;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_ATOMIC_AND
+
+ class Inst_MIMG__IMAGE_ATOMIC_OR : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_ATOMIC_OR(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_ATOMIC_OR();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 32;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_ATOMIC_OR
+
+ class Inst_MIMG__IMAGE_ATOMIC_XOR : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_ATOMIC_XOR(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_ATOMIC_XOR();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 32;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_ATOMIC_XOR
+
+ class Inst_MIMG__IMAGE_ATOMIC_INC : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_ATOMIC_INC(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_ATOMIC_INC();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 32;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_ATOMIC_INC
+
+ class Inst_MIMG__IMAGE_ATOMIC_DEC : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_ATOMIC_DEC(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_ATOMIC_DEC();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 32;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_ATOMIC_DEC
+
+ class Inst_MIMG__IMAGE_SAMPLE : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE
+
+ class Inst_MIMG__IMAGE_SAMPLE_CL : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_CL(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_CL();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_CL
+
+ class Inst_MIMG__IMAGE_SAMPLE_D : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_D(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_D();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_D
+
+ class Inst_MIMG__IMAGE_SAMPLE_D_CL : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_D_CL(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_D_CL();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_D_CL
+
+ class Inst_MIMG__IMAGE_SAMPLE_L : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_L(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_L();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_L
+
+ class Inst_MIMG__IMAGE_SAMPLE_B : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_B(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_B();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_B
+
+ class Inst_MIMG__IMAGE_SAMPLE_B_CL : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_B_CL(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_B_CL();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_B_CL
+
+ class Inst_MIMG__IMAGE_SAMPLE_LZ : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_LZ(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_LZ();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_LZ
+
+ class Inst_MIMG__IMAGE_SAMPLE_C : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_C(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_C();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_C
+
+ class Inst_MIMG__IMAGE_SAMPLE_C_CL : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_C_CL(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_C_CL();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_C_CL
+
+ class Inst_MIMG__IMAGE_SAMPLE_C_D : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_C_D(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_C_D();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_C_D
+
+ class Inst_MIMG__IMAGE_SAMPLE_C_D_CL : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_C_D_CL(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_C_D_CL();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_C_D_CL
+
+ class Inst_MIMG__IMAGE_SAMPLE_C_L : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_C_L(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_C_L();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_C_L
+
+ class Inst_MIMG__IMAGE_SAMPLE_C_B : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_C_B(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_C_B();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_C_B
+
+ class Inst_MIMG__IMAGE_SAMPLE_C_B_CL : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_C_B_CL(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_C_B_CL();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_C_B_CL
+
+ class Inst_MIMG__IMAGE_SAMPLE_C_LZ : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_C_LZ(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_C_LZ();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_C_LZ
+
+ class Inst_MIMG__IMAGE_SAMPLE_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_O
+
+ class Inst_MIMG__IMAGE_SAMPLE_CL_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_CL_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_CL_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_CL_O
+
+ class Inst_MIMG__IMAGE_SAMPLE_D_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_D_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_D_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_D_O
+
+ class Inst_MIMG__IMAGE_SAMPLE_D_CL_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_D_CL_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_D_CL_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_D_CL_O
+
+ class Inst_MIMG__IMAGE_SAMPLE_L_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_L_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_L_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_L_O
+
+ class Inst_MIMG__IMAGE_SAMPLE_B_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_B_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_B_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_B_O
+
+ class Inst_MIMG__IMAGE_SAMPLE_B_CL_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_B_CL_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_B_CL_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_B_CL_O
+
+ class Inst_MIMG__IMAGE_SAMPLE_LZ_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_LZ_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_LZ_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_LZ_O
+
+ class Inst_MIMG__IMAGE_SAMPLE_C_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_C_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_C_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_C_O
+
+ class Inst_MIMG__IMAGE_SAMPLE_C_CL_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_C_CL_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_C_CL_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_C_CL_O
+
+ class Inst_MIMG__IMAGE_SAMPLE_C_D_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_C_D_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_C_D_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_C_D_O
+
+ class Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O
+
+ class Inst_MIMG__IMAGE_SAMPLE_C_L_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_C_L_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_C_L_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_C_L_O
+
+ class Inst_MIMG__IMAGE_SAMPLE_C_B_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_C_B_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_C_B_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_C_B_O
+
+ class Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O
+
+ class Inst_MIMG__IMAGE_SAMPLE_C_LZ_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_C_LZ_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_C_LZ_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_C_LZ_O
+
+ class Inst_MIMG__IMAGE_GATHER4 : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4
+
+ class Inst_MIMG__IMAGE_GATHER4_CL : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_CL(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_CL();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_CL
+
+ class Inst_MIMG__IMAGE_GATHER4_L : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_L(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_L();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_L
+
+ class Inst_MIMG__IMAGE_GATHER4_B : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_B(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_B();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_B
+
+ class Inst_MIMG__IMAGE_GATHER4_B_CL : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_B_CL(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_B_CL();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_B_CL
+
+ class Inst_MIMG__IMAGE_GATHER4_LZ : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_LZ(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_LZ();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_LZ
+
+ class Inst_MIMG__IMAGE_GATHER4_C : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_C(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_C();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_C
+
+ class Inst_MIMG__IMAGE_GATHER4_C_CL : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_C_CL(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_C_CL();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_C_CL
+
+ class Inst_MIMG__IMAGE_GATHER4_C_L : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_C_L(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_C_L();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_C_L
+
+ class Inst_MIMG__IMAGE_GATHER4_C_B : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_C_B(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_C_B();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_C_B
+
+ class Inst_MIMG__IMAGE_GATHER4_C_B_CL : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_C_B_CL(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_C_B_CL();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_C_B_CL
+
+ class Inst_MIMG__IMAGE_GATHER4_C_LZ : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_C_LZ(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_C_LZ();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_C_LZ
+
+ class Inst_MIMG__IMAGE_GATHER4_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_O
+
+ class Inst_MIMG__IMAGE_GATHER4_CL_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_CL_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_CL_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_CL_O
+
+ class Inst_MIMG__IMAGE_GATHER4_L_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_L_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_L_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_L_O
+
+ class Inst_MIMG__IMAGE_GATHER4_B_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_B_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_B_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_B_O
+
+ class Inst_MIMG__IMAGE_GATHER4_B_CL_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_B_CL_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_B_CL_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_B_CL_O
+
+ class Inst_MIMG__IMAGE_GATHER4_LZ_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_LZ_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_LZ_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_LZ_O
+
+ class Inst_MIMG__IMAGE_GATHER4_C_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_C_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_C_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_C_O
+
+ class Inst_MIMG__IMAGE_GATHER4_C_CL_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_C_CL_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_C_CL_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_C_CL_O
+
+ class Inst_MIMG__IMAGE_GATHER4_C_L_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_C_L_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_C_L_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_C_L_O
+
+ class Inst_MIMG__IMAGE_GATHER4_C_B_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_C_B_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_C_B_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_C_B_O
+
+ class Inst_MIMG__IMAGE_GATHER4_C_B_CL_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_C_B_CL_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_C_B_CL_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_C_B_CL_O
+
+ class Inst_MIMG__IMAGE_GATHER4_C_LZ_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GATHER4_C_LZ_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GATHER4_C_LZ_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GATHER4_C_LZ_O
+
+ class Inst_MIMG__IMAGE_GET_LOD : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_GET_LOD(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_GET_LOD();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_GET_LOD
+
+ class Inst_MIMG__IMAGE_SAMPLE_CD : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_CD(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_CD();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_CD
+
+ class Inst_MIMG__IMAGE_SAMPLE_CD_CL : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_CD_CL(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_CD_CL();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_CD_CL
+
+ class Inst_MIMG__IMAGE_SAMPLE_C_CD : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_C_CD(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_C_CD();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_C_CD
+
+ class Inst_MIMG__IMAGE_SAMPLE_C_CD_CL : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_C_CD_CL(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_C_CD_CL();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_C_CD_CL
+
+ class Inst_MIMG__IMAGE_SAMPLE_CD_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_CD_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_CD_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_CD_O
+
+ class Inst_MIMG__IMAGE_SAMPLE_CD_CL_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_CD_CL_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_CD_CL_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_CD_CL_O
+
+ class Inst_MIMG__IMAGE_SAMPLE_C_CD_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_C_CD_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_C_CD_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_C_CD_O
+
+ class Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O : public Inst_MIMG
+ {
+ public:
+ Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O(InFmt_MIMG*);
+ ~Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 3; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return 4;
+ case 1: //sgpr_r
+ return 32;
+ case 2: //sgpr_s
+ return 4;
+ case 3: //vgpr_d
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return true;
+ case 1: //sgpr_r
+ return true;
+ case 2: //sgpr_s
+ return true;
+ case 3: //vgpr_d
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_a
+ return false;
+ case 1: //sgpr_r
+ return false;
+ case 2: //sgpr_s
+ return false;
+ case 3: //vgpr_d
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O
+
+ class Inst_EXP__EXP : public Inst_EXP
+ {
+ public:
+ Inst_EXP__EXP(InFmt_EXP*);
+ ~Inst_EXP__EXP();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 4; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //
+ return 32;
+ case 1: //
+ return 32;
+ case 2: //
+ return 32;
+ case 3: //
+ return 32;
+ case 4: //
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //
+ return true;
+ case 1: //
+ return true;
+ case 2: //
+ return true;
+ case 3: //
+ return true;
+ case 4: //
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //
+ return false;
+ case 1: //
+ return false;
+ case 2: //
+ return false;
+ case 3: //
+ return false;
+ case 4: //
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_EXP__EXP
+
+ class Inst_FLAT__FLAT_LOAD_UBYTE : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_LOAD_UBYTE(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_LOAD_UBYTE();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_dst
+ return 1;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_LOAD_UBYTE
+
+ class Inst_FLAT__FLAT_LOAD_SBYTE : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_LOAD_SBYTE(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_LOAD_SBYTE();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_dst
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_LOAD_SBYTE
+
+ class Inst_FLAT__FLAT_LOAD_USHORT : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_LOAD_USHORT(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_LOAD_USHORT();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_dst
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_LOAD_USHORT
+
+ class Inst_FLAT__FLAT_LOAD_SSHORT : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_LOAD_SSHORT(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_LOAD_SSHORT();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_dst
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_LOAD_SSHORT
+
+ class Inst_FLAT__FLAT_LOAD_DWORD : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_LOAD_DWORD(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_LOAD_DWORD();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_dst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_LOAD_DWORD
+
+ class Inst_FLAT__FLAT_LOAD_DWORDX2 : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_LOAD_DWORDX2(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_LOAD_DWORDX2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_dst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_LOAD_DWORDX2
+
+ class Inst_FLAT__FLAT_LOAD_DWORDX3 : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_LOAD_DWORDX3(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_LOAD_DWORDX3();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_dst
+ return 12;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_LOAD_DWORDX3
+
+ class Inst_FLAT__FLAT_LOAD_DWORDX4 : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_LOAD_DWORDX4(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_LOAD_DWORDX4();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 1; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_dst
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_LOAD_DWORDX4
+
+ class Inst_FLAT__FLAT_STORE_BYTE : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_STORE_BYTE(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_STORE_BYTE();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 1;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_STORE_BYTE
+
+ class Inst_FLAT__FLAT_STORE_SHORT : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_STORE_SHORT(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_STORE_SHORT();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 2;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_STORE_SHORT
+
+ class Inst_FLAT__FLAT_STORE_DWORD : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_STORE_DWORD(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_STORE_DWORD();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_STORE_DWORD
+
+ class Inst_FLAT__FLAT_STORE_DWORDX2 : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_STORE_DWORDX2(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_STORE_DWORDX2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_STORE_DWORDX2
+
+ class Inst_FLAT__FLAT_STORE_DWORDX3 : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_STORE_DWORDX3(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_STORE_DWORDX3();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 12;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_STORE_DWORDX3
+
+ class Inst_FLAT__FLAT_STORE_DWORDX4 : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_STORE_DWORDX4(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_STORE_DWORDX4();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 0; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 16;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_STORE_DWORDX4
+
+ class Inst_FLAT__FLAT_ATOMIC_SWAP : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_SWAP(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_SWAP();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 32;
+ case 2: //vgpr_dst
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_SWAP
+
+ class Inst_FLAT__FLAT_ATOMIC_CMPSWAP : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_CMPSWAP(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_CMPSWAP();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 8;
+ case 2: //vgpr_dst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_CMPSWAP
+
+ class Inst_FLAT__FLAT_ATOMIC_ADD : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_ADD(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_ADD();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 4;
+ case 2: //vgpr_dst
+ return 4;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_ADD
+
+ class Inst_FLAT__FLAT_ATOMIC_SUB : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_SUB(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_SUB();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 32;
+ case 2: //vgpr_dst
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_SUB
+
+ class Inst_FLAT__FLAT_ATOMIC_SMIN : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_SMIN(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_SMIN();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 32;
+ case 2: //vgpr_dst
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_SMIN
+
+ class Inst_FLAT__FLAT_ATOMIC_UMIN : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_UMIN(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_UMIN();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 32;
+ case 2: //vgpr_dst
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_UMIN
+
+ class Inst_FLAT__FLAT_ATOMIC_SMAX : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_SMAX(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_SMAX();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 32;
+ case 2: //vgpr_dst
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_SMAX
+
+ class Inst_FLAT__FLAT_ATOMIC_UMAX : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_UMAX(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_UMAX();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 32;
+ case 2: //vgpr_dst
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_UMAX
+
+ class Inst_FLAT__FLAT_ATOMIC_AND : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_AND(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_AND();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 32;
+ case 2: //vgpr_dst
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_AND
+
+ class Inst_FLAT__FLAT_ATOMIC_OR : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_OR(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_OR();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 32;
+ case 2: //vgpr_dst
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_OR
+
+ class Inst_FLAT__FLAT_ATOMIC_XOR : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_XOR(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_XOR();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 32;
+ case 2: //vgpr_dst
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_XOR
+
+ class Inst_FLAT__FLAT_ATOMIC_INC : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_INC(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_INC();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 32;
+ case 2: //vgpr_dst
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_INC
+
+ class Inst_FLAT__FLAT_ATOMIC_DEC : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_DEC(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_DEC();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 32;
+ case 2: //vgpr_dst
+ return 32;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_DEC
+
+ class Inst_FLAT__FLAT_ATOMIC_SWAP_X2 : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_SWAP_X2(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_SWAP_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 8;
+ case 2: //vgpr_dst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_SWAP_X2
+
+ class Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2 : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 16;
+ case 2: //vgpr_dst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2
+
+ class Inst_FLAT__FLAT_ATOMIC_ADD_X2 : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_ADD_X2(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_ADD_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 8;
+ case 2: //vgpr_dst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ void initiateAcc(GPUDynInstPtr) override;
+ void completeAcc(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_ADD_X2
+
+ class Inst_FLAT__FLAT_ATOMIC_SUB_X2 : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_SUB_X2(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_SUB_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 8;
+ case 2: //vgpr_dst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_SUB_X2
+
+ class Inst_FLAT__FLAT_ATOMIC_SMIN_X2 : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_SMIN_X2(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_SMIN_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 8;
+ case 2: //vgpr_dst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_SMIN_X2
+
+ class Inst_FLAT__FLAT_ATOMIC_UMIN_X2 : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_UMIN_X2(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_UMIN_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 8;
+ case 2: //vgpr_dst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_UMIN_X2
+
+ class Inst_FLAT__FLAT_ATOMIC_SMAX_X2 : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_SMAX_X2(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_SMAX_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 8;
+ case 2: //vgpr_dst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_SMAX_X2
+
+ class Inst_FLAT__FLAT_ATOMIC_UMAX_X2 : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_UMAX_X2(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_UMAX_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 8;
+ case 2: //vgpr_dst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_UMAX_X2
+
+ class Inst_FLAT__FLAT_ATOMIC_AND_X2 : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_AND_X2(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_AND_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 8;
+ case 2: //vgpr_dst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_AND_X2
+
+ class Inst_FLAT__FLAT_ATOMIC_OR_X2 : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_OR_X2(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_OR_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 8;
+ case 2: //vgpr_dst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_OR_X2
+
+ class Inst_FLAT__FLAT_ATOMIC_XOR_X2 : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_XOR_X2(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_XOR_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 8;
+ case 2: //vgpr_dst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_XOR_X2
+
+ class Inst_FLAT__FLAT_ATOMIC_INC_X2 : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_INC_X2(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_INC_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 8;
+ case 2: //vgpr_dst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_INC_X2
+
+ class Inst_FLAT__FLAT_ATOMIC_DEC_X2 : public Inst_FLAT
+ {
+ public:
+ Inst_FLAT__FLAT_ATOMIC_DEC_X2(InFmt_FLAT*);
+ ~Inst_FLAT__FLAT_ATOMIC_DEC_X2();
+
+ int
+ getNumOperands() override
+ {
+ return numDstRegOperands() + numSrcRegOperands();
+ } // getNumOperands
+
+ int numDstRegOperands() override { return 1; }
+ int numSrcRegOperands() override { return 2; }
+
+ int
+ getOperandSize(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return 8;
+ case 1: //vgpr_src
+ return 8;
+ case 2: //vgpr_dst
+ return 8;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return -1;
+ }
+ } // getOperandSize
+
+ bool
+ isSrcOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return true;
+ case 1: //vgpr_src
+ return true;
+ case 2: //vgpr_dst
+ return false;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isSrcOperand
+
+ bool
+ isDstOperand(int opIdx) override
+ {
+ switch (opIdx) {
+ case 0: //vgpr_addr
+ return false;
+ case 1: //vgpr_src
+ return false;
+ case 2: //vgpr_dst
+ return true;
+ default:
+ fatal("op idx %i out of bounds\n", opIdx);
+ return false;
+ }
+ } // isDstOperand
+
+ void execute(GPUDynInstPtr) override;
+ }; // Inst_FLAT__FLAT_ATOMIC_DEC_X2
+} // namespace Gcn3ISA
+
+#endif // __ARCH_GCN3_INSTS_INSTRUCTIONS_HH__
diff --git a/src/arch/gcn3/insts/op_encodings.cc b/src/arch/gcn3/insts/op_encodings.cc
new file mode 100644
index 0000000..2eb4042
--- /dev/null
+++ b/src/arch/gcn3/insts/op_encodings.cc
@@ -0,0 +1,2156 @@
+/*
+ * Copyright (c) 2016-2017 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * For use for simulation and test purposes only
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Anthony Gutierrez
+ */
+
+#include "arch/gcn3/insts/op_encodings.hh"
+
+#include <iomanip>
+
+namespace Gcn3ISA
+{
+ // --- Inst_SOP2 base class methods ---
+
+ Inst_SOP2::Inst_SOP2(InFmt_SOP2 *iFmt, const std::string &opcode)
+ : GCN3GPUStaticInst(opcode)
+ {
+ setFlag(Scalar);
+
+ // copy first instruction DWORD
+ instData = iFmt[0];
+ if (hasSecondDword(iFmt)) {
+ // copy second instruction DWORD into union
+ extData = ((MachInst)iFmt)[1];
+ _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
+ varSize = 4 + 4;
+ } else {
+ varSize = 4;
+ } // if
+ } // Inst_SOP2
+
+ int
+ Inst_SOP2::instSize() const
+ {
+ return varSize;
+ } // instSize
+
+ bool
+ Inst_SOP2::hasSecondDword(InFmt_SOP2 *iFmt)
+ {
+ if (iFmt->SSRC0 == REG_SRC_LITERAL)
+ return true;
+
+ if (iFmt->SSRC1 == REG_SRC_LITERAL)
+ return true;
+
+ return false;
+ }
+
+ void
+ Inst_SOP2::generateDisassembly()
+ {
+ std::stringstream dis_stream;
+ dis_stream << _opcode << " ";
+ dis_stream << opSelectorToRegSym(instData.SDST) << ", ";
+
+ if (instData.SSRC0 == REG_SRC_LITERAL) {
+ dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
+ << _srcLiteral << ", ";
+ } else {
+ dis_stream << opSelectorToRegSym(instData.SSRC0) << ", ";
+ }
+
+ if (instData.SSRC1 == REG_SRC_LITERAL) {
+ dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
+ << _srcLiteral;
+ } else {
+ dis_stream << opSelectorToRegSym(instData.SSRC1);
+ }
+
+ disassembly = dis_stream.str();
+ }
+
+ bool
+ Inst_SOP2::isScalarRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ return isScalarReg(instData.SSRC0);
+ case 1:
+ return isScalarReg(instData.SSRC1);
+ case 2:
+ return isScalarReg(instData.SDST);
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return false;
+ }
+ }
+
+ bool
+ Inst_SOP2::isVectorRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ // SOP2 instructions cannot access VGPRs
+ return false;
+ }
+
+ int
+ Inst_SOP2::getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ return opSelectorToRegIdx(instData.SSRC0,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ case 1:
+ return opSelectorToRegIdx(instData.SSRC1,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ case 2:
+ return opSelectorToRegIdx(instData.SDST,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return -1;
+ }
+ }
+
+ // --- Inst_SOPK base class methods ---
+
+ Inst_SOPK::Inst_SOPK(InFmt_SOPK *iFmt, const std::string &opcode)
+ : GCN3GPUStaticInst(opcode)
+ {
+ setFlag(Scalar);
+
+ // copy first instruction DWORD
+ instData = iFmt[0];
+ } // Inst_SOPK
+
+ Inst_SOPK::~Inst_SOPK()
+ {
+ } // ~Inst_SOPK
+
+ int
+ Inst_SOPK::instSize() const
+ {
+ return 4;
+ } // instSize
+
+ void
+ Inst_SOPK::generateDisassembly()
+ {
+ std::stringstream dis_stream;
+ dis_stream << _opcode << " ";
+ dis_stream << opSelectorToRegSym(instData.SDST) << ", ";
+
+ dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(4)
+ << instData.SIMM16;
+
+ disassembly = dis_stream.str();
+ }
+
+ bool
+ Inst_SOPK::isScalarRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ return false;
+ case 1:
+ return isScalarReg(instData.SDST);
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return false;
+ }
+ }
+
+ bool
+ Inst_SOPK::isVectorRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ // SOPK instruction cannot access VGPRs
+ return false;
+ }
+
+ int
+ Inst_SOPK::getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ return -1;
+ case 1:
+ return opSelectorToRegIdx(instData.SDST,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return -1;
+ }
+ }
+
+ // --- Inst_SOP1 base class methods ---
+
+ Inst_SOP1::Inst_SOP1(InFmt_SOP1 *iFmt, const std::string &opcode)
+ : GCN3GPUStaticInst(opcode)
+ {
+ setFlag(Scalar);
+
+ // copy first instruction DWORD
+ instData = iFmt[0];
+ if (hasSecondDword(iFmt)) {
+ // copy second instruction DWORD into union
+ extData = ((MachInst)iFmt)[1];
+ _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
+ varSize = 4 + 4;
+ } else {
+ varSize = 4;
+ } // if
+ } // Inst_SOP1
+
+ Inst_SOP1::~Inst_SOP1()
+ {
+ } // ~Inst_SOP1
+
+ int
+ Inst_SOP1::instSize() const
+ {
+ return varSize;
+ } // instSize
+
+ bool
+ Inst_SOP1::hasSecondDword(InFmt_SOP1 *iFmt)
+ {
+ if (iFmt->SSRC0 == REG_SRC_LITERAL)
+ return true;
+
+ return false;
+ }
+
+ void
+ Inst_SOP1::generateDisassembly()
+ {
+ std::stringstream dis_stream;
+ dis_stream << _opcode << " ";
+ dis_stream << opSelectorToRegSym(instData.SDST) << ", ";
+
+ if (instData.SSRC0 == REG_SRC_LITERAL) {
+ dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
+ << extData.imm_u32;
+ } else {
+ dis_stream << opSelectorToRegSym(instData.SSRC0);
+ }
+
+ disassembly = dis_stream.str();
+ }
+
+ bool
+ Inst_SOP1::isScalarRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ return isScalarReg(instData.SSRC0);
+ case 1:
+ return isScalarReg(instData.SDST);
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return false;
+ }
+ }
+
+ bool
+ Inst_SOP1::isVectorRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ // SOP1 instruction cannot access VGPRs
+ return false;
+ }
+
+ int
+ Inst_SOP1::getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ return opSelectorToRegIdx(instData.SSRC0,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ case 1:
+ return opSelectorToRegIdx(instData.SDST,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return -1;
+ }
+ }
+
+ // --- Inst_SOPC base class methods ---
+
+ Inst_SOPC::Inst_SOPC(InFmt_SOPC *iFmt, const std::string &opcode)
+ : GCN3GPUStaticInst(opcode)
+ {
+ setFlag(Scalar);
+
+ // copy first instruction DWORD
+ instData = iFmt[0];
+ if (hasSecondDword(iFmt)) {
+ // copy second instruction DWORD into union
+ extData = ((MachInst)iFmt)[1];
+ _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
+ varSize = 4 + 4;
+ } else {
+ varSize = 4;
+ } // if
+ } // Inst_SOPC
+
+ Inst_SOPC::~Inst_SOPC()
+ {
+ } // ~Inst_SOPC
+
+ int
+ Inst_SOPC::instSize() const
+ {
+ return varSize;
+ } // instSize
+
+ bool
+ Inst_SOPC::hasSecondDword(InFmt_SOPC *iFmt)
+ {
+ if (iFmt->SSRC0 == REG_SRC_LITERAL)
+ return true;
+
+ if (iFmt->SSRC1 == REG_SRC_LITERAL)
+ return true;
+
+ return false;
+ }
+
+ void
+ Inst_SOPC::generateDisassembly()
+ {
+ std::stringstream dis_stream;
+ dis_stream << _opcode << " ";
+
+ if (instData.SSRC0 == REG_SRC_LITERAL) {
+ dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
+ << extData.imm_u32;
+ } else {
+ dis_stream << opSelectorToRegSym(instData.SSRC0) << ", ";
+ }
+
+ if (instData.SSRC1 == REG_SRC_LITERAL) {
+ dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
+ << extData.imm_u32;
+ } else {
+ dis_stream << opSelectorToRegSym(instData.SSRC1);
+ }
+
+ disassembly = dis_stream.str();
+ }
+
+ bool
+ Inst_SOPC::isScalarRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ // SSRC0 is always a scalar reg or a constant
+ return isScalarReg(instData.SSRC0);
+ case 1:
+ // SSRC1 is always a scalar reg or a constant
+ return isScalarReg(instData.SSRC1);
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return false;
+ }
+ }
+
+ bool
+ Inst_SOPC::isVectorRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ // SOPC instructions cannot access VGPRs
+ return false;
+ }
+
+ int
+ Inst_SOPC::getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ return opSelectorToRegIdx(instData.SSRC0,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ case 1:
+ return opSelectorToRegIdx(instData.SSRC1,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return -1;
+ }
+ }
+
+ // --- Inst_SOPP base class methods ---
+
+ Inst_SOPP::Inst_SOPP(InFmt_SOPP *iFmt, const std::string &opcode)
+ : GCN3GPUStaticInst(opcode)
+ {
+ setFlag(Scalar);
+
+ // copy first instruction DWORD
+ instData = iFmt[0];
+ } // Inst_SOPP
+
+ Inst_SOPP::~Inst_SOPP()
+ {
+ } // ~Inst_SOPP
+
+ int
+ Inst_SOPP::instSize() const
+ {
+ return 4;
+ } // instSize
+
+ void
+ Inst_SOPP::generateDisassembly()
+ {
+ std::stringstream dis_stream;
+ dis_stream << _opcode;
+
+ switch (instData.OP) {
+ case 8:
+ {
+ dis_stream << " ";
+ int dest = 4 * instData.SIMM16 + 4;
+ dis_stream << "label_" << std::hex << dest;
+ }
+ break;
+ case 12:
+ {
+ dis_stream << " ";
+
+ int vm_cnt = 0;
+ int exp_cnt = 0;
+ int lgkm_cnt = 0;
+
+ vm_cnt = bits<uint16_t>(instData.SIMM16, 3, 0);
+ exp_cnt = bits<uint16_t>(instData.SIMM16, 6, 4);
+ lgkm_cnt = bits<uint16_t>(instData.SIMM16, 11, 8);
+
+ // if the counts are not maxed out, then we
+ // print out the count value
+ if (vm_cnt != 0xf) {
+ dis_stream << "vmcnt(" << vm_cnt << ")";
+ }
+
+ if (lgkm_cnt != 0xf) {
+ if (vm_cnt != 0xf)
+ dis_stream << " & ";
+
+ dis_stream << "lgkmcnt(" << lgkm_cnt << ")";
+ }
+
+ if (exp_cnt != 0x7) {
+ if (vm_cnt != 0xf || lgkm_cnt != 0xf)
+ dis_stream << " & ";
+
+ dis_stream << "expcnt(" << exp_cnt << ")";
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ disassembly = dis_stream.str();
+ }
+
+ bool
+ Inst_SOPP::isScalarRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ // SOPP instructions have a maximum of 1 operand,
+ // and it's always an immediate value
+ return false;
+ }
+
+ bool
+ Inst_SOPP::isVectorRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ // SOPP instructions have a maximum of 1 operand,
+ // and it's always an immediate value
+ return false;
+ }
+
+ int
+ Inst_SOPP::getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ // SOPP instructions have a maximum of 1 operand,
+ // and it's always an immediate value
+ return -1;
+ }
+
+ // --- Inst_SMEM base class methods ---
+
+ Inst_SMEM::Inst_SMEM(InFmt_SMEM *iFmt, const std::string &opcode)
+ : GCN3GPUStaticInst(opcode)
+ {
+ setFlag(Scalar);
+ setFlag(GlobalSegment);
+
+ // copy first instruction DWORD
+ instData = iFmt[0];
+ // copy second instruction DWORD
+ extData = ((InFmt_SMEM_1 *)iFmt)[1];
+ _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
+
+ if (instData.GLC)
+ setFlag(GloballyCoherent);
+ } // Inst_SMEM
+
+ Inst_SMEM::~Inst_SMEM()
+ {
+ } // ~Inst_SMEM
+
+ int
+ Inst_SMEM::instSize() const
+ {
+ return 8;
+ } // instSize
+
+ void
+ Inst_SMEM::generateDisassembly()
+ {
+ std::stringstream dis_stream;
+ dis_stream << _opcode << " ";
+ if (numDstRegOperands()) {
+ if (getOperandSize(getNumOperands() - 1) > 4) {
+ dis_stream << "s[" << instData.SDATA << ":"
+ << instData.SDATA + getOperandSize(getNumOperands() - 1) /
+ 4 - 1 << "], ";
+ } else {
+ dis_stream << "s" << instData.SDATA << ", ";
+ }
+ }
+
+ // SBASE has an implied LSB of 0, so we need
+ // to shift by one to get the actual value
+ dis_stream << "s[" << (instData.SBASE << 1) << ":"
+ << ((instData.SBASE << 1) + 1) << "], ";
+
+ if (instData.IMM) {
+ // IMM == 1 implies OFFSET should be
+ // used as the offset
+ dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(2)
+ << extData.OFFSET;
+ } else {
+ // IMM == 0 implies OFFSET should be
+ // used to specify SGRP in which the
+ // offset is held
+ dis_stream << "s" << extData.OFFSET;
+ }
+
+ disassembly = dis_stream.str();
+ }
+
+ bool
+ Inst_SMEM::isScalarRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ // SBASE is always a scalar
+ return true;
+ case 1:
+ if (instData.IMM) {
+ return false;
+ } else {
+ return isScalarReg(extData.OFFSET);
+ }
+ case 2:
+ return isScalarReg(instData.SDATA);
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return false;
+ }
+ }
+
+ bool
+ Inst_SMEM::isVectorRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ // SMEM instructions cannot access VGPRs
+ return false;
+ }
+
+ int
+ Inst_SMEM::getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ // SBASE has an implied LSB of 0, so we need
+ // to shift by one to get the actual value
+ return opSelectorToRegIdx(instData.SBASE << 1,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ case 1:
+ if (instData.IMM) {
+ // operand is an immediate value, not a register
+ return -1;
+ } else {
+ return extData.OFFSET;
+ }
+ case 2:
+ return opSelectorToRegIdx(instData.SDATA,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return -1;
+ }
+ }
+
+ // --- Inst_VOP2 base class methods ---
+
+ Inst_VOP2::Inst_VOP2(InFmt_VOP2 *iFmt, const std::string &opcode)
+ : GCN3GPUStaticInst(opcode)
+ {
+ // copy first instruction DWORD
+ instData = iFmt[0];
+ if (hasSecondDword(iFmt)) {
+ // copy second instruction DWORD into union
+ extData = ((MachInst)iFmt)[1];
+ _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
+ varSize = 4 + 4;
+ if (iFmt->SRC0 == REG_SRC_DPP) {
+ setFlag(IsDPP);
+ } else if (iFmt->SRC0 == REG_SRC_SWDA) {
+ setFlag(IsSDWA);
+ }
+ } else {
+ varSize = 4;
+ } // if
+ } // Inst_VOP2
+
+ Inst_VOP2::~Inst_VOP2()
+ {
+ } // ~Inst_VOP2
+
+ int
+ Inst_VOP2::instSize() const
+ {
+ return varSize;
+ } // instSize
+
+ bool
+ Inst_VOP2::hasSecondDword(InFmt_VOP2 *iFmt)
+ {
+ /*
+ There are a few cases where VOP2 instructions have a second dword:
+
+ 1. SRC0 is a literal
+ 2. SRC0 is being used to add a data parallel primitive (DPP)
+ operation to the instruction.
+ 3. SRC0 is being used for sub d-word addressing (SDWA) of the
+ operands in the instruction.
+ 4. VOP2 instructions also have four special opcodes:',
+ V_MADMK_{F16, F32} (0x24, 0x17), and V_MADAK_{F16, F32}',
+ (0x25, 0x18), that are always 64b. the only way to',
+ detect these special cases is to explicitly check,',
+ the opcodes',
+ */
+ if (iFmt->SRC0 == REG_SRC_LITERAL || (iFmt->SRC0 == REG_SRC_DPP) ||
+ (iFmt->SRC0 == REG_SRC_SWDA) || iFmt->OP == 0x17 ||
+ iFmt->OP == 0x18 || iFmt->OP == 0x24 || iFmt->OP == 0x25)
+ return true;
+
+ return false;
+ }
+
+ void
+ Inst_VOP2::generateDisassembly()
+ {
+ std::stringstream dis_stream;
+ dis_stream << _opcode << " ";
+ dis_stream << "v" << instData.VDST << ", ";
+
+ if (writesVCC())
+ dis_stream << "vcc, ";
+
+ if ((instData.SRC0 == REG_SRC_LITERAL) ||
+ (instData.SRC0 == REG_SRC_DPP) ||
+ (instData.SRC0 == REG_SRC_SWDA)) {
+ dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
+ << _srcLiteral << ", ";
+ } else {
+ dis_stream << opSelectorToRegSym(instData.SRC0) << ", ";
+ }
+
+ // VOP2 instructions have four special opcodes:',
+ // V_MADMK_{F16, F32} (0x24, 0x17), and V_MADAK_{F16, F32}',
+ // (0x25, 0x18), that are always 64b. the only way to',
+ // detect these special cases is to explicitly check,',
+ // the opcodes',
+ if (instData.OP == 0x17 || instData.OP == 0x18 || instData.OP == 0x24
+ || instData.OP == 0x25) {
+ dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
+ << extData.imm_u32 << ", ";
+ }
+
+ dis_stream << "v" << instData.VSRC1;
+
+ if (readsVCC())
+ dis_stream << ", vcc";
+
+ disassembly = dis_stream.str();
+ }
+
+ bool
+ Inst_VOP2::isScalarRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ // SRC0 may be a scalar or vector register, an
+ // inline constant, or a special HW register
+ return isScalarReg(instData.SRC0);
+ case 1:
+ // instData.VSRC1 is never a scalar reg
+ return false;
+ case 2:
+ if (readsVCC()) {
+ return true;
+ } else {
+ // instData.VDST is never a scalar reg
+ return false;
+ }
+ case 3:
+ // if a VOP2 instruction has more than 3 ops
+ // it must read from or write to VCC, and
+ // VCC is always in an SGPR
+ assert(readsVCC() || writesVCC());
+ if (readsVCC()) {
+ return false;
+ } else {
+ return true;
+ }
+ case 4:
+ // if a VOP2 instruction has more than 4 ops
+ // it must read from and write to VCC, and
+ // VCC is always in an SGPR
+ assert(writesVCC() && readsVCC());
+ return true;
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return false;
+ }
+ }
+
+ bool
+ Inst_VOP2::isVectorRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ // SRC0 may be a scalar or vector register, an
+ // inline constant, or a special HW register
+ return isVectorReg(instData.SRC0);
+ case 1:
+ // instData.VSRC1 is always a vector reg
+ return true;
+ case 2:
+ if (readsVCC()) {
+ return false;
+ } else {
+ // instData.VDST is always a vector reg
+ return true;
+ }
+ case 3:
+ // if a VOP2 instruction has more than 3 ops
+ // it must read from or write to VCC, and
+ // VCC is always in an SGPR
+ assert(writesVCC() || readsVCC());
+ if (readsVCC()) {
+ return true;
+ } else {
+ return false;
+ }
+ case 4:
+ // if a VOP2 instruction has more than 4 ops
+ // it must read from and write to VCC, and
+ // VCC is always in an SGPR
+ assert(writesVCC() && readsVCC());
+ return false;
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return false;
+ }
+ }
+
+ int
+ Inst_VOP2::getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ return opSelectorToRegIdx(instData.SRC0,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ case 1:
+ return instData.VSRC1;
+ case 2:
+ if (readsVCC()) {
+ return opSelectorToRegIdx(REG_VCC_LO,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ } else {
+ return instData.VDST;
+ }
+ case 3:
+ assert(writesVCC() || readsVCC());
+ if (readsVCC()) {
+ return instData.VDST;
+ } else {
+ return opSelectorToRegIdx(REG_VCC_LO,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ }
+ case 4:
+ assert(writesVCC() && readsVCC());
+ return opSelectorToRegIdx(REG_VCC_LO,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return -1;
+ }
+ }
+
+ // --- Inst_VOP1 base class methods ---
+
+ Inst_VOP1::Inst_VOP1(InFmt_VOP1 *iFmt, const std::string &opcode)
+ : GCN3GPUStaticInst(opcode)
+ {
+ // copy first instruction DWORD
+ instData = iFmt[0];
+ if (hasSecondDword(iFmt)) {
+ // copy second instruction DWORD into union
+ extData = ((MachInst)iFmt)[1];
+ _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
+ varSize = 4 + 4;
+ if (iFmt->SRC0 == REG_SRC_DPP) {
+ setFlag(IsDPP);
+ } else if (iFmt->SRC0 == REG_SRC_SWDA) {
+ setFlag(IsSDWA);
+ }
+ } else {
+ varSize = 4;
+ } // if
+ } // Inst_VOP1
+
+ Inst_VOP1::~Inst_VOP1()
+ {
+ } // ~Inst_VOP1
+
+ int
+ Inst_VOP1::instSize() const
+ {
+ return varSize;
+ } // instSize
+
+ bool
+ Inst_VOP1::hasSecondDword(InFmt_VOP1 *iFmt)
+ {
+ /*
+ There are several cases where VOP1 instructions have a second dword:
+
+ 1. SRC0 is a literal.
+ 2. SRC0 is being used to add a data parallel primitive (DPP)
+ operation to the instruction.
+ 3. SRC0 is being used for sub d-word addressing (SDWA) of the
+ operands in the instruction.
+ */
+ if ((iFmt->SRC0 == REG_SRC_LITERAL) || (iFmt->SRC0 == REG_SRC_DPP) ||
+ (iFmt->SRC0 == REG_SRC_SWDA))
+ return true;
+
+ return false;
+ }
+
+ void
+ Inst_VOP1::generateDisassembly()
+ {
+ std::stringstream dis_stream;
+ dis_stream << _opcode << " ";
+ dis_stream << "v" << instData.VDST << ", ";
+
+ if ((instData.SRC0 == REG_SRC_LITERAL) ||
+ (instData.SRC0 == REG_SRC_DPP) ||
+ (instData.SRC0 == REG_SRC_SWDA)) {
+ dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
+ << _srcLiteral;
+ } else {
+ dis_stream << opSelectorToRegSym(instData.SRC0);
+ }
+
+ disassembly = dis_stream.str();
+ }
+
+ bool
+ Inst_VOP1::isScalarRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ return isScalarReg(instData.SRC0);
+ case 1:
+ // VDST is never a scalar reg
+ return false;
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return false;
+ }
+ }
+
+ bool
+ Inst_VOP1::isVectorRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ return isVectorReg(instData.SRC0);
+ case 1:
+ // VDST is always a vector reg
+ return true;
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return false;
+ }
+ }
+
+ int
+ Inst_VOP1::getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ return opSelectorToRegIdx(instData.SRC0,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ case 1:
+ return instData.VDST;
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return -1;
+ }
+ }
+
+ // --- Inst_VOPC base class methods ---
+
+ Inst_VOPC::Inst_VOPC(InFmt_VOPC *iFmt, const std::string &opcode)
+ : GCN3GPUStaticInst(opcode)
+ {
+ // copy first instruction DWORD
+ instData = iFmt[0];
+ if (hasSecondDword(iFmt)) {
+ // copy second instruction DWORD into union
+ extData = ((MachInst)iFmt)[1];
+ _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
+ varSize = 4 + 4;
+ if (iFmt->SRC0 == REG_SRC_DPP) {
+ setFlag(IsDPP);
+ } else if (iFmt->SRC0 == REG_SRC_SWDA) {
+ setFlag(IsSDWA);
+ }
+ } else {
+ varSize = 4;
+ } // if
+ } // Inst_VOPC
+
+ Inst_VOPC::~Inst_VOPC()
+ {
+ } // ~Inst_VOPC
+
+ int
+ Inst_VOPC::instSize() const
+ {
+ return varSize;
+ } // instSize
+
+ bool
+ Inst_VOPC::hasSecondDword(InFmt_VOPC *iFmt)
+ {
+ /*
+ There are several cases where VOPC instructions have a second dword:
+
+ 1. SRC0 is a literal.
+ 2. SRC0 is being used to add a data parallel primitive (DPP)
+ operation to the instruction.
+ 3. SRC0 is being used for sub d-word addressing (SDWA) of the
+ operands in the instruction.
+ */
+ if ((iFmt->SRC0 == REG_SRC_LITERAL) || (iFmt->SRC0 == REG_SRC_DPP) ||
+ (iFmt->SRC0 == REG_SRC_SWDA))
+ return true;
+
+ return false;
+ }
+
+ void
+ Inst_VOPC::generateDisassembly()
+ {
+ std::stringstream dis_stream;
+ dis_stream << _opcode << " vcc, ";
+
+ dis_stream << opSelectorToRegSym(instData.SRC0) << ", ";
+ dis_stream << "v" << instData.VSRC1;
+
+ disassembly = dis_stream.str();
+ }
+
+ bool
+ Inst_VOPC::isScalarRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ return isScalarReg(instData.SRC0);
+ case 1:
+ // VSRC1 is never a scalar register
+ return false;
+ case 2:
+ // VCC is always a scalar register
+ return true;
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return false;
+ }
+ }
+
+ bool
+ Inst_VOPC::isVectorRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ return isVectorReg(instData.SRC0);
+ case 1:
+ // VSRC1 is never a scalar register
+ return true;
+ case 2:
+ // VCC is always a scalar register
+ return false;
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return false;
+ }
+ }
+
+ int
+ Inst_VOPC::getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ return opSelectorToRegIdx(instData.SRC0,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ case 1:
+ return instData.VSRC1;
+ case 2:
+ // VCC
+ return opSelectorToRegIdx(REG_VCC_LO,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return -1;
+ }
+ }
+
+ // --- Inst_VINTRP base class methods ---
+
+ Inst_VINTRP::Inst_VINTRP(InFmt_VINTRP *iFmt, const std::string &opcode)
+ : GCN3GPUStaticInst(opcode)
+ {
+ // copy first instruction DWORD
+ instData = iFmt[0];
+ } // Inst_VINTRP
+
+ Inst_VINTRP::~Inst_VINTRP()
+ {
+ } // ~Inst_VINTRP
+
+ int
+ Inst_VINTRP::instSize() const
+ {
+ return 4;
+ } // instSize
+
+ // --- Inst_VOP3 base class methods ---
+
+ Inst_VOP3::Inst_VOP3(InFmt_VOP3 *iFmt, const std::string &opcode,
+ bool sgpr_dst)
+ : GCN3GPUStaticInst(opcode), sgprDst(sgpr_dst)
+ {
+ // copy first instruction DWORD
+ instData = iFmt[0];
+ // copy second instruction DWORD
+ extData = ((InFmt_VOP3_1 *)iFmt)[1];
+ _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
+ } // Inst_VOP3
+
+ Inst_VOP3::~Inst_VOP3()
+ {
+ } // ~Inst_VOP3
+
+ int
+ Inst_VOP3::instSize() const
+ {
+ return 8;
+ } // instSize
+
+ void
+ Inst_VOP3::generateDisassembly()
+ {
+ std::stringstream dis_stream;
+ dis_stream << _opcode << " ";
+ int num_regs = 0;
+
+ if (getOperandSize(getNumOperands() - 1) > 4) {
+ num_regs = getOperandSize(getNumOperands() - 1) / 4;
+ if (sgprDst)
+ dis_stream << "s[";
+ else
+ dis_stream << "v[";
+ dis_stream << instData.VDST << ":" << instData.VDST +
+ num_regs - 1 << "], ";
+ } else {
+ if (sgprDst)
+ dis_stream << "s";
+ else
+ dis_stream << "v";
+ dis_stream << instData.VDST << ", ";
+ }
+
+ num_regs = getOperandSize(0) / 4;
+
+ if (extData.NEG & 0x1) {
+ dis_stream << "-" << opSelectorToRegSym(extData.SRC0, num_regs);
+ } else {
+ dis_stream << opSelectorToRegSym(extData.SRC0, num_regs);
+ }
+
+ if (numSrcRegOperands() > 1) {
+ num_regs = getOperandSize(1) / 4;
+
+ if (extData.NEG & 0x2) {
+ dis_stream << ", -"
+ << opSelectorToRegSym(extData.SRC1, num_regs);
+ } else {
+ dis_stream << ", "
+ << opSelectorToRegSym(extData.SRC1, num_regs);
+ }
+ }
+
+ if (numSrcRegOperands() > 2) {
+ num_regs = getOperandSize(2) / 4;
+
+ if (extData.NEG & 0x4) {
+ dis_stream << ", -"
+ << opSelectorToRegSym(extData.SRC2, num_regs);
+ } else {
+ dis_stream << ", "
+ << opSelectorToRegSym(extData.SRC2, num_regs);
+ }
+ }
+
+ disassembly = dis_stream.str();
+ }
+
+ bool
+ Inst_VOP3::isScalarRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ // SRC0 may be a scalar or vector register, an
+ // inline constant, or a special HW register
+ return isScalarReg(extData.SRC0);
+ case 1:
+ if (numSrcRegOperands() > 1) {
+ // if we have more than 1 source operand then
+ // op index 1 corresponds to SRC1. SRC1 may be
+ // a scalar or vector register, an inline
+ // constant, or a special HW register
+ return isScalarReg(extData.SRC1);
+ } else {
+ // if we only have 1 source operand, opIdx 1
+ // will be VDST, and VDST is only a scalar
+ // for v_cmp instructions
+ if (sgprDst)
+ return true;
+ return false;
+ }
+ case 2:
+ if (numSrcRegOperands() > 2) {
+ // if we have more than 2 source operand then
+ // op index 2 corresponds to SRC2. SRC2 may be
+ // a scalar or vector register, an inline
+ // constant, or a special HW register
+ return isScalarReg(extData.SRC2);
+ } else if (numSrcRegOperands() == 2) {
+ // if we only have 2 source operands, opIdx 2
+ // will be VDST, and VDST is only a scalar
+ // for v_cmp instructions
+ if (sgprDst)
+ return true;
+ return false;
+ } else {
+ // if this idx doesn't correspond to SRCX or
+ // VDST then it must be a VCC read or write,
+ // and VCC is always stored in an SGPR pair
+ assert(writesVCC() || readsVCC());
+ return true;
+ }
+ case 3:
+ if (numSrcRegOperands() == 3) {
+ // if we have 3 source operands, opIdx 3
+ // will be VDST, and VDST is only a scalar
+ // for v_cmp instructions
+ if (sgprDst)
+ return true;
+ return false;
+ } else {
+ // if this idx doesn't correspond to VDST
+ // then it must be a VCC read or write, and
+ // and VCC is always stored in an SGPR pair
+ assert(writesVCC() || readsVCC());
+ return true;
+ }
+ case 4:
+ // if a VOP3 instruction has more than 4 ops
+ // it must read from and write to VCC, and
+ // VCC is always in an SGPR
+ assert(writesVCC() || readsVCC());
+ return true;
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return false;
+ }
+ }
+
+ bool
+ Inst_VOP3::isVectorRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ // SRC0 may be a scalar or vector register, an
+ // inline constant, or a special HW register
+ return isVectorReg(extData.SRC0);
+ case 1:
+ if (numSrcRegOperands() > 1) {
+ // if we have more than 1 source operand then
+ // op index 1 corresponds to SRC1. SRC1 may be
+ // a scalar or vector register, an inline
+ // constant, or a special HW register
+ return isVectorReg(extData.SRC1);
+ } else {
+ // if we only have 1 source operands, opIdx 1
+ // will be VDST, and VDST is a scalar for v_cmp
+ // instructions
+ if (sgprDst)
+ return false;
+ return true;
+ }
+ case 2:
+ if (numSrcRegOperands() > 2) {
+ // if we have more than 2 source operand then
+ // op index 2 corresponds to SRC2. SRC2 may be
+ // a scalar or vector register, an inline
+ // constant, or a special HW register
+ return isVectorReg(extData.SRC2);
+ } else if (numSrcRegOperands() == 2) {
+ // if we only have 2 source operands, opIdx 2
+ // will be VDST, and VDST is a scalar for v_cmp
+ // instructions
+ if (sgprDst)
+ return false;
+ return true;
+ } else {
+ // if this idx doesn't correspond to SRCX or
+ // VDST then it must be a VCC read or write,
+ // and VCC is never stored in a VGPR
+ assert(writesVCC() || readsVCC());
+ return false;
+ }
+ case 3:
+ if (numSrcRegOperands() == 3) {
+ // if we have 3 source operands, opIdx 3
+ // will be VDST, and VDST is a scalar for v_cmp
+ // instructions
+ if (sgprDst)
+ return false;
+ return true;
+ } else {
+ // if this idx doesn't correspond to VDST
+ // then it must be a VCC read or write, and
+ // and VCC is never stored in a VGPR
+ assert(writesVCC() || readsVCC());
+ return false;
+ }
+ case 4:
+ // if a VOP3 instruction has more than 4 ops
+ // it must read from and write to VCC, and
+ // VCC is never stored in a VGPR
+ assert(writesVCC() || readsVCC());
+ return false;
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return false;
+ }
+ }
+
+ int
+ Inst_VOP3::getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ // SRC0
+ return opSelectorToRegIdx(extData.SRC0,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ case 1:
+ if (numSrcRegOperands() > 1) {
+ // if we have more than 1 source operand then
+ // op index 1 corresponds to SRC1
+ return opSelectorToRegIdx(extData.SRC1,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ } else {
+ // if we only have 1 source operand, opIdx 1
+ // will be VDST
+ if (sgprDst) {
+ return opSelectorToRegIdx(instData.VDST,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ }
+ return instData.VDST;
+ }
+ case 2:
+ if (numSrcRegOperands() > 2) {
+ // if we have more than 2 source operand then
+ // op index 2 corresponds to SRC2. SRC2 may be
+ // a scalar or vector register, an inline
+ // constant, or a special HW register
+ return opSelectorToRegIdx(extData.SRC2,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ } else if (numSrcRegOperands() == 2) {
+ // if we only have 2 source operands, opIdx 2
+ // will be VDST, and VDST is always a vector
+ // reg
+ if (sgprDst) {
+ return opSelectorToRegIdx(instData.VDST,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ }
+ return instData.VDST;
+ } else {
+ // if this idx doesn't correspond to SRCX or
+ // VDST then it must be a VCC read or write,
+ // and VCC is never stored in a VGPR
+ assert(writesVCC() || readsVCC());
+ return opSelectorToRegIdx(REG_VCC_LO,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ }
+ case 3:
+ if (numSrcRegOperands() == 3) {
+ // if we have 3 source operands then op
+ // idx 3 will correspond to VDST
+ if (sgprDst) {
+ return opSelectorToRegIdx(instData.VDST,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ }
+ return instData.VDST;
+ } else {
+ // if this idx doesn't correspond to VDST
+ // then it must be a VCC read or write
+ assert(writesVCC() || readsVCC());
+ return opSelectorToRegIdx(REG_VCC_LO,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ }
+ case 4:
+ // if a VOP3 instruction has more than 4 ops
+ // it must read from and write to VCC
+ assert(writesVCC() || readsVCC());
+ return opSelectorToRegIdx(REG_VCC_LO,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return -1;
+ }
+ }
+
+ // --- Inst_VOP3_SDST_ENC base class methods ---
+
+ Inst_VOP3_SDST_ENC::Inst_VOP3_SDST_ENC(InFmt_VOP3_SDST_ENC *iFmt,
+ const std::string &opcode)
+ : GCN3GPUStaticInst(opcode)
+ {
+ // copy first instruction DWORD
+ instData = iFmt[0];
+ // copy second instruction DWORD
+ extData = ((InFmt_VOP3_1 *)iFmt)[1];
+ _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
+ } // Inst_VOP3_SDST_ENC
+
+ Inst_VOP3_SDST_ENC::~Inst_VOP3_SDST_ENC()
+ {
+ } // ~Inst_VOP3_SDST_ENC
+
+ int
+ Inst_VOP3_SDST_ENC::instSize() const
+ {
+ return 8;
+ } // instSize
+
+ void
+ Inst_VOP3_SDST_ENC::generateDisassembly()
+ {
+ std::stringstream dis_stream;
+ dis_stream << _opcode << " ";
+
+ dis_stream << "v" << instData.VDST << ", ";
+
+ if (numDstRegOperands() == 2) {
+ if (getOperandSize(getNumOperands() - 1) > 4) {
+ int num_regs = getOperandSize(getNumOperands() - 1) / 4;
+ dis_stream << opSelectorToRegSym(instData.SDST, num_regs)
+ << ", ";
+ } else {
+ dis_stream << opSelectorToRegSym(instData.SDST) << ", ";
+ }
+ }
+
+ if (extData.NEG & 0x1) {
+ dis_stream << "-" << opSelectorToRegSym(extData.SRC0) << ", ";
+ } else {
+ dis_stream << opSelectorToRegSym(extData.SRC0) << ", ";
+ }
+
+ if (extData.NEG & 0x2) {
+ dis_stream << "-" << opSelectorToRegSym(extData.SRC1);
+ } else {
+ dis_stream << opSelectorToRegSym(extData.SRC1);
+ }
+
+ if (numSrcRegOperands() == 3) {
+ if (extData.NEG & 0x4) {
+ dis_stream << ", -" << opSelectorToRegSym(extData.SRC2);
+ } else {
+ dis_stream << ", " << opSelectorToRegSym(extData.SRC2);
+ }
+ }
+
+ if (readsVCC())
+ dis_stream << ", vcc";
+
+ disassembly = dis_stream.str();
+ }
+
+ bool
+ Inst_VOP3_SDST_ENC::isScalarRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ // SRC0 may be a scalar or vector register, an
+ // inline constant, or a special HW register
+ return isScalarReg(extData.SRC0);
+ case 1:
+ if (numSrcRegOperands() > 1) {
+ // if we have more than 1 source operand then
+ // op index 1 corresponds to SRC1. SRC1 may be
+ // a scalar or vector register, an inline
+ // constant, or a special HW register
+ return isScalarReg(extData.SRC1);
+ } else {
+ // if we only have 1 source operand, opIdx 1
+ // will be VDST, and VDST is never a scalar
+ // reg
+ if (instData.VDST == REG_VCC_LO)
+ return true;
+ return false;
+ }
+ case 2:
+ if (numSrcRegOperands() > 2) {
+ // if we have more than 2 source operand then
+ // op index 2 corresponds to SRC2. SRC2 may be
+ // a scalar or vector register, an inline
+ // constant, or a special HW register
+ return isScalarReg(extData.SRC2);
+ } else if (numSrcRegOperands() == 2) {
+ // if we only have 2 source operands, opIdx 2
+ // will be VDST, and VDST is never a scalar
+ // reg
+ if (instData.VDST == REG_VCC_LO)
+ return true;
+ return false;
+ } else {
+ // if this idx doesn't correspond to SRCX or
+ // VDST then it must be a VCC read or write,
+ // and VCC is always stored in an SGPR pair
+ assert(writesVCC() || readsVCC());
+ return true;
+ }
+ case 3:
+ if (numSrcRegOperands() == 3) {
+ // if we have 3 source operands then op
+ // idx 3 will correspond to VDST, and VDST
+ // is never a scalar reg
+ if (instData.VDST == REG_VCC_LO)
+ return true;
+ return false;
+ } else {
+ // if this idx doesn't correspond to VDST
+ // then it must be a VCC read or write, and
+ // and VCC is always stored in an SGPR pair
+ assert(writesVCC() || readsVCC());
+ return true;
+ }
+ case 4:
+ // if a VOP3 instruction has more than 4 ops
+ // it must read from and write to VCC, and
+ // VCC is always in an SGPR
+ assert(writesVCC() || readsVCC());
+ return true;
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return false;
+ }
+ }
+
+ bool
+ Inst_VOP3_SDST_ENC::isVectorRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ // SRC0 may be a scalar or vector register, an
+ // inline constant, or a special HW register
+ return isVectorReg(extData.SRC0);
+ case 1:
+ if (numSrcRegOperands() > 1) {
+ // if we have more than 1 source operand then
+ // op index 1 corresponds to SRC1. SRC1 may be
+ // a scalar or vector register, an inline
+ // constant, or a special HW register
+ return isVectorReg(extData.SRC1);
+ } else {
+ // if we only have 1 source operand, opIdx 1
+ // will be VDST, and VDST is always a vector
+ // reg
+ if (instData.VDST == REG_VCC_LO)
+ return false;
+ return true;
+ }
+ case 2:
+ if (numSrcRegOperands() > 2) {
+ // if we have more than 2 source operand then
+ // op index 2 corresponds to SRC2. SRC2 may be
+ // a scalar or vector register, an inline
+ // constant, or a special HW register
+ return isVectorReg(extData.SRC2);
+ } else if (numSrcRegOperands() == 2) {
+ // if we only have 2 source operands, opIdx 2
+ // will be VDST, and VDST is always a vector
+ // reg
+ if (instData.VDST == REG_VCC_LO)
+ return false;
+ return true;
+ } else {
+ // if this idx doesn't correspond to SRCX or
+ // VDST then it must be a VCC read or write,
+ // and VCC is never stored in a VGPR
+ assert(writesVCC() || readsVCC());
+ return false;
+ }
+ case 3:
+ if (numSrcRegOperands() == 3) {
+ // if we have 3 source operands then op
+ // idx 3 will correspond to VDST, and VDST
+ // is always a vector reg
+ if (instData.VDST == REG_VCC_LO)
+ return false;
+ return true;
+ } else {
+ // if this idx doesn't correspond to VDST
+ // then it must be a VCC read or write, and
+ // and VCC is never stored in a VGPR
+ assert(writesVCC() || readsVCC());
+ return false;
+ }
+ case 4:
+ // if a VOP3 instruction has more than 4 ops
+ // it must read from and write to VCC, and
+ // VCC is never stored in a VGPR
+ assert(writesVCC() || readsVCC());
+ return false;
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return false;
+ }
+ }
+
+ int
+ Inst_VOP3_SDST_ENC::getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ // SRC0
+ return opSelectorToRegIdx(extData.SRC0,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ case 1:
+ if (numSrcRegOperands() > 1) {
+ // if we have more than 1 source operand then
+ // op index 1 corresponds to SRC1
+ return opSelectorToRegIdx(extData.SRC1,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ } else {
+ // if we only have 1 source operand, opIdx 1
+ // will be VDST
+ return instData.VDST;
+ }
+ case 2:
+ if (numSrcRegOperands() > 2) {
+ // if we have more than 2 source operand then
+ // op index 2 corresponds to SRC2
+ return opSelectorToRegIdx(extData.SRC2,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ } else if (numSrcRegOperands() == 2) {
+ // if we only have 2 source operands, opIdx 2
+ // will be VDST
+ return instData.VDST;
+ } else {
+ // if this idx doesn't correspond to SRCX or
+ // VDST then it must be a VCC read or write
+ assert(writesVCC() || readsVCC());
+ return opSelectorToRegIdx(instData.SDST,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ }
+ case 3:
+ if (numSrcRegOperands() == 3) {
+ // if we have 3 source operands then op
+ // idx 3 will correspond to VDST
+ return instData.VDST;
+ } else {
+ // if this idx doesn't correspond to VDST
+ // then it must be a VCC read or write
+ assert(writesVCC() || readsVCC());
+ return opSelectorToRegIdx(instData.SDST,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ }
+ case 4:
+ // if a VOP3 instruction has more than 4 ops
+ // it must read from and write to VCC
+ assert(writesVCC() || readsVCC());
+ return opSelectorToRegIdx(instData.SDST,
+ gpuDynInst->wavefront()->reservedScalarRegs);
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return -1;
+ }
+ }
+
+ // --- Inst_DS base class methods ---
+
+ Inst_DS::Inst_DS(InFmt_DS *iFmt, const std::string &opcode)
+ : GCN3GPUStaticInst(opcode)
+ {
+ setFlag(GroupSegment);
+
+ // copy first instruction DWORD
+ instData = iFmt[0];
+ // copy second instruction DWORD
+ extData = ((InFmt_DS_1 *)iFmt)[1];
+ _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
+ } // Inst_DS
+
+ Inst_DS::~Inst_DS()
+ {
+ } // ~Inst_DS
+
+ int
+ Inst_DS::instSize() const
+ {
+ return 8;
+ } // instSize
+
+ void
+ Inst_DS::generateDisassembly()
+ {
+ std::stringstream dis_stream;
+ dis_stream << _opcode << " ";
+
+ if (numDstRegOperands())
+ dis_stream << "v" << extData.VDST << ", ";
+
+ dis_stream << "v" << extData.ADDR;
+
+ if (numSrcRegOperands() > 1)
+ dis_stream << ", v" << extData.DATA0;
+
+ if (numSrcRegOperands() > 2)
+ dis_stream << ", v" << extData.DATA1;
+
+ uint16_t offset = 0;
+
+ if (instData.OFFSET1) {
+ offset += instData.OFFSET1;
+ offset <<= 8;
+ }
+
+ if (instData.OFFSET0)
+ offset += instData.OFFSET0;
+
+ if (offset)
+ dis_stream << " offset:" << offset;
+
+ disassembly = dis_stream.str();
+ }
+
+ bool
+ Inst_DS::isScalarRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ // DS instructions cannot access SGPRs
+ return false;
+ }
+
+ bool
+ Inst_DS::isVectorRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ // DS instructions only access VGPRs
+ return true;
+ }
+
+ int
+ Inst_DS::getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ return extData.ADDR;
+ case 1:
+ if (numSrcRegOperands() > 1) {
+ return extData.DATA0;
+ } else if (numDstRegOperands()) {
+ return extData.VDST;
+ }
+ case 2:
+ if (numSrcRegOperands() > 2) {
+ return extData.DATA1;
+ } else if (numDstRegOperands()) {
+ return extData.VDST;
+ }
+ case 3:
+ assert(numDstRegOperands());
+ return extData.VDST;
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return -1;
+ }
+ }
+
+ // --- Inst_MUBUF base class methods ---
+
+ Inst_MUBUF::Inst_MUBUF(InFmt_MUBUF *iFmt, const std::string &opcode)
+ : GCN3GPUStaticInst(opcode)
+ {
+ // copy first instruction DWORD
+ instData = iFmt[0];
+ // copy second instruction DWORD
+ extData = ((InFmt_MUBUF_1 *)iFmt)[1];
+ _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
+
+ if (instData.GLC)
+ setFlag(GloballyCoherent);
+
+ if (instData.SLC)
+ setFlag(SystemCoherent);
+ } // Inst_MUBUF
+
+ Inst_MUBUF::~Inst_MUBUF()
+ {
+ } // ~Inst_MUBUF
+
+ int
+ Inst_MUBUF::instSize() const
+ {
+ return 8;
+ } // instSize
+
+ void
+ Inst_MUBUF::generateDisassembly()
+ {
+ // SRSRC is always in units of 4 SGPRs
+ int srsrc_val = extData.SRSRC * 4;
+ std::stringstream dis_stream;
+ dis_stream << _opcode << " ";
+ dis_stream << "v" << extData.VDATA << ", v" << extData.VADDR << ", ";
+ dis_stream << "s[" << srsrc_val << ":"
+ << srsrc_val + 3 << "], ";
+ dis_stream << "s" << extData.SOFFSET;
+
+ if (instData.OFFSET)
+ dis_stream << ", offset:" << instData.OFFSET;
+
+ disassembly = dis_stream.str();
+ }
+
+ bool
+ Inst_MUBUF::isScalarRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ return false;
+ case 1:
+ return true;
+ case 2:
+ return true;
+ case 3:
+ return false;
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return false;
+ }
+ }
+
+ bool
+ Inst_MUBUF::isVectorRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ return true;
+ case 1:
+ return false;
+ case 2:
+ return false;
+ case 3:
+ return true;
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return false;
+ }
+ }
+
+ int
+ Inst_MUBUF::getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ return extData.VADDR;
+ case 1:
+ // SRSRC is always in units of 4 SGPRs
+ return extData.SRSRC * 4;
+ case 2:
+ return extData.SOFFSET;
+ case 3:
+ return extData.VDATA;
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return -1;
+ }
+ }
+
+ // --- Inst_MTBUF base class methods ---
+
+ Inst_MTBUF::Inst_MTBUF(InFmt_MTBUF *iFmt, const std::string &opcode)
+ : GCN3GPUStaticInst(opcode)
+ {
+ // copy first instruction DWORD
+ instData = iFmt[0];
+ // copy second instruction DWORD
+ extData = ((InFmt_MTBUF_1 *)iFmt)[1];
+ _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
+
+ if (instData.GLC)
+ setFlag(GloballyCoherent);
+
+ if (extData.SLC)
+ setFlag(SystemCoherent);
+
+ } // Inst_MTBUF
+
+ Inst_MTBUF::~Inst_MTBUF()
+ {
+ } // ~Inst_MTBUF
+
+ int
+ Inst_MTBUF::instSize() const
+ {
+ return 8;
+ } // instSize
+
+ // --- Inst_MIMG base class methods ---
+
+ Inst_MIMG::Inst_MIMG(InFmt_MIMG *iFmt, const std::string &opcode)
+ : GCN3GPUStaticInst(opcode)
+ {
+ // copy first instruction DWORD
+ instData = iFmt[0];
+ // copy second instruction DWORD
+ extData = ((InFmt_MIMG_1 *)iFmt)[1];
+ _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
+
+ if (instData.GLC)
+ setFlag(GloballyCoherent);
+
+ if (instData.SLC)
+ setFlag(SystemCoherent);
+ } // Inst_MIMG
+
+ Inst_MIMG::~Inst_MIMG()
+ {
+ } // ~Inst_MIMG
+
+ int
+ Inst_MIMG::instSize() const
+ {
+ return 8;
+ } // instSize
+
+ // --- Inst_EXP base class methods ---
+
+ Inst_EXP::Inst_EXP(InFmt_EXP *iFmt, const std::string &opcode)
+ : GCN3GPUStaticInst(opcode)
+ {
+ // copy first instruction DWORD
+ instData = iFmt[0];
+ // copy second instruction DWORD
+ extData = ((InFmt_EXP_1 *)iFmt)[1];
+ _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
+ } // Inst_EXP
+
+ Inst_EXP::~Inst_EXP()
+ {
+ } // ~Inst_EXP
+
+ int
+ Inst_EXP::instSize() const
+ {
+ return 8;
+ } // instSize
+
+ // --- Inst_FLAT base class methods ---
+
+ Inst_FLAT::Inst_FLAT(InFmt_FLAT *iFmt, const std::string &opcode)
+ : GCN3GPUStaticInst(opcode)
+ {
+ setFlag(Flat);
+ // copy first instruction DWORD
+ instData = iFmt[0];
+ // copy second instruction DWORD
+ extData = ((InFmt_FLAT_1 *)iFmt)[1];
+ _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
+
+ if (instData.GLC)
+ setFlag(GloballyCoherent);
+
+ if (instData.SLC)
+ setFlag(SystemCoherent);
+ } // Inst_FLAT
+
+ Inst_FLAT::~Inst_FLAT()
+ {
+ } // ~Inst_FLAT
+
+ int
+ Inst_FLAT::instSize() const
+ {
+ return 8;
+ } // instSize
+
+ void
+ Inst_FLAT::generateDisassembly()
+ {
+ std::stringstream dis_stream;
+ dis_stream << _opcode << " ";
+
+ if (isLoad())
+ dis_stream << "v" << extData.VDST << ", ";
+
+ dis_stream << "v[" << extData.ADDR << ":" << extData.ADDR + 1 << "]";
+
+ if (isStore())
+ dis_stream << ", v" << extData.DATA;
+
+ disassembly = dis_stream.str();
+ }
+
+ bool
+ Inst_FLAT::isScalarRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ // if a FLAT instruction has more than two
+ // operands it must be an atomic
+ if (opIdx == 2)
+ assert(isAtomic());
+
+ // FLAT instructions cannot access SGPRs
+ return false;
+ }
+
+ bool
+ Inst_FLAT::isVectorRegister(int opIdx)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ // if a FLAT instruction has more than two
+ // operands it must be an atomic
+ if (opIdx == 2)
+ assert(isAtomic());
+
+ // FLAT instructions only access VGPRs
+ return true;
+ }
+
+ int
+ Inst_FLAT::getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst)
+ {
+ assert(opIdx >= 0);
+ assert(opIdx < getNumOperands());
+
+ switch (opIdx) {
+ case 0:
+ return extData.ADDR;
+ case 1:
+ if (isStore()) {
+ return extData.DATA;
+ } else if (isLoad()) {
+ return extData.VDST;
+ } else if (isAtomic()) {
+ // For flat_atomic instructions,
+ // the DATA VGPR gives the source
+ return extData.DATA;
+ } else {
+ fatal("Unsupported flat instr type\n");
+ }
+ case 2:
+ // if a FLAT instruction has more than two
+ // operands it must be an atomic
+ assert(isAtomic());
+ return extData.VDST;
+ default:
+ fatal("Operand at idx %i does not exist\n", opIdx);
+ return -1;
+ }
+ }
+} // namespace Gcn3ISA
diff --git a/src/arch/gcn3/insts/op_encodings.hh b/src/arch/gcn3/insts/op_encodings.hh
new file mode 100644
index 0000000..8bb49c0
--- /dev/null
+++ b/src/arch/gcn3/insts/op_encodings.hh
@@ -0,0 +1,916 @@
+/*
+ * Copyright (c) 2016-2017 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * For use for simulation and test purposes only
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Anthony Gutierrez
+ */
+
+#ifndef __ARCH_GCN3_INSTS_OP_ENCODINGS_HH__
+#define __ARCH_GCN3_INSTS_OP_ENCODINGS_HH__
+
+#include "arch/gcn3/gpu_decoder.hh"
+#include "arch/gcn3/insts/gpu_static_inst.hh"
+#include "arch/gcn3/operand.hh"
+#include "debug/GPUExec.hh"
+#include "mem/ruby/system/RubySystem.hh"
+
+namespace Gcn3ISA
+{
+ // --- purely virtual instruction classes ---
+
+ class Inst_SOP2 : public GCN3GPUStaticInst
+ {
+ public:
+ Inst_SOP2(InFmt_SOP2*, const std::string &opcode);
+
+ int instSize() const override;
+ void generateDisassembly() override;
+
+ bool isScalarRegister(int opIdx) override;
+ bool isVectorRegister(int opIdx) override;
+ int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
+
+ protected:
+ // first instruction DWORD
+ InFmt_SOP2 instData;
+ // possible second DWORD
+ InstFormat extData;
+ uint32_t varSize;
+
+ private:
+ bool hasSecondDword(InFmt_SOP2 *);
+ }; // Inst_SOP2
+
+ class Inst_SOPK : public GCN3GPUStaticInst
+ {
+ public:
+ Inst_SOPK(InFmt_SOPK*, const std::string &opcode);
+ ~Inst_SOPK();
+
+ int instSize() const override;
+ void generateDisassembly() override;
+
+ bool isScalarRegister(int opIdx) override;
+ bool isVectorRegister(int opIdx) override;
+ int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
+
+ protected:
+ // first instruction DWORD
+ InFmt_SOPK instData;
+ }; // Inst_SOPK
+
+ class Inst_SOP1 : public GCN3GPUStaticInst
+ {
+ public:
+ Inst_SOP1(InFmt_SOP1*, const std::string &opcode);
+ ~Inst_SOP1();
+
+ int instSize() const override;
+ void generateDisassembly() override;
+
+ bool isScalarRegister(int opIdx) override;
+ bool isVectorRegister(int opIdx) override;
+ int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
+
+ protected:
+ // first instruction DWORD
+ InFmt_SOP1 instData;
+ // possible second DWORD
+ InstFormat extData;
+ uint32_t varSize;
+
+ private:
+ bool hasSecondDword(InFmt_SOP1 *);
+ }; // Inst_SOP1
+
+ class Inst_SOPC : public GCN3GPUStaticInst
+ {
+ public:
+ Inst_SOPC(InFmt_SOPC*, const std::string &opcode);
+ ~Inst_SOPC();
+
+ int instSize() const override;
+ void generateDisassembly() override;
+
+ bool isScalarRegister(int opIdx) override;
+ bool isVectorRegister(int opIdx) override;
+ int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
+
+ protected:
+ // first instruction DWORD
+ InFmt_SOPC instData;
+ // possible second DWORD
+ InstFormat extData;
+ uint32_t varSize;
+
+ private:
+ bool hasSecondDword(InFmt_SOPC *);
+ }; // Inst_SOPC
+
+ class Inst_SOPP : public GCN3GPUStaticInst
+ {
+ public:
+ Inst_SOPP(InFmt_SOPP*, const std::string &opcode);
+ ~Inst_SOPP();
+
+ int instSize() const override;
+ void generateDisassembly() override;
+
+ bool isScalarRegister(int opIdx) override;
+ bool isVectorRegister(int opIdx) override;
+ int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
+
+ protected:
+ // first instruction DWORD
+ InFmt_SOPP instData;
+ }; // Inst_SOPP
+
+ class Inst_SMEM : public GCN3GPUStaticInst
+ {
+ public:
+ Inst_SMEM(InFmt_SMEM*, const std::string &opcode);
+ ~Inst_SMEM();
+
+ int instSize() const override;
+ void generateDisassembly() override;
+
+ bool isScalarRegister(int opIdx) override;
+ bool isVectorRegister(int opIdx) override;
+ int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
+
+ protected:
+ /**
+ * initiate a memory read access for N dwords
+ */
+ template<int N>
+ void
+ initMemRead(GPUDynInstPtr gpuDynInst)
+ {
+ int block_size = gpuDynInst->computeUnit()->cacheLineSize();
+ int req_size = N * sizeof(ScalarRegU32);
+ Addr vaddr = gpuDynInst->scalarAddr;
+
+ /**
+ * the base address of the cache line where the the last byte of
+ * the request will be stored.
+ */
+ Addr split_addr = roundDown(vaddr + req_size - 1, block_size);
+
+ assert(split_addr <= vaddr || split_addr - vaddr < block_size);
+ /**
+ * if the base cache line address of the last byte is greater
+ * than the address of the first byte then we have a misaligned
+ * access.
+ */
+ bool misaligned_acc = split_addr > vaddr;
+
+ RequestPtr req = new Request(0, vaddr, req_size, 0,
+ gpuDynInst->computeUnit()->masterId(), 0,
+ gpuDynInst->wfDynId);
+
+ if (misaligned_acc) {
+ RequestPtr req1, req2;
+ req->splitOnVaddr(split_addr, req1, req2);
+ gpuDynInst->numScalarReqs = 2;
+ gpuDynInst->setRequestFlags(req1);
+ gpuDynInst->setRequestFlags(req2);
+ PacketPtr pkt1 = new Packet(req1, MemCmd::ReadReq);
+ PacketPtr pkt2 = new Packet(req2, MemCmd::ReadReq);
+ pkt1->dataStatic(gpuDynInst->scalar_data);
+ pkt2->dataStatic(gpuDynInst->scalar_data + req1->getSize());
+ gpuDynInst->computeUnit()->sendScalarRequest(gpuDynInst, pkt1);
+ gpuDynInst->computeUnit()->sendScalarRequest(gpuDynInst, pkt2);
+ delete req;
+ } else {
+ gpuDynInst->numScalarReqs = 1;
+ gpuDynInst->setRequestFlags(req);
+ PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
+ pkt->dataStatic(gpuDynInst->scalar_data);
+ gpuDynInst->computeUnit()->sendScalarRequest(gpuDynInst, pkt);
+ }
+ }
+
+ /**
+ * initiate a memory write access for N dwords
+ */
+ template<int N>
+ void
+ initMemWrite(GPUDynInstPtr gpuDynInst)
+ {
+ int block_size = gpuDynInst->computeUnit()->cacheLineSize();
+ int req_size = N * sizeof(ScalarRegU32);
+ Addr vaddr = gpuDynInst->scalarAddr;
+
+ /**
+ * the base address of the cache line where the the last byte of
+ * the request will be stored.
+ */
+ Addr split_addr = roundDown(vaddr + req_size - 1, block_size);
+
+ assert(split_addr <= vaddr || split_addr - vaddr < block_size);
+ /**
+ * if the base cache line address of the last byte is greater
+ * than the address of the first byte then we have a misaligned
+ * access.
+ */
+ bool misaligned_acc = split_addr > vaddr;
+
+ RequestPtr req = new Request(0, vaddr, req_size, 0,
+ gpuDynInst->computeUnit()->masterId(), 0,
+ gpuDynInst->wfDynId);
+
+ if (misaligned_acc) {
+ RequestPtr req1, req2;
+ req->splitOnVaddr(split_addr, req1, req2);
+ gpuDynInst->numScalarReqs = 2;
+ gpuDynInst->setRequestFlags(req1);
+ gpuDynInst->setRequestFlags(req2);
+ PacketPtr pkt1 = new Packet(req1, MemCmd::WriteReq);
+ PacketPtr pkt2 = new Packet(req2, MemCmd::WriteReq);
+ pkt1->dataStatic(gpuDynInst->scalar_data);
+ pkt2->dataStatic(gpuDynInst->scalar_data + req1->getSize());
+ gpuDynInst->computeUnit()->sendScalarRequest(gpuDynInst, pkt1);
+ gpuDynInst->computeUnit()->sendScalarRequest(gpuDynInst, pkt2);
+ delete req;
+ } else {
+ gpuDynInst->numScalarReqs = 1;
+ gpuDynInst->setRequestFlags(req);
+ PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
+ pkt->dataStatic(gpuDynInst->scalar_data);
+ gpuDynInst->computeUnit()->sendScalarRequest(gpuDynInst, pkt);
+ }
+ }
+
+ void
+ calcAddr(GPUDynInstPtr gpuDynInst, ConstScalarOperandU64 &addr,
+ ScalarRegU32 offset)
+ {
+ Addr vaddr = addr.rawData();
+ vaddr += offset;
+ vaddr &= ~0x3;
+ gpuDynInst->scalarAddr = vaddr;
+ }
+
+ // first instruction DWORD
+ InFmt_SMEM instData;
+ // second instruction DWORD
+ InFmt_SMEM_1 extData;
+ }; // Inst_SMEM
+
+ class Inst_VOP2 : public GCN3GPUStaticInst
+ {
+ public:
+ Inst_VOP2(InFmt_VOP2*, const std::string &opcode);
+ ~Inst_VOP2();
+
+ int instSize() const override;
+ void generateDisassembly() override;
+
+ bool isScalarRegister(int opIdx) override;
+ bool isVectorRegister(int opIdx) override;
+ int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
+
+ protected:
+ // first instruction DWORD
+ InFmt_VOP2 instData;
+ // possible second DWORD
+ InstFormat extData;
+ uint32_t varSize;
+
+ private:
+ bool hasSecondDword(InFmt_VOP2 *);
+ }; // Inst_VOP2
+
+ class Inst_VOP1 : public GCN3GPUStaticInst
+ {
+ public:
+ Inst_VOP1(InFmt_VOP1*, const std::string &opcode);
+ ~Inst_VOP1();
+
+ int instSize() const override;
+ void generateDisassembly() override;
+
+ bool isScalarRegister(int opIdx) override;
+ bool isVectorRegister(int opIdx) override;
+ int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
+
+ protected:
+ // first instruction DWORD
+ InFmt_VOP1 instData;
+ // possible second DWORD
+ InstFormat extData;
+ uint32_t varSize;
+
+ private:
+ bool hasSecondDword(InFmt_VOP1 *);
+ }; // Inst_VOP1
+
+ class Inst_VOPC : public GCN3GPUStaticInst
+ {
+ public:
+ Inst_VOPC(InFmt_VOPC*, const std::string &opcode);
+ ~Inst_VOPC();
+
+ int instSize() const override;
+ void generateDisassembly() override;
+
+ bool isScalarRegister(int opIdx) override;
+ bool isVectorRegister(int opIdx) override;
+ int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
+
+ protected:
+ // first instruction DWORD
+ InFmt_VOPC instData;
+ // possible second DWORD
+ InstFormat extData;
+ uint32_t varSize;
+
+ private:
+ bool hasSecondDword(InFmt_VOPC *);
+ }; // Inst_VOPC
+
+ class Inst_VINTRP : public GCN3GPUStaticInst
+ {
+ public:
+ Inst_VINTRP(InFmt_VINTRP*, const std::string &opcode);
+ ~Inst_VINTRP();
+
+ int instSize() const override;
+
+ protected:
+ // first instruction DWORD
+ InFmt_VINTRP instData;
+ }; // Inst_VINTRP
+
+ class Inst_VOP3 : public GCN3GPUStaticInst
+ {
+ public:
+ Inst_VOP3(InFmt_VOP3*, const std::string &opcode, bool sgpr_dst);
+ ~Inst_VOP3();
+
+ int instSize() const override;
+ void generateDisassembly() override;
+
+ bool isScalarRegister(int opIdx) override;
+ bool isVectorRegister(int opIdx) override;
+ int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
+
+ protected:
+ // first instruction DWORD
+ InFmt_VOP3 instData;
+ // second instruction DWORD
+ InFmt_VOP3_1 extData;
+
+ private:
+ bool hasSecondDword(InFmt_VOP3 *);
+ /**
+ * the v_cmp and readlane instructions in the VOP3
+ * encoding are unique because they are the only
+ * instructions that use the VDST field to specify
+ * a scalar register destination. for VOP3::V_CMP insts
+ * VDST specifies the arbitrary SGPR pair used to write
+ * VCC. for V_READLANE VDST specifies the SGPR to return
+ * the value of the selected lane in the source VGPR
+ * from which we are reading.
+ */
+ const bool sgprDst;
+ }; // Inst_VOP3
+
+ class Inst_VOP3_SDST_ENC : public GCN3GPUStaticInst
+ {
+ public:
+ Inst_VOP3_SDST_ENC(InFmt_VOP3_SDST_ENC*, const std::string &opcode);
+ ~Inst_VOP3_SDST_ENC();
+
+ int instSize() const override;
+ void generateDisassembly() override;
+
+ bool isScalarRegister(int opIdx) override;
+ bool isVectorRegister(int opIdx) override;
+ int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
+
+ protected:
+ // first instruction DWORD
+ InFmt_VOP3_SDST_ENC instData;
+ // second instruction DWORD
+ InFmt_VOP3_1 extData;
+
+ private:
+ bool hasSecondDword(InFmt_VOP3_SDST_ENC *);
+ }; // Inst_VOP3_SDST_ENC
+
+ class Inst_DS : public GCN3GPUStaticInst
+ {
+ public:
+ Inst_DS(InFmt_DS*, const std::string &opcode);
+ ~Inst_DS();
+
+ int instSize() const override;
+ void generateDisassembly() override;
+
+ bool isScalarRegister(int opIdx) override;
+ bool isVectorRegister(int opIdx) override;
+ int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
+
+ protected:
+ template<typename T>
+ void
+ initMemRead(GPUDynInstPtr gpuDynInst, Addr offset)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ Addr vaddr = gpuDynInst->addr[lane] + offset;
+
+ (reinterpret_cast<T*>(gpuDynInst->d_data))[lane]
+ = wf->ldsChunk->read<T>(vaddr);
+ }
+ }
+ }
+
+ template<typename T>
+ void
+ initDualMemRead(GPUDynInstPtr gpuDynInst, Addr offset0, Addr offset1)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ Addr vaddr0 = gpuDynInst->addr[lane] + offset0;
+ Addr vaddr1 = gpuDynInst->addr[lane] + offset1;
+
+ (reinterpret_cast<T*>(gpuDynInst->d_data))[lane * 2]
+ = wf->ldsChunk->read<T>(vaddr0);
+ (reinterpret_cast<T*>(gpuDynInst->d_data))[lane * 2 + 1]
+ = wf->ldsChunk->read<T>(vaddr1);
+ }
+ }
+ }
+
+ template<typename T>
+ void
+ initMemWrite(GPUDynInstPtr gpuDynInst, Addr offset)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ Addr vaddr = gpuDynInst->addr[lane] + offset;
+ wf->ldsChunk->write<T>(vaddr,
+ (reinterpret_cast<T*>(gpuDynInst->d_data))[lane]);
+ }
+ }
+ }
+
+ template<typename T>
+ void
+ initDualMemWrite(GPUDynInstPtr gpuDynInst, Addr offset0, Addr offset1)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ Addr vaddr0 = gpuDynInst->addr[lane] + offset0;
+ Addr vaddr1 = gpuDynInst->addr[lane] + offset1;
+ wf->ldsChunk->write<T>(vaddr0, (reinterpret_cast<T*>(
+ gpuDynInst->d_data))[lane * 2]);
+ wf->ldsChunk->write<T>(vaddr1, (reinterpret_cast<T*>(
+ gpuDynInst->d_data))[lane * 2 + 1]);
+ }
+ }
+ }
+
+ void
+ calcAddr(GPUDynInstPtr gpuDynInst, ConstVecOperandU32 &addr)
+ {
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (wf->execMask(lane)) {
+ gpuDynInst->addr.at(lane) = (Addr)addr[lane];
+ }
+ }
+ }
+
+ // first instruction DWORD
+ InFmt_DS instData;
+ // second instruction DWORD
+ InFmt_DS_1 extData;
+ }; // Inst_DS
+
+ class Inst_MUBUF : public GCN3GPUStaticInst
+ {
+ public:
+ Inst_MUBUF(InFmt_MUBUF*, const std::string &opcode);
+ ~Inst_MUBUF();
+
+ int instSize() const override;
+ void generateDisassembly() override;
+
+ bool isScalarRegister(int opIdx) override;
+ bool isVectorRegister(int opIdx) override;
+ int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
+
+ protected:
+ struct BufferRsrcDescriptor
+ {
+ uint64_t baseAddr : 48;
+ uint32_t stride : 14;
+ uint32_t cacheSwizzle : 1;
+ uint32_t swizzleEn : 1;
+ uint32_t numRecords : 32;
+ uint32_t dstSelX : 3;
+ uint32_t dstSelY : 3;
+ uint32_t dstSelZ : 3;
+ uint32_t dstSelW : 3;
+ uint32_t numFmt : 3;
+ uint32_t dataFmt : 4;
+ uint32_t elemSize : 2;
+ uint32_t idxStride : 2;
+ uint32_t addTidEn : 1;
+ uint32_t atc : 1;
+ uint32_t hashEn : 1;
+ uint32_t heap : 1;
+ uint32_t mType : 3;
+ uint32_t type : 2;
+ };
+
+ template<typename T>
+ void
+ initMemRead(GPUDynInstPtr gpuDynInst)
+ {
+ gpuDynInst->statusBitVector = gpuDynInst->exec_mask;
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ Addr vaddr = gpuDynInst->addr[lane];
+
+ RequestPtr req = new Request(0, vaddr, sizeof(T), 0,
+ gpuDynInst->computeUnit()->masterId(), 0,
+ gpuDynInst->wfDynId);
+
+ gpuDynInst->setRequestFlags(req);
+
+ PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
+ pkt->dataStatic(&(reinterpret_cast<T*>(
+ gpuDynInst->d_data))[lane]);
+
+ gpuDynInst->computeUnit()->sendRequest(gpuDynInst, lane,
+ pkt);
+ }
+ }
+ }
+
+ template<typename T>
+ void
+ initMemWrite(GPUDynInstPtr gpuDynInst)
+ {
+ gpuDynInst->statusBitVector = gpuDynInst->exec_mask;
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ Addr vaddr = gpuDynInst->addr[lane];
+
+ RequestPtr req = new Request(0, vaddr, sizeof(T), 0,
+ gpuDynInst->computeUnit()->masterId(),
+ 0, gpuDynInst->wfDynId);
+
+ gpuDynInst->setRequestFlags(req);
+ PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
+ pkt->dataStatic(&(reinterpret_cast<T*>(
+ gpuDynInst->d_data))[lane]);
+ gpuDynInst->computeUnit()->sendRequest(gpuDynInst, lane,
+ pkt);
+ }
+ }
+ }
+
+ void
+ injectGlobalMemFence(GPUDynInstPtr gpuDynInst)
+ {
+ // create request and set flags
+ gpuDynInst->statusBitVector = VectorMask(1);
+ Request *req = new Request(0, 0, 0, 0,
+ gpuDynInst->computeUnit()->
+ masterId(), 0,
+ gpuDynInst->wfDynId);
+ gpuDynInst->setRequestFlags(req);
+ gpuDynInst->computeUnit()->
+ injectGlobalMemFence(gpuDynInst, false, req);
+ }
+
+ /**
+ * MUBUF insructions calculate their addresses as follows:
+ *
+ * index = (IDXEN ? vgpr_idx : 0) + (const_add_tid_en ? TID : 0)
+ * offset = (OFFEN ? vgpr_off : 0) + inst_off
+ *
+ * / ====================== LINEAR ADDRESSING ====================== /
+ * VADDR = base + sgpr_off + offset + stride * index
+ *
+ * / ===================== SWIZZLED ADDRESSING ===================== /
+ * index_msb = index / const_index_stride
+ * index_lsb = index % const_index_stride
+ * offset_msb = offset / const_element_size
+ * offset_lsb = offset % const_element_size
+ * buffer_offset = ((index_msb * stride + offset_msb *
+ * const_element_size) * const_index_stride +
+ * index_lsb * const_element_size + offset_lsb)
+ *
+ * VADDR = base + sgpr_off + buffer_offset
+ */
+ template<typename VOFF, typename VIDX, typename SRSRC, typename SOFF>
+ void
+ calcAddr(GPUDynInstPtr gpuDynInst, VOFF v_off, VIDX v_idx,
+ SRSRC s_rsrc_desc, SOFF s_offset, int inst_offset)
+ {
+ Addr vaddr = 0;
+ Addr base_addr = 0;
+ Addr stride = 0;
+ Addr buf_idx = 0;
+ Addr buf_off = 0;
+ BufferRsrcDescriptor rsrc_desc;
+
+ std::memcpy((void*)&rsrc_desc, s_rsrc_desc.rawDataPtr(),
+ sizeof(BufferRsrcDescriptor));
+
+ base_addr = rsrc_desc.baseAddr;
+
+ stride = rsrc_desc.addTidEn ? ((rsrc_desc.dataFmt << 14)
+ + rsrc_desc.stride) : rsrc_desc.stride;
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ vaddr = base_addr + s_offset.rawData();
+ /**
+ * first we calculate the buffer's index and offset.
+ * these will be used for either linear or swizzled
+ * buffers.
+ */
+ buf_idx = v_idx[lane] + (rsrc_desc.addTidEn ? lane : 0);
+
+ buf_off = v_off[lane] + inst_offset;
+
+ if (rsrc_desc.swizzleEn) {
+ Addr idx_stride = 8 << rsrc_desc.idxStride;
+ Addr elem_size = 2 << rsrc_desc.elemSize;
+ Addr idx_msb = buf_idx / idx_stride;
+ Addr idx_lsb = buf_idx % idx_stride;
+ Addr off_msb = buf_off / elem_size;
+ Addr off_lsb = buf_off % elem_size;
+
+ vaddr += ((idx_msb * stride + off_msb * elem_size)
+ * idx_stride + idx_lsb * elem_size + off_lsb);
+ } else {
+ vaddr += buf_off + stride * buf_idx;
+ }
+
+ gpuDynInst->addr.at(lane) = vaddr;
+ }
+ }
+ }
+
+ // first instruction DWORD
+ InFmt_MUBUF instData;
+ // second instruction DWORD
+ InFmt_MUBUF_1 extData;
+ }; // Inst_MUBUF
+
+ class Inst_MTBUF : public GCN3GPUStaticInst
+ {
+ public:
+ Inst_MTBUF(InFmt_MTBUF*, const std::string &opcode);
+ ~Inst_MTBUF();
+
+ int instSize() const override;
+
+ protected:
+ // first instruction DWORD
+ InFmt_MTBUF instData;
+ // second instruction DWORD
+ InFmt_MTBUF_1 extData;
+
+ private:
+ bool hasSecondDword(InFmt_MTBUF *);
+ }; // Inst_MTBUF
+
+ class Inst_MIMG : public GCN3GPUStaticInst
+ {
+ public:
+ Inst_MIMG(InFmt_MIMG*, const std::string &opcode);
+ ~Inst_MIMG();
+
+ int instSize() const override;
+
+ protected:
+ // first instruction DWORD
+ InFmt_MIMG instData;
+ // second instruction DWORD
+ InFmt_MIMG_1 extData;
+ }; // Inst_MIMG
+
+ class Inst_EXP : public GCN3GPUStaticInst
+ {
+ public:
+ Inst_EXP(InFmt_EXP*, const std::string &opcode);
+ ~Inst_EXP();
+
+ int instSize() const override;
+
+ protected:
+ // first instruction DWORD
+ InFmt_EXP instData;
+ // second instruction DWORD
+ InFmt_EXP_1 extData;
+ }; // Inst_EXP
+
+ class Inst_FLAT : public GCN3GPUStaticInst
+ {
+ public:
+ Inst_FLAT(InFmt_FLAT*, const std::string &opcode);
+ ~Inst_FLAT();
+
+ int instSize() const override;
+ void generateDisassembly() override;
+
+ bool isScalarRegister(int opIdx) override;
+ bool isVectorRegister(int opIdx) override;
+ int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override;
+
+ protected:
+ template<typename T>
+ void
+ initMemRead(GPUDynInstPtr gpuDynInst)
+ {
+ gpuDynInst->statusBitVector = gpuDynInst->exec_mask;
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ Addr vaddr = gpuDynInst->addr[lane];
+
+ RequestPtr req = new Request(0, vaddr, sizeof(T), 0,
+ gpuDynInst->computeUnit()->masterId(), 0,
+ gpuDynInst->wfDynId);
+
+ gpuDynInst->setRequestFlags(req);
+ PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
+ pkt->dataStatic(&(reinterpret_cast<T*>(
+ gpuDynInst->d_data))[lane]);
+ gpuDynInst->computeUnit()
+ ->sendRequest(gpuDynInst, lane, pkt);
+ }
+ }
+ }
+
+ template<int N>
+ void
+ initMemRead(GPUDynInstPtr gpuDynInst)
+ {
+ int req_size = N * sizeof(VecElemU32);
+ gpuDynInst->statusBitVector = gpuDynInst->exec_mask;
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ Addr vaddr = gpuDynInst->addr[lane];
+
+ RequestPtr req = new Request(0, vaddr, req_size, 0,
+ gpuDynInst->computeUnit()->masterId(), 0,
+ gpuDynInst->wfDynId);
+
+ gpuDynInst->setRequestFlags(req);
+ PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
+ pkt->dataStatic(&(reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane * N]);
+ gpuDynInst->computeUnit()
+ ->sendRequest(gpuDynInst, lane, pkt);
+ }
+ }
+ }
+
+ template<typename T>
+ void
+ initMemWrite(GPUDynInstPtr gpuDynInst)
+ {
+ gpuDynInst->statusBitVector = gpuDynInst->exec_mask;
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ Addr vaddr = gpuDynInst->addr[lane];
+
+ RequestPtr req = new Request(0, vaddr, sizeof(T), 0,
+ gpuDynInst->computeUnit()->masterId(),
+ 0, gpuDynInst->wfDynId);
+
+ gpuDynInst->setRequestFlags(req);
+ PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
+ pkt->dataStatic(&(reinterpret_cast<T*>(
+ gpuDynInst->d_data))[lane]);
+ gpuDynInst->computeUnit()->sendRequest(gpuDynInst, lane,
+ pkt);
+ }
+ }
+ }
+
+ template<int N>
+ void
+ initMemWrite(GPUDynInstPtr gpuDynInst)
+ {
+ int req_size = N * sizeof(VecElemU32);
+ gpuDynInst->statusBitVector = gpuDynInst->exec_mask;
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ Addr vaddr = gpuDynInst->addr[lane];
+
+ RequestPtr req = new Request(0, vaddr, req_size, 0,
+ gpuDynInst->computeUnit()->masterId(),
+ 0, gpuDynInst->wfDynId);
+
+ gpuDynInst->setRequestFlags(req);
+ PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
+ pkt->dataStatic(&(reinterpret_cast<VecElemU32*>(
+ gpuDynInst->d_data))[lane * N]);
+ gpuDynInst->computeUnit()->sendRequest(gpuDynInst, lane,
+ pkt);
+ }
+ }
+ }
+
+ template<typename T>
+ void
+ initAtomicAccess(GPUDynInstPtr gpuDynInst)
+ {
+ gpuDynInst->statusBitVector = gpuDynInst->exec_mask;
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ Addr vaddr = gpuDynInst->addr[lane];
+
+ RequestPtr req = new Request(0, vaddr, sizeof(T), 0,
+ gpuDynInst->computeUnit()->masterId(), 0,
+ gpuDynInst->wfDynId,
+ gpuDynInst->makeAtomicOpFunctor<T>(
+ &(reinterpret_cast<T*>(gpuDynInst->a_data))[lane],
+ &(reinterpret_cast<T*>(
+ gpuDynInst->x_data))[lane]));
+
+ gpuDynInst->setRequestFlags(req);
+
+ PacketPtr pkt = new Packet(req, MemCmd::SwapReq);
+ pkt->dataStatic(&(reinterpret_cast<T*>(
+ gpuDynInst->d_data))[lane]);
+
+ gpuDynInst->computeUnit()->sendRequest(gpuDynInst, lane,
+ pkt);
+ }
+ }
+ }
+
+ void
+ calcAddr(GPUDynInstPtr gpuDynInst, ConstVecOperandU64 &addr)
+ {
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ gpuDynInst->addr.at(lane) = addr[lane];
+ }
+ }
+ gpuDynInst->resolveFlatSegment(gpuDynInst->exec_mask);
+ }
+
+ // first instruction DWORD
+ InFmt_FLAT instData;
+ // second instruction DWORD
+ InFmt_FLAT_1 extData;
+ }; // Inst_FLAT
+} // namespace Gcn3ISA
+
+#endif // __ARCH_GCN3_INSTS_OP_ENCODINGS_HH__
diff --git a/src/arch/gcn3/isa.cc b/src/arch/gcn3/isa.cc
new file mode 100644
index 0000000..036c771
--- /dev/null
+++ b/src/arch/gcn3/isa.cc
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2016-2017 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * For use for simulation and test purposes only
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Anthony Gutierrez
+ */
+
+#include "arch/gcn3/gpu_isa.hh"
+
+#include <numeric>
+
+#include "gpu-compute/gpu_static_inst.hh"
+#include "gpu-compute/wavefront.hh"
+
+namespace Gcn3ISA
+{
+ GPUISA::GPUISA(Wavefront &wf) : wavefront(wf), m0(0)
+ {
+ }
+
+ ScalarRegU32
+ GPUISA::readMiscReg(int opIdx) const
+ {
+ if (opIdx >= REG_INT_CONST_POS_MIN && opIdx <= REG_INT_CONST_POS_MAX) {
+ return readPosConstReg(opIdx);
+ }
+
+ if (opIdx >= REG_INT_CONST_NEG_MIN && opIdx <= REG_INT_CONST_NEG_MAX) {
+ return readNegConstReg(opIdx);
+ }
+
+ switch (opIdx) {
+ case REG_M0:
+ return m0;
+ case REG_ZERO:
+ return 0;
+ case REG_SCC:
+ return statusReg.SCC;
+ default:
+ fatal("attempting to read from unsupported or non-readable "
+ "register. selector val: %i\n", opIdx);
+ return 0;
+ }
+ }
+
+ void
+ GPUISA::writeMiscReg(int opIdx, ScalarRegU32 operandVal)
+ {
+ switch (opIdx) {
+ case REG_M0:
+ m0 = operandVal;
+ break;
+ case REG_SCC:
+ statusReg.SCC = operandVal ? 1 : 0;
+ break;
+ default:
+ fatal("attempting to write to an unsupported or non-writable "
+ "register. selector val: %i\n", opIdx);
+ break;
+ }
+ }
+
+ void
+ GPUISA::advancePC(GPUDynInstPtr gpuDynInst)
+ {
+ wavefront.pc(wavefront.pc()
+ + gpuDynInst->staticInstruction()->instSize());
+ }
+
+ const std::array<const ScalarRegU32, NumPosConstRegs>
+ GPUISA::posConstRegs = { {
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
+ 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
+ 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
+ 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
+ } };
+
+ const std::array<const ScalarRegI32, NumNegConstRegs>
+ GPUISA::negConstRegs = { {
+ -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15,
+ -16
+ } };
+} // namespace Gcn3ISA
diff --git a/src/arch/gcn3/operand.hh b/src/arch/gcn3/operand.hh
new file mode 100644
index 0000000..ac340f1
--- /dev/null
+++ b/src/arch/gcn3/operand.hh
@@ -0,0 +1,696 @@
+/*
+ * Copyright (c) 2017 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * For use for simulation and test purposes only
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Anthony Gutierrez
+ */
+
+#ifndef __ARCH_GCN3_OPERAND_HH__
+#define __ARCH_GCN3_OPERAND_HH__
+
+#include <array>
+
+#include "arch/gcn3/registers.hh"
+#include "arch/generic/vec_reg.hh"
+#include "gpu-compute/scalar_register_file.hh"
+#include "gpu-compute/vector_register_file.hh"
+#include "gpu-compute/wavefront.hh"
+
+/**
+ * classes that represnt vector/scalar operands in GCN3 ISA. these classes
+ * wrap the generic vector register type (i.e., src/arch/generic/vec_reg.hh)
+ * and allow them to be manipulated in ways that are unique to GCN3 insts.
+ */
+
+namespace Gcn3ISA
+{
+ /**
+ * convenience traits so we can automatically infer the correct FP type
+ * without looking at the number of dwords (i.e., to determine if we
+ * need a float or a double when creating FP constants).
+ */
+ template<typename T> struct OpTraits { typedef float FloatT; };
+ template<> struct OpTraits<ScalarRegF64> { typedef double FloatT; };
+ template<> struct OpTraits<ScalarRegU64> { typedef double FloatT; };
+
+ class Operand
+ {
+ public:
+ Operand() = delete;
+
+ Operand(GPUDynInstPtr gpuDynInst, int opIdx)
+ : _gpuDynInst(gpuDynInst), _opIdx(opIdx)
+ {
+ assert(_gpuDynInst);
+ assert(_opIdx >= 0);
+ }
+
+ /**
+ * read from and write to the underlying register(s) that
+ * this operand is referring to.
+ */
+ virtual void read() = 0;
+ virtual void write() = 0;
+
+ protected:
+ /**
+ * instruction object that owns this operand
+ */
+ GPUDynInstPtr _gpuDynInst;
+ /**
+ * op selector value for this operand. note that this is not
+ * the same as the register file index, be it scalar or vector.
+ * this could refer to inline constants, system regs, or even
+ * special values.
+ */
+ int _opIdx;
+ };
+
+ template<typename DataType, bool Const, size_t NumDwords>
+ class ScalarOperand;
+
+ template<typename DataType, bool Const,
+ size_t NumDwords = sizeof(DataType) / sizeof(VecElemU32)>
+ class VecOperand final : public Operand
+ {
+ static_assert(NumDwords >= 1 && NumDwords <= MaxOperandDwords,
+ "Incorrect number of DWORDS for GCN3 operand.");
+
+ public:
+ VecOperand() = delete;
+
+ VecOperand(GPUDynInstPtr gpuDynInst, int opIdx)
+ : Operand(gpuDynInst, opIdx), scalar(false), absMod(false),
+ negMod(false), scRegData(gpuDynInst, _opIdx),
+ vrfData{{ nullptr }}
+ {
+ vecReg.zero();
+ }
+
+ ~VecOperand()
+ {
+ }
+
+ /**
+ * certain vector operands can read from the vrf/srf or constants.
+ * we use this method to first determine the type of the operand,
+ * then we read from the appropriate source. if vector we read
+ * directly from the vrf. if scalar, we read in the data through
+ * the scalar operand component. this should only be used for VSRC
+ * operands.
+ */
+ void
+ readSrc()
+ {
+ if (isVectorReg(_opIdx)) {
+ _opIdx = opSelectorToRegIdx(_opIdx, _gpuDynInst->wavefront()
+ ->reservedScalarRegs);
+ read();
+ } else {
+ readScalar();
+ }
+ }
+
+ /**
+ * read from the vrf. this should only be used by vector inst
+ * source operands that are explicitly vector (i.e., VSRC).
+ */
+ void
+ read() override
+ {
+ assert(_gpuDynInst);
+ assert(_gpuDynInst->wavefront());
+ assert(_gpuDynInst->computeUnit());
+ Wavefront *wf = _gpuDynInst->wavefront();
+ ComputeUnit *cu = _gpuDynInst->computeUnit();
+
+ for (auto i = 0; i < NumDwords; ++i) {
+ int vgprIdx = cu->registerManager.mapVgpr(wf, _opIdx + i);
+ vrfData[i] = &cu->vrf[wf->simdId]->readWriteable(vgprIdx);
+
+ DPRINTF(GPUVRF, "Read v[%d]\n", vgprIdx);
+ cu->vrf[wf->simdId]->printReg(wf, vgprIdx);
+ }
+
+ if (NumDwords == 1) {
+ assert(vrfData[0]);
+ auto vgpr = vecReg.template as<DataType>();
+ auto reg_file_vgpr = vrfData[0]->template as<VecElemU32>();
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ std::memcpy((void*)&vgpr[lane],
+ (void*)®_file_vgpr[lane], sizeof(DataType));
+ }
+ } else if (NumDwords == 2) {
+ assert(vrfData[0]);
+ assert(vrfData[1]);
+ auto vgpr = vecReg.template as<VecElemU64>();
+ auto reg_file_vgpr0 = vrfData[0]->template as<VecElemU32>();
+ auto reg_file_vgpr1 = vrfData[1]->template as<VecElemU32>();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ VecElemU64 tmp_val(0);
+ ((VecElemU32*)&tmp_val)[0] = reg_file_vgpr0[lane];
+ ((VecElemU32*)&tmp_val)[1] = reg_file_vgpr1[lane];
+ vgpr[lane] = tmp_val;
+ }
+ }
+ }
+
+ /**
+ * write to the vrf. we maintain a copy of the underlying vector
+ * reg(s) for this operand (i.e., vrfData/scRegData), as well as a
+ * temporary vector register representation (i.e., vecReg) of the
+ * vector register, which allows the execute() methods of instructions
+ * to easily write their operand data using operator[] regardless of
+ * their size. after the result is calculated we use write() to write
+ * the data to the actual register file storage. this allows us to do
+ * type conversion, etc., in a single call as opposed to doing it
+ * in each execute() method.
+ */
+ void
+ write() override
+ {
+ assert(_gpuDynInst);
+ assert(_gpuDynInst->wavefront());
+ assert(_gpuDynInst->computeUnit());
+ Wavefront *wf = _gpuDynInst->wavefront();
+ ComputeUnit *cu = _gpuDynInst->computeUnit();
+ VectorMask &exec_mask = _gpuDynInst->isLoad()
+ ? _gpuDynInst->exec_mask : wf->execMask();
+
+ if (NumDwords == 1) {
+ int vgprIdx = cu->registerManager.mapVgpr(wf, _opIdx);
+ vrfData[0] = &cu->vrf[wf->simdId]->readWriteable(vgprIdx);
+ assert(vrfData[0]);
+ auto reg_file_vgpr = vrfData[0]->template as<VecElemU32>();
+ auto vgpr = vecReg.template as<DataType>();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (exec_mask[lane] || _gpuDynInst->ignoreExec()) {
+ std::memcpy((void*)®_file_vgpr[lane],
+ (void*)&vgpr[lane], sizeof(DataType));
+ }
+ }
+
+ DPRINTF(GPUVRF, "Write v[%d]\n", vgprIdx);
+ cu->vrf[wf->simdId]->printReg(wf, vgprIdx);
+ } else if (NumDwords == 2) {
+ int vgprIdx0 = cu->registerManager.mapVgpr(wf, _opIdx);
+ int vgprIdx1 = cu->registerManager.mapVgpr(wf, _opIdx + 1);
+ vrfData[0] = &cu->vrf[wf->simdId]->readWriteable(vgprIdx0);
+ vrfData[1] = &cu->vrf[wf->simdId]->readWriteable(vgprIdx1);
+ assert(vrfData[0]);
+ assert(vrfData[1]);
+ auto reg_file_vgpr0 = vrfData[0]->template as<VecElemU32>();
+ auto reg_file_vgpr1 = vrfData[1]->template as<VecElemU32>();
+ auto vgpr = vecReg.template as<VecElemU64>();
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (exec_mask[lane] || _gpuDynInst->ignoreExec()) {
+ reg_file_vgpr0[lane] = ((VecElemU32*)&vgpr[lane])[0];
+ reg_file_vgpr1[lane] = ((VecElemU32*)&vgpr[lane])[1];
+ }
+ }
+
+ DPRINTF(GPUVRF, "Write v[%d:%d]\n", vgprIdx0, vgprIdx1);
+ cu->vrf[wf->simdId]->printReg(wf, vgprIdx0);
+ cu->vrf[wf->simdId]->printReg(wf, vgprIdx1);
+ }
+ }
+
+ void
+ negModifier()
+ {
+ negMod = true;
+ }
+
+ void
+ absModifier()
+ {
+ absMod = true;
+ }
+
+ /**
+ * getter [] operator. only enable if this operand is constant
+ * (i.e, a source operand) and if it can be represented using
+ * primitive types (i.e., 8b to 64b primitives).
+ */
+ template<bool Condition = (NumDwords == 1 || NumDwords == 2) && Const>
+ typename std::enable_if<Condition, const DataType>::type
+ operator[](size_t idx) const
+ {
+ assert(idx < NumVecElemPerVecReg);
+
+ if (scalar) {
+ DataType ret_val = scRegData.rawData();
+
+ if (absMod) {
+ assert(std::is_floating_point<DataType>::value);
+ ret_val = std::fabs(ret_val);
+ }
+
+ if (negMod) {
+ assert(std::is_floating_point<DataType>::value);
+ ret_val = -ret_val;
+ }
+
+ return ret_val;
+ } else {
+ auto vgpr = vecReg.template as<DataType>();
+ DataType ret_val = vgpr[idx];
+
+ if (absMod) {
+ assert(std::is_floating_point<DataType>::value);
+ ret_val = std::fabs(ret_val);
+ }
+
+ if (negMod) {
+ assert(std::is_floating_point<DataType>::value);
+ ret_val = -ret_val;
+ }
+
+ return ret_val;
+ }
+ }
+
+ /**
+ * setter [] operator. only enable if this operand is non-constant
+ * (i.e, a destination operand) and if it can be represented using
+ * primitive types (i.e., 8b to 64b primitives).
+ */
+ template<bool Condition = (NumDwords == 1 || NumDwords == 2) && !Const>
+ typename std::enable_if<Condition, DataType&>::type
+ operator[](size_t idx)
+ {
+ assert(!scalar);
+ assert(idx < NumVecElemPerVecReg);
+
+ return vecReg.template as<DataType>()[idx];
+ }
+
+ private:
+ /**
+ * if we determine that this operand is a scalar (reg or constant)
+ * then we read the scalar data into the scalar operand data member.
+ */
+ void
+ readScalar()
+ {
+ scalar = true;
+ scRegData.read();
+ }
+
+ using VecRegCont = typename std::conditional<NumDwords == 2,
+ VecRegContainerU64, typename std::conditional<sizeof(DataType)
+ == sizeof(VecElemU16), VecRegContainerU16,
+ typename std::conditional<sizeof(DataType)
+ == sizeof(VecElemU8), VecRegContainerU8,
+ VecRegContainerU32>::type>::type>::type;
+
+ /**
+ * whether this operand a scalar or not.
+ */
+ bool scalar;
+ /**
+ * absolute value and negative modifiers. VOP3 instructions
+ * may indicate that their input/output operands must be
+ * modified, either by taking the absolute value or negating
+ * them. these bools indicate which modifier, if any, to use.
+ */
+ bool absMod;
+ bool negMod;
+ /**
+ * this holds all the operand data in a single vector register
+ * object (i.e., if an operand is 64b, this will hold the data
+ * from both registers the operand is using).
+ */
+ VecRegCont vecReg;
+ /**
+ * for src operands that read scalars (i.e., scalar regs or
+ * a scalar constant).
+ */
+ ScalarOperand<DataType, Const, NumDwords> scRegData;
+ /**
+ * pointers to the underlyding registers (i.e., the actual
+ * registers in the register file).
+ */
+ std::array<VecRegContainerU32*, NumDwords> vrfData;
+ };
+
+ template<typename DataType, bool Const,
+ size_t NumDwords = sizeof(DataType) / sizeof(ScalarRegU32)>
+ class ScalarOperand final : public Operand
+ {
+ static_assert(NumDwords >= 1 && NumDwords <= MaxOperandDwords,
+ "Incorrect number of DWORDS for GCN3 operand.");
+ public:
+ ScalarOperand() = delete;
+
+ ScalarOperand(GPUDynInstPtr gpuDynInst, int opIdx)
+ : Operand(gpuDynInst, opIdx)
+ {
+ std::memset(srfData.data(), 0, NumDwords * sizeof(ScalarRegU32));
+ }
+
+ ~ScalarOperand()
+ {
+ }
+
+ /**
+ * we store scalar data in a std::array, however if we need the
+ * full operand data we use this method to copy all elements of
+ * the scalar operand data to a single primitive container. only
+ * useful for 8b to 64b primitive types, as they are the only types
+ * that we need to perform computation on.
+ */
+ template<bool Condition = NumDwords == 1 || NumDwords == 2>
+ typename std::enable_if<Condition, DataType>::type
+ rawData() const
+ {
+ assert(sizeof(DataType) <= sizeof(srfData));
+ DataType raw_data((DataType)0);
+ std::memcpy((void*)&raw_data, (void*)srfData.data(),
+ sizeof(DataType));
+
+ return raw_data;
+ }
+
+ void*
+ rawDataPtr()
+ {
+ return (void*)srfData.data();
+ }
+
+ void
+ read() override
+ {
+ Wavefront *wf = _gpuDynInst->wavefront();
+ ComputeUnit *cu = _gpuDynInst->computeUnit();
+
+ if (!isScalarReg(_opIdx)) {
+ readSpecialVal();
+ } else {
+ for (auto i = 0; i < NumDwords; ++i) {
+ int sgprIdx = regIdx(i);
+ srfData[i] = cu->srf[wf->simdId]->read(sgprIdx);
+ DPRINTF(GPUSRF, "Read s[%d]\n", sgprIdx);
+ cu->srf[wf->simdId]->printReg(wf, sgprIdx);
+ }
+ }
+ }
+
+ void
+ write() override
+ {
+ Wavefront *wf = _gpuDynInst->wavefront();
+ ComputeUnit *cu = _gpuDynInst->computeUnit();
+
+ if (!isScalarReg(_opIdx)) {
+ if (_opIdx == REG_EXEC_LO) {
+ uint64_t new_exec_mask_val(0);
+ std::memcpy((void*)&new_exec_mask_val,
+ (void*)srfData.data(), sizeof(new_exec_mask_val));
+ VectorMask new_exec_mask(new_exec_mask_val);
+ wf->execMask() = new_exec_mask;
+ DPRINTF(GPUSRF, "Write EXEC\n");
+ DPRINTF(GPUSRF, "EXEC = %#x\n", new_exec_mask_val);
+ } else {
+ _gpuDynInst->writeMiscReg(_opIdx, srfData[0]);
+ }
+ } else {
+ for (auto i = 0; i < NumDwords; ++i) {
+ int sgprIdx = regIdx(i);
+ auto &sgpr = cu->srf[wf->simdId]->readWriteable(sgprIdx);
+ if (_gpuDynInst->isLoad()) {
+ assert(sizeof(DataType) <= sizeof(ScalarRegU64));
+ sgpr = reinterpret_cast<ScalarRegU32*>(
+ _gpuDynInst->scalar_data)[i];
+ } else {
+ sgpr = srfData[i];
+ }
+ DPRINTF(GPUSRF, "Write s[%d]\n", sgprIdx);
+ cu->srf[wf->simdId]->printReg(wf, sgprIdx);
+ }
+ }
+ }
+
+ /**
+ * bit access to scalar data. primarily used for setting vcc bits.
+ */
+ template<bool Condition = NumDwords == 1 || NumDwords == 2>
+ typename std::enable_if<Condition, void>::type
+ setBit(int bit, int bit_val)
+ {
+ DataType &sgpr = *((DataType*)srfData.data());
+ replaceBits(sgpr, bit, bit_val);
+ }
+
+ template<bool Condition = (NumDwords == 1 || NumDwords == 2) && !Const>
+ typename std::enable_if<Condition, ScalarOperand&>::type
+ operator=(DataType rhs)
+ {
+ std::memcpy((void*)srfData.data(), (void*)&rhs, sizeof(DataType));
+ return *this;
+ }
+
+ private:
+ /**
+ * we have determined that we are not reading our scalar operand data
+ * from the register file, so here we figure out which special value
+ * we are reading (i.e., float constant, int constant, inline
+ * constant, or various other system registers (e.g., exec mask).
+ */
+ void
+ readSpecialVal()
+ {
+ assert(NumDwords == 1 || NumDwords == 2);
+
+ switch(_opIdx) {
+ case REG_EXEC_LO:
+ {
+ assert(NumDwords == 2);
+ ScalarRegU64 exec_mask = _gpuDynInst->wavefront()->
+ execMask().to_ullong();
+ std::memcpy((void*)srfData.data(), (void*)&exec_mask,
+ sizeof(srfData));
+ DPRINTF(GPUSRF, "Read EXEC\n");
+ DPRINTF(GPUSRF, "EXEC = %#x\n", exec_mask);
+ }
+ break;
+ case REG_SRC_SWDA:
+ case REG_SRC_DPP:
+ case REG_SRC_LITERAL:
+ assert(NumDwords == 1);
+ srfData[0] = _gpuDynInst->srcLiteral();
+ break;
+ case REG_POS_HALF:
+ {
+ typename OpTraits<DataType>::FloatT pos_half = 0.5;
+ std::memcpy((void*)srfData.data(), (void*)&pos_half,
+ sizeof(srfData));
+
+ }
+ break;
+ case REG_NEG_HALF:
+ {
+ typename OpTraits<DataType>::FloatT neg_half = -0.5;
+ std::memcpy((void*)srfData.data(), (void*)&neg_half,
+ sizeof(srfData));
+ }
+ break;
+ case REG_POS_ONE:
+ {
+ typename OpTraits<DataType>::FloatT pos_one = 1.0;
+ std::memcpy(srfData.data(), &pos_one, sizeof(srfData));
+ }
+ break;
+ case REG_NEG_ONE:
+ {
+ typename OpTraits<DataType>::FloatT neg_one = -1.0;
+ std::memcpy(srfData.data(), &neg_one, sizeof(srfData));
+ }
+ break;
+ case REG_POS_TWO:
+ {
+ typename OpTraits<DataType>::FloatT pos_two = 2.0;
+ std::memcpy(srfData.data(), &pos_two, sizeof(srfData));
+ }
+ break;
+ case REG_NEG_TWO:
+ {
+ typename OpTraits<DataType>::FloatT neg_two = -2.0;
+ std::memcpy(srfData.data(), &neg_two, sizeof(srfData));
+ }
+ break;
+ case REG_POS_FOUR:
+ {
+ typename OpTraits<DataType>::FloatT pos_four = 4.0;
+ std::memcpy(srfData.data(), &pos_four, sizeof(srfData));
+ }
+ break;
+ case REG_NEG_FOUR:
+ {
+ typename OpTraits<DataType>::FloatT neg_four = -4.0;
+ std::memcpy((void*)srfData.data(), (void*)&neg_four ,
+ sizeof(srfData));
+ }
+ break;
+ case REG_PI:
+ {
+ assert(sizeof(DataType) == sizeof(ScalarRegF64)
+ || sizeof(DataType) == sizeof(ScalarRegF32));
+
+ const ScalarRegU32 pi_u32(0x3e22f983UL);
+ const ScalarRegU64 pi_u64(0x3fc45f306dc9c882ULL);
+
+ if (sizeof(DataType) == sizeof(ScalarRegF64)) {
+ std::memcpy((void*)srfData.data(),
+ (void*)&pi_u64, sizeof(srfData));
+ } else {
+ std::memcpy((void*)srfData.data(),
+ (void*)&pi_u32, sizeof(srfData));
+ }
+ }
+ break;
+ default:
+ {
+ assert(sizeof(DataType) <= sizeof(srfData));
+ DataType misc_val
+ = (DataType)_gpuDynInst->readMiscReg(_opIdx);
+ std::memcpy((void*)srfData.data(), (void*)&misc_val,
+ sizeof(DataType));
+ }
+ }
+ }
+
+ /**
+ * for scalars we need to do some extra work to figure out how to
+ * map the op selector to the sgpr idx because some op selectors
+ * do not map directly to the srf (i.e., vcc/flat_scratch).
+ */
+ int
+ regIdx(int dword) const
+ {
+ Wavefront *wf = _gpuDynInst->wavefront();
+ ComputeUnit *cu = _gpuDynInst->computeUnit();
+ int sgprIdx(-1);
+
+ if (_opIdx == REG_VCC_LO) {
+ sgprIdx = cu->registerManager
+ .mapSgpr(wf, wf->reservedScalarRegs - 2 + dword);
+ } else if (_opIdx == REG_FLAT_SCRATCH_HI) {
+ sgprIdx = cu->registerManager
+ .mapSgpr(wf, wf->reservedScalarRegs - 3 + dword);
+ } else if (_opIdx == REG_FLAT_SCRATCH_LO) {
+ assert(NumDwords == 1);
+ sgprIdx = cu->registerManager
+ .mapSgpr(wf, wf->reservedScalarRegs - 4 + dword);
+ } else {
+ sgprIdx = cu->registerManager.mapSgpr(wf, _opIdx + dword);
+ }
+
+ assert(sgprIdx > -1);
+
+ return sgprIdx;
+ }
+
+ /**
+ * in GCN3 each register is represented as a 32b unsigned value,
+ * however operands may require up to 16 registers, so we store
+ * all the individual 32b components here. for sub-dword operand
+ * we still consider them to be 1 dword because the minimum size
+ * of a register is 1 dword. this class will take care to do the
+ * proper packing/unpacking of sub-dword operands.
+ */
+ std::array<ScalarRegU32, NumDwords> srfData;
+ };
+
+ // typedefs for the various sizes/types of scalar operands
+ using ScalarOperandU8 = ScalarOperand<ScalarRegU8, false, 1>;
+ using ScalarOperandI8 = ScalarOperand<ScalarRegI8, false, 1>;
+ using ScalarOperandU16 = ScalarOperand<ScalarRegU16, false, 1>;
+ using ScalarOperandI16 = ScalarOperand<ScalarRegI16, false, 1>;
+ using ScalarOperandU32 = ScalarOperand<ScalarRegU32, false>;
+ using ScalarOperandI32 = ScalarOperand<ScalarRegI32, false>;
+ using ScalarOperandF32 = ScalarOperand<ScalarRegF32, false>;
+ using ScalarOperandU64 = ScalarOperand<ScalarRegU64, false>;
+ using ScalarOperandI64 = ScalarOperand<ScalarRegI64, false>;
+ using ScalarOperandF64 = ScalarOperand<ScalarRegF64, false>;
+ using ScalarOperandU128 = ScalarOperand<ScalarRegU32, false, 4>;
+ using ScalarOperandU256 = ScalarOperand<ScalarRegU32, false, 8>;
+ using ScalarOperandU512 = ScalarOperand<ScalarRegU32, false, 16>;
+ // non-writeable versions of scalar operands
+ using ConstScalarOperandU8 = ScalarOperand<ScalarRegU8, true, 1>;
+ using ConstScalarOperandI8 = ScalarOperand<ScalarRegI8, true, 1>;
+ using ConstScalarOperandU16 = ScalarOperand<ScalarRegU16, true, 1>;
+ using ConstScalarOperandI16 = ScalarOperand<ScalarRegI16, true, 1>;
+ using ConstScalarOperandU32 = ScalarOperand<ScalarRegU32, true>;
+ using ConstScalarOperandI32 = ScalarOperand<ScalarRegI32, true>;
+ using ConstScalarOperandF32 = ScalarOperand<ScalarRegF32, true>;
+ using ConstScalarOperandU64 = ScalarOperand<ScalarRegU64, true>;
+ using ConstScalarOperandI64 = ScalarOperand<ScalarRegI64, true>;
+ using ConstScalarOperandF64 = ScalarOperand<ScalarRegF64, true>;
+ using ConstScalarOperandU128 = ScalarOperand<ScalarRegU32, true, 4>;
+ using ConstScalarOperandU256 = ScalarOperand<ScalarRegU32, true, 8>;
+ using ConstScalarOperandU512 = ScalarOperand<ScalarRegU32, true, 16>;
+ // typedefs for the various sizes/types of vector operands
+ using VecOperandU8 = VecOperand<VecElemU8, false, 1>;
+ using VecOperandI8 = VecOperand<VecElemI8, false, 1>;
+ using VecOperandU16 = VecOperand<VecElemU16, false, 1>;
+ using VecOperandI16 = VecOperand<VecElemI16, false, 1>;
+ using VecOperandU32 = VecOperand<VecElemU32, false>;
+ using VecOperandI32 = VecOperand<VecElemI32, false>;
+ using VecOperandF32 = VecOperand<VecElemF32, false>;
+ using VecOperandU64 = VecOperand<VecElemU64, false>;
+ using VecOperandF64 = VecOperand<VecElemF64, false>;
+ using VecOperandI64 = VecOperand<VecElemI64, false>;
+ using VecOperandU96 = VecOperand<VecElemU32, false, 3>;
+ using VecOperandU128 = VecOperand<VecElemU32, false, 4>;
+ using VecOperandU256 = VecOperand<VecElemU32, false, 8>;
+ using VecOperandU512 = VecOperand<VecElemU32, false, 16>;
+ // non-writeable versions of vector operands
+ using ConstVecOperandU8 = VecOperand<VecElemU8, true, 1>;
+ using ConstVecOperandI8 = VecOperand<VecElemI8, true, 1>;
+ using ConstVecOperandU16 = VecOperand<VecElemU16, true, 1>;
+ using ConstVecOperandI16 = VecOperand<VecElemI16, true, 1>;
+ using ConstVecOperandU32 = VecOperand<VecElemU32, true>;
+ using ConstVecOperandI32 = VecOperand<VecElemI32, true>;
+ using ConstVecOperandF32 = VecOperand<VecElemF32, true>;
+ using ConstVecOperandU64 = VecOperand<VecElemU64, true>;
+ using ConstVecOperandI64 = VecOperand<VecElemI64, true>;
+ using ConstVecOperandF64 = VecOperand<VecElemF64, true>;
+ using ConstVecOperandU96 = VecOperand<VecElemU32, true, 3>;
+ using ConstVecOperandU128 = VecOperand<VecElemU32, true, 4>;
+ using ConstVecOperandU256 = VecOperand<VecElemU32, true, 8>;
+ using ConstVecOperandU512 = VecOperand<VecElemU32, true, 16>;
+}
+
+#endif // __ARCH_GCN3_OPERAND_HH__
diff --git a/src/arch/gcn3/registers.cc b/src/arch/gcn3/registers.cc
new file mode 100644
index 0000000..0872ff9
--- /dev/null
+++ b/src/arch/gcn3/registers.cc
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * For use for simulation and test purposes only
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Anthony Gutierrez
+ */
+
+#include "arch/gcn3/registers.hh"
+
+namespace Gcn3ISA
+{
+ std::string
+ opSelectorToRegSym(int idx, int numRegs)
+ {
+ std::string reg_sym;
+
+ // we have an SGPR
+ if (idx <= REG_SGPR_MAX) {
+ if (numRegs > 1)
+ reg_sym = "s[" + std::to_string(idx) + ":" +
+ std::to_string(idx + numRegs - 1) + "]";
+ else
+ reg_sym = "s" + std::to_string(idx);
+ return reg_sym;
+ } else if (idx >= REG_VGPR_MIN && idx <= REG_VGPR_MAX) {
+ if (numRegs > 1)
+ reg_sym = "v[" + std::to_string(idx - REG_VGPR_MIN) + ":" +
+ std::to_string(idx - REG_VGPR_MIN + numRegs - 1) + "]";
+ else
+ reg_sym = "v" + std::to_string(idx - REG_VGPR_MIN);
+ return reg_sym;
+ } else if (idx >= REG_INT_CONST_POS_MIN &&
+ idx <= REG_INT_CONST_POS_MAX) {
+ reg_sym = std::to_string(idx - REG_INT_CONST_POS_MIN + 1);
+ return reg_sym;
+ } else if (idx >= REG_INT_CONST_NEG_MIN &&
+ idx <= REG_INT_CONST_NEG_MAX) {
+ int inline_val = -1 - (idx - REG_INT_CONST_NEG_MIN);
+ reg_sym = std::to_string(inline_val);
+ return reg_sym;
+ }
+
+ switch (idx) {
+ case REG_FLAT_SCRATCH_LO:
+ reg_sym = "flat_scratch_lo";
+ break;
+ case REG_FLAT_SCRATCH_HI:
+ reg_sym = "flat_scratch_hi";
+ break;
+ case REG_VCC_LO:
+ reg_sym = "vcc";
+ break;
+ case REG_M0:
+ reg_sym = "m0";
+ break;
+ case REG_EXEC_LO:
+ reg_sym = "exec";
+ break;
+ case REG_ZERO:
+ reg_sym = "0";
+ break;
+ case REG_POS_HALF:
+ reg_sym = "0.5";
+ break;
+ case REG_NEG_HALF:
+ reg_sym = "-0.5";
+ break;
+ case REG_POS_ONE:
+ reg_sym = "1";
+ break;
+ case REG_NEG_ONE:
+ reg_sym = "-1";
+ break;
+ case REG_POS_TWO:
+ reg_sym = "2";
+ break;
+ case REG_NEG_TWO:
+ reg_sym = "-2";
+ break;
+ case REG_POS_FOUR:
+ reg_sym = "4";
+ break;
+ case REG_NEG_FOUR:
+ reg_sym = "-4";
+ break;
+ default:
+ fatal("GCN3 ISA instruction has unknown register index %u\n", idx);
+ break;
+ }
+
+ return reg_sym;
+ }
+
+ int
+ opSelectorToRegIdx(int idx, int numScalarRegs)
+ {
+ int regIdx = -1;
+
+ if (idx <= REG_SGPR_MAX) {
+ regIdx = idx;
+ } else if (idx >= REG_VGPR_MIN && idx <= REG_VGPR_MAX) {
+ regIdx = idx - REG_VGPR_MIN;
+ } else if (idx == REG_VCC_LO) {
+ /**
+ * the VCC register occupies the two highest numbered
+ * SRF entries. VCC is typically indexed by specifying
+ * VCC_LO (simply called VCC) in the instruction encoding
+ * and reading it as a 64b value so we only return the
+ * index to the lower half of the VCC register.
+ *
+ * VCC_LO = s[NUM_SGPRS - 2]
+ * VCC_HI = s[NUM_SGPRS - 1]
+ *
+ */
+ regIdx = numScalarRegs - 2;
+ } else if (idx == REG_FLAT_SCRATCH_LO) {
+ /**
+ * the FLAT_SCRATCH register occupies the two SRF entries
+ * just below VCC. FLAT_SCRATCH is typically indexed by
+ * specifying FLAT_SCRATCH_LO (simply called FLAT_SCRATCH)
+ * in the instruction encoding and reading it as a 64b value
+ * so we only return the index to the lower half of the
+ * FLAT_SCRATCH register.
+ *
+ * FLAT_SCRATCH_LO = s[NUM_SGPRS - 4]
+ * FLAT_SCRATCH_HI = s[NUM_SGPRS - 3]
+ *
+ */
+ regIdx = numScalarRegs - 4;
+ } else if (idx == REG_FLAT_SCRATCH_HI) {
+ regIdx = numScalarRegs - 3;
+ }
+
+ return regIdx;
+ }
+
+ bool
+ isLiteral(int opIdx)
+ {
+ return opIdx == REG_SRC_LITERAL;
+ }
+
+ bool
+ isExecMask(int opIdx)
+ {
+ return opIdx == REG_EXEC_LO || opIdx == REG_EXEC_HI;
+ }
+
+ bool
+ isVccReg(int opIdx)
+ {
+ return opIdx == REG_VCC_LO || opIdx == REG_VCC_HI;
+ }
+
+ bool
+ isFlatScratchReg(int opIdx)
+ {
+ return opIdx == REG_FLAT_SCRATCH_LO || opIdx == REG_FLAT_SCRATCH_HI;
+ }
+
+ bool
+ isScalarReg(int opIdx)
+ {
+ // FLAT_SCRATCH and VCC are stored in an SGPR pair
+ if (opIdx <= REG_SGPR_MAX || opIdx == REG_FLAT_SCRATCH_LO ||
+ opIdx == REG_FLAT_SCRATCH_HI || opIdx == REG_VCC_LO ||
+ opIdx == REG_VCC_HI) {
+ return true;
+ }
+
+ return false;
+ }
+
+ bool
+ isVectorReg(int opIdx)
+ {
+ if (opIdx >= REG_VGPR_MIN && opIdx <= REG_VGPR_MAX)
+ return true;
+
+ return false;
+ }
+
+} // namespace Gcn3ISA
diff --git a/src/arch/gcn3/registers.hh b/src/arch/gcn3/registers.hh
new file mode 100644
index 0000000..9922e5d
--- /dev/null
+++ b/src/arch/gcn3/registers.hh
@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * For use for simulation and test purposes only
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Anthony Gutierrez
+ */
+
+#ifndef __ARCH_GCN3_REGISTERS_HH__
+#define __ARCH_GCN3_REGISTERS_HH__
+
+#include <array>
+#include <cstdint>
+#include <string>
+
+#include "arch/generic/vec_reg.hh"
+#include "base/intmath.hh"
+#include "base/logging.hh"
+
+namespace Gcn3ISA
+{
+ enum OpSelector : int
+ {
+ REG_SGPR_MIN = 0,
+ REG_SGPR_MAX = 101,
+ REG_FLAT_SCRATCH_LO = 102,
+ REG_FLAT_SCRATCH_HI = 103,
+ REG_XNACK_MASK_LO = 104,
+ REG_XNACK_MASK_HI = 105,
+ REG_VCC_LO = 106,
+ REG_VCC_HI = 107,
+ REG_TBA_LO = 108,
+ REG_TBA_HI = 109,
+ REG_TMA_LO = 110,
+ REG_TMA_HI = 111,
+ REG_TTMP_0 = 112,
+ REG_TTMP_1 = 113,
+ REG_TTMP_2 = 114,
+ REG_TTMP_3 = 115,
+ REG_TTMP_4 = 116,
+ REG_TTMP_5 = 117,
+ REG_TTMP_6 = 118,
+ REG_TTMP_7 = 119,
+ REG_TTMP_8 = 120,
+ REG_TTMP_9 = 121,
+ REG_TTMP_10 = 122,
+ REG_TTMP_11 = 123,
+ REG_M0 = 124,
+ REG_RESERVED_1 = 125,
+ REG_EXEC_LO = 126,
+ REG_EXEC_HI = 127,
+ REG_ZERO = 128,
+ REG_INT_CONST_POS_MIN = 129,
+ REG_INT_CONST_POS_MAX = 192,
+ REG_INT_CONST_NEG_MIN = 193,
+ REG_INT_CONST_NEG_MAX = 208,
+ REG_RESERVED_2 = 209,
+ REG_RESERVED_3 = 210,
+ REG_RESERVED_4 = 211,
+ REG_RESERVED_5 = 212,
+ REG_RESERVED_6 = 213,
+ REG_RESERVED_7 = 214,
+ REG_RESERVED_8 = 215,
+ REG_RESERVED_9 = 216,
+ REG_RESERVED_10 = 217,
+ REG_RESERVED_11 = 218,
+ REG_RESERVED_12 = 219,
+ REG_RESERVED_13 = 220,
+ REG_RESERVED_14 = 221,
+ REG_RESERVED_15 = 222,
+ REG_RESERVED_16 = 223,
+ REG_RESERVED_17 = 224,
+ REG_RESERVED_18 = 225,
+ REG_RESERVED_19 = 226,
+ REG_RESERVED_20 = 227,
+ REG_RESERVED_21 = 228,
+ REG_RESERVED_22 = 229,
+ REG_RESERVED_23 = 230,
+ REG_RESERVED_24 = 231,
+ REG_RESERVED_25 = 232,
+ REG_RESERVED_26 = 233,
+ REG_RESERVED_27 = 234,
+ REG_RESERVED_28 = 235,
+ REG_RESERVED_29 = 236,
+ REG_RESERVED_30 = 237,
+ REG_RESERVED_31 = 238,
+ REG_RESERVED_32 = 239,
+ REG_POS_HALF = 240,
+ REG_NEG_HALF = 241,
+ REG_POS_ONE = 242,
+ REG_NEG_ONE = 243,
+ REG_POS_TWO = 244,
+ REG_NEG_TWO = 245,
+ REG_POS_FOUR = 246,
+ REG_NEG_FOUR = 247,
+ REG_PI = 248,
+ /* NOTE: SDWA and SWDA both refer to sub d-word addressing */
+ REG_SRC_SWDA = 249,
+ REG_SRC_DPP = 250,
+ REG_VCCZ = 251,
+ REG_EXECZ = 252,
+ REG_SCC = 253,
+ REG_LDS_DIRECT = 254,
+ REG_SRC_LITERAL = 255,
+ REG_VGPR_MIN = 256,
+ REG_VGPR_MAX = 511
+ };
+
+ constexpr size_t MaxOperandDwords(16);
+ const int NumVecElemPerVecReg(64);
+ // op selector values 129 - 192 correspond to const values 1 - 64
+ const int NumPosConstRegs = REG_INT_CONST_POS_MAX
+ - REG_INT_CONST_POS_MIN + 1;
+ // op selector values 193 - 208 correspond to const values -1 - 16
+ const int NumNegConstRegs = REG_INT_CONST_NEG_MAX
+ - REG_INT_CONST_NEG_MIN + 1;
+ const int BITS_PER_BYTE = 8;
+ const int BITS_PER_WORD = 16;
+ const int MSB_PER_BYTE = (BITS_PER_BYTE - 1);
+ const int MSB_PER_WORD = (BITS_PER_WORD - 1);
+
+ // typedefs for the various sizes/types of scalar regs
+ typedef uint8_t ScalarRegU8;
+ typedef int8_t ScalarRegI8;
+ typedef uint16_t ScalarRegU16;
+ typedef int16_t ScalarRegI16;
+ typedef uint32_t ScalarRegU32;
+ typedef int32_t ScalarRegI32;
+ typedef float ScalarRegF32;
+ typedef uint64_t ScalarRegU64;
+ typedef int64_t ScalarRegI64;
+ typedef double ScalarRegF64;
+
+ // typedefs for the various sizes/types of vector reg elements
+ typedef uint8_t VecElemU8;
+ typedef int8_t VecElemI8;
+ typedef uint16_t VecElemU16;
+ typedef int16_t VecElemI16;
+ typedef uint32_t VecElemU32;
+ typedef int32_t VecElemI32;
+ typedef float VecElemF32;
+ typedef uint64_t VecElemU64;
+ typedef int64_t VecElemI64;
+ typedef double VecElemF64;
+
+ // typedefs for the various sizes/types of vector regs
+ using VecRegU8 = ::VecRegT<VecElemU8, NumVecElemPerVecReg, false>;
+ using VecRegI8 = ::VecRegT<VecElemI8, NumVecElemPerVecReg, false>;
+ using VecRegU16 = ::VecRegT<VecElemU16, NumVecElemPerVecReg, false>;
+ using VecRegI16 = ::VecRegT<VecElemI16, NumVecElemPerVecReg, false>;
+ using VecRegU32 = ::VecRegT<VecElemU32, NumVecElemPerVecReg, false>;
+ using VecRegI32 = ::VecRegT<VecElemI32, NumVecElemPerVecReg, false>;
+ using VecRegF32 = ::VecRegT<VecElemF32, NumVecElemPerVecReg, false>;
+ using VecRegU64 = ::VecRegT<VecElemU64, NumVecElemPerVecReg, false>;
+ using VecRegI64 = ::VecRegT<VecElemI64, NumVecElemPerVecReg, false>;
+ using VecRegF64 = ::VecRegT<VecElemF64, NumVecElemPerVecReg, false>;
+ // non-writeable versions of vector regs
+ using ConstVecRegU8 = ::VecRegT<VecElemU8, NumVecElemPerVecReg, true>;
+ using ConstVecRegI8 = ::VecRegT<VecElemI8, NumVecElemPerVecReg, true>;
+ using ConstVecRegU16 = ::VecRegT<VecElemU16, NumVecElemPerVecReg, true>;
+ using ConstVecRegI16 = ::VecRegT<VecElemI16, NumVecElemPerVecReg, true>;
+ using ConstVecRegU32 = ::VecRegT<VecElemU32, NumVecElemPerVecReg, true>;
+ using ConstVecRegI32 = ::VecRegT<VecElemI32, NumVecElemPerVecReg, true>;
+ using ConstVecRegF32 = ::VecRegT<VecElemF32, NumVecElemPerVecReg, true>;
+ using ConstVecRegU64 = ::VecRegT<VecElemU64, NumVecElemPerVecReg, true>;
+ using ConstVecRegI64 = ::VecRegT<VecElemI64, NumVecElemPerVecReg, true>;
+ using ConstVecRegF64 = ::VecRegT<VecElemF64, NumVecElemPerVecReg, true>;
+
+ using VecRegContainerU8 = VecRegU8::Container;
+ using VecRegContainerU16 = VecRegU16::Container;
+ using VecRegContainerU32 = VecRegU32::Container;
+ using VecRegContainerU64 = VecRegU64::Container;
+
+ struct StatusReg
+ {
+ StatusReg() : SCC(0), SPI_PRIO(0), USER_PRIO(0), PRIV(0), TRAP_EN(0),
+ TTRACE_EN(0), EXPORT_RDY(0), EXECZ(0), VCCZ(0), IN_TG(0),
+ IN_BARRIER(0), HALT(0), TRAP(0), TTRACE_CU_EN(0), VALID(0),
+ ECC_ERR(0), SKIP_EXPORT(0), PERF_EN(0), COND_DBG_USER(0),
+ COND_DBG_SYS(0), ALLOW_REPLAY(0), INSTRUCTION_ATC(0), RESERVED(0),
+ MUST_EXPORT(0), RESERVED_1(0)
+ {
+ }
+
+ uint32_t SCC : 1;
+ uint32_t SPI_PRIO : 2;
+ uint32_t USER_PRIO : 2;
+ uint32_t PRIV : 1;
+ uint32_t TRAP_EN : 1;
+ uint32_t TTRACE_EN : 1;
+ uint32_t EXPORT_RDY : 1;
+ uint32_t EXECZ : 1;
+ uint32_t VCCZ : 1;
+ uint32_t IN_TG : 1;
+ uint32_t IN_BARRIER : 1;
+ uint32_t HALT : 1;
+ uint32_t TRAP : 1;
+ uint32_t TTRACE_CU_EN : 1;
+ uint32_t VALID : 1;
+ uint32_t ECC_ERR : 1;
+ uint32_t SKIP_EXPORT : 1;
+ uint32_t PERF_EN : 1;
+ uint32_t COND_DBG_USER : 1;
+ uint32_t COND_DBG_SYS : 1;
+ uint32_t ALLOW_REPLAY : 1;
+ uint32_t INSTRUCTION_ATC : 1;
+ uint32_t RESERVED : 3;
+ uint32_t MUST_EXPORT : 1;
+ uint32_t RESERVED_1 : 4;
+ };
+
+ std::string opSelectorToRegSym(int opIdx, int numRegs=0);
+ int opSelectorToRegIdx(int opIdx, int numScalarRegs);
+ bool isLiteral(int opIdx);
+ bool isScalarReg(int opIdx);
+ bool isVectorReg(int opIdx);
+ bool isFlatScratchReg(int opIdx);
+ bool isExecMask(int opIdx);
+ bool isVccReg(int opIdx);
+} // namespace Gcn3ISA
+
+#endif // __ARCH_GCN3_REGISTERS_HH__
diff --git a/util/git-commit-msg.py b/util/git-commit-msg.py
index fd258c2..23270bc 100755
--- a/util/git-commit-msg.py
+++ b/util/git-commit-msg.py
@@ -88,13 +88,14 @@
# @todo this is error prone, and should be extracted automatically from
# a file
- valid_tags = ["arch", "arch-alpha", "arch-arm", "arch-hsail", "arch-mips",
- "arch-power", "arch-riscv", "arch-sparc", "arch-x86", "base",
- "configs", "cpu", "cpu-kvm", "cpu-minor", "cpu-o3", "cpu-simple",
- "dev", "dev-arm", "dev-virtio", "ext", "fastmodel", "gpu-compute",
- "learning-gem5", "mem", "mem-cache", "mem-garnet", "mem-ruby", "misc",
- "python", "scons", "sim", "sim-se", "sim-power", "stats", "system",
- "system-alpha", "system-arm", "systemc", "tests", "util", "RFC", "WIP"]
+ valid_tags = ["arch", "arch-alpha", "arch-arm", "arch-gcn3", "arch-hsail",
+ "arch-mips", "arch-power", "arch-riscv", "arch-sparc", "arch-x86",
+ "base", "configs", "cpu", "cpu-kvm", "cpu-minor", "cpu-o3",
+ "cpu-simple", "dev", "dev-arm", "dev-virtio", "ext", "fastmodel",
+ "gpu-compute", "learning-gem5", "mem", "mem-cache", "mem-garnet",
+ "mem-ruby", "misc", "python", "scons", "sim", "sim-se", "sim-power",
+ "stats", "system", "system-alpha", "system-arm", "systemc", "tests",
+ "util", "RFC", "WIP"]
tags = ''.join(commit_header.split(':')[0].split()).split(',')
if (any(tag not in valid_tags for tag in tags)):
