commit 96fdb20871b16782ed405e58e9d9cc005d661b21
author Giacomo Travaglini <giacomo.travaglini@arm.com> Mon Sep 02 10:28:12 2019 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Fri Sep 06 20:00:34 2019 +0000
tree 88d9696afe5506eef3b420893eff0460ca038209
parent 982a7d4f13e8919cd50dccc29d001f1e98fc2fbb

dev-arm: Add read/writeBanked helpers to GICv3

These will be used by AA64 security banked registers in GICv3.

Change-Id: Ia980c4f5c14187ab9c18da1d1d596562644111ae
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20624
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/dev/arm/gic_v3_cpu_interface.cc

diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc
index cc630b4..d3d73a3 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -1623,6 +1623,20 @@
     }
 }
 
+RegVal
+Gicv3CPUInterface::readBankedMiscReg(MiscRegIndex misc_reg) const
+{
+    return isa->readMiscRegNoEffect(
+        isa->snsBankedIndex64(misc_reg, !isSecureBelowEL3()));
+}
+
+void
+Gicv3CPUInterface::setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const
+{
+    isa->setMiscRegNoEffect(
+        isa->snsBankedIndex64(misc_reg, !isSecureBelowEL3()), val);
+}
+
 int
 Gicv3CPUInterface::virtualFindActive(uint32_t int_id) const
 {

src/dev/arm/gic_v3_cpu_interface.hh

diff --git a/src/dev/arm/gic_v3_cpu_interface.hh b/src/dev/arm/gic_v3_cpu_interface.hh
index 56a6695..9e1c9a0 100644
--- a/src/dev/arm/gic_v3_cpu_interface.hh
+++ b/src/dev/arm/gic_v3_cpu_interface.hh
@@ -338,6 +338,8 @@
     void virtualUpdate();
     RegVal bpr1(Gicv3::GroupId group);
 
+    RegVal readBankedMiscReg(MiscRegIndex misc_reg) const;
+    void setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const;
   public:
 
     Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id);