misc: Adopt the gem5 namespace
Apply the gem5 namespace to the codebase.
Some anonymous namespaces could theoretically be removed,
but since this change's main goal was to keep conflicts
at a minimum, it was decided not to modify much the
general shape of the files.
A few missing comments of the form "// namespace X" that
occurred before the newly added "} // namespace gem5"
have been added for consistency.
std out should not be included in the gem5 namespace, so
they weren't.
ProtoMessage has not been included in the gem5 namespace,
since I'm not familiar with how proto works.
Regarding the SystemC files, although they belong to gem5,
they actually perform integration between gem5 and SystemC;
therefore, it deserved its own separate namespace.
Files that are automatically generated have been included
in the gem5 namespace.
The .isa files currently are limited to a single namespace.
This limitation should be later removed to make it easier
to accomodate a better API.
Regarding the files in util, gem5:: was prepended where
suitable. Notice that this patch was tested as much as
possible given that most of these were already not
previously compiling.
Change-Id: Ia53d404ec79c46edaa98f654e23bc3b0e179fe2d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46323
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/ext/sst/ExtMaster.cc b/ext/sst/ExtMaster.cc
index 3afd6b4..e727537 100644
--- a/ext/sst/ExtMaster.cc
+++ b/ext/sst/ExtMaster.cc
@@ -56,10 +56,10 @@
using namespace SST::gem5;
using namespace SST::MemHierarchy;
-ExtMaster::ExtMaster(gem5Component *g, Output &o, ::ExternalMaster& p,
+ExtMaster::ExtMaster(gem5Component *g, Output &o, ::gem5::ExternalMaster& p,
std::string &n) :
- Port(n, p), out(o), port(p), simPhase(CONSTRUCTION),
- gem5(g), name(n)
+ ::gem5::ExternalMaster::Port(n, p), out(o), port(p),
+ simPhase(CONSTRUCTION), gem5(g), name(n)
{
Params _p; // will be ignored
nic = dynamic_cast<MemNIC*>(gem5->loadModuleWithComponent("memHierarchy.memNIC", g, _p));
@@ -130,12 +130,12 @@
}
Command cmdI = ev->getCmd(); // command in - SST
- MemCmd::Command cmdO; // command out - gem5
+ ::gem5::MemCmd::Command cmdO; // command out - gem5
bool data = false;
switch (cmdI) {
- case GetS: cmdO = MemCmd::ReadReq; break;
- case GetX: cmdO = MemCmd::WriteReq; data = true; break;
+ case GetS: cmdO = ::gem5::MemCmd::ReadReq; break;
+ case GetX: cmdO = ::gem5::MemCmd::WriteReq; data = true; break;
case GetSEx:
case PutS:
case PutM:
@@ -158,23 +158,24 @@
CommandString[cmdI]);
}
- Request::FlagsType flags = 0;
+ ::gem5::Request::FlagsType flags = 0;
if (ev->queryFlag(MemEvent::F_LOCKED))
- flags |= Request::LOCKED_RMW;
+ flags |= ::gem5::Request::LOCKED_RMW;
if (ev->queryFlag(MemEvent::F_NONCACHEABLE))
- flags |= Request::UNCACHEABLE;
+ flags |= ::gem5::Request::UNCACHEABLE;
if (ev->isLoadLink()) {
assert(cmdI == GetS);
- cmdO = MemCmd::LoadLockedReq;
+ cmdO = ::gem5::MemCmd::LoadLockedReq;
} else if (ev->isStoreConditional()) {
assert(cmdI == GetX);
- cmdO = MemCmd::StoreCondReq;
+ cmdO = ::gem5::MemCmd::StoreCondReq;
}
- auto req = std::make_shared<Request>(ev->getAddr(), ev->getSize(), flags, 0);
+ auto req = std::make_shared<::gem5::Request>(
+ ev->getAddr(), ev->getSize(), flags, 0);
req->setContext(ev->getGroupId());
- auto pkt = new Packet(req, cmdO);
+ auto pkt = new ::gem5::Packet(req, cmdO);
pkt->allocate();
if (data) {
pkt->setData(ev->getPayload().data());
@@ -186,7 +187,7 @@
}
bool
-ExtMaster::recvTimingResp(PacketPtr pkt) {
+ExtMaster::recvTimingResp(::gem5::PacketPtr pkt) {
if (simPhase == INIT) {
out.fatal(CALL_INFO, 1, "not prepared to handle INIT-phase traffic\n");
}
diff --git a/ext/sst/ExtMaster.hh b/ext/sst/ExtMaster.hh
index 04e98e5..8b4020b 100644
--- a/ext/sst/ExtMaster.hh
+++ b/ext/sst/ExtMaster.hh
@@ -51,10 +51,11 @@
#include <core/component.h>
#include <elements/memHierarchy/memEvent.h>
-#include <sim/sim_object.hh>
+#include <base/addr_range.hh>
+#include <mem/external_master.hh>
#include <mem/packet.hh>
#include <mem/request.hh>
-#include <mem/external_master.hh>
+#include <sim/sim_object.hh>
namespace SST {
@@ -70,34 +71,35 @@
class gem5Component;
-class ExtMaster : public ExternalMaster::Port {
+class ExtMaster : public ::gem5::ExternalMaster::Port
+{
enum Phase { CONSTRUCTION, INIT, RUN };
Output& out;
- const ExternalMaster& port;
+ const ::gem5::ExternalMaster& port;
Phase simPhase;
gem5Component *const gem5;
const std::string name;
- std::list<PacketPtr> sendQ;
+ std::list<::gem5::PacketPtr> sendQ;
bool blocked() { return !sendQ.empty(); }
MemHierarchy::MemNIC * nic;
- struct SenderState : public Packet::SenderState
+ struct SenderState : public ::gem5::Packet::SenderState
{
MemEvent *event;
SenderState(MemEvent* e) : event(e) {}
};
- std::set<AddrRange> ranges;
+ std::set<::gem5::AddrRange> ranges;
public:
- bool recvTimingResp(PacketPtr);
+ bool recvTimingResp(::gem5::PacketPtr);
void recvReqRetry();
- ExtMaster(gem5Component*, Output&, ExternalMaster&, std::string&);
+ ExtMaster(gem5Component*, Output&, ::gem5::ExternalMaster&, std::string&);
void init(unsigned phase);
void setup();
void finish();
diff --git a/ext/sst/ExtSlave.cc b/ext/sst/ExtSlave.cc
index 0e2f8b4..b9a5e78 100644
--- a/ext/sst/ExtSlave.cc
+++ b/ext/sst/ExtSlave.cc
@@ -48,13 +48,15 @@
#undef fatal
#endif
+#include <base/types.hh>
+
using namespace SST;
using namespace SST::gem5;
using namespace SST::MemHierarchy;
ExtSlave::ExtSlave(gem5Component *g5c, Output &out,
- ::ExternalSlave& port, std::string &name) :
- Port(name, port),
+ ::gem5::ExternalSlave& port, std::string &name) :
+ ::gem5::ExternalSlave::Port(name, port),
comp(g5c), out(out), simPhase(CONSTRUCTION), initPackets(NULL),
link(comp->configureLink(name, new Event::Handler<ExtSlave>(this,
&ExtSlave::handleEvent)))
@@ -64,7 +66,8 @@
}
}
-void ExtSlave::init(unsigned phase)
+void
+ExtSlave::init(unsigned phase)
{
simPhase = INIT;
if (initPackets) {
@@ -78,15 +81,16 @@
}
void
-ExtSlave::recvFunctional(PacketPtr pkt)
+ExtSlave::recvFunctional(::gem5::PacketPtr pkt)
{
if (simPhase == CONSTRUCTION) {
if (initPackets == NULL) {
initPackets = new std::list<MemEvent*>;
}
- ::MemCmd::Command pktCmd = (::MemCmd::Command)pkt->cmd.toInt();
- assert(pktCmd == ::MemCmd::WriteReq);
- Addr a = pkt->getAddr();
+ ::gem5::MemCmd::Command pktCmd =
+ (::gem5::MemCmd::Command)pkt->cmd.toInt();
+ assert(pktCmd == ::gem5::MemCmd::WriteReq);
+ ::gem5::Addr a = pkt->getAddr();
MemEvent* ev = new MemEvent(comp, a, a, GetX);
ev->setPayload(pkt->getSize(), pkt->getPtr<uint8_t>());
initPackets->push_back(ev);
@@ -96,17 +100,17 @@
}
bool
-ExtSlave::recvTimingReq(PacketPtr pkt)
+ExtSlave::recvTimingReq(::gem5::PacketPtr pkt)
{
Command cmd;
- switch ((::MemCmd::Command)pkt->cmd.toInt()) {
- case ::MemCmd::HardPFReq:
- case ::MemCmd::SoftPFReq:
- case ::MemCmd::LoadLockedReq:
- case ::MemCmd::ReadExReq:
- case ::MemCmd::ReadReq: cmd = GetS; break;
- case ::MemCmd::StoreCondReq:
- case ::MemCmd::WriteReq: cmd = GetX; break;
+ switch ((::gem5::MemCmd::Command)pkt->cmd.toInt()) {
+ case ::gem5::MemCmd::HardPFReq:
+ case ::gem5::MemCmd::SoftPFReq:
+ case ::gem5::MemCmd::LoadLockedReq:
+ case ::gem5::MemCmd::ReadExReq:
+ case ::gem5::MemCmd::ReadReq: cmd = GetS; break;
+ case ::gem5::MemCmd::StoreCondReq:
+ case ::gem5::MemCmd::WriteReq: cmd = GetX; break;
default:
out.fatal(CALL_INFO, 1, "Don't know how to convert gem5 packet "
"command %s to SST\n", pkt->cmd.toString().c_str());
@@ -114,10 +118,13 @@
auto ev = new MemEvent(comp, pkt->getAddr(), pkt->getAddr(), cmd);
ev->setPayload(pkt->getSize(), pkt->getPtr<uint8_t>());
- if ((::MemCmd::Command)pkt->cmd.toInt() == ::MemCmd::LoadLockedReq)
+ if ((::gem5::MemCmd::Command)pkt->cmd.toInt() ==
+ ::gem5::MemCmd::LoadLockedReq) {
ev->setLoadLink();
- else if ((::MemCmd::Command)pkt->cmd.toInt() == ::MemCmd::StoreCondReq)
+ } else if ((::gem5::MemCmd::Command)pkt->cmd.toInt() ==
+ ::gem5::MemCmd::StoreCondReq) {
ev->setStoreConditional();
+ }
if (pkt->req->isLockedRMW()) ev->setFlag(MemEvent::F_LOCKED);
if (pkt->req->isUncacheable()) ev->setFlag(MemEvent::F_NONCACHEABLE);
@@ -152,7 +159,7 @@
PacketMap_t::iterator mi = PacketMap.find(id);
if (mi != PacketMap.end()) { // replying to prior request
- PacketPtr pkt = mi->second;
+ ::gem5::PacketPtr pkt = mi->second;
PacketMap.erase(mi);
pkt->makeResponse(); // Convert to a response packet
@@ -175,10 +182,10 @@
// make Req/Pkt for Snoop/no response needed
// presently no consideration for masterId, packet type, flags...
- RequestPtr req = std::make_shared<Request>(
+ ::gem5::RequestPtr req = std::make_shared<::gem5::Request>(
event->getAddr(), event->getSize(), 0, 0);
- auto pkt = new Packet(req, ::MemCmd::InvalidateReq);
+ auto pkt = new ::gem5::Packet(req, ::gem5::MemCmd::InvalidateReq);
// Clear out bus delay notifications
pkt->headerDelay = pkt->payloadDelay = 0;
diff --git a/ext/sst/ExtSlave.hh b/ext/sst/ExtSlave.hh
index cef7c1e..fa32655 100644
--- a/ext/sst/ExtSlave.hh
+++ b/ext/sst/ExtSlave.hh
@@ -45,12 +45,16 @@
#ifndef EXT_SST_EXTSLAVE_HH
#define EXT_SST_EXTSLAVE_HH
+#include <list>
+#include <string>
+
#include <core/interfaces/simpleMem.h>
-#include <sim/sim_object.hh>
+#include <base/logging.hh>
#include <mem/packet.hh>
#include <mem/request.hh>
#include <mem/external_slave.hh>
+#include <sim/sim_object.hh>
namespace SST {
class Link;
@@ -60,25 +64,26 @@
class gem5Component;
-class ExtSlave : public ExternalSlave::Port {
+class ExtSlave : public ::gem5::ExternalSlave::Port
+{
public:
const std::string name;
bool
- recvTimingSnoopResp(PacketPtr packet)
+ recvTimingSnoopResp(::gem5::PacketPtr packet)
{
fatal("recvTimingSnoopResp unimplemented");
return false;
}
- bool recvTimingReq(PacketPtr packet);
+ bool recvTimingReq(::gem5::PacketPtr packet);
- void recvFunctional(PacketPtr packet);
+ void recvFunctional(::gem5::PacketPtr packet);
void recvRespRetry();
- Tick
- recvAtomic(PacketPtr packet)
+ ::gem5::Tick
+ recvAtomic(::gem5::PacketPtr packet)
{
fatal("recvAtomic unimplemented");
}
@@ -91,14 +96,14 @@
std::list<MemEvent*>* initPackets;
Link* link;
- std::list<PacketPtr> respQ;
+ std::list<::gem5::PacketPtr> respQ;
bool blocked() { return !respQ.empty(); }
- typedef std::map<Event::id_type, ::Packet*> PacketMap_t;
+ typedef std::map<Event::id_type, ::gem5::Packet*> PacketMap_t;
PacketMap_t PacketMap; // SST Event id -> gem5 Packet*
public:
- ExtSlave(gem5Component*, Output&, ExternalSlave&, std::string&);
+ ExtSlave(gem5Component*, Output&, ::gem5::ExternalSlave&, std::string&);
void init(unsigned phase);
void
diff --git a/ext/sst/gem5.cc b/ext/sst/gem5.cc
index 3d48e93..efe73eb 100644
--- a/ext/sst/gem5.cc
+++ b/ext/sst/gem5.cc
@@ -108,14 +108,15 @@
splitCommandArgs(gem5DbgFlags, flags);
for (auto flag : flags) {
dbg.output(CALL_INFO, " Setting Debug Flag [%s]\n", flag);
- setDebugFlag(flag);
+ ::gem5::setDebugFlag(flag);
}
- ExternalMaster::registerHandler("sst", this); // these are idempotent
- ExternalSlave ::registerHandler("sst", this);
+ // These are idempotent
+ ::gem5::ExternalMaster::registerHandler("sst", this);
+ ::gem5::ExternalSlave::registerHandler("sst", this);
- // Initialize m5 special signal handling.
- initSignals();
+ // Initialize gem5's special signal handling.
+ ::gem5::initSignals();
initPython(args.size(), &args[0]);
@@ -172,11 +173,12 @@
m->clock();
}
- GlobalSimLoopExitEvent *event = simulate(sim_cycles);
+ ::gem5::GlobalSimLoopExitEvent *event = ::gem5::simulate(sim_cycles);
++clocks_processed;
if (event != simulate_limit_event) {
info.output("exiting: curTick()=%lu cause=`%s` code=%d\n",
- curTick(), event->getCause().c_str(), event->getCode());
+ ::gem5::curTick(), event->getCause().c_str(),
+ event->getCode());
primaryComponentOKToEndSim();
return true;
}
@@ -248,9 +250,9 @@
}
}
-ExternalMaster::Port*
+::gem5::ExternalMaster::Port*
gem5Component::getExternalPort(const std::string &name,
- ExternalMaster &owner, const std::string &port_data)
+ ::gem5::ExternalMaster &owner, const std::string &port_data)
{
std::string s(name); // bridges non-& result and &-arg
auto master = new ExtMaster(this, info, owner, s);
@@ -258,9 +260,9 @@
return master;
}
-ExternalSlave::Port*
+::gem5::ExternalSlave::Port*
gem5Component::getExternalPort(const std::string &name,
- ExternalSlave &owner, const std::string &port_data)
+ ::gem5::ExternalSlave &owner, const std::string &port_data)
{
std::string s(name); // bridges non-& result and &-arg
auto slave = new ExtSlave(this, info, owner, s);
diff --git a/ext/sst/gem5.hh b/ext/sst/gem5.hh
index 0f1bed8..4dc0213 100644
--- a/ext/sst/gem5.hh
+++ b/ext/sst/gem5.hh
@@ -45,12 +45,15 @@
#ifndef EXT_SST_GEM5_HH
#define EXT_SST_GEM5_HH
+#include <cstdint>
#include <string>
#include <vector>
#include <core/sst_config.h>
#include <core/component.h>
+#include <mem/external_master.hh>
+#include <mem/external_slave.hh>
#include <sim/simulate.hh>
#include "ExtMaster.hh"
@@ -60,8 +63,9 @@
namespace gem5 {
class gem5Component : public SST::Component,
- public ExternalSlave::Handler,
- public ExternalMaster::Handler {
+ public ::gem5::ExternalSlave::Handler,
+ public ::gem5::ExternalMaster::Handler
+{
private:
Output dbg;
@@ -83,12 +87,12 @@
virtual void finish();
bool clockTick(Cycle_t);
- virtual ExternalMaster::Port *getExternalPort(
- const std::string &name, ExternalMaster &owner,
+ virtual ::gem5::ExternalMaster::Port *getExternalPort(
+ const std::string &name, ::gem5::ExternalMaster &owner,
const std::string &port_data);
- virtual ExternalSlave::Port *getExternalPort(
- const std::string &name, ExternalSlave &owner,
+ virtual ::gem5::ExternalSlave::Port *getExternalPort(
+ const std::string &name, ::gem5::ExternalSlave &owner,
const std::string &port_data);
};
diff --git a/src/SConscript b/src/SConscript
index 804160b..c254269 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1084,6 +1084,9 @@
if not hasattr(simobj, 'abstract') or not simobj.abstract:
code('#include "cxx_config/${name}.hh"')
code()
+ code('namespace gem5')
+ code('{')
+ code()
code('void cxxConfigInit()')
code('{')
code.indent()
@@ -1095,6 +1098,8 @@
'${name}CxxConfigParams::makeDirectoryEntry();')
code.dedent()
code('}')
+ code('')
+ code('} // namespace gem5')
code.write(target[0].abspath)
py_source = PySource.modules[simobj.__module__]
@@ -1151,6 +1156,9 @@
code('''
#include "base/debug.hh"
+namespace gem5
+{
+
namespace Debug {
''')
@@ -1189,6 +1197,7 @@
code.append(comp_code)
code()
code('} // namespace Debug')
+ code('} // namespace gem5')
code.write(str(target[0]))
@@ -1205,6 +1214,9 @@
#ifndef __DEBUG_${name}_HH__
#define __DEBUG_${name}_HH__
+namespace gem5
+{
+
namespace Debug {
''')
@@ -1220,7 +1232,8 @@
code('extern SimpleFlag& $name;')
code('''
-}
+} // namespace Debug
+} // namespace gem5
#endif // __DEBUG_${name}_HH__
''')
@@ -1282,7 +1295,10 @@
code('''\
#include "sim/init.hh"
-namespace {
+namespace gem5
+{
+namespace
+{
''')
blobToCpp(data, 'data_' + sym, code)
@@ -1298,6 +1314,7 @@
${{len(marshalled)}});
} // anonymous namespace
+} // namespace gem5
''')
code.write(str(target[0]))
diff --git a/src/arch/amdgpu/gcn3/decoder.cc b/src/arch/amdgpu/gcn3/decoder.cc
index 366b9fb..ec7ee4e 100644
--- a/src/arch/amdgpu/gcn3/decoder.cc
+++ b/src/arch/amdgpu/gcn3/decoder.cc
@@ -37,6 +37,9 @@
#include "arch/amdgpu/gcn3/insts/gpu_static_inst.hh"
#include "arch/amdgpu/gcn3/insts/instructions.hh"
+namespace gem5
+{
+
namespace Gcn3ISA
{
Decoder::Decoder()
@@ -10810,3 +10813,4 @@
return nullptr;
}
} // namespace Gcn3ISA
+} // namespace gem5
diff --git a/src/arch/amdgpu/gcn3/gpu_decoder.hh b/src/arch/amdgpu/gcn3/gpu_decoder.hh
index 52bd222..02a420b 100644
--- a/src/arch/amdgpu/gcn3/gpu_decoder.hh
+++ b/src/arch/amdgpu/gcn3/gpu_decoder.hh
@@ -39,6 +39,9 @@
#include "arch/amdgpu/gcn3/gpu_types.hh"
+namespace gem5
+{
+
class GPUStaticInst;
namespace Gcn3ISA
@@ -1670,5 +1673,6 @@
float imm_f32;
}; // union InstFormat
} // namespace Gcn3ISA
+} // namespace gem5
#endif // __ARCH_GCN3_DECODER_HH__
diff --git a/src/arch/amdgpu/gcn3/gpu_isa.hh b/src/arch/amdgpu/gcn3/gpu_isa.hh
index 5d90556..076e2a6 100644
--- a/src/arch/amdgpu/gcn3/gpu_isa.hh
+++ b/src/arch/amdgpu/gcn3/gpu_isa.hh
@@ -42,6 +42,9 @@
#include "gpu-compute/hsa_queue_entry.hh"
#include "gpu-compute/misc.hh"
+namespace gem5
+{
+
class Wavefront;
namespace Gcn3ISA
@@ -99,5 +102,6 @@
ScalarRegU32 m0;
};
} // namespace Gcn3ISA
+} // namespace gem5
#endif // __ARCH_GCN3_GPU_ISA_HH__
diff --git a/src/arch/amdgpu/gcn3/gpu_mem_helpers.hh b/src/arch/amdgpu/gcn3/gpu_mem_helpers.hh
index 0562622..0a0b304 100644
--- a/src/arch/amdgpu/gcn3/gpu_mem_helpers.hh
+++ b/src/arch/amdgpu/gcn3/gpu_mem_helpers.hh
@@ -39,6 +39,9 @@
#include "debug/GPUMem.hh"
#include "gpu-compute/gpu_dyn_inst.hh"
+namespace gem5
+{
+
/**
* Helper function for instructions declared in op_encodings. This function
* takes in all of the arguments for a given memory request we are trying to
@@ -183,4 +186,6 @@
}
}
+} // namespace gem5
+
#endif // __ARCH_GCN3_GPU_MEM_HELPERS_HH__
diff --git a/src/arch/amdgpu/gcn3/gpu_registers.hh b/src/arch/amdgpu/gcn3/gpu_registers.hh
index 783b16f..e897d68 100644
--- a/src/arch/amdgpu/gcn3/gpu_registers.hh
+++ b/src/arch/amdgpu/gcn3/gpu_registers.hh
@@ -42,6 +42,9 @@
#include "base/intmath.hh"
#include "base/logging.hh"
+namespace gem5
+{
+
namespace Gcn3ISA
{
enum OpSelector : int
@@ -227,5 +230,6 @@
bool isExecMask(int opIdx);
bool isVccReg(int opIdx);
} // namespace Gcn3ISA
+} // namespace gem5
#endif // __ARCH_GCN3_REGISTERS_HH__
diff --git a/src/arch/amdgpu/gcn3/gpu_types.hh b/src/arch/amdgpu/gcn3/gpu_types.hh
index 79839c8..4c7e288 100644
--- a/src/arch/amdgpu/gcn3/gpu_types.hh
+++ b/src/arch/amdgpu/gcn3/gpu_types.hh
@@ -36,6 +36,9 @@
#include <cstdint>
+namespace gem5
+{
+
namespace Gcn3ISA
{
union InstFormat;
@@ -60,5 +63,6 @@
typedef InstFormat *MachInst;
} // namespace Gcn3ISA
+} // namespace gem5
#endif // __ARCH_GCN3_GPU_TYPES_HH__
diff --git a/src/arch/amdgpu/gcn3/insts/gpu_static_inst.cc b/src/arch/amdgpu/gcn3/insts/gpu_static_inst.cc
index 4fa2ba1..2cedbe1 100644
--- a/src/arch/amdgpu/gcn3/insts/gpu_static_inst.cc
+++ b/src/arch/amdgpu/gcn3/insts/gpu_static_inst.cc
@@ -38,6 +38,9 @@
#include "debug/GPUExec.hh"
#include "gpu-compute/shader.hh"
+namespace gem5
+{
+
namespace Gcn3ISA
{
GCN3GPUStaticInst::GCN3GPUStaticInst(const std::string &opcode)
@@ -55,3 +58,4 @@
fatal("Encountered unimplemented GCN3 instruction: %s\n", _opcode);
}
} // namespace Gcn3ISA
+} // namespace gem5
diff --git a/src/arch/amdgpu/gcn3/insts/gpu_static_inst.hh b/src/arch/amdgpu/gcn3/insts/gpu_static_inst.hh
index c590e82..82f5714 100644
--- a/src/arch/amdgpu/gcn3/insts/gpu_static_inst.hh
+++ b/src/arch/amdgpu/gcn3/insts/gpu_static_inst.hh
@@ -41,6 +41,9 @@
#include "gpu-compute/vector_register_file.hh"
#include "gpu-compute/wavefront.hh"
+namespace gem5
+{
+
namespace Gcn3ISA
{
class GCN3GPUStaticInst : public GPUStaticInst
@@ -88,4 +91,6 @@
}; // class GCN3GPUStaticInst
} // namespace Gcn3ISA
+} // namespace gem5
+
#endif //__ARCH_GCN3_INSTS_GPU_STATIC_INST_HH__
diff --git a/src/arch/amdgpu/gcn3/insts/inst_util.hh b/src/arch/amdgpu/gcn3/insts/inst_util.hh
index 9f73592..95cb6db 100644
--- a/src/arch/amdgpu/gcn3/insts/inst_util.hh
+++ b/src/arch/amdgpu/gcn3/insts/inst_util.hh
@@ -38,6 +38,9 @@
#include "arch/amdgpu/gcn3/gpu_registers.hh"
+namespace gem5
+{
+
// values for SDWA select operations
enum SDWASelVals : int
{
@@ -890,5 +893,6 @@
sdwaInstDstImpl(dst, origDst, clamp, dst_sel, dst_unusedBits_format);
}
} // namespace Gcn3ISA
+} // namespace gem5
#endif // __ARCH_GCN3_INSTS_INST_UTIL_HH__
diff --git a/src/arch/amdgpu/gcn3/insts/instructions.cc b/src/arch/amdgpu/gcn3/insts/instructions.cc
index 0a9a966..b5a4300 100644
--- a/src/arch/amdgpu/gcn3/insts/instructions.cc
+++ b/src/arch/amdgpu/gcn3/insts/instructions.cc
@@ -40,6 +40,9 @@
#include "debug/GPUSync.hh"
#include "gpu-compute/shader.hh"
+namespace gem5
+{
+
namespace Gcn3ISA
{
@@ -41909,3 +41912,4 @@
}
} // completeAcc
} // namespace Gcn3ISA
+} // namespace gem5
diff --git a/src/arch/amdgpu/gcn3/insts/instructions.hh b/src/arch/amdgpu/gcn3/insts/instructions.hh
index 2e239c2..1ee8220 100644
--- a/src/arch/amdgpu/gcn3/insts/instructions.hh
+++ b/src/arch/amdgpu/gcn3/insts/instructions.hh
@@ -39,6 +39,9 @@
#include "arch/amdgpu/gcn3/insts/op_encodings.hh"
#include "debug/GCN3.hh"
+namespace gem5
+{
+
namespace Gcn3ISA
{
class Inst_SOP2__S_ADD_U32 : public Inst_SOP2
@@ -42709,5 +42712,6 @@
void completeAcc(GPUDynInstPtr) override;
}; // Inst_FLAT__FLAT_ATOMIC_DEC_X2
} // namespace Gcn3ISA
+} // namespace gem5
#endif // __ARCH_GCN3_INSTS_INSTRUCTIONS_HH__
diff --git a/src/arch/amdgpu/gcn3/insts/op_encodings.cc b/src/arch/amdgpu/gcn3/insts/op_encodings.cc
index 6fd2be3..cbbb767 100644
--- a/src/arch/amdgpu/gcn3/insts/op_encodings.cc
+++ b/src/arch/amdgpu/gcn3/insts/op_encodings.cc
@@ -35,6 +35,9 @@
#include <iomanip>
+namespace gem5
+{
+
namespace Gcn3ISA
{
// --- Inst_SOP2 base class methods ---
@@ -1588,3 +1591,4 @@
disassembly = dis_stream.str();
}
} // namespace Gcn3ISA
+} // namespace gem5
diff --git a/src/arch/amdgpu/gcn3/insts/op_encodings.hh b/src/arch/amdgpu/gcn3/insts/op_encodings.hh
index ee42824..c4e107c 100644
--- a/src/arch/amdgpu/gcn3/insts/op_encodings.hh
+++ b/src/arch/amdgpu/gcn3/insts/op_encodings.hh
@@ -42,6 +42,9 @@
#include "debug/GPUExec.hh"
#include "mem/ruby/system/RubySystem.hh"
+namespace gem5
+{
+
namespace Gcn3ISA
{
struct BufferRsrcDescriptor
@@ -806,5 +809,6 @@
InFmt_FLAT_1 extData;
}; // Inst_FLAT
} // namespace Gcn3ISA
+} // namespace gem5
#endif // __ARCH_GCN3_INSTS_OP_ENCODINGS_HH__
diff --git a/src/arch/amdgpu/gcn3/isa.cc b/src/arch/amdgpu/gcn3/isa.cc
index 560985d..9349045 100644
--- a/src/arch/amdgpu/gcn3/isa.cc
+++ b/src/arch/amdgpu/gcn3/isa.cc
@@ -38,6 +38,9 @@
#include "gpu-compute/gpu_static_inst.hh"
#include "gpu-compute/wavefront.hh"
+namespace gem5
+{
+
namespace Gcn3ISA
{
GPUISA::GPUISA(Wavefront &wf) : wavefront(wf), m0(0)
@@ -99,3 +102,4 @@
-16
} };
} // namespace Gcn3ISA
+} // namespace gem5
diff --git a/src/arch/amdgpu/gcn3/operand.hh b/src/arch/amdgpu/gcn3/operand.hh
index 9ff4c8c..12f5d27 100644
--- a/src/arch/amdgpu/gcn3/operand.hh
+++ b/src/arch/amdgpu/gcn3/operand.hh
@@ -42,6 +42,9 @@
#include "gpu-compute/vector_register_file.hh"
#include "gpu-compute/wavefront.hh"
+namespace gem5
+{
+
/**
* classes that represnt vector/scalar operands in GCN3 ISA. these classes
* wrap the generic vector register type (i.e., src/arch/generic/vec_reg.hh)
@@ -743,4 +746,6 @@
using ConstVecOperandU512 = VecOperand<VecElemU32, true, 16>;
}
+} // namespace gem5
+
#endif // __ARCH_GCN3_OPERAND_HH__
diff --git a/src/arch/amdgpu/gcn3/registers.cc b/src/arch/amdgpu/gcn3/registers.cc
index 182f677..7a06567 100644
--- a/src/arch/amdgpu/gcn3/registers.cc
+++ b/src/arch/amdgpu/gcn3/registers.cc
@@ -33,6 +33,9 @@
#include "arch/amdgpu/gcn3/gpu_registers.hh"
+namespace gem5
+{
+
namespace Gcn3ISA
{
std::string
@@ -234,3 +237,4 @@
}
} // namespace Gcn3ISA
+} // namespace gem5
diff --git a/src/arch/amdgpu/vega/decoder.cc b/src/arch/amdgpu/vega/decoder.cc
index 363f7e1..359e125 100644
--- a/src/arch/amdgpu/vega/decoder.cc
+++ b/src/arch/amdgpu/vega/decoder.cc
@@ -37,6 +37,9 @@
#include "arch/amdgpu/vega/insts/gpu_static_inst.hh"
#include "arch/amdgpu/vega/insts/instructions.hh"
+namespace gem5
+{
+
namespace VegaISA
{
Decoder::Decoder()
@@ -12830,3 +12833,4 @@
return nullptr;
}
} // namespace VegaISA
+} // namespace gem5
diff --git a/src/arch/amdgpu/vega/gpu_decoder.hh b/src/arch/amdgpu/vega/gpu_decoder.hh
index 0159589..878dc8b 100644
--- a/src/arch/amdgpu/vega/gpu_decoder.hh
+++ b/src/arch/amdgpu/vega/gpu_decoder.hh
@@ -39,6 +39,9 @@
#include "arch/amdgpu/vega/gpu_types.hh"
+namespace gem5
+{
+
class GPUStaticInst;
namespace VegaISA
@@ -1934,5 +1937,6 @@
float imm_f32;
}; // union InstFormat
} // namespace VegaISA
+} // namespace gem5
#endif // __ARCH_VEGA_DECODER_HH__
diff --git a/src/arch/amdgpu/vega/gpu_isa.hh b/src/arch/amdgpu/vega/gpu_isa.hh
index 3c6d80f..c962398 100644
--- a/src/arch/amdgpu/vega/gpu_isa.hh
+++ b/src/arch/amdgpu/vega/gpu_isa.hh
@@ -42,6 +42,9 @@
#include "gpu-compute/hsa_queue_entry.hh"
#include "gpu-compute/misc.hh"
+namespace gem5
+{
+
class Wavefront;
namespace VegaISA
@@ -99,5 +102,6 @@
ScalarRegU32 m0;
};
} // namespace VegaISA
+} // namespace gem5
#endif // __ARCH_VEGA_GPU_ISA_HH__
diff --git a/src/arch/amdgpu/vega/gpu_mem_helpers.hh b/src/arch/amdgpu/vega/gpu_mem_helpers.hh
index 3f4084c..3b2aa77 100644
--- a/src/arch/amdgpu/vega/gpu_mem_helpers.hh
+++ b/src/arch/amdgpu/vega/gpu_mem_helpers.hh
@@ -39,6 +39,9 @@
#include "debug/GPUMem.hh"
#include "gpu-compute/gpu_dyn_inst.hh"
+namespace gem5
+{
+
/**
* Helper function for instructions declared in op_encodings. This function
* takes in all of the arguments for a given memory request we are trying to
@@ -183,4 +186,6 @@
}
}
+} // namespace gem5
+
#endif // __ARCH_VEGA_GPU_MEM_HELPERS_HH__
diff --git a/src/arch/amdgpu/vega/gpu_registers.hh b/src/arch/amdgpu/vega/gpu_registers.hh
index 6118fb2..d744a90 100644
--- a/src/arch/amdgpu/vega/gpu_registers.hh
+++ b/src/arch/amdgpu/vega/gpu_registers.hh
@@ -42,6 +42,9 @@
#include "base/intmath.hh"
#include "base/logging.hh"
+namespace gem5
+{
+
namespace VegaISA
{
enum OpSelector : int
@@ -229,5 +232,6 @@
bool isExecMask(int opIdx);
bool isVccReg(int opIdx);
} // namespace VegaISA
+} // namespace gem5
#endif // __ARCH_VEGA_REGISTERS_HH__
diff --git a/src/arch/amdgpu/vega/gpu_types.hh b/src/arch/amdgpu/vega/gpu_types.hh
index 42b1127..e40230a 100644
--- a/src/arch/amdgpu/vega/gpu_types.hh
+++ b/src/arch/amdgpu/vega/gpu_types.hh
@@ -36,6 +36,9 @@
#include <cstdint>
+namespace gem5
+{
+
namespace VegaISA
{
union InstFormat;
@@ -60,5 +63,6 @@
typedef InstFormat *MachInst;
} // namespace VegaISA
+} // namespace gem5
#endif // __ARCH_VEGA_GPU_TYPES_HH__
diff --git a/src/arch/amdgpu/vega/insts/gpu_static_inst.cc b/src/arch/amdgpu/vega/insts/gpu_static_inst.cc
index a78834a..ffaffab 100644
--- a/src/arch/amdgpu/vega/insts/gpu_static_inst.cc
+++ b/src/arch/amdgpu/vega/insts/gpu_static_inst.cc
@@ -39,6 +39,9 @@
#include "gpu-compute/flexible_pool_manager.hh"
#include "gpu-compute/shader.hh"
+namespace gem5
+{
+
namespace VegaISA
{
VEGAGPUStaticInst::VEGAGPUStaticInst(const std::string &opcode)
@@ -56,3 +59,4 @@
fatal("Encountered unimplemented VEGA instruction: %s\n", _opcode);
}
} // namespace VegaISA
+} // namespace gem5
diff --git a/src/arch/amdgpu/vega/insts/gpu_static_inst.hh b/src/arch/amdgpu/vega/insts/gpu_static_inst.hh
index 8d31672..64151f7 100644
--- a/src/arch/amdgpu/vega/insts/gpu_static_inst.hh
+++ b/src/arch/amdgpu/vega/insts/gpu_static_inst.hh
@@ -41,6 +41,9 @@
#include "gpu-compute/vector_register_file.hh"
#include "gpu-compute/wavefront.hh"
+namespace gem5
+{
+
namespace VegaISA
{
class VEGAGPUStaticInst : public GPUStaticInst
@@ -82,4 +85,6 @@
}; // class VEGAGPUStaticInst
} // namespace VegaISA
+} // namespace gem5
+
#endif //__ARCH_VEGA_INSTS_GPU_STATIC_INST_HH__
diff --git a/src/arch/amdgpu/vega/insts/inst_util.hh b/src/arch/amdgpu/vega/insts/inst_util.hh
index 39c0eb1..d392ac8 100644
--- a/src/arch/amdgpu/vega/insts/inst_util.hh
+++ b/src/arch/amdgpu/vega/insts/inst_util.hh
@@ -38,6 +38,9 @@
#include "arch/amdgpu/vega/gpu_registers.hh"
+namespace gem5
+{
+
// values for SDWA select operations
enum SDWASelVals : int
{
@@ -890,5 +893,6 @@
sdwaInstDstImpl(dst, origDst, clamp, dst_sel, dst_unusedBits_format);
}
} // namespace VegaISA
+} // namespace gem5
#endif // __ARCH_VEGA_INSTS_INST_UTIL_HH__
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc b/src/arch/amdgpu/vega/insts/instructions.cc
index b0a6cb0..9e707ba 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -40,6 +40,9 @@
#include "debug/GPUSync.hh"
#include "gpu-compute/shader.hh"
+namespace gem5
+{
+
namespace VegaISA
{
// --- Inst_SOP2__S_ADD_U32 class methods ---
@@ -44433,3 +44436,4 @@
panicUnimplemented();
} // execute
} // namespace VegaISA
+} // namespace gem5
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh b/src/arch/amdgpu/vega/insts/instructions.hh
index b815d3e..14e04cf 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -39,6 +39,9 @@
#include "arch/amdgpu/vega/insts/op_encodings.hh"
#include "debug/VEGA.hh"
+namespace gem5
+{
+
namespace VegaISA
{
class Inst_SOP2__S_ADD_U32 : public Inst_SOP2
@@ -42799,5 +42802,6 @@
void execute(GPUDynInstPtr) override;
}; // Inst_FLAT__FLAT_ATOMIC_DEC_X2
} // namespace VegaISA
+} // namespace gem5
#endif // __ARCH_VEGA_INSTS_INSTRUCTIONS_HH__
diff --git a/src/arch/amdgpu/vega/insts/op_encodings.cc b/src/arch/amdgpu/vega/insts/op_encodings.cc
index 1c25f6b..e37a2fb 100644
--- a/src/arch/amdgpu/vega/insts/op_encodings.cc
+++ b/src/arch/amdgpu/vega/insts/op_encodings.cc
@@ -35,6 +35,9 @@
#include <iomanip>
+namespace gem5
+{
+
namespace VegaISA
{
// --- Inst_SOP2 base class methods ---
@@ -1590,3 +1593,4 @@
disassembly = dis_stream.str();
}
} // namespace VegaISA
+} // namespace gem5
diff --git a/src/arch/amdgpu/vega/insts/op_encodings.hh b/src/arch/amdgpu/vega/insts/op_encodings.hh
index 6952c1f..83e559b 100644
--- a/src/arch/amdgpu/vega/insts/op_encodings.hh
+++ b/src/arch/amdgpu/vega/insts/op_encodings.hh
@@ -42,6 +42,9 @@
#include "debug/VEGA.hh"
#include "mem/ruby/system/RubySystem.hh"
+namespace gem5
+{
+
namespace VegaISA
{
struct BufferRsrcDescriptor
@@ -807,5 +810,6 @@
InFmt_FLAT_1 extData;
}; // Inst_FLAT
} // namespace VegaISA
+} // namespace gem5
#endif // __ARCH_VEGA_INSTS_OP_ENCODINGS_HH__
diff --git a/src/arch/amdgpu/vega/isa.cc b/src/arch/amdgpu/vega/isa.cc
index fdd8828..459a6e5 100644
--- a/src/arch/amdgpu/vega/isa.cc
+++ b/src/arch/amdgpu/vega/isa.cc
@@ -38,6 +38,9 @@
#include "gpu-compute/gpu_static_inst.hh"
#include "gpu-compute/wavefront.hh"
+namespace gem5
+{
+
namespace VegaISA
{
GPUISA::GPUISA(Wavefront &wf) : wavefront(wf), m0(0)
@@ -99,3 +102,4 @@
-16
} };
} // namespace VegaISA
+} // namespace gem5
diff --git a/src/arch/amdgpu/vega/operand.hh b/src/arch/amdgpu/vega/operand.hh
index bb89fb3..aa8b854 100644
--- a/src/arch/amdgpu/vega/operand.hh
+++ b/src/arch/amdgpu/vega/operand.hh
@@ -42,6 +42,9 @@
#include "gpu-compute/vector_register_file.hh"
#include "gpu-compute/wavefront.hh"
+namespace gem5
+{
+
/**
* classes that represnt vector/scalar operands in VEGA ISA. these classes
* wrap the generic vector register type (i.e., src/arch/generic/vec_reg.hh)
@@ -733,4 +736,6 @@
using ConstVecOperandU512 = VecOperand<VecElemU32, true, 16>;
}
+} // namespace gem5
+
#endif // __ARCH_VEGA_OPERAND_HH__
diff --git a/src/arch/amdgpu/vega/registers.cc b/src/arch/amdgpu/vega/registers.cc
index 4352c88..6b75222 100644
--- a/src/arch/amdgpu/vega/registers.cc
+++ b/src/arch/amdgpu/vega/registers.cc
@@ -33,6 +33,9 @@
#include "arch/amdgpu/vega/gpu_registers.hh"
+namespace gem5
+{
+
namespace VegaISA
{
std::string
@@ -243,3 +246,4 @@
}
} // namespace VegaISA
+} // namespace gem5
diff --git a/src/arch/arm/ArmFsWorkload.py b/src/arch/arm/ArmFsWorkload.py
index b57b1f0..974600b 100644
--- a/src/arch/arm/ArmFsWorkload.py
+++ b/src/arch/arm/ArmFsWorkload.py
@@ -48,7 +48,7 @@
class ArmFsWorkload(KernelWorkload):
type = 'ArmFsWorkload'
cxx_header = "arch/arm/fs_workload.hh"
- cxx_class = "ArmISA::FsWorkload"
+ cxx_class = 'gem5::ArmISA::FsWorkload'
boot_loader = VectorParam.String([],
"File that contains the boot loader code. Zero or more files may be "
@@ -75,7 +75,7 @@
class ArmFsLinux(ArmFsWorkload):
type = 'ArmFsLinux'
cxx_header = "arch/arm/linux/fs_workload.hh"
- cxx_class = "ArmISA::FsLinux"
+ cxx_class = 'gem5::ArmISA::FsLinux'
load_addr_mask = 0
@@ -87,4 +87,4 @@
class ArmFsFreebsd(ArmFsWorkload):
type = 'ArmFsFreebsd'
cxx_header = "arch/arm/freebsd/fs_workload.hh"
- cxx_class = "ArmISA::FsFreebsd"
+ cxx_class = 'gem5::ArmISA::FsFreebsd'
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index f210f7e..55dcdf4 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -47,7 +47,7 @@
class ArmISA(BaseISA):
type = 'ArmISA'
- cxx_class = 'ArmISA::ISA'
+ cxx_class = 'gem5::ArmISA::ISA'
cxx_header = "arch/arm/isa.hh"
system = Param.System(Parent.any, "System this ISA object belongs to")
diff --git a/src/arch/arm/ArmInterrupts.py b/src/arch/arm/ArmInterrupts.py
index aec7a28..c683fe2 100644
--- a/src/arch/arm/ArmInterrupts.py
+++ b/src/arch/arm/ArmInterrupts.py
@@ -28,5 +28,5 @@
class ArmInterrupts(BaseInterrupts):
type = 'ArmInterrupts'
- cxx_class = 'ArmISA::Interrupts'
+ cxx_class = 'gem5::ArmISA::Interrupts'
cxx_header = "arch/arm/interrupts.hh"
diff --git a/src/arch/arm/ArmMMU.py b/src/arch/arm/ArmMMU.py
index e44be84..00a0b31 100644
--- a/src/arch/arm/ArmMMU.py
+++ b/src/arch/arm/ArmMMU.py
@@ -44,7 +44,7 @@
# Basic stage 1 translation objects
class ArmTableWalker(ClockedObject):
type = 'ArmTableWalker'
- cxx_class = 'ArmISA::TableWalker'
+ cxx_class = 'gem5::ArmISA::TableWalker'
cxx_header = "arch/arm/table_walker.hh"
is_stage2 = Param.Bool(False, "Is this object for stage 2 translation?")
num_squash_per_cycle = Param.Unsigned(2,
@@ -60,7 +60,7 @@
class ArmMMU(BaseMMU):
type = 'ArmMMU'
- cxx_class = 'ArmISA::MMU'
+ cxx_class = 'gem5::ArmISA::MMU'
cxx_header = 'arch/arm/mmu.hh'
itb = ArmITB()
dtb = ArmDTB()
diff --git a/src/arch/arm/ArmNativeTrace.py b/src/arch/arm/ArmNativeTrace.py
index f01647a..c8bc272 100644
--- a/src/arch/arm/ArmNativeTrace.py
+++ b/src/arch/arm/ArmNativeTrace.py
@@ -30,7 +30,7 @@
class ArmNativeTrace(NativeTrace):
type = 'ArmNativeTrace'
- cxx_class = 'Trace::ArmNativeTrace'
+ cxx_class = 'gem5::Trace::ArmNativeTrace'
cxx_header = "arch/arm/nativetrace.hh"
stop_on_pc_error = Param.Bool(True,
"Stop M5 if it and statetrace's pcs are different")
diff --git a/src/arch/arm/ArmPMU.py b/src/arch/arm/ArmPMU.py
index 1839010..ec5dc2f 100644
--- a/src/arch/arm/ArmPMU.py
+++ b/src/arch/arm/ArmPMU.py
@@ -67,7 +67,7 @@
class ArmPMU(SimObject):
type = 'ArmPMU'
- cxx_class = 'ArmISA::PMU'
+ cxx_class = 'gem5::ArmISA::PMU'
cxx_header = 'arch/arm/pmu.hh'
cxx_exports = [
diff --git a/src/arch/arm/ArmSeWorkload.py b/src/arch/arm/ArmSeWorkload.py
index ca0e8a1..dfde24d 100644
--- a/src/arch/arm/ArmSeWorkload.py
+++ b/src/arch/arm/ArmSeWorkload.py
@@ -30,13 +30,13 @@
class ArmSEWorkload(SEWorkload):
type = 'ArmSEWorkload'
cxx_header = "arch/arm/se_workload.hh"
- cxx_class = 'ArmISA::SEWorkload'
+ cxx_class = 'gem5::ArmISA::SEWorkload'
abstract = True
class ArmEmuLinux(ArmSEWorkload):
type = 'ArmEmuLinux'
cxx_header = "arch/arm/linux/se_workload.hh"
- cxx_class = 'ArmISA::EmuLinux'
+ cxx_class = 'gem5::ArmISA::EmuLinux'
@classmethod
def _is_compatible_with(cls, obj):
@@ -46,7 +46,7 @@
class ArmEmuFreebsd(ArmSEWorkload):
type = 'ArmEmuFreebsd'
cxx_header = "arch/arm/freebsd/se_workload.hh"
- cxx_class = 'ArmISA::EmuFreebsd'
+ cxx_class = 'gem5::ArmISA::EmuFreebsd'
@classmethod
def _is_compatible_with(cls, obj):
diff --git a/src/arch/arm/ArmSemihosting.py b/src/arch/arm/ArmSemihosting.py
index 8674edc..8064a68 100644
--- a/src/arch/arm/ArmSemihosting.py
+++ b/src/arch/arm/ArmSemihosting.py
@@ -42,6 +42,7 @@
class ArmSemihosting(SimObject):
type = 'ArmSemihosting'
cxx_header = "arch/arm/semihosting.hh"
+ cxx_class = 'gem5::ArmSemihosting'
cmd_line = Param.String("", "Command line to report to guest");
stdin = Param.String("stdin",
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 142d6c7..585df3b 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -46,6 +46,8 @@
class ArmSystem(System):
type = 'ArmSystem'
cxx_header = "arch/arm/system.hh"
+ cxx_class = 'gem5::ArmSystem'
+
multi_proc = Param.Bool(True, "Multiprocessor system?")
gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface")
have_security = Param.Bool(False,
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index db981d6..4681d2e 100644
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -42,7 +42,7 @@
class ArmTLB(BaseTLB):
type = 'ArmTLB'
- cxx_class = 'ArmISA::TLB'
+ cxx_class = 'gem5::ArmISA::TLB'
cxx_header = "arch/arm/tlb.hh"
sys = Param.System(Parent.any, "system object parameter")
size = Param.Int(64, "TLB size")
diff --git a/src/arch/arm/aapcs32.hh b/src/arch/arm/aapcs32.hh
index 6302a6a..d773ad4 100644
--- a/src/arch/arm/aapcs32.hh
+++ b/src/arch/arm/aapcs32.hh
@@ -41,6 +41,9 @@
#include "sim/guest_abi.hh"
#include "sim/proxy_ptr.hh"
+namespace gem5
+{
+
class ThreadContext;
struct Aapcs32
@@ -637,5 +640,6 @@
};
} // namespace guest_abi
+} // namespace gem5
#endif // __ARCH_ARM_AAPCS32_HH__
diff --git a/src/arch/arm/aapcs64.hh b/src/arch/arm/aapcs64.hh
index 55e24d8..dd5a62e 100644
--- a/src/arch/arm/aapcs64.hh
+++ b/src/arch/arm/aapcs64.hh
@@ -40,6 +40,9 @@
#include "sim/guest_abi.hh"
#include "sim/proxy_ptr.hh"
+namespace gem5
+{
+
class ThreadContext;
struct Aapcs64
@@ -422,5 +425,6 @@
};
} // namespace guest_abi
+} // namespace gem5
#endif // __ARCH_ARM_AAPCS64_HH__
diff --git a/src/arch/arm/aapcs64.test.cc b/src/arch/arm/aapcs64.test.cc
index 8155d66..5d96ff6 100644
--- a/src/arch/arm/aapcs64.test.cc
+++ b/src/arch/arm/aapcs64.test.cc
@@ -29,6 +29,8 @@
#include "arch/arm/aapcs64.hh"
+using namespace gem5;
+
TEST(Aapcs64, IsAapcs64ShortVector)
{
using Scalar = uint64_t;
diff --git a/src/arch/arm/decoder.cc b/src/arch/arm/decoder.cc
index 4c1ec40..1867e90 100644
--- a/src/arch/arm/decoder.cc
+++ b/src/arch/arm/decoder.cc
@@ -46,6 +46,9 @@
#include "debug/Decoder.hh"
#include "sim/full_system.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -191,4 +194,5 @@
return decode(this_emi, pc.instAddr());
}
-}
+} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/decoder.hh b/src/arch/arm/decoder.hh
index 2542f47..34abf5e 100644
--- a/src/arch/arm/decoder.hh
+++ b/src/arch/arm/decoder.hh
@@ -52,6 +52,9 @@
#include "debug/Decode.hh"
#include "enums/DecoderFlavor.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -218,5 +221,6 @@
};
} // namespace ArmISA
+} // namespace gem5
#endif // __ARCH_ARM_DECODER_HH__
diff --git a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
index f6f678b..8ce0a52 100644
--- a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
+++ b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
@@ -38,7 +38,7 @@
class FastModelCortexA76(IrisBaseCPU):
type = 'FastModelCortexA76'
- cxx_class = 'fastmodel::CortexA76'
+ cxx_class = 'gem5::fastmodel::CortexA76'
cxx_header = 'arch/arm/fastmodel/CortexA76/cortex_a76.hh'
cntfrq = Param.UInt64(0x1800000, "Value for the CNTFRQ timer register")
@@ -136,7 +136,7 @@
class FastModelCortexA76Cluster(SimObject):
type = 'FastModelCortexA76Cluster'
- cxx_class = 'fastmodel::CortexA76Cluster'
+ cxx_class = 'gem5::fastmodel::CortexA76Cluster'
cxx_header = 'arch/arm/fastmodel/CortexA76/cortex_a76.hh'
cores = VectorParam.FastModelCortexA76(
@@ -366,7 +366,8 @@
class FastModelScxEvsCortexA76x1(SystemC_ScModule):
type = 'FastModelScxEvsCortexA76x1'
- cxx_class = 'fastmodel::ScxEvsCortexA76<fastmodel::ScxEvsCortexA76x1Types>'
+ cxx_class = \
+ 'gem5::fastmodel::ScxEvsCortexA76<fastmodel::ScxEvsCortexA76x1Types>'
cxx_template_params = [ 'class Types' ]
cxx_header = 'arch/arm/fastmodel/CortexA76/evs.hh'
@@ -377,7 +378,8 @@
class FastModelScxEvsCortexA76x2(SystemC_ScModule):
type = 'FastModelScxEvsCortexA76x2'
- cxx_class = 'fastmodel::ScxEvsCortexA76<fastmodel::ScxEvsCortexA76x2Types>'
+ cxx_class = \
+ 'gem5::fastmodel::ScxEvsCortexA76<fastmodel::ScxEvsCortexA76x2Types>'
cxx_template_params = [ 'class Types' ]
cxx_header = 'arch/arm/fastmodel/CortexA76/evs.hh'
@@ -389,7 +391,8 @@
class FastModelScxEvsCortexA76x3(SystemC_ScModule):
type = 'FastModelScxEvsCortexA76x3'
- cxx_class = 'fastmodel::ScxEvsCortexA76<fastmodel::ScxEvsCortexA76x3Types>'
+ cxx_class = \
+ 'gem5::fastmodel::ScxEvsCortexA76<fastmodel::ScxEvsCortexA76x3Types>'
cxx_template_params = [ 'class Types' ]
cxx_header = 'arch/arm/fastmodel/CortexA76/evs.hh'
@@ -402,7 +405,8 @@
class FastModelScxEvsCortexA76x4(SystemC_ScModule):
type = 'FastModelScxEvsCortexA76x4'
- cxx_class = 'fastmodel::ScxEvsCortexA76<fastmodel::ScxEvsCortexA76x4Types>'
+ cxx_class = \
+ 'gem5::fastmodel::ScxEvsCortexA76<fastmodel::ScxEvsCortexA76x4Types>'
cxx_template_params = [ 'class Types' ]
cxx_header = 'arch/arm/fastmodel/CortexA76/evs.hh'
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
index 98c2922..5f7562e 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -34,6 +34,9 @@
#include "sim/core.hh"
#include "systemc/tlm_bridge/gem5_to_tlm.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
namespace fastmodel
{
@@ -199,3 +202,4 @@
}
} // namespace fastmodel
+} // namespace gem5
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
index 769b281..79d9eee 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
@@ -37,6 +37,9 @@
#include "sim/port.hh"
#include "systemc/ext/core/sc_module.hh"
+namespace gem5
+{
+
class BaseCPU;
GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
@@ -108,5 +111,6 @@
}
} // namespace fastmodel
+} // namespace gem5
#endif // __ARCH_ARM_FASTMODEL_CORTEXA76_CORETEX_A76_HH__
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc b/src/arch/arm/fastmodel/CortexA76/evs.cc
index 5b88077..4e0add6 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -34,6 +34,9 @@
#include "sim/core.hh"
#include "systemc/tlm_bridge/gem5_to_tlm.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
namespace fastmodel
{
@@ -155,3 +158,4 @@
template class ScxEvsCortexA76<ScxEvsCortexA76x4Types>;
} // namespace fastmodel
+} // namespace gem5
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh b/src/arch/arm/fastmodel/CortexA76/evs.hh
index 8d98e1e..f0e2ef5 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -47,6 +47,9 @@
#include "systemc/ext/core/sc_module.hh"
#include "systemc/tlm_port_wrapper.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
namespace fastmodel
{
@@ -149,5 +152,6 @@
extern template class ScxEvsCortexA76<ScxEvsCortexA76x4Types>;
} // namespace fastmodel
+} // namespace gem5
#endif // __ARCH_ARM_FASTMODEL_CORTEXA76_EVS_HH__
diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
index 6bc5971..4b1dbda 100644
--- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
@@ -32,12 +32,15 @@
#include "iris/detail/IrisCppAdapter.h"
#include "iris/detail/IrisObjects.h"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
namespace fastmodel
{
-CortexA76TC::CortexA76TC(::BaseCPU *cpu, int id, System *system,
- ::BaseMMU *mmu, ::BaseISA *isa,
+CortexA76TC::CortexA76TC(gem5::BaseCPU *cpu, int id, System *system,
+ gem5::BaseMMU *mmu, gem5::BaseISA *isa,
iris::IrisConnectionInterface *iris_if,
const std::string &iris_path) :
ThreadContext(cpu, id, system, mmu, isa, iris_if, iris_path)
@@ -954,3 +957,4 @@
std::vector<iris::MemorySpaceId> CortexA76TC::bpSpaceIds;
} // namespace fastmodel
+} // namespace gem5
diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.hh b/src/arch/arm/fastmodel/CortexA76/thread_context.hh
index 41ce4d5..d7b8ed5 100644
--- a/src/arch/arm/fastmodel/CortexA76/thread_context.hh
+++ b/src/arch/arm/fastmodel/CortexA76/thread_context.hh
@@ -30,6 +30,9 @@
#include "arch/arm/fastmodel/iris/thread_context.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
namespace fastmodel
{
@@ -48,8 +51,8 @@
static std::vector<iris::MemorySpaceId> bpSpaceIds;
public:
- CortexA76TC(::BaseCPU *cpu, int id, System *system,
- ::BaseMMU *mmu, ::BaseISA *isa,
+ CortexA76TC(gem5::BaseCPU *cpu, int id, System *system,
+ gem5::BaseMMU *mmu, gem5::BaseISA *isa,
iris::IrisConnectionInterface *iris_if,
const std::string &iris_path);
@@ -67,5 +70,6 @@
};
} // namespace fastmodel
+} // namespace gem5
#endif // __ARCH_ARM_FASTMODEL_CORTEXA76_THREAD_CONTEXT_HH__
diff --git a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
index e3daf78..7c8a0fa 100644
--- a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
+++ b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
@@ -36,7 +36,7 @@
class FastModelCortexR52(IrisBaseCPU):
type = 'FastModelCortexR52'
- cxx_class = 'fastmodel::CortexR52'
+ cxx_class = 'gem5::fastmodel::CortexR52'
cxx_header = 'arch/arm/fastmodel/CortexR52/cortex_r52.hh'
evs = Parent.evs
@@ -96,7 +96,7 @@
class FastModelCortexR52Cluster(SimObject):
type = 'FastModelCortexR52Cluster'
- cxx_class = 'fastmodel::CortexR52Cluster'
+ cxx_class = 'gem5::fastmodel::CortexR52Cluster'
cxx_header = 'arch/arm/fastmodel/CortexR52/cortex_r52.hh'
cores = VectorParam.FastModelCortexR52(
@@ -171,7 +171,8 @@
class FastModelScxEvsCortexR52x1(SystemC_ScModule):
type = 'FastModelScxEvsCortexR52x1'
- cxx_class = 'fastmodel::ScxEvsCortexR52<fastmodel::ScxEvsCortexR52x1Types>'
+ cxx_class = \
+ 'gem5::fastmodel::ScxEvsCortexR52<fastmodel::ScxEvsCortexR52x1Types>'
cxx_template_params = [ 'class Types' ]
cxx_header = 'arch/arm/fastmodel/CortexR52/evs.hh'
@@ -182,7 +183,8 @@
class FastModelScxEvsCortexR52x2(SystemC_ScModule):
type = 'FastModelScxEvsCortexR52x2'
- cxx_class = 'fastmodel::ScxEvsCortexR52<fastmodel::ScxEvsCortexR52x2Types>'
+ cxx_class = \
+ 'gem5::fastmodel::ScxEvsCortexR52<fastmodel::ScxEvsCortexR52x2Types>'
cxx_template_params = [ 'class Types' ]
cxx_header = 'arch/arm/fastmodel/CortexR52/evs.hh'
@@ -194,7 +196,8 @@
class FastModelScxEvsCortexR52x3(SystemC_ScModule):
type = 'FastModelScxEvsCortexR52x3'
- cxx_class = 'fastmodel::ScxEvsCortexR52<fastmodel::ScxEvsCortexR52x3Types>'
+ cxx_class = \
+ 'gem5::fastmodel::ScxEvsCortexR52<fastmodel::ScxEvsCortexR52x3Types>'
cxx_template_params = [ 'class Types' ]
cxx_header = 'arch/arm/fastmodel/CortexR52/evs.hh'
@@ -207,7 +210,8 @@
class FastModelScxEvsCortexR52x4(SystemC_ScModule):
type = 'FastModelScxEvsCortexR52x4'
- cxx_class = 'fastmodel::ScxEvsCortexR52<fastmodel::ScxEvsCortexR52x4Types>'
+ cxx_class = \
+ 'gem5::fastmodel::ScxEvsCortexR52<fastmodel::ScxEvsCortexR52x4Types>'
cxx_template_params = [ 'class Types' ]
cxx_header = 'arch/arm/fastmodel/CortexR52/evs.hh'
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
index 3fed9b6..1ab1b29 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -33,6 +33,9 @@
#include "sim/core.hh"
#include "systemc/tlm_bridge/gem5_to_tlm.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
namespace fastmodel
{
@@ -154,3 +157,4 @@
}
} // namespace fastmodel
+} // namespace gem5
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh b/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
index 8d2055f..c43052b 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
@@ -37,6 +37,9 @@
#include "sim/port.hh"
#include "systemc/ext/core/sc_module.hh"
+namespace gem5
+{
+
class BaseCPU;
GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
@@ -106,5 +109,6 @@
}
} // namespace fastmodel
+} // namespace gem5
#endif // __ARCH_ARM_FASTMODEL_CORTEXR52_CORETEX_R52_HH__
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc b/src/arch/arm/fastmodel/CortexR52/evs.cc
index 0e1b745..90612ae 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -33,6 +33,9 @@
#include "sim/core.hh"
#include "systemc/tlm_bridge/gem5_to_tlm.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
namespace fastmodel
{
@@ -133,3 +136,4 @@
template class ScxEvsCortexR52<ScxEvsCortexR52x4Types>;
} // namespace fastmodel
+} // namespace gem5
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh b/src/arch/arm/fastmodel/CortexR52/evs.hh
index b2000c3..b27e7e2 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -49,6 +49,9 @@
#include "systemc/ext/core/sc_module.hh"
#include "systemc/tlm_port_wrapper.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
namespace fastmodel
{
@@ -183,5 +186,6 @@
extern template class ScxEvsCortexR52<ScxEvsCortexR52x4Types>;
} // namespace fastmodel
+} // namespace gem5
#endif // __ARCH_ARM_FASTMODEL_CORTEXR52_EVS_HH__
diff --git a/src/arch/arm/fastmodel/CortexR52/thread_context.cc b/src/arch/arm/fastmodel/CortexR52/thread_context.cc
index 4ad449d..62c7a8c 100644
--- a/src/arch/arm/fastmodel/CortexR52/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexR52/thread_context.cc
@@ -32,13 +32,16 @@
#include "iris/detail/IrisCppAdapter.h"
#include "iris/detail/IrisObjects.h"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
namespace fastmodel
{
CortexR52TC::CortexR52TC(
- ::BaseCPU *cpu, int id, System *system, ::BaseMMU *mmu,
- ::BaseISA *isa, iris::IrisConnectionInterface *iris_if,
+ gem5::BaseCPU *cpu, int id, System *system, gem5::BaseMMU *mmu,
+ gem5::BaseISA *isa, iris::IrisConnectionInterface *iris_if,
const std::string &iris_path) :
ThreadContext(cpu, id, system, mmu, isa, iris_if, iris_path)
{}
@@ -195,3 +198,4 @@
std::vector<iris::MemorySpaceId> CortexR52TC::bpSpaceIds;
} // namespace fastmodel
+} // namespace gem5
diff --git a/src/arch/arm/fastmodel/CortexR52/thread_context.hh b/src/arch/arm/fastmodel/CortexR52/thread_context.hh
index 88c80d5..8c4e2f1 100644
--- a/src/arch/arm/fastmodel/CortexR52/thread_context.hh
+++ b/src/arch/arm/fastmodel/CortexR52/thread_context.hh
@@ -30,6 +30,9 @@
#include "arch/arm/fastmodel/iris/thread_context.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
namespace fastmodel
{
@@ -44,8 +47,8 @@
static std::vector<iris::MemorySpaceId> bpSpaceIds;
public:
- CortexR52TC(::BaseCPU *cpu, int id, System *system,
- ::BaseMMU *mmu, ::BaseISA *isa,
+ CortexR52TC(gem5::BaseCPU *cpu, int id, System *system,
+ gem5::BaseMMU *mmu, gem5::BaseISA *isa,
iris::IrisConnectionInterface *iris_if,
const std::string &iris_path);
@@ -106,5 +109,6 @@
};
} // namespace fastmodel
+} // namespace gem5
#endif // __ARCH_ARM_FASTMODEL_CORTEXR52_THREAD_CONTEXT_HH__
diff --git a/src/arch/arm/fastmodel/FastModel.py b/src/arch/arm/fastmodel/FastModel.py
index 534a15e..66785f8 100644
--- a/src/arch/arm/fastmodel/FastModel.py
+++ b/src/arch/arm/fastmodel/FastModel.py
@@ -93,7 +93,7 @@
class AmbaToTlmBridge64(SystemC_ScModule):
type = 'AmbaToTlmBridge64'
- cxx_class = 'fastmodel::AmbaToTlmBridge64'
+ cxx_class = 'gem5::fastmodel::AmbaToTlmBridge64'
cxx_header = 'arch/arm/fastmodel/amba_to_tlm_bridge.hh'
amba = AmbaTargetSocket(64, 'AMBA PV target socket')
@@ -101,7 +101,7 @@
class AmbaFromTlmBridge64(SystemC_ScModule):
type = 'AmbaFromTlmBridge64'
- cxx_class = 'fastmodel::AmbaFromTlmBridge64'
+ cxx_class = 'gem5::fastmodel::AmbaFromTlmBridge64'
cxx_header = 'arch/arm/fastmodel/amba_from_tlm_bridge.hh'
tlm = TlmTargetSocket(64, 'TLM target socket')
diff --git a/src/arch/arm/fastmodel/GIC/FastModelGIC.py b/src/arch/arm/fastmodel/GIC/FastModelGIC.py
index 9212735..2386b2f 100644
--- a/src/arch/arm/fastmodel/GIC/FastModelGIC.py
+++ b/src/arch/arm/fastmodel/GIC/FastModelGIC.py
@@ -66,7 +66,7 @@
class SCFastModelGIC(SystemC_ScModule):
type = 'SCFastModelGIC'
- cxx_class = 'fastmodel::SCGIC'
+ cxx_class = 'gem5::fastmodel::SCGIC'
cxx_header = 'arch/arm/fastmodel/GIC/gic.hh'
enabled = Param.Bool(True, "Enable GICv3 functionality; when false the "
@@ -464,7 +464,7 @@
class FastModelGIC(BaseGic):
type = 'FastModelGIC'
- cxx_class = 'fastmodel::GIC'
+ cxx_class = 'gem5::fastmodel::GIC'
cxx_header = 'arch/arm/fastmodel/GIC/gic.hh'
sc_gic = Param.SCFastModelGIC(SCFastModelGIC(),
diff --git a/src/arch/arm/fastmodel/GIC/gic.cc b/src/arch/arm/fastmodel/GIC/gic.cc
index 2830c83..d1b5980 100644
--- a/src/arch/arm/fastmodel/GIC/gic.cc
+++ b/src/arch/arm/fastmodel/GIC/gic.cc
@@ -31,6 +31,9 @@
#include "params/FastModelGIC.hh"
#include "params/SCFastModelGIC.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
namespace fastmodel
{
@@ -359,3 +362,4 @@
}
} // namespace fastmodel
+} // namespace gem5
diff --git a/src/arch/arm/fastmodel/GIC/gic.hh b/src/arch/arm/fastmodel/GIC/gic.hh
index b283108..27eccd4 100644
--- a/src/arch/arm/fastmodel/GIC/gic.hh
+++ b/src/arch/arm/fastmodel/GIC/gic.hh
@@ -43,6 +43,9 @@
#include "systemc/ext/core/sc_module_name.hh"
#include "systemc/sc_port_wrapper.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
namespace fastmodel
{
@@ -138,5 +141,6 @@
};
} // namespace fastmodel
+} // namespace gem5
#endif // __ARCH_ARM_FASTMODEL_GIC_GIC_HH__
diff --git a/src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py b/src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py
index 6cd6c98..ab61b74 100644
--- a/src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py
+++ b/src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py
@@ -30,7 +30,7 @@
class FastModelPL330(SystemC_ScModule):
type = 'FastModelPL330'
- cxx_class = 'fastmodel::PL330'
+ cxx_class = 'gem5::fastmodel::PL330'
cxx_header = 'arch/arm/fastmodel/PL330_DMAC/pl330.hh'
clock = Param.Frequency("Clock frequency")
diff --git a/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc b/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
index 354dc28..6fe843d 100644
--- a/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
+++ b/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
@@ -32,6 +32,9 @@
#include "params/FastModelPL330.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
namespace fastmodel
{
@@ -260,3 +263,4 @@
}
} // namespace fastmodel
+} // namespace gem5
diff --git a/src/arch/arm/fastmodel/PL330_DMAC/pl330.hh b/src/arch/arm/fastmodel/PL330_DMAC/pl330.hh
index ba21f46..3af56f2 100644
--- a/src/arch/arm/fastmodel/PL330_DMAC/pl330.hh
+++ b/src/arch/arm/fastmodel/PL330_DMAC/pl330.hh
@@ -46,6 +46,9 @@
#include "systemc/ext/core/sc_module_name.hh"
#include "systemc/sc_port_wrapper.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
namespace fastmodel
{
@@ -76,7 +79,7 @@
PL330(params, params.name.c_str())
{}
- ::Port &gem5_getPort(const std::string &if_name, int idx=-1) override;
+ gem5::Port &gem5_getPort(const std::string &if_name, int idx=-1) override;
void
end_of_elaboration() override
@@ -88,5 +91,6 @@
};
} // namespace fastmodel
+} // namespace gem5
#endif // __ARCH_ARM_FASTMODEL_PL330_PL330_HH__
diff --git a/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc b/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
index 88bbe16..4005355 100644
--- a/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
+++ b/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
@@ -29,6 +29,9 @@
#include "params/AmbaFromTlmBridge64.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
namespace fastmodel
{
@@ -59,3 +62,5 @@
{
return new fastmodel::AmbaFromTlmBridge64(name.c_str());
}
+
+} // namespace gem5
diff --git a/src/arch/arm/fastmodel/amba_from_tlm_bridge.hh b/src/arch/arm/fastmodel/amba_from_tlm_bridge.hh
index e05e099..a54617d 100644
--- a/src/arch/arm/fastmodel/amba_from_tlm_bridge.hh
+++ b/src/arch/arm/fastmodel/amba_from_tlm_bridge.hh
@@ -35,6 +35,9 @@
#include "arch/arm/fastmodel/amba_ports.hh"
#include "systemc/tlm_port_wrapper.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
namespace fastmodel
{
@@ -46,7 +49,7 @@
public:
AmbaFromTlmBridge64(const char *name);
- ::Port &gem5_getPort(const std::string &if_name, int idx=-1) override;
+ gem5::Port &gem5_getPort(const std::string &if_name, int idx=-1) override;
private:
AmbaInitiator ambaWrapper;
@@ -54,5 +57,6 @@
};
} // namespace fastmodel
+} // namespace gem5
#endif // __ARCH_ARM_FASTMODEL_AMBA_FROM_TLM_BRIDGE_HH__
diff --git a/src/arch/arm/fastmodel/amba_ports.hh b/src/arch/arm/fastmodel/amba_ports.hh
index 83c9a57..845c5e9 100644
--- a/src/arch/arm/fastmodel/amba_ports.hh
+++ b/src/arch/arm/fastmodel/amba_ports.hh
@@ -35,6 +35,9 @@
#include "systemc/tlm_port_wrapper.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
namespace fastmodel
{
@@ -45,5 +48,6 @@
64, amba_pv::amba_pv_protocol_types> AmbaTarget;
} // namespace fastmodel
+} // namespace gem5
#endif // __ARCH_ARM_FASTMODEL_AMBA_PORTS_HH__
diff --git a/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc b/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
index 06e8372..ad87509 100644
--- a/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
+++ b/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
@@ -33,6 +33,9 @@
#include "pv_userpayload_extension.h"
#include "systemc/tlm_bridge/sc_ext.hh"
+namespace gem5
+{
+
namespace {
// According to AbstractMemory::access in mem/abstract_mem.cc, the gem5 memory
@@ -173,3 +176,5 @@
{
return new fastmodel::AmbaToTlmBridge64(name.c_str());
}
+
+} // namespace gem5
diff --git a/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh b/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
index c3e9514..6594fe4 100644
--- a/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
+++ b/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
@@ -35,6 +35,9 @@
#include "arch/arm/fastmodel/amba_ports.hh"
#include "systemc/tlm_port_wrapper.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
namespace fastmodel
{
@@ -46,7 +49,7 @@
public:
AmbaToTlmBridge64(const sc_core::sc_module_name &name);
- ::Port &gem5_getPort(const std::string &if_name, int idx=-1) override;
+ gem5::Port &gem5_getPort(const std::string &if_name, int idx=-1) override;
private:
void bTransport(amba_pv::amba_pv_transaction &trans, sc_core::sc_time &t);
@@ -66,5 +69,6 @@
};
} // namespace fastmodel
+} // namespace gem5
#endif // __ARCH_ARM_FASTMODEL_AMBA_TO_TLM_BRIDGE_HH__
diff --git a/src/arch/arm/fastmodel/common/signal_receiver.hh b/src/arch/arm/fastmodel/common/signal_receiver.hh
index 7ddf053..0025e39 100644
--- a/src/arch/arm/fastmodel/common/signal_receiver.hh
+++ b/src/arch/arm/fastmodel/common/signal_receiver.hh
@@ -37,6 +37,9 @@
#include "base/compiler.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
namespace fastmodel
{
@@ -78,5 +81,6 @@
};
} // namespace fastmodel
+} // namespace gem5
#endif // __ARCH_ARM_FASTMODEL_COMMON_SIGNAL_RECEIVER_HH__
diff --git a/src/arch/arm/fastmodel/fastmodel.cc b/src/arch/arm/fastmodel/fastmodel.cc
index 8cda54f..33a0c43 100644
--- a/src/arch/arm/fastmodel/fastmodel.cc
+++ b/src/arch/arm/fastmodel/fastmodel.cc
@@ -41,6 +41,9 @@
#include "scx/scx.h"
#include "sim/init.hh"
+namespace gem5
+{
+
namespace
{
@@ -119,3 +122,4 @@
EmbeddedPyBind embed_("arm_fast_model", &arm_fast_model_pybind);
} // anonymous namespace
+} // namespace gem5
diff --git a/src/arch/arm/fastmodel/iris/Iris.py b/src/arch/arm/fastmodel/iris/Iris.py
index defe766..4bc6add 100644
--- a/src/arch/arm/fastmodel/iris/Iris.py
+++ b/src/arch/arm/fastmodel/iris/Iris.py
@@ -46,30 +46,30 @@
class IrisTLB(BaseTLB):
type = 'IrisTLB'
- cxx_class = 'Iris::TLB'
+ cxx_class = 'gem5::Iris::TLB'
cxx_header = 'arch/arm/fastmodel/iris/tlb.hh'
class IrisMMU(BaseMMU):
type = 'IrisMMU'
- cxx_class = 'Iris::MMU'
+ cxx_class = 'gem5::Iris::MMU'
cxx_header = 'arch/arm/fastmodel/iris/mmu.hh'
itb = IrisTLB()
dtb = IrisTLB()
class IrisInterrupts(BaseInterrupts):
type = 'IrisInterrupts'
- cxx_class = 'Iris::Interrupts'
+ cxx_class = 'gem5::Iris::Interrupts'
cxx_header = 'arch/arm/fastmodel/iris/interrupts.hh'
class IrisISA(BaseISA):
type = 'IrisISA'
- cxx_class = 'Iris::ISA'
+ cxx_class = 'gem5::Iris::ISA'
cxx_header = 'arch/arm/fastmodel/iris/isa.hh'
class IrisBaseCPU(BaseCPU):
type = 'IrisBaseCPU'
abstract = True
- cxx_class = 'Iris::BaseCPU'
+ cxx_class = 'gem5::Iris::BaseCPU'
cxx_header = 'arch/arm/fastmodel/iris/cpu.hh'
@classmethod
diff --git a/src/arch/arm/fastmodel/iris/cpu.cc b/src/arch/arm/fastmodel/iris/cpu.cc
index a155dea..db5fa60 100644
--- a/src/arch/arm/fastmodel/iris/cpu.cc
+++ b/src/arch/arm/fastmodel/iris/cpu.cc
@@ -31,11 +31,14 @@
#include "scx/scx.h"
#include "sim/serialize.hh"
+namespace gem5
+{
+
namespace Iris
{
BaseCPU::BaseCPU(const BaseCPUParams ¶ms, sc_core::sc_module *_evs) :
- ::BaseCPU::BaseCPU(params), evs(_evs),
+ gem5::BaseCPU::BaseCPU(params), evs(_evs),
evs_base_cpu(dynamic_cast<Iris::BaseCpuEvs *>(_evs))
{
panic_if(!evs_base_cpu, "EVS should be of type BaseCpuEvs");
@@ -66,7 +69,7 @@
void
BaseCPU::init()
{
- ::BaseCPU::init();
+ gem5::BaseCPU::init();
for (auto *tc: threadContexts)
tc->initMemProxies(tc);
}
@@ -74,7 +77,8 @@
void
BaseCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const
{
- ::serialize(*threadContexts[tid], cp);
+ gem5::serialize(*threadContexts[tid], cp);
}
} // namespace Iris
+} // namespace gem5
diff --git a/src/arch/arm/fastmodel/iris/cpu.hh b/src/arch/arm/fastmodel/iris/cpu.hh
index 7ae0f7f..75db722 100644
--- a/src/arch/arm/fastmodel/iris/cpu.hh
+++ b/src/arch/arm/fastmodel/iris/cpu.hh
@@ -35,6 +35,9 @@
#include "systemc/ext/core/sc_event.hh"
#include "systemc/ext/core/sc_module.hh"
+namespace gem5
+{
+
namespace Iris
{
@@ -54,7 +57,7 @@
// model CPUs to each other. It acts as a base class for the gem5 CPU, and
// holds a pointer to the EVS. It also has some methods for setting up some
// attributes in the fast model CPU to control its clock rate.
-class BaseCPU : public ::BaseCPU
+class BaseCPU : public gem5::BaseCPU
{
public:
BaseCPU(const BaseCPUParams ¶ms, sc_core::sc_module *_evs);
@@ -76,7 +79,7 @@
wakeup(ThreadID tid) override
{
auto *tc = threadContexts.at(tid);
- if (tc->status() == ::ThreadContext::Suspended)
+ if (tc->status() == gem5::ThreadContext::Suspended)
tc->activate();
}
@@ -129,5 +132,6 @@
};
} // namespace Iris
+} // namespace gem5
#endif // __ARCH_ARM_FASTMODEL_IRIS_CPU_HH__
diff --git a/src/arch/arm/fastmodel/iris/interrupts.cc b/src/arch/arm/fastmodel/iris/interrupts.cc
index 914f81e..9fb09de 100644
--- a/src/arch/arm/fastmodel/iris/interrupts.cc
+++ b/src/arch/arm/fastmodel/iris/interrupts.cc
@@ -34,6 +34,9 @@
#include "arch/arm/types.hh"
#include "params/IrisInterrupts.hh"
+namespace gem5
+{
+
void
Iris::Interrupts::serialize(CheckpointOut &cp) const
{
@@ -106,3 +109,5 @@
Iris::Interrupts::unserialize(CheckpointIn &cp)
{
}
+
+} // namespace gem5
diff --git a/src/arch/arm/fastmodel/iris/interrupts.hh b/src/arch/arm/fastmodel/iris/interrupts.hh
index c73a628..0d4b5b3 100644
--- a/src/arch/arm/fastmodel/iris/interrupts.hh
+++ b/src/arch/arm/fastmodel/iris/interrupts.hh
@@ -32,6 +32,9 @@
#include "arch/generic/interrupts.hh"
#include "params/IrisInterrupts.hh"
+namespace gem5
+{
+
namespace Iris
{
@@ -53,5 +56,6 @@
};
} // namespace Iris
+} // namespace gem5
#endif // __ARCH_ARM_FASTMODEL_IRIS_INTERRUPTS_HH__
diff --git a/src/arch/arm/fastmodel/iris/isa.cc b/src/arch/arm/fastmodel/iris/isa.cc
index 9312d4e..4301a7d 100644
--- a/src/arch/arm/fastmodel/iris/isa.cc
+++ b/src/arch/arm/fastmodel/iris/isa.cc
@@ -32,6 +32,9 @@
#include "cpu/thread_context.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
void
Iris::ISA::serialize(CheckpointOut &cp) const
{
@@ -46,3 +49,5 @@
{
panic("copyRegsFrom not implemented");
}
+
+} // namespace gem5
diff --git a/src/arch/arm/fastmodel/iris/isa.hh b/src/arch/arm/fastmodel/iris/isa.hh
index 9b2828c..8caa994 100644
--- a/src/arch/arm/fastmodel/iris/isa.hh
+++ b/src/arch/arm/fastmodel/iris/isa.hh
@@ -31,6 +31,9 @@
#include "arch/arm/utility.hh"
#include "arch/generic/isa.hh"
+namespace gem5
+{
+
namespace Iris
{
@@ -52,5 +55,6 @@
};
} // namespace Iris
+} // namespace gem5
#endif // __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__
diff --git a/src/arch/arm/fastmodel/iris/memory_spaces.hh b/src/arch/arm/fastmodel/iris/memory_spaces.hh
index 3840a76..cf677c8 100644
--- a/src/arch/arm/fastmodel/iris/memory_spaces.hh
+++ b/src/arch/arm/fastmodel/iris/memory_spaces.hh
@@ -28,6 +28,9 @@
#ifndef __ARCH_ARM_FASTMODEL_IRIS_MEMORY_SPACES_HH__
#define __ARCH_ARM_FASTMODEL_IRIS_MEMORY_SPACES_HH__
+namespace gem5
+{
+
namespace Iris
{
@@ -47,5 +50,6 @@
};
} // namespace Iris
+} // namespace gem5
#endif // __ARCH_ARM_FASTMODEL_IRIS_MEMORY_SPACES_HH__
diff --git a/src/arch/arm/fastmodel/iris/mmu.hh b/src/arch/arm/fastmodel/iris/mmu.hh
index 1a7c289..3dbcd05 100644
--- a/src/arch/arm/fastmodel/iris/mmu.hh
+++ b/src/arch/arm/fastmodel/iris/mmu.hh
@@ -42,6 +42,9 @@
#include "params/IrisMMU.hh"
+namespace gem5
+{
+
namespace Iris
{
@@ -52,5 +55,6 @@
};
} // namespace Iris
+} // namespace gem5
#endif // __ARCH_ARM_FASTMODEL_IRIS_MMU_HH__
diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc b/src/arch/arm/fastmodel/iris/thread_context.cc
index 0219ab5..0ff5bd7 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -50,6 +50,9 @@
#include "mem/translating_port_proxy.hh"
#include "sim/pseudo_inst.hh"
+namespace gem5
+{
+
namespace Iris
{
@@ -305,7 +308,7 @@
}
ThreadContext::ThreadContext(
- ::BaseCPU *cpu, int id, System *system, ::BaseMMU *mmu,
+ gem5::BaseCPU *cpu, int id, System *system, gem5::BaseMMU *mmu,
BaseISA *isa, iris::IrisConnectionInterface *iris_if,
const std::string &iris_path) :
_cpu(cpu), _threadId(id), _system(system), _mmu(mmu), _isa(isa),
@@ -475,7 +478,7 @@
}
void
-ThreadContext::initMemProxies(::ThreadContext *tc)
+ThreadContext::initMemProxies(gem5::ThreadContext *tc)
{
assert(!virtProxy);
if (FullSystem) {
@@ -717,3 +720,4 @@
}
} // namespace Iris
+} // namespace gem5
diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh b/src/arch/arm/fastmodel/iris/thread_context.hh
index 22ea42b..6d42288 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -40,12 +40,15 @@
#include "iris/detail/IrisObjects.h"
#include "sim/system.hh"
+namespace gem5
+{
+
namespace Iris
{
// This class is the base for ThreadContexts which read and write state using
// the Iris API.
-class ThreadContext : public ::ThreadContext
+class ThreadContext : public gem5::ThreadContext
{
public:
typedef std::map<std::string, iris::ResourceInfo> ResourceMap;
@@ -54,12 +57,12 @@
typedef std::map<int, std::string> IdxNameMap;
protected:
- ::BaseCPU *_cpu;
+ gem5::BaseCPU *_cpu;
int _threadId;
ContextID _contextId;
System *_system;
- ::BaseMMU *_mmu;
- ::BaseISA *_isa;
+ gem5::BaseMMU *_mmu;
+ gem5::BaseISA *_isa;
std::string _irisPath;
iris::InstanceId _instId = iris::IRIS_UINT64_MAX;
@@ -166,8 +169,8 @@
Addr vaddr, iris::MemorySpaceId v_space);
public:
- ThreadContext(::BaseCPU *cpu, int id, System *system,
- ::BaseMMU *mmu, ::BaseISA *isa,
+ ThreadContext(gem5::BaseCPU *cpu, int id, System *system,
+ gem5::BaseMMU *mmu, gem5::BaseISA *isa,
iris::IrisConnectionInterface *iris_if,
const std::string &iris_path);
virtual ~ThreadContext();
@@ -181,7 +184,7 @@
void descheduleInstCountEvent(Event *event) override;
Tick getCurrentInstCount() override;
- ::BaseCPU *getCpuPtr() override { return _cpu; }
+ gem5::BaseCPU *getCpuPtr() override { return _cpu; }
int cpuId() const override { return _cpu->cpuId(); }
uint32_t socketId() const override { return _cpu->socketId(); }
@@ -213,7 +216,7 @@
}
PortProxy &getVirtProxy() override { return *virtProxy; }
- void initMemProxies(::ThreadContext *tc) override;
+ void initMemProxies(gem5::ThreadContext *tc) override;
void sendFunctional(PacketPtr pkt) override;
@@ -235,7 +238,7 @@
void halt() override { setStatus(Halted); }
void
- takeOverFrom(::ThreadContext *old_context) override
+ takeOverFrom(gem5::ThreadContext *old_context) override
{
panic("%s not implemented.", __FUNCTION__);
}
@@ -255,7 +258,7 @@
}
void
- copyArchRegs(::ThreadContext *tc) override
+ copyArchRegs(gem5::ThreadContext *tc) override
{
panic("%s not implemented.", __FUNCTION__);
}
@@ -468,5 +471,6 @@
};
} // namespace Iris
+} // namespace gem5
#endif // __ARCH_ARM_FASTMODEL_IRIS_THREAD_CONTEXT_HH__
diff --git a/src/arch/arm/fastmodel/iris/tlb.cc b/src/arch/arm/fastmodel/iris/tlb.cc
index 45bd810..648d3f5 100644
--- a/src/arch/arm/fastmodel/iris/tlb.cc
+++ b/src/arch/arm/fastmodel/iris/tlb.cc
@@ -32,9 +32,12 @@
#include "params/IrisTLB.hh"
#include "sim/faults.hh"
+namespace gem5
+{
+
Fault
Iris::TLB::translateFunctional(
- const RequestPtr &req, ::ThreadContext *tc, Mode mode)
+ const RequestPtr &req, gem5::ThreadContext *tc, Mode mode)
{
auto *itc = dynamic_cast<Iris::ThreadContext *>(tc);
panic_if(!itc, "Failed to cast to Iris::ThreadContext *");
@@ -53,15 +56,17 @@
Fault
Iris::TLB::translateAtomic(
- const RequestPtr &req, ::ThreadContext *tc, Mode mode)
+ const RequestPtr &req, gem5::ThreadContext *tc, Mode mode)
{
return translateFunctional(req, tc, mode);
}
void
-Iris::TLB::translateTiming(const RequestPtr &req, ::ThreadContext *tc,
+Iris::TLB::translateTiming(const RequestPtr &req, gem5::ThreadContext *tc,
Translation *translation, Mode mode)
{
assert(translation);
translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
}
+
+} // namespace gem5
diff --git a/src/arch/arm/fastmodel/iris/tlb.hh b/src/arch/arm/fastmodel/iris/tlb.hh
index 75d8743..0801506 100644
--- a/src/arch/arm/fastmodel/iris/tlb.hh
+++ b/src/arch/arm/fastmodel/iris/tlb.hh
@@ -30,6 +30,9 @@
#include "arch/generic/tlb.hh"
+namespace gem5
+{
+
namespace Iris
{
@@ -43,21 +46,22 @@
void takeOverFrom(BaseTLB *otlb) override {}
Fault translateFunctional(
- const RequestPtr &req, ::ThreadContext *tc, Mode mode) override;
+ const RequestPtr &req, gem5::ThreadContext *tc, Mode mode) override;
Fault translateAtomic(
- const RequestPtr &req, ::ThreadContext *tc, Mode mode) override;
+ const RequestPtr &req, gem5::ThreadContext *tc, Mode mode) override;
void translateTiming(
- const RequestPtr &req, ::ThreadContext *tc,
+ const RequestPtr &req, gem5::ThreadContext *tc,
Translation *translation, Mode mode) override;
Fault
- finalizePhysical(
- const RequestPtr &req, ::ThreadContext *tc, Mode mode) const override
+ finalizePhysical(const RequestPtr &req, gem5::ThreadContext *tc,
+ Mode mode) const override
{
return NoFault;
}
};
} // namespace Iris
+} // namespace gem5
#endif // __ARCH_ARM_FASTMODEL_IRIS_TLB_HH__
diff --git a/src/arch/arm/fastmodel/protocol/exported_clock_rate_control.hh b/src/arch/arm/fastmodel/protocol/exported_clock_rate_control.hh
index aa5b6e9..835648a 100644
--- a/src/arch/arm/fastmodel/protocol/exported_clock_rate_control.hh
+++ b/src/arch/arm/fastmodel/protocol/exported_clock_rate_control.hh
@@ -32,6 +32,9 @@
#include <systemc>
#include <tlm>
+namespace gem5
+{
+
// This protocol is an exportable version of the clock rate protocol native to
// fast models. It's identical to the original, except it has some extra info
// which lets it be exported into systemc.
@@ -119,4 +122,6 @@
}
};
+} // namespace gem5
+
#endif // __ARCH_ARM_FASTMODEL_PROTOCOL_EXPORTED_CLOCK_RATE_CONTROL_HH__
diff --git a/src/arch/arm/fastmodel/protocol/signal_interrupt.hh b/src/arch/arm/fastmodel/protocol/signal_interrupt.hh
index dc7f07f..d4b4000 100644
--- a/src/arch/arm/fastmodel/protocol/signal_interrupt.hh
+++ b/src/arch/arm/fastmodel/protocol/signal_interrupt.hh
@@ -32,6 +32,9 @@
#include <systemc>
#include <tlm>
+namespace gem5
+{
+
struct SignalInterruptDummyProtocolType {};
class SignalInterruptFwIf : public virtual sc_core::sc_interface
@@ -116,4 +119,6 @@
}
};
+} // namespace gem5
+
#endif // __ARCH_ARM_FASTMODEL_PROTOCOL_SIGNAL_INTERRUPT_HH__
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index aa1bae5..adb1207 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -54,6 +54,9 @@
#include "debug/Faults.hh"
#include "sim/full_system.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -1850,3 +1853,4 @@
}
} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index a477c75..da05eb9 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -50,6 +50,9 @@
#include "sim/faults.hh"
#include "sim/full_system.hh"
+namespace gem5
+{
+
// The design of the "name" and "vect" functions is in sim/faults.hh
namespace ArmISA
@@ -725,7 +728,7 @@
*/
bool getFaultVAddr(Fault fault, Addr &va);
-
} // namespace ArmISA
+} // namespace gem5
#endif // __ARM_FAULTS_HH__
diff --git a/src/arch/arm/freebsd/freebsd.cc b/src/arch/arm/freebsd/freebsd.cc
index 326e1e7..a67e347 100644
--- a/src/arch/arm/freebsd/freebsd.cc
+++ b/src/arch/arm/freebsd/freebsd.cc
@@ -34,6 +34,9 @@
#include <fcntl.h>
+namespace gem5
+{
+
// open(2) flags translation table
const std::map<int, int> ArmFreebsd32::openFlagTable = {
{ ArmFreebsd32::TGT_O_RDONLY, O_RDONLY },
@@ -73,3 +76,5 @@
{ ArmFreebsd64::TGT_O_DIRECTORY, O_DIRECTORY },
{ ArmFreebsd64::TGT_O_NOFOLLOW, O_NOFOLLOW },
};
+
+} // namespace gem5
diff --git a/src/arch/arm/freebsd/freebsd.hh b/src/arch/arm/freebsd/freebsd.hh
index 465b6fa..f47fb4e 100644
--- a/src/arch/arm/freebsd/freebsd.hh
+++ b/src/arch/arm/freebsd/freebsd.hh
@@ -38,6 +38,9 @@
#include "kern/freebsd/freebsd.hh"
#include "sim/byteswap.hh"
+namespace gem5
+{
+
class ArmFreebsd : public FreeBSD
{
public:
@@ -374,4 +377,6 @@
};
};
+} // namespace gem5
+
#endif
diff --git a/src/arch/arm/freebsd/fs_workload.cc b/src/arch/arm/freebsd/fs_workload.cc
index d2cc750..fe04fd4 100644
--- a/src/arch/arm/freebsd/fs_workload.cc
+++ b/src/arch/arm/freebsd/fs_workload.cc
@@ -45,6 +45,9 @@
#include "mem/physical.hh"
#include "sim/stat_control.hh"
+namespace gem5
+{
+
using namespace free_bsd;
namespace ArmISA
@@ -124,3 +127,4 @@
}
} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/freebsd/fs_workload.hh b/src/arch/arm/freebsd/fs_workload.hh
index b5268cd..23a7156 100644
--- a/src/arch/arm/freebsd/fs_workload.hh
+++ b/src/arch/arm/freebsd/fs_workload.hh
@@ -39,6 +39,9 @@
#include "kern/freebsd/events.hh"
#include "params/ArmFsFreebsd.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -98,5 +101,6 @@
};
} // namespace ArmISA
+} // namespace gem5
#endif // __ARCH_ARM_FREEBSD_FS_WORKLOAD_HH__
diff --git a/src/arch/arm/freebsd/se_workload.cc b/src/arch/arm/freebsd/se_workload.cc
index 70eab8a..d478b59d 100644
--- a/src/arch/arm/freebsd/se_workload.cc
+++ b/src/arch/arm/freebsd/se_workload.cc
@@ -44,6 +44,9 @@
#include "cpu/thread_context.hh"
#include "sim/syscall_emul.hh"
+namespace gem5
+{
+
namespace
{
@@ -157,3 +160,4 @@
}
} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/freebsd/se_workload.hh b/src/arch/arm/freebsd/se_workload.hh
index f2bfaf3..a96dcf2 100644
--- a/src/arch/arm/freebsd/se_workload.hh
+++ b/src/arch/arm/freebsd/se_workload.hh
@@ -41,6 +41,9 @@
#include "params/ArmEmuFreebsd.hh"
#include "sim/syscall_desc.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -94,5 +97,6 @@
};
} // namespace guest_abi
+} // namespace gem5
#endif // __ARCH_ARM_FREEBSD_SE_WORKLOAD_HH__
diff --git a/src/arch/arm/fs_workload.cc b/src/arch/arm/fs_workload.cc
index 21ca993..6bbe664 100644
--- a/src/arch/arm/fs_workload.cc
+++ b/src/arch/arm/fs_workload.cc
@@ -48,6 +48,9 @@
#include "kern/system_events.hh"
#include "params/ArmFsWorkload.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -157,3 +160,4 @@
}
} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/fs_workload.hh b/src/arch/arm/fs_workload.hh
index b3d7f48..c917ffd 100644
--- a/src/arch/arm/fs_workload.hh
+++ b/src/arch/arm/fs_workload.hh
@@ -52,6 +52,9 @@
#include "sim/kernel_workload.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -161,5 +164,6 @@
};
} // namespace ArmISA
+} // namespace gem5
#endif // __ARCH_ARM_FS_WORKLOAD_HH__
diff --git a/src/arch/arm/htm.cc b/src/arch/arm/htm.cc
index f977a61..0062b56 100644
--- a/src/arch/arm/htm.cc
+++ b/src/arch/arm/htm.cc
@@ -41,6 +41,9 @@
#include "arch/arm/regs/misc.hh"
#include "cpu/thread_context.hh"
+namespace gem5
+{
+
void
ArmISA::HTMCheckpoint::reset()
{
@@ -164,3 +167,5 @@
BaseHTMCheckpoint::restore(tc, cause);
}
+
+} // namespace gem5
diff --git a/src/arch/arm/htm.hh b/src/arch/arm/htm.hh
index 3f1f60e..7323687 100644
--- a/src/arch/arm/htm.hh
+++ b/src/arch/arm/htm.hh
@@ -49,6 +49,9 @@
#include "arch/generic/htm.hh"
#include "base/types.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -85,5 +88,6 @@
};
} // namespace ArmISA
+} // namespace gem5
#endif
diff --git a/src/arch/arm/insts/branch.cc b/src/arch/arm/insts/branch.cc
index 91a9d51..88e2e7a 100644
--- a/src/arch/arm/insts/branch.cc
+++ b/src/arch/arm/insts/branch.cc
@@ -39,6 +39,9 @@
#include "base/cprintf.hh"
+namespace gem5
+{
+
namespace ArmISA {
std::string
@@ -74,3 +77,4 @@
}
} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/insts/branch.hh b/src/arch/arm/insts/branch.hh
index 52836f6..252fb50 100644
--- a/src/arch/arm/insts/branch.hh
+++ b/src/arch/arm/insts/branch.hh
@@ -43,6 +43,9 @@
#include "arch/arm/insts/pred_inst.hh"
+namespace gem5
+{
+
namespace ArmISA
{
// Branch to a target computed with an immediate
@@ -136,6 +139,7 @@
{}
};
-}
+} // namespace ArmISA
+} // namespace gem5
#endif //__ARCH_ARM_INSTS_BRANCH_HH__
diff --git a/src/arch/arm/insts/branch64.cc b/src/arch/arm/insts/branch64.cc
index 1fe1919..b8a22fc 100644
--- a/src/arch/arm/insts/branch64.cc
+++ b/src/arch/arm/insts/branch64.cc
@@ -37,6 +37,9 @@
#include "arch/arm/insts/branch64.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -174,3 +177,4 @@
}
} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/insts/branch64.hh b/src/arch/arm/insts/branch64.hh
index 407866b..6af5ffc 100644
--- a/src/arch/arm/insts/branch64.hh
+++ b/src/arch/arm/insts/branch64.hh
@@ -40,6 +40,9 @@
#include "arch/arm/insts/static_inst.hh"
+namespace gem5
+{
+
namespace ArmISA
{
// Branch to a target computed with an immediate
@@ -214,6 +217,7 @@
Addr pc, const loader::SymbolTable *symtab) const override;
};
-}
+} // namespace ArmISA
+} // namespace gem5
#endif //__ARCH_ARM_INSTS_BRANCH_HH__
diff --git a/src/arch/arm/insts/crypto.cc b/src/arch/arm/insts/crypto.cc
index 51e019a..c0d3ddc 100644
--- a/src/arch/arm/insts/crypto.cc
+++ b/src/arch/arm/insts/crypto.cc
@@ -41,6 +41,9 @@
#include "crypto.hh"
+namespace gem5
+{
+
namespace ArmISA {
const uint8_t
@@ -513,3 +516,4 @@
}
} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/insts/crypto.hh b/src/arch/arm/insts/crypto.hh
index cd37243..23eda5b 100644
--- a/src/arch/arm/insts/crypto.hh
+++ b/src/arch/arm/insts/crypto.hh
@@ -38,6 +38,9 @@
#ifndef __ARCH_ARM_INSTS_CRYPTO_HH__
#define __ARCH_ARM_INSTS_CRYPTO_HH__
+namespace gem5
+{
+
namespace ArmISA {
class Crypto
@@ -142,5 +145,6 @@
};
} // namespace ArmISA
+} // namespace gem5
#endif //__ARCH_ARM_INSTS_CRYPTO_HH__
diff --git a/src/arch/arm/insts/data64.cc b/src/arch/arm/insts/data64.cc
index 847834f..3c2a6c1 100644
--- a/src/arch/arm/insts/data64.cc
+++ b/src/arch/arm/insts/data64.cc
@@ -37,6 +37,9 @@
#include "arch/arm/insts/data64.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -208,4 +211,5 @@
return ss.str();
}
-}
+} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/insts/data64.hh b/src/arch/arm/insts/data64.hh
index cb29f54..d83602f 100644
--- a/src/arch/arm/insts/data64.hh
+++ b/src/arch/arm/insts/data64.hh
@@ -41,6 +41,9 @@
#include "arch/arm/insts/static_inst.hh"
#include "base/trace.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -263,6 +266,7 @@
Addr pc, const loader::SymbolTable *symtab) const override;
};
-}
+} // namespace ArmISA
+} // namespace gem5
#endif //__ARCH_ARM_INSTS_PREDINST_HH__
diff --git a/src/arch/arm/insts/fplib.cc b/src/arch/arm/insts/fplib.cc
index a97943f..2b5034f 100644
--- a/src/arch/arm/insts/fplib.cc
+++ b/src/arch/arm/insts/fplib.cc
@@ -44,6 +44,9 @@
#include "base/logging.hh"
#include "fplib.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -5037,4 +5040,5 @@
return fp64_defaultNaN();
}
-}
+} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/insts/fplib.hh b/src/arch/arm/insts/fplib.hh
index 512c3d6..a537ce3 100644
--- a/src/arch/arm/insts/fplib.hh
+++ b/src/arch/arm/insts/fplib.hh
@@ -51,6 +51,9 @@
#include "arch/arm/regs/misc.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -414,6 +417,8 @@
uint32_t fplibDefaultNaN();
template <>
uint64_t fplibDefaultNaN();
-}
+
+} // namespace ArmISA
+} // namespace gem5
#endif
diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc
index fa31a95..36df626 100644
--- a/src/arch/arm/insts/macromem.cc
+++ b/src/arch/arm/insts/macromem.cc
@@ -46,6 +46,9 @@
#include "arch/arm/insts/neon64_mem.hh"
#include "base/compiler.hh"
+namespace gem5
+{
+
using namespace ArmISAInst;
namespace ArmISA
@@ -1622,4 +1625,5 @@
return ss.str();
}
-}
+} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh
index 048b548..b1c2438 100644
--- a/src/arch/arm/insts/macromem.hh
+++ b/src/arch/arm/insts/macromem.hh
@@ -44,6 +44,9 @@
#include "arch/arm/insts/pred_inst.hh"
#include "arch/arm/tlb.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -539,6 +542,7 @@
bool writeback, bool load, uint32_t offset);
};
-}
+} // namespace ArmISA
+} // namespace gem5
#endif //__ARCH_ARM_INSTS_MACROMEM_HH__
diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc
index f72f337..aed9933 100644
--- a/src/arch/arm/insts/mem.cc
+++ b/src/arch/arm/insts/mem.cc
@@ -42,6 +42,9 @@
#include "base/loader/symtab.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -177,4 +180,5 @@
}
}
-}
+} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh
index eae6aab..7bee981 100644
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -43,6 +43,9 @@
#include "arch/arm/insts/pred_inst.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -485,6 +488,8 @@
return ss.str();
}
};
-}
+
+} // namespace ArmISA
+} // namespace gem5
#endif //__ARCH_ARM_INSTS_MEM_HH__
diff --git a/src/arch/arm/insts/mem64.cc b/src/arch/arm/insts/mem64.cc
index 28ca88f..091987e 100644
--- a/src/arch/arm/insts/mem64.cc
+++ b/src/arch/arm/insts/mem64.cc
@@ -41,6 +41,9 @@
#include "base/loader/symtab.hh"
#include "mem/request.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -218,4 +221,5 @@
return ss.str();
}
-}
+} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/insts/mem64.hh b/src/arch/arm/insts/mem64.hh
index 82635a1..7fb168c 100644
--- a/src/arch/arm/insts/mem64.hh
+++ b/src/arch/arm/insts/mem64.hh
@@ -41,6 +41,9 @@
#include "arch/arm/insts/misc64.hh"
#include "arch/arm/insts/static_inst.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -284,6 +287,7 @@
Addr pc, const loader::SymbolTable *symtab) const override;
};
-}
+} // namespace ArmISA
+} // namespace gem5
#endif //__ARCH_ARM_INSTS_MEM_HH__
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 37ad1e6..4bb02c9 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -40,6 +40,9 @@
#include "cpu/reg_class.hh"
+namespace gem5
+{
+
using namespace ArmISA;
std::string
@@ -402,3 +405,5 @@
{
return csprintf("%-10s (implementation defined)", mnemonic);
}
+
+} // namespace gem5
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index 3fd24ea..263434a 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -40,6 +40,9 @@
#include "arch/arm/insts/pred_inst.hh"
+namespace gem5
+{
+
class MrsOp : public ArmISA::PredOp
{
protected:
@@ -436,4 +439,6 @@
};
+} // namespace gem5
+
#endif
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index fa43413..0f301b0 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -38,6 +38,9 @@
#include "arch/arm/insts/misc64.hh"
#include "arch/arm/isa.hh"
+namespace gem5
+{
+
using namespace ArmISA;
std::string
@@ -881,3 +884,5 @@
printIntReg(ss, dest);
return ss.str();
}
+
+} // namespace gem5
diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index cc4425d..e38f43a 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -40,6 +40,9 @@
#include "arch/arm/insts/static_inst.hh"
+namespace gem5
+{
+
class ImmOp64 : public ArmISA::ArmStaticInst
{
protected:
@@ -249,4 +252,6 @@
Addr pc, const loader::SymbolTable *symtab) const;
};
+} // namespace gem5
+
#endif
diff --git a/src/arch/arm/insts/mult.hh b/src/arch/arm/insts/mult.hh
index da08101..5939b56 100644
--- a/src/arch/arm/insts/mult.hh
+++ b/src/arch/arm/insts/mult.hh
@@ -41,6 +41,9 @@
#include "arch/arm/insts/static_inst.hh"
#include "base/trace.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -73,6 +76,8 @@
Mult3(mnem, _machInst, __opClass, _reg0, _reg1, _reg2), reg3(_reg3)
{}
};
-}
+
+} // namespace ArmISA
+} // namespace gem5
#endif //__ARCH_ARM_INSTS_MULT_HH__
diff --git a/src/arch/arm/insts/neon64_mem.hh b/src/arch/arm/insts/neon64_mem.hh
index bf1e924..914b64b 100644
--- a/src/arch/arm/insts/neon64_mem.hh
+++ b/src/arch/arm/insts/neon64_mem.hh
@@ -41,6 +41,12 @@
#ifndef __ARCH_ARM_INSTS_NEON64_MEM_HH__
#define __ARCH_ARM_INSTS_NEON64_MEM_HH__
+#include <cassert>
+#include <cstdint>
+
+namespace gem5
+{
+
namespace ArmISA
{
@@ -121,6 +127,7 @@
return data;
}
-} // namespace ArmISA
+} // namespace ArmISA
+} // namespace gem5
#endif // __ARCH_ARM_INSTS_NEON64_MEM_HH__
diff --git a/src/arch/arm/insts/pred_inst.cc b/src/arch/arm/insts/pred_inst.cc
index c385e8c..517d511 100644
--- a/src/arch/arm/insts/pred_inst.cc
+++ b/src/arch/arm/insts/pred_inst.cc
@@ -40,6 +40,9 @@
#include "arch/arm/insts/pred_inst.hh"
+namespace gem5
+{
+
namespace ArmISA
{
std::string
@@ -115,4 +118,6 @@
return ss.str();
}
-}
+
+} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/insts/pred_inst.hh b/src/arch/arm/insts/pred_inst.hh
index ebcca62..f62a2e5 100644
--- a/src/arch/arm/insts/pred_inst.hh
+++ b/src/arch/arm/insts/pred_inst.hh
@@ -46,6 +46,9 @@
#include "base/logging.hh"
#include "base/trace.hh"
+namespace gem5
+{
+
namespace ArmISA
{
static inline uint32_t
@@ -396,6 +399,8 @@
pcState.uAdvance();
}
};
-}
+
+} // namespace ArmISA
+} // namespace gem5
#endif //__ARCH_ARM_INSTS_PREDINST_HH__
diff --git a/src/arch/arm/insts/pseudo.cc b/src/arch/arm/insts/pseudo.cc
index 51312e1..7d61b7e 100644
--- a/src/arch/arm/insts/pseudo.cc
+++ b/src/arch/arm/insts/pseudo.cc
@@ -42,6 +42,9 @@
#include "cpu/exec_context.hh"
+namespace gem5
+{
+
using namespace ArmISA;
DecoderFaultInst::DecoderFaultInst(ExtMachInst _machInst)
@@ -212,3 +215,5 @@
pc_state.stepped());
}
+
+} // namespace gem5
diff --git a/src/arch/arm/insts/pseudo.hh b/src/arch/arm/insts/pseudo.hh
index b4eccc0..215f965 100644
--- a/src/arch/arm/insts/pseudo.hh
+++ b/src/arch/arm/insts/pseudo.hh
@@ -43,6 +43,9 @@
#include "arch/arm/insts/static_inst.hh"
+namespace gem5
+{
+
class DecoderFaultInst : public ArmISA::ArmStaticInst
{
protected:
@@ -141,4 +144,6 @@
Trace::InstRecord *traceData) const override;
};
+} // namespace gem5
+
#endif
diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index 3489b25..2b00a77 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -50,6 +50,9 @@
#include "base/loader/symtab.hh"
#include "cpu/reg_class.hh"
+namespace gem5
+{
+
namespace ArmISA
{
// Shift Rm by an immediate value
@@ -1219,4 +1222,5 @@
return isa->getCurSveVecLenInBits();
}
-}
+} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index b7dbf0d..383a5b8 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -54,6 +54,9 @@
#include "sim/byteswap.hh"
#include "sim/full_system.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -574,6 +577,8 @@
return getCurSveVecLenInBits(tc) / (8 * sizeof(T));
}
};
-}
+
+} // namespace ArmISA
+} // namespace gem5
#endif //__ARCH_ARM_INSTS_STATICINST_HH__
diff --git a/src/arch/arm/insts/sve.cc b/src/arch/arm/insts/sve.cc
index ee9edd5..9a525b1 100644
--- a/src/arch/arm/insts/sve.cc
+++ b/src/arch/arm/insts/sve.cc
@@ -39,6 +39,9 @@
#include "arch/arm/insts/sve.hh"
+namespace gem5
+{
+
namespace ArmISA {
const char*
@@ -966,4 +969,5 @@
}
}
-} // namespace ArmISA
+} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/insts/sve.hh b/src/arch/arm/insts/sve.hh
index 22f53d9..5a0f605 100644
--- a/src/arch/arm/insts/sve.hh
+++ b/src/arch/arm/insts/sve.hh
@@ -40,6 +40,9 @@
#include "arch/arm/insts/static_inst.hh"
+namespace gem5
+{
+
namespace ArmISA {
enum class SvePredType
@@ -978,6 +981,7 @@
/// @return Encoding of the expanded value.
uint64_t sveExpandFpImmMul(uint8_t imm, uint8_t size);
-} // namespace ArmISA
+} // namespace ArmISA
+} // namespace gem5
#endif // __ARCH_ARM_INSTS_SVE_HH__
diff --git a/src/arch/arm/insts/sve_macromem.hh b/src/arch/arm/insts/sve_macromem.hh
index eb97e04..84e2f94 100644
--- a/src/arch/arm/insts/sve_macromem.hh
+++ b/src/arch/arm/insts/sve_macromem.hh
@@ -41,6 +41,9 @@
#include "arch/arm/generated/decoder.hh"
#include "arch/arm/insts/pred_inst.hh"
+namespace gem5
+{
+
namespace ArmISA {
template <typename Element,
@@ -537,6 +540,7 @@
}
};
-} // namespace ArmISA
+} // namespace ArmISA
+} // namespace gem5
#endif // __ARCH_ARM_SVE_MACROMEM_HH__
diff --git a/src/arch/arm/insts/sve_mem.cc b/src/arch/arm/insts/sve_mem.cc
index 4d3c337..2158eaf 100644
--- a/src/arch/arm/insts/sve_mem.cc
+++ b/src/arch/arm/insts/sve_mem.cc
@@ -37,6 +37,9 @@
#include "arch/arm/insts/sve_mem.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -113,4 +116,5 @@
return ss.str();
}
-} // namespace ArmISA
+} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/insts/sve_mem.hh b/src/arch/arm/insts/sve_mem.hh
index 2bf9b87..17176d0 100644
--- a/src/arch/arm/insts/sve_mem.hh
+++ b/src/arch/arm/insts/sve_mem.hh
@@ -41,6 +41,9 @@
#include "arch/arm/insts/static_inst.hh"
#include "arch/arm/tlb.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -150,6 +153,7 @@
Addr pc, const loader::SymbolTable *symtab) const override;
};
-} // namespace ArmISA
+} // namespace ArmISA
+} // namespace gem5
#endif // __ARCH_ARM_SVE_MEM_HH__
diff --git a/src/arch/arm/insts/tme64.cc b/src/arch/arm/insts/tme64.cc
index b7432df..12a66a8 100644
--- a/src/arch/arm/insts/tme64.cc
+++ b/src/arch/arm/insts/tme64.cc
@@ -35,10 +35,14 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
- #include "arch/arm/insts/tme64.hh"
- #include "debug/ArmTme.hh"
+#include "arch/arm/insts/tme64.hh"
- #include <sstream>
+#include <sstream>
+
+#include "debug/ArmTme.hh"
+
+namespace gem5
+{
using namespace ArmISA;
@@ -249,4 +253,5 @@
microOps[1]->setLastMicroop();
}
-} // namespace
+} // namespace ArmISAInst
+} // namespace gem5
diff --git a/src/arch/arm/insts/tme64.hh b/src/arch/arm/insts/tme64.hh
index 40cb320..c61764a 100644
--- a/src/arch/arm/insts/tme64.hh
+++ b/src/arch/arm/insts/tme64.hh
@@ -42,6 +42,9 @@
#include "arch/arm/insts/pred_inst.hh"
#include "arch/arm/insts/static_inst.hh"
+namespace gem5
+{
+
namespace ArmISAInst {
class MicroTmeOp : public ArmISA::MicroOp
@@ -163,6 +166,7 @@
Tcommit64(ArmISA::ExtMachInst _machInst);
};
-} // namespace
+} // namespace ArmISAInst
+} // namespace gem5
#endif
diff --git a/src/arch/arm/insts/tme64classic.cc b/src/arch/arm/insts/tme64classic.cc
index b8fb627..c6c1e54 100644
--- a/src/arch/arm/insts/tme64classic.cc
+++ b/src/arch/arm/insts/tme64classic.cc
@@ -38,6 +38,9 @@
#include "arch/arm/faults.hh"
#include "arch/arm/insts/tme64.hh"
+namespace gem5
+{
+
using namespace ArmISA;
namespace ArmISAInst {
@@ -106,4 +109,5 @@
}
-} // namespace
+} // namespace ArmISAInst
+} // namespace gem5
diff --git a/src/arch/arm/insts/tme64ruby.cc b/src/arch/arm/insts/tme64ruby.cc
index defc622..26ff3d0 100644
--- a/src/arch/arm/insts/tme64ruby.cc
+++ b/src/arch/arm/insts/tme64ruby.cc
@@ -44,6 +44,9 @@
#include "mem/packet_access.hh"
#include "mem/request.hh"
+namespace gem5
+{
+
using namespace ArmISA;
namespace ArmISAInst {
@@ -266,4 +269,5 @@
return fault;
}
-} // namespace
+} // namespace ArmISAInst
+} // namespace gem5
diff --git a/src/arch/arm/insts/vfp.cc b/src/arch/arm/insts/vfp.cc
index e0c404b..4246af6 100644
--- a/src/arch/arm/insts/vfp.cc
+++ b/src/arch/arm/insts/vfp.cc
@@ -37,6 +37,9 @@
#include "arch/arm/insts/vfp.hh"
+namespace gem5
+{
+
using namespace ArmISA;
/*
@@ -1204,4 +1207,5 @@
dest = addStride(dest, stride);
}
-}
+} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/insts/vfp.hh b/src/arch/arm/insts/vfp.hh
index 40111c7..5f5b374 100644
--- a/src/arch/arm/insts/vfp.hh
+++ b/src/arch/arm/insts/vfp.hh
@@ -45,6 +45,9 @@
#include "arch/arm/insts/misc.hh"
#include "arch/arm/regs/misc.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -1052,6 +1055,7 @@
Addr pc, const loader::SymbolTable *symtab) const override;
};
-}
+} // namespace ArmISA
+} // namespace gem5
#endif //__ARCH_ARM_INSTS_VFP_HH__
diff --git a/src/arch/arm/interrupts.cc b/src/arch/arm/interrupts.cc
index 6b75403..b0f18df 100644
--- a/src/arch/arm/interrupts.cc
+++ b/src/arch/arm/interrupts.cc
@@ -39,6 +39,9 @@
#include "arch/arm/system.hh"
+namespace gem5
+{
+
bool
ArmISA::Interrupts::takeInt(InterruptTypes int_type) const
{
@@ -156,3 +159,4 @@
(mask != INT_MASK_P);
}
+} // namespace gem5
diff --git a/src/arch/arm/interrupts.hh b/src/arch/arm/interrupts.hh
index ead22d0..2f99d6e 100644
--- a/src/arch/arm/interrupts.hh
+++ b/src/arch/arm/interrupts.hh
@@ -49,6 +49,9 @@
#include "debug/Interrupt.hh"
#include "params/ArmInterrupts.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -298,6 +301,8 @@
UNSERIALIZE_SCALAR(intStatus);
}
};
+
} // namespace ARM_ISA
+} // namespace gem5
#endif // __ARCH_ARM_INTERRUPT_HH__
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 08a5d66..054baa9 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -58,6 +58,9 @@
#include "sim/stat_control.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -2541,4 +2544,5 @@
return *this;
}
-} // namespace ArmISA
+} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 13fa942..7f0988b 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -55,6 +55,9 @@
#include "enums/VecRegRenameMode.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
struct ArmISAParams;
struct DummyArmISADeviceParams;
class Checkpoint;
@@ -917,6 +920,8 @@
void copyRegsFrom(ThreadContext *src) override;
};
-}
+
+} // namespace ArmISA
+} // namespace gem5
#endif
diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa
index a09655b..3ec3e65 100644
--- a/src/arch/arm/isa/includes.isa
+++ b/src/arch/arm/isa/includes.isa
@@ -70,10 +70,13 @@
#include "mem/packet.hh"
#include "sim/faults.hh"
+namespace gem5
+{
namespace ArmISAInst
{
using namespace ArmISA;
-}
+} // namespace ArmISAInst
+} // namespace gem5
}};
@@ -91,6 +94,7 @@
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh"
+using namespace gem5;
using namespace ArmISA;
}};
@@ -116,6 +120,7 @@
#include "sim/pseudo_inst.hh"
#include "sim/sim_exit.hh"
+using namespace gem5;
using namespace ArmISA;
}};
diff --git a/src/arch/arm/isa_device.cc b/src/arch/arm/isa_device.cc
index 497e74d..8a340e8 100644
--- a/src/arch/arm/isa_device.cc
+++ b/src/arch/arm/isa_device.cc
@@ -40,6 +40,9 @@
#include "arch/arm/regs/misc.hh"
#include "base/logging.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -72,5 +75,5 @@
return 0;
}
-
-}
+} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/isa_device.hh b/src/arch/arm/isa_device.hh
index 63e6b8e..c44821f 100644
--- a/src/arch/arm/isa_device.hh
+++ b/src/arch/arm/isa_device.hh
@@ -41,6 +41,9 @@
#include "base/compiler.hh"
#include "base/types.hh"
+namespace gem5
+{
+
class ThreadContext;
namespace ArmISA
@@ -102,6 +105,7 @@
RegVal readMiscReg(int misc_reg) override;
};
-}
+} // namespace ArmISA
+} // namespace gem5
#endif // __ARCH_ARM_ISA_DEVICE_HH__
diff --git a/src/arch/arm/kvm/ArmKvmCPU.py b/src/arch/arm/kvm/ArmKvmCPU.py
index 76dbb26..4c1f62d 100644
--- a/src/arch/arm/kvm/ArmKvmCPU.py
+++ b/src/arch/arm/kvm/ArmKvmCPU.py
@@ -39,3 +39,4 @@
class ArmKvmCPU(BaseKvmCPU):
type = 'ArmKvmCPU'
cxx_header = "arch/arm/kvm/arm_cpu.hh"
+ cxx_class = 'gem5::ArmKvmCPU'
diff --git a/src/arch/arm/kvm/ArmV8KvmCPU.py b/src/arch/arm/kvm/ArmV8KvmCPU.py
index 02d202c..2f4ddd3 100644
--- a/src/arch/arm/kvm/ArmV8KvmCPU.py
+++ b/src/arch/arm/kvm/ArmV8KvmCPU.py
@@ -39,3 +39,4 @@
class ArmV8KvmCPU(BaseArmKvmCPU):
type = 'ArmV8KvmCPU'
cxx_header = "arch/arm/kvm/armv8_cpu.hh"
+ cxx_class = 'gem5::ArmV8KvmCPU'
diff --git a/src/arch/arm/kvm/BaseArmKvmCPU.py b/src/arch/arm/kvm/BaseArmKvmCPU.py
index 3a44f1a..63a11d8 100644
--- a/src/arch/arm/kvm/BaseArmKvmCPU.py
+++ b/src/arch/arm/kvm/BaseArmKvmCPU.py
@@ -39,4 +39,5 @@
class BaseArmKvmCPU(BaseKvmCPU):
type = 'BaseArmKvmCPU'
cxx_header = "arch/arm/kvm/base_cpu.hh"
+ cxx_class = 'gem5::BaseArmKvmCPU'
abstract = True
diff --git a/src/arch/arm/kvm/KvmGic.py b/src/arch/arm/kvm/KvmGic.py
index ce85ecb..c435f44 100644
--- a/src/arch/arm/kvm/KvmGic.py
+++ b/src/arch/arm/kvm/KvmGic.py
@@ -41,6 +41,7 @@
class MuxingKvmGic(GicV2):
type = 'MuxingKvmGic'
cxx_header = "arch/arm/kvm/gic.hh"
+ cxx_class = 'gem5::MuxingKvmGic'
simulate_gic = Param.Bool(False,
"Forcing the simulation to use the gem5 GIC instead of the host GIC")
diff --git a/src/arch/arm/kvm/arm_cpu.cc b/src/arch/arm/kvm/arm_cpu.cc
index b4740e4..1661f05 100644
--- a/src/arch/arm/kvm/arm_cpu.cc
+++ b/src/arch/arm/kvm/arm_cpu.cc
@@ -53,6 +53,9 @@
#include "debug/KvmInt.hh"
#include "sim/pseudo_inst.hh"
+namespace gem5
+{
+
using namespace ArmISA;
namespace
@@ -933,3 +936,5 @@
warn("Unhandled VFP register: 0x%x\n", id);
}
}
+
+} // namespace gem5
diff --git a/src/arch/arm/kvm/arm_cpu.hh b/src/arch/arm/kvm/arm_cpu.hh
index fabf065..95d5339 100644
--- a/src/arch/arm/kvm/arm_cpu.hh
+++ b/src/arch/arm/kvm/arm_cpu.hh
@@ -44,6 +44,9 @@
#include "cpu/kvm/base.hh"
#include "params/ArmKvmCPU.hh"
+namespace gem5
+{
+
/**
* ARM implementation of a KVM-based hardware virtualized CPU.
* Architecture specific limitations:
@@ -165,4 +168,6 @@
static const std::set<uint64_t> invariant_regs;
};
+} // namespace gem5
+
#endif // __ARCH_ARM_KVM_ARM_CPU_HH__
diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index a1445b1..d8c87f6 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -42,6 +42,9 @@
#include "debug/KvmContext.hh"
#include "params/ArmV8KvmCPU.hh"
+namespace gem5
+{
+
using namespace ArmISA;
// Unlike gem5, kvm doesn't count the SP as a normal integer register,
@@ -398,3 +401,5 @@
return sysRegMap;
}
+
+} // namespace gem5
diff --git a/src/arch/arm/kvm/armv8_cpu.hh b/src/arch/arm/kvm/armv8_cpu.hh
index 555d597..adca379 100644
--- a/src/arch/arm/kvm/armv8_cpu.hh
+++ b/src/arch/arm/kvm/armv8_cpu.hh
@@ -45,6 +45,9 @@
#include "arch/arm/regs/int.hh"
#include "arch/arm/regs/misc.hh"
+namespace gem5
+{
+
struct ArmV8KvmCPUParams;
/**
@@ -147,4 +150,6 @@
mutable std::vector<ArmV8KvmCPU::MiscRegInfo> sysRegMap;
};
+} // namespace gem5
+
#endif // __ARCH_ARM_KVM_ARMV8_CPU_HH__
diff --git a/src/arch/arm/kvm/base_cpu.cc b/src/arch/arm/kvm/base_cpu.cc
index ae53095..d7df280 100644
--- a/src/arch/arm/kvm/base_cpu.cc
+++ b/src/arch/arm/kvm/base_cpu.cc
@@ -47,6 +47,9 @@
#include "params/BaseArmKvmCPU.hh"
#include "params/GenericTimer.hh"
+namespace gem5
+{
+
using namespace ArmISA;
#define INTERRUPT_ID(type, vcpu, irq) ( \
@@ -233,3 +236,5 @@
return true;
}
}
+
+} // namespace gem5
diff --git a/src/arch/arm/kvm/base_cpu.hh b/src/arch/arm/kvm/base_cpu.hh
index e4bc49f..81e8596 100644
--- a/src/arch/arm/kvm/base_cpu.hh
+++ b/src/arch/arm/kvm/base_cpu.hh
@@ -43,6 +43,9 @@
#include "cpu/kvm/base.hh"
#include "dev/arm/base_gic.hh"
+namespace gem5
+{
+
struct BaseArmKvmCPUParams;
class BaseArmKvmCPU : public BaseKvmCPU
@@ -126,4 +129,6 @@
mutable RegIndexVector _regIndexList;
};
+} // namespace gem5
+
#endif // __ARCH_ARM_KVM_BASE_CPU_HH__
diff --git a/src/arch/arm/kvm/gic.cc b/src/arch/arm/kvm/gic.cc
index feb764f..ac7a7f5 100644
--- a/src/arch/arm/kvm/gic.cc
+++ b/src/arch/arm/kvm/gic.cc
@@ -44,6 +44,9 @@
#include "debug/Interrupt.hh"
#include "params/MuxingKvmGic.hh"
+namespace gem5
+{
+
KvmKernelGicV2::KvmKernelGicV2(KvmVM &_vm, Addr cpu_addr, Addr dist_addr,
unsigned it_lines)
: cpuRange(RangeSize(cpu_addr, KVM_VGIC_V2_CPU_SIZE)),
@@ -426,3 +429,5 @@
assert((cpuPriority[cpu] & ~0xff) == 0);
}
}
+
+} // namespace gem5
diff --git a/src/arch/arm/kvm/gic.hh b/src/arch/arm/kvm/gic.hh
index 79463b3..465ecdf 100644
--- a/src/arch/arm/kvm/gic.hh
+++ b/src/arch/arm/kvm/gic.hh
@@ -44,6 +44,9 @@
#include "dev/arm/gic_v2.hh"
#include "dev/platform.hh"
+namespace gem5
+{
+
/**
* KVM in-kernel GIC abstraction
*
@@ -220,4 +223,6 @@
Addr daddr, size_t size);
};
+} // namespace gem5
+
#endif // __ARCH_ARM_KVM_GIC_HH__
diff --git a/src/arch/arm/linux/atag.hh b/src/arch/arm/linux/atag.hh
index 00dcb47..cc8f601 100644
--- a/src/arch/arm/linux/atag.hh
+++ b/src/arch/arm/linux/atag.hh
@@ -43,6 +43,9 @@
#include "base/types.hh"
+namespace gem5
+{
+
enum
{
CoreTag = 0x54410001,
@@ -293,5 +296,6 @@
};
*/
+} // namespace gem5
#endif // __ARCH_ARM_LINUX_ATAG_HH__
diff --git a/src/arch/arm/linux/fs_workload.cc b/src/arch/arm/linux/fs_workload.cc
index 14a2b02..d512067 100644
--- a/src/arch/arm/linux/fs_workload.cc
+++ b/src/arch/arm/linux/fs_workload.cc
@@ -57,6 +57,9 @@
#include "mem/physical.hh"
#include "sim/stat_control.hh"
+namespace gem5
+{
+
using namespace linux;
namespace ArmISA
@@ -361,3 +364,4 @@
}
} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/linux/fs_workload.hh b/src/arch/arm/linux/fs_workload.hh
index 03fb6c1..3531ea9 100644
--- a/src/arch/arm/linux/fs_workload.hh
+++ b/src/arch/arm/linux/fs_workload.hh
@@ -54,6 +54,9 @@
#include "params/ArmFsLinux.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -164,6 +167,6 @@
};
} // namespace ArmISA
+} // namespace gem5
#endif // __ARCH_ARM_LINUX_FS_WORKLOAD_HH__
-
diff --git a/src/arch/arm/linux/linux.hh b/src/arch/arm/linux/linux.hh
index 6947d2d..15faede 100644
--- a/src/arch/arm/linux/linux.hh
+++ b/src/arch/arm/linux/linux.hh
@@ -48,6 +48,9 @@
#include "base/compiler.hh"
#include "kern/linux/linux.hh"
+namespace gem5
+{
+
class ArmLinux : public Linux
{
public:
@@ -555,4 +558,6 @@
}
};
+} // namespace gem5
+
#endif
diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc
index 8b20e59..b555ad4 100644
--- a/src/arch/arm/linux/process.cc
+++ b/src/arch/arm/linux/process.cc
@@ -54,6 +54,9 @@
#include "sim/syscall_emul.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace ArmISA;
const Addr ArmLinuxProcess32::commPage = 0xffff0000;
@@ -111,3 +114,5 @@
ArmProcess64::initState();
// The 64 bit equivalent of the comm page would be set up here.
}
+
+} // namespace gem5
diff --git a/src/arch/arm/linux/process.hh b/src/arch/arm/linux/process.hh
index bca5372..2884d92 100644
--- a/src/arch/arm/linux/process.hh
+++ b/src/arch/arm/linux/process.hh
@@ -45,6 +45,9 @@
#include "arch/arm/process.hh"
+namespace gem5
+{
+
/// A process with emulated Arm/Linux syscalls.
class ArmLinuxProcess32 : public ArmProcess32
{
@@ -72,4 +75,6 @@
void initState() override;
};
+} // namespace gem5
+
#endif // __ARM_LINUX_PROCESS_HH__
diff --git a/src/arch/arm/linux/se_workload.cc b/src/arch/arm/linux/se_workload.cc
index 4297e3c..f2d702a 100644
--- a/src/arch/arm/linux/se_workload.cc
+++ b/src/arch/arm/linux/se_workload.cc
@@ -48,6 +48,9 @@
#include "cpu/thread_context.hh"
#include "sim/syscall_emul.hh"
+namespace gem5
+{
+
namespace
{
@@ -863,3 +866,4 @@
}
} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/linux/se_workload.hh b/src/arch/arm/linux/se_workload.hh
index 62df4ba..0f9b9b9 100644
--- a/src/arch/arm/linux/se_workload.hh
+++ b/src/arch/arm/linux/se_workload.hh
@@ -34,6 +34,9 @@
#include "params/ArmEmuLinux.hh"
#include "sim/syscall_desc.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -79,5 +82,6 @@
};
} // namespace guest_abi
+} // namespace gem5
#endif // __ARCH_ARM_LINUX_SE_WORKLOAD_HH__
diff --git a/src/arch/arm/locked_mem.hh b/src/arch/arm/locked_mem.hh
index b23a157..103c07f 100644
--- a/src/arch/arm/locked_mem.hh
+++ b/src/arch/arm/locked_mem.hh
@@ -54,6 +54,9 @@
#include "mem/packet.hh"
#include "mem/request.hh"
+namespace gem5
+{
+
namespace ArmISA
{
template <class XC>
@@ -160,5 +163,6 @@
}
} // namespace ArmISA
+} // namespace gem5
#endif
diff --git a/src/arch/arm/mmu.cc b/src/arch/arm/mmu.cc
index 6045c33..b241f47 100644
--- a/src/arch/arm/mmu.cc
+++ b/src/arch/arm/mmu.cc
@@ -39,6 +39,9 @@
#include "arch/arm/table_walker.hh"
#include "arch/arm/tlbi_op.hh"
+namespace gem5
+{
+
using namespace ArmISA;
MMU::MMU(const ArmMMUParams &p)
@@ -128,3 +131,5 @@
getDTBPtr()->invalidateMiscReg();
}
}
+
+} // namespace gem5
diff --git a/src/arch/arm/mmu.hh b/src/arch/arm/mmu.hh
index 6d35b3f..54498f1 100644
--- a/src/arch/arm/mmu.hh
+++ b/src/arch/arm/mmu.hh
@@ -43,6 +43,9 @@
#include "params/ArmMMU.hh"
+namespace gem5
+{
+
namespace ArmISA {
class MMU : public BaseMMU
@@ -168,7 +171,7 @@
return mmu;
}
-
} // namespace ArmISA
+} // namespace gem5
#endif // __ARCH_ARM_MMU_HH__
diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc
index d94e21e..c1af3b1 100644
--- a/src/arch/arm/nativetrace.cc
+++ b/src/arch/arm/nativetrace.cc
@@ -48,6 +48,9 @@
#include "params/ArmNativeTrace.hh"
#include "sim/byteswap.hh"
+namespace gem5
+{
+
using namespace ArmISA;
namespace Trace {
@@ -217,3 +220,4 @@
}
} // namespace Trace
+} // namespace gem5
diff --git a/src/arch/arm/nativetrace.hh b/src/arch/arm/nativetrace.hh
index cf96c4a..c5abd44 100644
--- a/src/arch/arm/nativetrace.hh
+++ b/src/arch/arm/nativetrace.hh
@@ -33,6 +33,9 @@
#include "cpu/nativetrace.hh"
#include "params/ArmNativeTrace.hh"
+namespace gem5
+{
+
namespace Trace {
class ArmNativeTrace : public NativeTrace
@@ -108,5 +111,6 @@
};
} // namespace Trace
+} // namespace gem5
#endif // __ARCH_ARM_NATIVETRACE_HH__
diff --git a/src/arch/arm/page_size.hh b/src/arch/arm/page_size.hh
index 1fbd46a..b871bf6 100644
--- a/src/arch/arm/page_size.hh
+++ b/src/arch/arm/page_size.hh
@@ -44,10 +44,15 @@
#include "base/types.hh"
+namespace gem5
+{
+
namespace ArmISA
{
const Addr PageShift = 12;
const Addr PageBytes = 1ULL << PageShift;
+
} // namespace ArmISA
+} // namespace gem5
#endif // __ARCH_ARM_PAGE_SIZE_HH__
diff --git a/src/arch/arm/pagetable.hh b/src/arch/arm/pagetable.hh
index 35053b2..53780d7 100644
--- a/src/arch/arm/pagetable.hh
+++ b/src/arch/arm/pagetable.hh
@@ -48,6 +48,9 @@
#include "arch/arm/utility.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -363,8 +366,7 @@
};
+} // namespace ArmISA
+} // namespace gem5
-
-}
#endif // __ARCH_ARM_PAGETABLE_H__
-
diff --git a/src/arch/arm/pauth_helpers.cc b/src/arch/arm/pauth_helpers.cc
index aa93384..c204a07 100644
--- a/src/arch/arm/pauth_helpers.cc
+++ b/src/arch/arm/pauth_helpers.cc
@@ -40,6 +40,9 @@
#include "arch/arm/faults.hh"
#include "base/bitfield.hh"
+namespace gem5
+{
+
using namespace ArmISA;
bool
@@ -918,3 +921,4 @@
return NoFault;
}
+} // namespace gem5
diff --git a/src/arch/arm/pauth_helpers.hh b/src/arch/arm/pauth_helpers.hh
index 24e745c..11aec26 100644
--- a/src/arch/arm/pauth_helpers.hh
+++ b/src/arch/arm/pauth_helpers.hh
@@ -46,6 +46,9 @@
#include "base/bitunion.hh"
#include "cpu/thread_context.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -121,5 +124,7 @@
Fault
stripPAC(ThreadContext* tc, uint64_t A, bool data, uint64_t* out);
-};
+} // namespace ArmISA
+} // namespace gem5
+
#endif //__ARCH_ARM_PAUTH_HELPERS_HH__
diff --git a/src/arch/arm/pcstate.hh b/src/arch/arm/pcstate.hh
index f82afa2..b3d7c93 100644
--- a/src/arch/arm/pcstate.hh
+++ b/src/arch/arm/pcstate.hh
@@ -46,6 +46,9 @@
#include "base/types.hh"
#include "debug/Decoder.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -417,5 +420,6 @@
};
} // namespace ArmISA
+} // namespace gem5
#endif
diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc
index 51dfdca..ad4ea24 100644
--- a/src/arch/arm/pmu.cc
+++ b/src/arch/arm/pmu.cc
@@ -47,6 +47,9 @@
#include "dev/arm/generic_timer.hh"
#include "params/ArmPMU.hh"
+namespace gem5
+{
+
namespace ArmISA {
const RegVal PMU::reg_pmcr_wr_mask = 0x39;
@@ -807,3 +810,4 @@
}
} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/pmu.hh b/src/arch/arm/pmu.hh
index 739fd05..b9b2747 100644
--- a/src/arch/arm/pmu.hh
+++ b/src/arch/arm/pmu.hh
@@ -51,6 +51,9 @@
#include "sim/sim_object.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
struct ArmPMUParams;
class Platform;
class ThreadContext;
@@ -628,4 +631,6 @@
};
} // namespace ArmISA
+} // namespace gem5
+
#endif
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 3cca661..a2b0b60 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -57,6 +57,9 @@
#include "sim/syscall_return.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace ArmISA;
ArmProcess::ArmProcess(const ProcessParams ¶ms,
@@ -475,3 +478,5 @@
//Align the "stackMin" to a page boundary.
memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
}
+
+} // namespace gem5
diff --git a/src/arch/arm/process.hh b/src/arch/arm/process.hh
index bf57575..de6d171 100644
--- a/src/arch/arm/process.hh
+++ b/src/arch/arm/process.hh
@@ -50,6 +50,9 @@
#include "sim/process.hh"
#include "sim/syscall_abi.hh"
+namespace gem5
+{
+
class ArmProcess : public Process
{
protected:
@@ -98,5 +101,6 @@
uint32_t armHwcapImpl() const override;
};
-#endif // __ARM_PROCESS_HH__
+} // namespace gem5
+#endif // __ARM_PROCESS_HH__
diff --git a/src/arch/arm/qarma.cc b/src/arch/arm/qarma.cc
index 5805709..2ec302a 100644
--- a/src/arch/arm/qarma.cc
+++ b/src/arch/arm/qarma.cc
@@ -41,6 +41,9 @@
#include "base/bitfield.hh"
+namespace gem5
+{
+
using namespace QARMA;
@@ -393,3 +396,4 @@
return workingval;
}
+} // namespace gem5
diff --git a/src/arch/arm/qarma.hh b/src/arch/arm/qarma.hh
index 39aade0..9b19c37 100644
--- a/src/arch/arm/qarma.hh
+++ b/src/arch/arm/qarma.hh
@@ -41,6 +41,9 @@
#include "base/bitfield.hh"
#include "base/bitunion.hh"
+namespace gem5
+{
+
namespace QARMA
{
@@ -89,5 +92,8 @@
BIT64
computePAC(BIT64 data, BIT64 modifier, BIT64 key0, BIT64 key1);
-};
+
+} // namespace QARMA
+} // namespace gem5
+
#endif //__ARCH_ARM_QARMA_HH__
diff --git a/src/arch/arm/reg_abi.cc b/src/arch/arm/reg_abi.cc
index ba1511c..3422eb1 100644
--- a/src/arch/arm/reg_abi.cc
+++ b/src/arch/arm/reg_abi.cc
@@ -27,6 +27,9 @@
#include "arch/arm/reg_abi.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -34,3 +37,4 @@
const std::vector<int> RegABI64::ArgumentRegs = {0, 1, 2, 3, 4, 5, 6};
} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/reg_abi.hh b/src/arch/arm/reg_abi.hh
index b1e3e5e..c8f3eff 100644
--- a/src/arch/arm/reg_abi.hh
+++ b/src/arch/arm/reg_abi.hh
@@ -33,6 +33,9 @@
#include "base/logging.hh"
#include "sim/syscall_abi.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -74,5 +77,6 @@
};
} // namespace guest_abi
+} // namespace gem5
#endif // __ARCH_ARM_REG_ABI_HH__
diff --git a/src/arch/arm/regs/cc.hh b/src/arch/arm/regs/cc.hh
index edcf0db..9f3aaa1 100644
--- a/src/arch/arm/regs/cc.hh
+++ b/src/arch/arm/regs/cc.hh
@@ -38,6 +38,9 @@
#ifndef __ARCH_ARM_REGS_CC_HH__
#define __ARCH_ARM_REGS_CC_HH__
+namespace gem5
+{
+
namespace ArmISA
{
@@ -81,6 +84,7 @@
COND_UC // 15
};
-}
+} // namespace ArmISA
+} // namespace gem5
#endif // __ARCH_ARM_REGS_CC_HH__
diff --git a/src/arch/arm/regs/int.hh b/src/arch/arm/regs/int.hh
index fa52c16..30230e8 100644
--- a/src/arch/arm/regs/int.hh
+++ b/src/arch/arm/regs/int.hh
@@ -47,6 +47,9 @@
#include "base/logging.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -547,6 +550,7 @@
const int SyscallPseudoReturnReg = ReturnValueReg;
const int SyscallSuccessReg = ReturnValueReg;
-}
+} // namespace ArmISA
+} // namespace gem5
#endif
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 433c5ec..0306e9f 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -44,6 +44,9 @@
#include "cpu/thread_context.hh"
#include "sim/full_system.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -6033,3 +6036,4 @@
}
} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index 33d773e..0e9825d 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -48,6 +48,9 @@
#include "base/compiler.hh"
#include "dev/arm/generic_timer_miscregs_types.hh"
+namespace gem5
+{
+
class ThreadContext;
@@ -2278,6 +2281,7 @@
int
unflattenMiscReg(int reg);
-}
+} // namespace ArmISA
+} // namespace gem5
#endif // __ARCH_ARM_REGS_MISC_HH__
diff --git a/src/arch/arm/regs/misc_types.hh b/src/arch/arm/regs/misc_types.hh
index 66b1809..3d1a1a6 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -43,6 +43,9 @@
#include "base/bitunion.hh"
+namespace gem5
+{
+
namespace ArmISA
{
BitUnion32(CPSR)
@@ -786,6 +789,7 @@
Bitfield<3,0> pcsample;
EndBitUnion(DEVID)
-}
+} // namespace ArmISA
+} // namespace gem5
#endif // __ARCH_ARM_REGS_MISC_TYPES_HH__
diff --git a/src/arch/arm/regs/vec.hh b/src/arch/arm/regs/vec.hh
index 3bcc390..6a7d6e4 100644
--- a/src/arch/arm/regs/vec.hh
+++ b/src/arch/arm/regs/vec.hh
@@ -45,6 +45,9 @@
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -56,12 +59,12 @@
using VecElem = uint32_t;
using VecRegContainer =
- ::VecRegContainer<NumVecElemPerVecReg * sizeof(VecElem)>;
+ gem5::VecRegContainer<NumVecElemPerVecReg * sizeof(VecElem)>;
-using VecPredReg = ::VecPredRegT<VecElem, NumVecElemPerVecReg,
- false, false>;
-using ConstVecPredReg = ::VecPredRegT<VecElem, NumVecElemPerVecReg,
- false, true>;
+using VecPredReg =
+ gem5::VecPredRegT<VecElem, NumVecElemPerVecReg, false, false>;
+using ConstVecPredReg =
+ gem5::VecPredRegT<VecElem, NumVecElemPerVecReg, false, true>;
using VecPredRegContainer = VecPredReg::Container;
// Vec, PredVec
@@ -88,5 +91,6 @@
const int PREDREG_UREG0 = 17;
} // namespace ArmISA
+} // namespace gem5
#endif
diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index da53654..be56739 100644
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -163,6 +163,9 @@
#include "sim/full_system.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace ArmISA;
static bool
@@ -357,3 +360,5 @@
else
return ®Cache32;
}
+
+} // namespace gem5
diff --git a/src/arch/arm/remote_gdb.hh b/src/arch/arm/remote_gdb.hh
index 80d06d0..847dee7 100644
--- a/src/arch/arm/remote_gdb.hh
+++ b/src/arch/arm/remote_gdb.hh
@@ -51,6 +51,9 @@
#include "base/compiler.hh"
#include "base/remote_gdb.hh"
+namespace gem5
+{
+
class System;
class ThreadContext;
@@ -124,6 +127,8 @@
};
bool getXferFeaturesRead(const std::string &annex, std::string &output);
};
+
} // namespace ArmISA
+} // namespace gem5
#endif /* __ARCH_ARM_REMOTE_GDB_H__ */
diff --git a/src/arch/arm/se_workload.hh b/src/arch/arm/se_workload.hh
index eac2ad6..6d1d8ed 100644
--- a/src/arch/arm/se_workload.hh
+++ b/src/arch/arm/se_workload.hh
@@ -33,29 +33,33 @@
#include "params/ArmSEWorkload.hh"
#include "sim/se_workload.hh"
+namespace gem5
+{
+
namespace ArmISA
{
-class SEWorkload : public ::SEWorkload
+class SEWorkload : public gem5::SEWorkload
{
public:
using Params = ArmSEWorkloadParams;
- SEWorkload(const Params &p) : ::SEWorkload(p) {}
+ SEWorkload(const Params &p) : gem5::SEWorkload(p) {}
void
setSystem(System *sys) override
{
- ::SEWorkload::setSystem(sys);
+ gem5::SEWorkload::setSystem(sys);
gdb = BaseRemoteGDB::build<RemoteGDB>(system);
}
- ::loader::Arch getArch() const override { return ::loader::Arm64; }
+ loader::Arch getArch() const override { return loader::Arm64; }
using SyscallABI32 = RegABI32;
using SyscallABI64 = RegABI64;
};
} // namespace ArmISA
+} // namespace gem5
#endif // __ARCH_ARM_SE_WORKLOAD_HH__
diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index 310ccb4..21d4000 100644
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -42,6 +42,9 @@
#include "arch/arm/regs/misc_types.hh"
#include "base/bitfield.hh"
+namespace gem5
+{
+
using namespace ArmISA;
Fault
@@ -834,3 +837,4 @@
return false;
}
+} // namespace gem5
diff --git a/src/arch/arm/self_debug.hh b/src/arch/arm/self_debug.hh
index d1db5cc..f2499fd 100644
--- a/src/arch/arm/self_debug.hh
+++ b/src/arch/arm/self_debug.hh
@@ -48,6 +48,9 @@
#include "arch/generic/tlb.hh"
#include "cpu/thread_context.hh"
+namespace gem5
+{
+
class ThreadContext;
namespace ArmISA
@@ -461,5 +464,7 @@
void init(ThreadContext *tc);
};
-}
+} // namespace ArmISA
+} // namespace gem5
+
#endif
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 91a6205..1f06b51 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -58,6 +58,9 @@
#include "sim/sim_exit.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
const std::map<uint32_t, ArmSemihosting::SemiCall> ArmSemihosting::calls{
{ SYS_OPEN, { "SYS_OPEN", &ArmSemihosting::callOpen } },
{ SYS_CLOSE, { "SYS_CLOSE", &ArmSemihosting::callClose } },
@@ -1044,3 +1047,5 @@
ccprintf(os, "[%#x-%#x)", ipa.addr, ipa.addr + ipa.size - 1);
return os;
}
+
+} // namespace gem5
diff --git a/src/arch/arm/semihosting.hh b/src/arch/arm/semihosting.hh
index 6a38a98..2c237ca 100644
--- a/src/arch/arm/semihosting.hh
+++ b/src/arch/arm/semihosting.hh
@@ -52,6 +52,9 @@
#include "sim/guest_abi.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
struct ArmSemihostingParams;
class SerialDevice;
@@ -657,5 +660,6 @@
};
} // namespace guest_abi
+} // namespace gem5
#endif // __ARCH_ARM_SEMIHOSTING_HH__
diff --git a/src/arch/arm/stacktrace.hh b/src/arch/arm/stacktrace.hh
index 6a83fce..0304046 100644
--- a/src/arch/arm/stacktrace.hh
+++ b/src/arch/arm/stacktrace.hh
@@ -31,6 +31,9 @@
#include "cpu/profile.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -41,5 +44,6 @@
};
} // Namespace ArmISA
+} // namespace gem5
#endif // __ARCH_ARM_STACKTRACE_HH__
diff --git a/src/arch/arm/stage2_lookup.cc b/src/arch/arm/stage2_lookup.cc
index 93843ab..dac107c 100644
--- a/src/arch/arm/stage2_lookup.cc
+++ b/src/arch/arm/stage2_lookup.cc
@@ -48,6 +48,9 @@
#include "debug/TLBVerbose.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace ArmISA;
Fault
@@ -201,3 +204,4 @@
}
}
+} // namespace gem5
diff --git a/src/arch/arm/stage2_lookup.hh b/src/arch/arm/stage2_lookup.hh
index 66b1359..a2416ea 100644
--- a/src/arch/arm/stage2_lookup.hh
+++ b/src/arch/arm/stage2_lookup.hh
@@ -45,6 +45,9 @@
#include "arch/arm/tlb.hh"
#include "mem/request.hh"
+namespace gem5
+{
+
class ThreadContext;
namespace ArmISA {
@@ -99,8 +102,7 @@
BaseTLB::Mode mode);
};
-
} // namespace ArmISA
+} // namespace gem5
#endif //__ARCH_ARM_STAGE2_LOOKUP_HH__
-
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 4d3a70b..f19978e 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -51,6 +51,9 @@
#include "dev/arm/gic_v2.hh"
#include "mem/physical.hh"
+namespace gem5
+{
+
using namespace linux;
using namespace ArmISA;
@@ -234,3 +237,5 @@
if (FVPBasePwrCtrl *pwr_ctrl = getArmSystem(tc)->getPowerController())
pwr_ctrl->clearWakeRequest(tc);
}
+
+} // namespace gem5
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index a91f220..f2ec5c3 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -51,6 +51,9 @@
#include "sim/sim_object.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
class GenericTimer;
class BaseGic;
class FVPBasePwrCtrl;
@@ -356,4 +359,6 @@
static void callClearWakeRequest(ThreadContext *tc);
};
+} // namespace gem5
+
#endif
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index bc2d9bd..9d4a313 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -53,6 +53,9 @@
#include "debug/TLBVerbose.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace ArmISA;
TableWalker::TableWalker(const Params &p)
@@ -2587,3 +2590,5 @@
requestOrigin.ysubname(0,"Data");
requestOrigin.ysubname(1,"Inst");
}
+
+} // namespace gem5
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 5ba03cb..3446504 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -52,6 +52,9 @@
#include "sim/clocked_object.hh"
#include "sim/eventq.hh"
+namespace gem5
+{
+
class ThreadContext;
namespace ArmISA {
@@ -1020,7 +1023,7 @@
DrainState drain() override;
void drainResume() override;
- ::Port &getPort(const std::string &if_name,
+ gem5::Port &getPort(const std::string &if_name,
PortID idx=InvalidPortID) override;
Port &getTableWalkerPort();
@@ -1100,6 +1103,6 @@
};
} // namespace ArmISA
+} // namespace gem5
#endif //__ARCH_ARM_TABLE_WALKER_HH__
-
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index c8174b4..bc49aae 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -71,6 +71,9 @@
#include "sim/process.hh"
#include "sim/pseudo_inst.hh"
+namespace gem5
+{
+
using namespace ArmISA;
TLB::TLB(const ArmTLBParams &p)
@@ -1731,3 +1734,5 @@
domain, lookup_level);
}
}
+
+} // namespace gem5
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index b59fd67..9f875ea 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -51,6 +51,9 @@
#include "params/ArmTLB.hh"
#include "sim/probe/pmu.hh"
+namespace gem5
+{
+
class ThreadContext;
namespace ArmISA {
@@ -461,5 +464,6 @@
};
} // namespace ArmISA
+} // namespace gem5
#endif // __ARCH_ARM_TLB_HH__
diff --git a/src/arch/arm/tlbi_op.cc b/src/arch/arm/tlbi_op.cc
index d918454..5f2cc5a 100644
--- a/src/arch/arm/tlbi_op.cc
+++ b/src/arch/arm/tlbi_op.cc
@@ -40,6 +40,9 @@
#include "arch/arm/mmu.hh"
#include "cpu/checker/cpu.hh"
+namespace gem5
+{
+
namespace ArmISA {
void
@@ -191,3 +194,4 @@
}
} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/tlbi_op.hh b/src/arch/arm/tlbi_op.hh
index e2f3eee..0151ff9 100644
--- a/src/arch/arm/tlbi_op.hh
+++ b/src/arch/arm/tlbi_op.hh
@@ -48,6 +48,10 @@
* Instructions. Those are the ISA interface for TLB flushing
* operations.
*/
+
+namespace gem5
+{
+
namespace ArmISA {
class TLBIOp
@@ -360,5 +364,6 @@
};
} // namespace ArmISA
+} // namespace gem5
#endif //__ARCH_ARM_TLBI_HH__
diff --git a/src/arch/arm/tracers/TarmacTrace.py b/src/arch/arm/tracers/TarmacTrace.py
index b9ffe39..faf2db0 100644
--- a/src/arch/arm/tracers/TarmacTrace.py
+++ b/src/arch/arm/tracers/TarmacTrace.py
@@ -39,7 +39,7 @@
class TarmacParser(InstTracer):
type = 'TarmacParser'
- cxx_class = 'Trace::TarmacParser'
+ cxx_class = 'gem5::Trace::TarmacParser'
cxx_header = "arch/arm/tracers/tarmac_parser.hh"
path_to_trace = Param.String("tarmac.log", "path to TARMAC trace")
@@ -64,7 +64,7 @@
class TarmacTracer(InstTracer):
type = 'TarmacTracer'
- cxx_class = 'Trace::TarmacTracer'
+ cxx_class = 'gem5::Trace::TarmacTracer'
cxx_header = "arch/arm/tracers/tarmac_tracer.hh"
start_tick = Param.Tick(0,
diff --git a/src/arch/arm/tracers/tarmac_base.cc b/src/arch/arm/tracers/tarmac_base.cc
index c05605b..d0f0bcd 100644
--- a/src/arch/arm/tracers/tarmac_base.cc
+++ b/src/arch/arm/tracers/tarmac_base.cc
@@ -45,6 +45,9 @@
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+namespace gem5
+{
+
using namespace ArmISA;
namespace Trace {
@@ -115,3 +118,4 @@
}
} // namespace Trace
+} // namespace gem5
diff --git a/src/arch/arm/tracers/tarmac_base.hh b/src/arch/arm/tracers/tarmac_base.hh
index aaf909a..a29eb74 100644
--- a/src/arch/arm/tracers/tarmac_base.hh
+++ b/src/arch/arm/tracers/tarmac_base.hh
@@ -54,6 +54,9 @@
#include "cpu/static_inst.hh"
#include "sim/insttracer.hh"
+namespace gem5
+{
+
class ThreadContext;
namespace Trace {
@@ -144,5 +147,6 @@
} // namespace Trace
+} // namespace gem5
#endif // __ARCH_ARM_TRACERS_TARMAC_BASE_HH__
diff --git a/src/arch/arm/tracers/tarmac_parser.cc b/src/arch/arm/tracers/tarmac_parser.cc
index c18c6ca..52b9558 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -53,6 +53,9 @@
#include "sim/faults.hh"
#include "sim/sim_exit.hh"
+namespace gem5
+{
+
using namespace ArmISA;
namespace Trace {
@@ -1366,3 +1369,4 @@
}
} // namespace Trace
+} // namespace gem5
diff --git a/src/arch/arm/tracers/tarmac_parser.hh b/src/arch/arm/tracers/tarmac_parser.hh
index 000a874..6de0172 100644
--- a/src/arch/arm/tracers/tarmac_parser.hh
+++ b/src/arch/arm/tracers/tarmac_parser.hh
@@ -58,6 +58,9 @@
#include "sim/insttracer.hh"
#include "tarmac_base.hh"
+namespace gem5
+{
+
namespace Trace {
class TarmacParserRecord : public TarmacBaseRecord
@@ -295,5 +298,6 @@
};
} // namespace Trace
+} // namespace gem5
#endif // __ARCH_ARM_TRACERS_TARMAC_PARSER_HH__
diff --git a/src/arch/arm/tracers/tarmac_record.cc b/src/arch/arm/tracers/tarmac_record.cc
index b7729b4..57d307a 100644
--- a/src/arch/arm/tracers/tarmac_record.cc
+++ b/src/arch/arm/tracers/tarmac_record.cc
@@ -42,6 +42,9 @@
#include "arch/arm/insts/static_inst.hh"
#include "tarmac_tracer.hh"
+namespace gem5
+{
+
using namespace ArmISA;
namespace Trace {
@@ -461,3 +464,4 @@
}
} // namespace Trace
+} // namespace gem5
diff --git a/src/arch/arm/tracers/tarmac_record.hh b/src/arch/arm/tracers/tarmac_record.hh
index deaca5ec..a1d42b2 100644
--- a/src/arch/arm/tracers/tarmac_record.hh
+++ b/src/arch/arm/tracers/tarmac_record.hh
@@ -51,6 +51,9 @@
#include "cpu/reg_class.hh"
#include "cpu/static_inst.hh"
+namespace gem5
+{
+
namespace Trace {
class TarmacContext;
@@ -267,5 +270,6 @@
};
} // namespace Trace
+} // namespace gem5
#endif // __ARCH_ARM_TRACERS_TARMAC_RECORD_HH__
diff --git a/src/arch/arm/tracers/tarmac_record_v8.cc b/src/arch/arm/tracers/tarmac_record_v8.cc
index 4b19921..8dd96d1 100644
--- a/src/arch/arm/tracers/tarmac_record_v8.cc
+++ b/src/arch/arm/tracers/tarmac_record_v8.cc
@@ -43,6 +43,9 @@
#include "arch/arm/mmu.hh"
#include "arch/arm/tracers/tarmac_tracer.hh"
+namespace gem5
+{
+
using namespace ArmISA;
namespace Trace {
@@ -323,3 +326,4 @@
}
} // namespace Trace
+} // namespace gem5
diff --git a/src/arch/arm/tracers/tarmac_record_v8.hh b/src/arch/arm/tracers/tarmac_record_v8.hh
index 3de41eb..4a65806 100644
--- a/src/arch/arm/tracers/tarmac_record_v8.hh
+++ b/src/arch/arm/tracers/tarmac_record_v8.hh
@@ -45,6 +45,9 @@
#include "tarmac_record.hh"
+namespace gem5
+{
+
namespace Trace {
/**
@@ -163,5 +166,6 @@
};
} // namespace Trace
+} // namespace gem5
#endif // __ARCH_ARM_TRACERS_TARMAC_RECORD_V8_HH__
diff --git a/src/arch/arm/tracers/tarmac_tracer.cc b/src/arch/arm/tracers/tarmac_tracer.cc
index f56e0ad..06aab74 100644
--- a/src/arch/arm/tracers/tarmac_tracer.cc
+++ b/src/arch/arm/tracers/tarmac_tracer.cc
@@ -42,6 +42,9 @@
#include "arch/arm/system.hh"
#include "cpu/base.hh"
+namespace gem5
+{
+
namespace Trace {
std::string
@@ -93,3 +96,4 @@
}
} // namespace Trace
+} // namespace gem5
diff --git a/src/arch/arm/tracers/tarmac_tracer.hh b/src/arch/arm/tracers/tarmac_tracer.hh
index fb2d96d..908f185 100644
--- a/src/arch/arm/tracers/tarmac_tracer.hh
+++ b/src/arch/arm/tracers/tarmac_tracer.hh
@@ -48,6 +48,9 @@
#include "params/TarmacTracer.hh"
#include "sim/insttracer.hh"
+namespace gem5
+{
+
class ThreadContext;
namespace Trace {
@@ -126,5 +129,6 @@
};
} // namespace Trace
+} // namespace gem5
#endif // __ARCH_ARM_TRACERS_TARMAC_TRACER_HH__
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 60566fc..a4d1f33 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -47,6 +47,9 @@
#include "base/bitunion.hh"
#include "base/logging.hh"
+namespace gem5
+{
+
namespace ArmISA
{
typedef uint32_t MachInst;
@@ -461,6 +464,8 @@
constexpr unsigned VecRegSizeBytes = MaxSveVecLenInBytes;
constexpr unsigned VecPredRegSizeBits = MaxSveVecLenInBytes;
+
} // namespace ArmISA
+} // namespace gem5
#endif
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 263ceb7..68a1115 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -53,6 +53,9 @@
#include "mem/port_proxy.hh"
#include "sim/full_system.hh"
+namespace gem5
+{
+
namespace ArmISA
{
@@ -1328,3 +1331,4 @@
}
} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index d7858ef..9b2496e 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -52,6 +52,9 @@
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+namespace gem5
+{
+
class ArmSystem;
namespace ArmISA {
@@ -413,5 +416,7 @@
bool isUnpriviledgeAccess(ThreadContext * tc);
-}
+} // namespace ArmISA
+} // namespace gem5
+
#endif
diff --git a/src/arch/gcn3/registers.hh b/src/arch/gcn3/registers.hh
index 21ff322..130f052 100644
--- a/src/arch/gcn3/registers.hh
+++ b/src/arch/gcn3/registers.hh
@@ -42,6 +42,9 @@
#include "base/intmath.hh"
#include "base/logging.hh"
+namespace gem5
+{
+
namespace Gcn3ISA
{
enum OpSelector : int
@@ -227,5 +230,6 @@
bool isExecMask(int opIdx);
bool isVccReg(int opIdx);
} // namespace Gcn3ISA
+} // namespace gem5
#endif // __ARCH_GCN3_REGISTERS_HH__
diff --git a/src/arch/generic/BaseISA.py b/src/arch/generic/BaseISA.py
index 2cc2c45..fa07d73 100644
--- a/src/arch/generic/BaseISA.py
+++ b/src/arch/generic/BaseISA.py
@@ -30,3 +30,4 @@
type = 'BaseISA'
abstract = True
cxx_header = "arch/generic/isa.hh"
+ cxx_class = 'gem5::BaseISA'
diff --git a/src/arch/generic/BaseInterrupts.py b/src/arch/generic/BaseInterrupts.py
index a5b7ad5..ab26323 100644
--- a/src/arch/generic/BaseInterrupts.py
+++ b/src/arch/generic/BaseInterrupts.py
@@ -30,3 +30,4 @@
type = 'BaseInterrupts'
abstract = True
cxx_header = "arch/generic/interrupts.hh"
+ cxx_class = 'gem5::BaseInterrupts'
diff --git a/src/arch/generic/BaseMMU.py b/src/arch/generic/BaseMMU.py
index a4ea0e1..c9ea25a 100644
--- a/src/arch/generic/BaseMMU.py
+++ b/src/arch/generic/BaseMMU.py
@@ -43,6 +43,8 @@
type = 'BaseMMU'
abstract = True
cxx_header = "arch/generic/mmu.hh"
+ cxx_class = 'gem5::BaseMMU'
+
itb = Param.BaseTLB("Instruction TLB")
dtb = Param.BaseTLB("Data TLB")
diff --git a/src/arch/generic/BaseTLB.py b/src/arch/generic/BaseTLB.py
index 03fb68b..a090a06 100644
--- a/src/arch/generic/BaseTLB.py
+++ b/src/arch/generic/BaseTLB.py
@@ -32,6 +32,8 @@
type = 'BaseTLB'
abstract = True
cxx_header = "arch/generic/tlb.hh"
+ cxx_class = 'gem5::BaseTLB'
+
# Ports to connect with other TLB levels
cpu_side_ports = VectorResponsePort("Ports closer to the CPU side")
slave = DeprecatedParam(cpu_side_ports,
diff --git a/src/arch/generic/debugfaults.hh b/src/arch/generic/debugfaults.hh
index dd95f2c..d3886e0 100644
--- a/src/arch/generic/debugfaults.hh
+++ b/src/arch/generic/debugfaults.hh
@@ -45,6 +45,9 @@
#include "cpu/thread_context.hh"
#include "sim/faults.hh"
+namespace gem5
+{
+
namespace GenericISA
{
@@ -171,5 +174,6 @@
M5InformFaultBase<M5DebugOnceFault<M5InformFault>>;
} // namespace GenericISA
+} // namespace gem5
#endif // __ARCH_GENERIC_DEBUGFAULTS_HH__
diff --git a/src/arch/generic/decode_cache.hh b/src/arch/generic/decode_cache.hh
index b4caa72..387a5ac 100644
--- a/src/arch/generic/decode_cache.hh
+++ b/src/arch/generic/decode_cache.hh
@@ -33,6 +33,9 @@
#include "cpu/decode_cache.hh"
#include "cpu/static_inst_fwd.hh"
+namespace gem5
+{
+
namespace GenericISA
{
@@ -74,5 +77,6 @@
};
} // namespace GenericISA
+} // namespace gem5
#endif // __ARCH_GENERIC_DECODE_CACHE_HH__
diff --git a/src/arch/generic/decoder.cc b/src/arch/generic/decoder.cc
index c28fa00..22e4d53 100644
--- a/src/arch/generic/decoder.cc
+++ b/src/arch/generic/decoder.cc
@@ -29,8 +29,13 @@
#include "base/logging.hh"
+namespace gem5
+{
+
StaticInstPtr
InstDecoder::fetchRomMicroop(MicroPC micropc, StaticInstPtr curMacroop)
{
panic("ROM based microcode isn't implemented.");
}
+
+} // namespace gem5
diff --git a/src/arch/generic/decoder.hh b/src/arch/generic/decoder.hh
index cb6e4cd..6bfc199 100644
--- a/src/arch/generic/decoder.hh
+++ b/src/arch/generic/decoder.hh
@@ -33,6 +33,9 @@
#include "base/types.hh"
#include "cpu/static_inst_fwd.hh"
+namespace gem5
+{
+
class InstDecoder
{
protected:
@@ -55,4 +58,6 @@
Addr pcMask() const { return _pcMask; }
};
+} // namespace gem5
+
#endif // __ARCH_DECODER_GENERIC_HH__
diff --git a/src/arch/generic/freebsd/threadinfo.hh b/src/arch/generic/freebsd/threadinfo.hh
index 6c89450..f77772a 100644
--- a/src/arch/generic/freebsd/threadinfo.hh
+++ b/src/arch/generic/freebsd/threadinfo.hh
@@ -36,6 +36,9 @@
#include "cpu/thread_context.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(FreeBSD, free_bsd);
namespace free_bsd
{
@@ -57,5 +60,6 @@
};
} // namespace free_bsd
+} // namespace gem5
#endif // __ARCH_GENERIC_FREEBSD_THREADINFO_HH__
diff --git a/src/arch/generic/htm.cc b/src/arch/generic/htm.cc
index 238178d..4e29efe 100644
--- a/src/arch/generic/htm.cc
+++ b/src/arch/generic/htm.cc
@@ -37,4 +37,9 @@
#include "arch/generic/htm.hh"
+namespace gem5
+{
+
uint64_t BaseHTMCheckpoint::globalHtmUid = 0;
+
+} // namespace gem5
diff --git a/src/arch/generic/htm.hh b/src/arch/generic/htm.hh
index 5f45f5d..5b110ca 100644
--- a/src/arch/generic/htm.hh
+++ b/src/arch/generic/htm.hh
@@ -112,6 +112,9 @@
#include "mem/htm.hh"
+namespace gem5
+{
+
/**
* @file
*
@@ -211,4 +214,6 @@
bool _valid;
};
+} // namespace gem5
+
#endif // __ARCH_GENERIC_HTM_HH__
diff --git a/src/arch/generic/interrupts.hh b/src/arch/generic/interrupts.hh
index a4c640f..5107755 100644
--- a/src/arch/generic/interrupts.hh
+++ b/src/arch/generic/interrupts.hh
@@ -32,6 +32,9 @@
#include "params/BaseInterrupts.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class ThreadContext;
class BaseCPU;
@@ -88,4 +91,6 @@
}
};
+} // namespace gem5
+
#endif // __ARCH_GENERIC_INTERRUPTS_HH__
diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index 5bf9928..98b80d0 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -46,6 +46,9 @@
#include "enums/VecRegRenameMode.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class ThreadContext;
class BaseISA : public SimObject
@@ -83,4 +86,6 @@
const RegClasses ®Classes() const { return _regClasses; }
};
+} // namespace gem5
+
#endif // __ARCH_GENERIC_ISA_HH__
diff --git a/src/arch/generic/linux/threadinfo.hh b/src/arch/generic/linux/threadinfo.hh
index 3579589..c880d4d 100644
--- a/src/arch/generic/linux/threadinfo.hh
+++ b/src/arch/generic/linux/threadinfo.hh
@@ -32,6 +32,9 @@
#include "cpu/thread_context.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Linux, linux);
namespace linux
{
@@ -186,5 +189,6 @@
};
} // namespace linux
+} // namespace gem5
#endif // __ARCH_GENERIC_LINUX_THREADINFO_HH__
diff --git a/src/arch/generic/locked_mem.hh b/src/arch/generic/locked_mem.hh
index f963513..8a78e66 100644
--- a/src/arch/generic/locked_mem.hh
+++ b/src/arch/generic/locked_mem.hh
@@ -51,6 +51,9 @@
#include "mem/packet.hh"
#include "mem/request.hh"
+namespace gem5
+{
+
namespace GenericISA
{
@@ -93,5 +96,6 @@
} // namespace locked_mem
} // namespace Generic ISA
+} // namespace gem5
#endif
diff --git a/src/arch/generic/memhelpers.hh b/src/arch/generic/memhelpers.hh
index d9adfdc..b07a654 100644
--- a/src/arch/generic/memhelpers.hh
+++ b/src/arch/generic/memhelpers.hh
@@ -47,6 +47,9 @@
#include "sim/byteswap.hh"
#include "sim/insttracer.hh"
+namespace gem5
+{
+
template <class XC>
Fault
initiateMemRead(XC *xc, Addr addr, std::size_t size,
@@ -281,4 +284,6 @@
return xc->initiateMemAMO(addr, sizeof(MemT), flags, std::move(amo_op));
}
+} // namespace gem5
+
#endif
diff --git a/src/arch/generic/mmu.cc b/src/arch/generic/mmu.cc
index 4ef45fb..55f6622 100644
--- a/src/arch/generic/mmu.cc
+++ b/src/arch/generic/mmu.cc
@@ -43,6 +43,9 @@
#include "arch/generic/mmu.hh"
+namespace gem5
+{
+
void
BaseMMU::takeOverFrom(BaseMMU *old_mmu)
{
@@ -60,3 +63,5 @@
itb->takeOverFrom(old_mmu->itb);
dtb->takeOverFrom(old_mmu->dtb);
}
+
+} // namespace gem5
diff --git a/src/arch/generic/mmu.hh b/src/arch/generic/mmu.hh
index d7c048c..50b2c98 100644
--- a/src/arch/generic/mmu.hh
+++ b/src/arch/generic/mmu.hh
@@ -42,6 +42,9 @@
#include "params/BaseMMU.hh"
+namespace gem5
+{
+
class BaseMMU : public SimObject
{
protected:
@@ -110,4 +113,6 @@
BaseTLB* itb;
};
+} // namespace gem5
+
#endif
diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh
index 59b3a01..a9328e4 100644
--- a/src/arch/generic/tlb.hh
+++ b/src/arch/generic/tlb.hh
@@ -45,6 +45,9 @@
#include "mem/request.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class ThreadContext;
class BaseTLB : public SimObject
@@ -139,4 +142,6 @@
void memInvalidate() { flushAll(); }
};
+} // namespace gem5
+
#endif // __ARCH_GENERIC_TLB_HH__
diff --git a/src/arch/generic/types.hh b/src/arch/generic/types.hh
index 2e3b847..470e9e5 100644
--- a/src/arch/generic/types.hh
+++ b/src/arch/generic/types.hh
@@ -47,6 +47,9 @@
#include "base/types.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
namespace GenericISA
{
@@ -477,4 +480,6 @@
}
+} // namespace gem5
+
#endif
diff --git a/src/arch/generic/vec_pred_reg.hh b/src/arch/generic/vec_pred_reg.hh
index fce2706..eb96949 100644
--- a/src/arch/generic/vec_pred_reg.hh
+++ b/src/arch/generic/vec_pred_reg.hh
@@ -46,6 +46,9 @@
#include "base/cprintf.hh"
#include "sim/serialize_handlers.hh"
+namespace gem5
+{
+
template <size_t NumBits, bool Packed>
class VecPredRegContainer;
@@ -392,4 +395,6 @@
using DummyVecPredRegContainer = VecPredRegContainer<8, false>;
/// @}
+} // namespace gem5
+
#endif // __ARCH_GENERIC_VEC_PRED_REG_HH__
diff --git a/src/arch/generic/vec_reg.hh b/src/arch/generic/vec_reg.hh
index d9a764f..1bc9099 100644
--- a/src/arch/generic/vec_reg.hh
+++ b/src/arch/generic/vec_reg.hh
@@ -105,6 +105,9 @@
#include "base/logging.hh"
#include "sim/serialize_handlers.hh"
+namespace gem5
+{
+
constexpr unsigned MaxVecRegLenInBytes = 4096;
/**
@@ -266,4 +269,6 @@
VecRegContainer<DummyNumVecElemPerVecReg * sizeof(DummyVecElem)>;
/** @} */
+} // namespace gem5
+
#endif /* __ARCH_GENERIC_VEC_REG_HH__ */
diff --git a/src/arch/isa_parser/isa_parser.py b/src/arch/isa_parser/isa_parser.py
index bfe9c91..9cfd5ba 100755
--- a/src/arch/isa_parser/isa_parser.py
+++ b/src/arch/isa_parser/isa_parser.py
@@ -606,8 +606,10 @@
fn = 'decoder-ns.hh.inc'
assert(fn in self.files)
- f.write('namespace %s {\n#include "%s"\n}\n'
- % (self.namespace, fn))
+ f.write('namespace gem5\n{\n')
+ f.write('namespace %s {\n#include "%s"\n} // namespace %s\n'
+ % (self.namespace, fn, self.namespace))
+ f.write('} // namespace gem5')
f.write('\n#endif // __ARCH_%s_GENERATED_DECODER_HH__\n' %
self.isa_name.upper())
@@ -648,11 +650,13 @@
fn = 'decoder-ns.cc.inc'
assert(fn in self.files)
+ print('namespace gem5\n{\n', file=f)
print('namespace %s {' % self.namespace, file=f)
if splits > 1:
print('#define __SPLIT %u' % i, file=f)
print('#include "%s"' % fn, file=f)
- print('}', file=f)
+ print('} // namespace %s' % self.namespace, file=f)
+ print('} // namespace gem5', file=f)
# instruction execution
splits = self.splits[self.get_file('exec')]
@@ -669,11 +673,13 @@
fn = 'exec-ns.cc.inc'
assert(fn in self.files)
+ print('namespace gem5\n{\n', file=f)
print('namespace %s {' % self.namespace, file=f)
if splits > 1:
print('#define __SPLIT %u' % i, file=f)
print('#include "%s"' % fn, file=f)
- print('}', file=f)
+ print('} // namespace %s' % self.namespace, file=f)
+ print('} // namespace gem5', file=f)
scaremonger_template ='''// DO NOT EDIT
// This file was automatically generated from an ISA description:
@@ -1152,6 +1158,7 @@
'top_level_decode_block : decode_block'
codeObj = t[1]
codeObj.wrap_decode_block('''
+using namespace gem5;
StaticInstPtr
%(isa_name)s::Decoder::decodeInst(%(isa_name)s::ExtMachInst machInst)
{
diff --git a/src/arch/mips/MipsISA.py b/src/arch/mips/MipsISA.py
index 5194e18..eae00f9 100644
--- a/src/arch/mips/MipsISA.py
+++ b/src/arch/mips/MipsISA.py
@@ -40,7 +40,7 @@
class MipsISA(BaseISA):
type = 'MipsISA'
- cxx_class = 'MipsISA::ISA'
+ cxx_class = 'gem5::MipsISA::ISA'
cxx_header = "arch/mips/isa.hh"
system = Param.System(Parent.any, "System this ISA object belongs to")
diff --git a/src/arch/mips/MipsInterrupts.py b/src/arch/mips/MipsInterrupts.py
index fdd7fc7..de0a038 100644
--- a/src/arch/mips/MipsInterrupts.py
+++ b/src/arch/mips/MipsInterrupts.py
@@ -28,5 +28,5 @@
class MipsInterrupts(BaseInterrupts):
type = 'MipsInterrupts'
- cxx_class = 'MipsISA::Interrupts'
+ cxx_class = 'gem5::MipsISA::Interrupts'
cxx_header = 'arch/mips/interrupts.hh'
diff --git a/src/arch/mips/MipsMMU.py b/src/arch/mips/MipsMMU.py
index e6dcd97..0de1002 100644
--- a/src/arch/mips/MipsMMU.py
+++ b/src/arch/mips/MipsMMU.py
@@ -40,7 +40,7 @@
class MipsMMU(BaseMMU):
type = 'MipsMMU'
- cxx_class = 'MipsISA::MMU'
+ cxx_class = 'gem5::MipsISA::MMU'
cxx_header = 'arch/mips/mmu.hh'
itb = MipsTLB()
dtb = MipsTLB()
diff --git a/src/arch/mips/MipsSeWorkload.py b/src/arch/mips/MipsSeWorkload.py
index 453a2c4..d95bc5c 100644
--- a/src/arch/mips/MipsSeWorkload.py
+++ b/src/arch/mips/MipsSeWorkload.py
@@ -30,13 +30,13 @@
class MipsSEWorkload(SEWorkload):
type = 'MipsSEWorkload'
cxx_header = "arch/mips/se_workload.hh"
- cxx_class = 'MipsISA::SEWorkload'
+ cxx_class = 'gem5::MipsISA::SEWorkload'
abstract = True
class MipsEmuLinux(MipsSEWorkload):
type = 'MipsEmuLinux'
cxx_header = "arch/mips/linux/se_workload.hh"
- cxx_class = 'MipsISA::EmuLinux'
+ cxx_class = 'gem5::MipsISA::EmuLinux'
@classmethod
def _is_compatible_with(cls, obj):
diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py
index d43b6d7..74b6eb6 100644
--- a/src/arch/mips/MipsTLB.py
+++ b/src/arch/mips/MipsTLB.py
@@ -33,6 +33,6 @@
class MipsTLB(BaseTLB):
type = 'MipsTLB'
- cxx_class = 'MipsISA::TLB'
+ cxx_class = 'gem5::MipsISA::TLB'
cxx_header = 'arch/mips/tlb.hh'
size = Param.Int(64, "TLB size")
diff --git a/src/arch/mips/decoder.cc b/src/arch/mips/decoder.cc
index de53817..0e30f70 100644
--- a/src/arch/mips/decoder.cc
+++ b/src/arch/mips/decoder.cc
@@ -28,9 +28,13 @@
#include "arch/mips/decoder.hh"
+namespace gem5
+{
+
namespace MipsISA
{
GenericISA::BasicDecodeCache<Decoder, ExtMachInst> Decoder::defaultCache;
-}
+} // namespace MipsISA
+} // namespace gem5
diff --git a/src/arch/mips/decoder.hh b/src/arch/mips/decoder.hh
index 4b8a84c..0e8e2ca 100644
--- a/src/arch/mips/decoder.hh
+++ b/src/arch/mips/decoder.hh
@@ -37,6 +37,9 @@
#include "cpu/static_inst.hh"
#include "debug/Decode.hh"
+namespace gem5
+{
+
namespace MipsISA
{
@@ -118,5 +121,6 @@
};
} // namespace MipsISA
+} // namespace gem5
#endif // __ARCH_MIPS_DECODER_HH__
diff --git a/src/arch/mips/dsp.cc b/src/arch/mips/dsp.cc
index 425cf50..7d73799 100644
--- a/src/arch/mips/dsp.cc
+++ b/src/arch/mips/dsp.cc
@@ -33,6 +33,9 @@
#include "cpu/static_inst.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
using namespace MipsISA;
int32_t
@@ -1185,3 +1188,5 @@
return *dspctl & fmask;
}
+
+} // namespace gem5
diff --git a/src/arch/mips/dsp.hh b/src/arch/mips/dsp.hh
index 18dc15f..9021dd0 100644
--- a/src/arch/mips/dsp.hh
+++ b/src/arch/mips/dsp.hh
@@ -33,6 +33,9 @@
#include "base/logging.hh"
#include "base/types.hh"
+namespace gem5
+{
+
class ThreadContext;
namespace MipsISA {
@@ -200,5 +203,6 @@
uint32_t readDSPControl(uint32_t *dspctl, uint32_t mask);
} // namespace MipsISA
+} // namespace gem5
#endif // __ARCH_MIPS_DSP_HH__
diff --git a/src/arch/mips/dt_constants.hh b/src/arch/mips/dt_constants.hh
index ffc6e0c..93a1bac 100644
--- a/src/arch/mips/dt_constants.hh
+++ b/src/arch/mips/dt_constants.hh
@@ -32,6 +32,9 @@
#include "arch/mips/types.hh"
#include "base/bitunion.hh"
+namespace gem5
+{
+
namespace MipsISA
{
@@ -129,6 +132,8 @@
Bitfield<1> tup;
Bitfield<0> paco;
EndBitUnion(Debug2Reg)
+
} // namespace MipsISA
+} // namespace gem5
#endif
diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index b38bedf..a9f5239 100644
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -37,6 +37,9 @@
#include "mem/page_table.hh"
#include "sim/process.hh"
+namespace gem5
+{
+
namespace MipsISA
{
@@ -167,4 +170,4 @@
}
} // namespace MipsISA
-
+} // namespace gem5
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index aeb37a7..7b86c33 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -38,6 +38,9 @@
#include "sim/faults.hh"
#include "sim/full_system.hh"
+namespace gem5
+{
+
namespace MipsISA
{
@@ -325,5 +328,6 @@
} // namespace MipsISA
+} // namespace gem5
#endif // __MIPS_FAULTS_HH__
diff --git a/src/arch/mips/idle_event.cc b/src/arch/mips/idle_event.cc
index a2b3b0c..dd5a4a3 100644
--- a/src/arch/mips/idle_event.cc
+++ b/src/arch/mips/idle_event.cc
@@ -30,6 +30,9 @@
#include "cpu/thread_context.hh"
+namespace gem5
+{
+
using namespace MipsISA;
void
@@ -37,3 +40,5 @@
{
fatal("Idle Start Event Not Defined for MIPS ISA ");
}
+
+} // namespace gem5
diff --git a/src/arch/mips/idle_event.hh b/src/arch/mips/idle_event.hh
index d332b87..442ae3a 100644
--- a/src/arch/mips/idle_event.hh
+++ b/src/arch/mips/idle_event.hh
@@ -31,6 +31,9 @@
#include "cpu/pc_event.hh"
+namespace gem5
+{
+
class IdleStartEvent : public PCEvent
{
public:
@@ -40,4 +43,6 @@
virtual void process(ThreadContext *tc);
};
+} // namespace gem5
+
#endif // __ARCH_MIPS_IDLE_EVENT_HH__
diff --git a/src/arch/mips/interrupts.cc b/src/arch/mips/interrupts.cc
index a489826..960bb0d 100644
--- a/src/arch/mips/interrupts.cc
+++ b/src/arch/mips/interrupts.cc
@@ -34,6 +34,9 @@
#include "cpu/thread_context.hh"
#include "debug/Interrupt.hh"
+namespace gem5
+{
+
namespace MipsISA
{
@@ -183,4 +186,5 @@
}
-}
+} // namespace MipsISA
+} // namespace gem5
diff --git a/src/arch/mips/interrupts.hh b/src/arch/mips/interrupts.hh
index ebfc420..9045312 100644
--- a/src/arch/mips/interrupts.hh
+++ b/src/arch/mips/interrupts.hh
@@ -38,6 +38,9 @@
#include "params/MipsInterrupts.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
class BaseCPU;
class Checkpoint;
@@ -107,7 +110,7 @@
}
};
-}
+} // namespace MipsISA
+} // namespace gem5
#endif
-
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 7494e9d..2a075ec 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -41,6 +41,9 @@
#include "debug/MipsPRA.hh"
#include "params/MipsISA.hh"
+namespace gem5
+{
+
namespace MipsISA
{
@@ -592,4 +595,5 @@
}
}
-}
+} // namespace MipsISA
+} // namespace gem5
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 490008c..915039f 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -41,6 +41,9 @@
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class BaseCPU;
class Checkpoint;
struct MipsISAParams;
@@ -165,6 +168,7 @@
void copyRegsFrom(ThreadContext *src) override;
};
-}
+} // namespace MipsISA
+} // namespace gem5
#endif
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index 8ee2877..6802810 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -64,6 +64,7 @@
#include "mem/packet.hh"
#include "sim/full_system.hh"
+using namespace gem5;
using namespace MipsISA;
}};
@@ -95,6 +96,7 @@
#include "sim/sim_events.hh"
#include "sim/sim_exit.hh"
+using namespace gem5;
using namespace MipsISA;
}};
diff --git a/src/arch/mips/linux/aligned.hh b/src/arch/mips/linux/aligned.hh
index 413b15a..a2dea5d 100644
--- a/src/arch/mips/linux/aligned.hh
+++ b/src/arch/mips/linux/aligned.hh
@@ -34,8 +34,13 @@
#include "base/compiler.hh"
#include "base/types.hh"
+namespace gem5
+{
+
typedef GEM5_ALIGNED(8) uint64_t uint64_ta;
typedef GEM5_ALIGNED(8) int64_t int64_ta;
typedef GEM5_ALIGNED(8) Addr Addr_a;
+} // namespace gem5
+
#endif /* __ARCH_MIPS_LINUX_ALIGNED_HH__ */
diff --git a/src/arch/mips/linux/hwrpb.hh b/src/arch/mips/linux/hwrpb.hh
index 8686d26..b5dcb18 100644
--- a/src/arch/mips/linux/hwrpb.hh
+++ b/src/arch/mips/linux/hwrpb.hh
@@ -27,6 +27,9 @@
#include "arch/mips/linux/aligned.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Linux, linux);
namespace linux
{
@@ -41,5 +44,7 @@
uint64_ta rpb_fen;
uint64_ta res1, res2;
};
-}
+} // namespace linux
+} // namespace gem5
+
#endif // __ARCH_MIPS_LINUX_HWRPB_HH__
diff --git a/src/arch/mips/linux/linux.hh b/src/arch/mips/linux/linux.hh
index 73ccf5e..180f0a8 100644
--- a/src/arch/mips/linux/linux.hh
+++ b/src/arch/mips/linux/linux.hh
@@ -33,6 +33,9 @@
#include "kern/linux/linux.hh"
+namespace gem5
+{
+
class MipsLinux : public Linux
{
public:
@@ -194,4 +197,6 @@
};
+} // namespace gem5
+
#endif
diff --git a/src/arch/mips/linux/se_workload.cc b/src/arch/mips/linux/se_workload.cc
index d0460fc..647c0ca 100644
--- a/src/arch/mips/linux/se_workload.cc
+++ b/src/arch/mips/linux/se_workload.cc
@@ -38,6 +38,9 @@
#include "cpu/thread_context.hh"
#include "sim/syscall_emul.hh"
+namespace gem5
+{
+
namespace
{
@@ -478,3 +481,4 @@
};
} // namespace MipsISA
+} // namespace gem5
diff --git a/src/arch/mips/linux/se_workload.hh b/src/arch/mips/linux/se_workload.hh
index 13e2110..04100d2 100644
--- a/src/arch/mips/linux/se_workload.hh
+++ b/src/arch/mips/linux/se_workload.hh
@@ -34,6 +34,9 @@
#include "params/MipsEmuLinux.hh"
#include "sim/syscall_desc.hh"
+namespace gem5
+{
+
namespace MipsISA
{
@@ -52,5 +55,6 @@
};
} // namespace MipsISA
+} // namespace gem5
#endif // __ARCH_MIPS_LINUX_SE_WORKLOAD_HH__
diff --git a/src/arch/mips/linux/thread_info.hh b/src/arch/mips/linux/thread_info.hh
index cec97f0..df376f0 100644
--- a/src/arch/mips/linux/thread_info.hh
+++ b/src/arch/mips/linux/thread_info.hh
@@ -31,6 +31,9 @@
#include "arch/mips/linux/hwrpb.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Linux, linux);
namespace linux
{
@@ -39,6 +42,7 @@
struct pcb_struct pcb;
Addr_a task;
};
-}
+} // namespace linux
+} // namespace gem5
#endif // __ARCH_MIPS_LINUX_THREAD_INFO_H__
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 42a4ed2..f8e1b29 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -55,6 +55,9 @@
#include "mem/packet.hh"
#include "mem/request.hh"
+namespace gem5
+{
+
namespace MipsISA
{
template <class XC>
@@ -146,5 +149,6 @@
}
} // namespace MipsISA
+} // namespace gem5
#endif
diff --git a/src/arch/mips/mmu.hh b/src/arch/mips/mmu.hh
index 1ac1577..13ea937 100644
--- a/src/arch/mips/mmu.hh
+++ b/src/arch/mips/mmu.hh
@@ -42,6 +42,9 @@
#include "params/MipsMMU.hh"
+namespace gem5
+{
+
namespace MipsISA {
class MMU : public BaseMMU
@@ -53,5 +56,6 @@
};
} // namespace MipsISA
+} // namespace gem5
#endif // __ARCH_MIPS_MMU_HH__
diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh
index ae4ed97..91fcf50 100644
--- a/src/arch/mips/mt.hh
+++ b/src/arch/mips/mt.hh
@@ -46,6 +46,9 @@
#include "base/trace.hh"
#include "cpu/exec_context.hh"
+namespace gem5
+{
+
namespace MipsISA
{
@@ -332,6 +335,6 @@
}
} // namespace MipsISA
-
+} // namespace gem5
#endif
diff --git a/src/arch/mips/mt_constants.hh b/src/arch/mips/mt_constants.hh
index c6244c9..c99af71 100644
--- a/src/arch/mips/mt_constants.hh
+++ b/src/arch/mips/mt_constants.hh
@@ -32,6 +32,9 @@
#include "arch/mips/types.hh"
#include "base/bitunion.hh"
+namespace gem5
+{
+
namespace MipsISA
{
@@ -97,5 +100,6 @@
EndBitUnion(TCHaltReg)
} // namespace MipsISA
+} // namespace gem5
#endif
diff --git a/src/arch/mips/page_size.hh b/src/arch/mips/page_size.hh
index bdb13a6..4d786d8 100644
--- a/src/arch/mips/page_size.hh
+++ b/src/arch/mips/page_size.hh
@@ -32,6 +32,9 @@
#include "base/types.hh"
+namespace gem5
+{
+
namespace MipsISA
{
@@ -39,5 +42,6 @@
const Addr PageBytes = 1ULL << PageShift;
} // namespace MipsISA
+} // namespace gem5
#endif // __ARCH_MIPS_PAGE_SIZE_HH__
diff --git a/src/arch/mips/pagetable.cc b/src/arch/mips/pagetable.cc
index f3a9922..a71b7d5 100644
--- a/src/arch/mips/pagetable.cc
+++ b/src/arch/mips/pagetable.cc
@@ -31,6 +31,9 @@
#include "sim/serialize.hh"
+namespace gem5
+{
+
namespace MipsISA
{
@@ -72,4 +75,5 @@
UNSERIALIZE_SCALAR(OffsetMask);
}
-}
+} // namespace MipsISA
+} // namespace gem5
diff --git a/src/arch/mips/pagetable.hh b/src/arch/mips/pagetable.hh
index 26c8485..24e0e46 100644
--- a/src/arch/mips/pagetable.hh
+++ b/src/arch/mips/pagetable.hh
@@ -34,6 +34,9 @@
#include "base/types.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
namespace MipsISA {
// ITB/DTB page table entry
@@ -104,6 +107,7 @@
};
-};
-#endif // __ARCH_MIPS_PAGETABLE_H__
+} // namespace MipsISA
+} // namespace gem5
+#endif // __ARCH_MIPS_PAGETABLE_H__
diff --git a/src/arch/mips/pcstate.hh b/src/arch/mips/pcstate.hh
index 12334d6..2c58719 100644
--- a/src/arch/mips/pcstate.hh
+++ b/src/arch/mips/pcstate.hh
@@ -31,10 +31,15 @@
#include "arch/generic/types.hh"
+namespace gem5
+{
+
namespace MipsISA
{
typedef GenericISA::DelaySlotPCState<4> PCState;
} // namespace MipsISA
-#endif
+} // namespace gem5
+
+#endif // __ARCH_MIPS_PCSTATE_HH__
diff --git a/src/arch/mips/pra_constants.hh b/src/arch/mips/pra_constants.hh
index ac7f701..67b30b7 100644
--- a/src/arch/mips/pra_constants.hh
+++ b/src/arch/mips/pra_constants.hh
@@ -32,6 +32,9 @@
#include "arch/mips/types.hh"
#include "base/bitunion.hh"
+namespace gem5
+{
+
namespace MipsISA
{
@@ -324,5 +327,6 @@
EndBitUnion(TagLoReg)
} // namespace MipsISA
+} // namespace gem5
#endif
diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc
index c855394..b0fe339 100644
--- a/src/arch/mips/process.cc
+++ b/src/arch/mips/process.cc
@@ -44,6 +44,9 @@
#include "sim/syscall_return.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace MipsISA;
MipsProcess::MipsProcess(const ProcessParams ¶ms,
@@ -203,3 +206,5 @@
tc->pcState(getStartPC());
}
+
+} // namespace gem5
diff --git a/src/arch/mips/process.hh b/src/arch/mips/process.hh
index 5d354e1..181dd25 100644
--- a/src/arch/mips/process.hh
+++ b/src/arch/mips/process.hh
@@ -31,6 +31,9 @@
#include "sim/process.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Loader, loader);
namespace loader
{
@@ -49,4 +52,6 @@
void argsInit(int pageSize);
};
+} // namespace gem5
+
#endif // __MIPS_PROCESS_HH__
diff --git a/src/arch/mips/regs/float.hh b/src/arch/mips/regs/float.hh
index 8a0769f..52472f3 100644
--- a/src/arch/mips/regs/float.hh
+++ b/src/arch/mips/regs/float.hh
@@ -32,6 +32,9 @@
#include <cstdint>
+namespace gem5
+{
+
namespace MipsISA
{
@@ -71,5 +74,6 @@
};
} // namespace MipsISA
+} // namespace gem5
#endif
diff --git a/src/arch/mips/regs/int.hh b/src/arch/mips/regs/int.hh
index 0d0f35d..65f2779 100644
--- a/src/arch/mips/regs/int.hh
+++ b/src/arch/mips/regs/int.hh
@@ -30,6 +30,9 @@
#ifndef __ARCH_MIPS_REGS_INT_HH__
#define __ARCH_MIPS_REGS_INT_HH__
+namespace gem5
+{
+
namespace MipsISA
{
@@ -69,5 +72,6 @@
const int SyscallPseudoReturnReg = 3;
} // namespace MipsISA
+} // namespace gem5
#endif
diff --git a/src/arch/mips/regs/misc.hh b/src/arch/mips/regs/misc.hh
index c3df37e..65635e8 100644
--- a/src/arch/mips/regs/misc.hh
+++ b/src/arch/mips/regs/misc.hh
@@ -30,6 +30,9 @@
#ifndef __ARCH_MIPS_REGS_MISC_HH__
#define __ARCH_MIPS_REGS_MISC_HH__
+namespace gem5
+{
+
namespace MipsISA
{
@@ -192,5 +195,6 @@
};
} // namespace MipsISA
+} // namespace gem5
#endif
diff --git a/src/arch/mips/remote_gdb.cc b/src/arch/mips/remote_gdb.cc
index 6f869fc..6940a67 100644
--- a/src/arch/mips/remote_gdb.cc
+++ b/src/arch/mips/remote_gdb.cc
@@ -146,6 +146,9 @@
#include "mem/page_table.hh"
#include "sim/full_system.hh"
+namespace gem5
+{
+
using namespace MipsISA;
RemoteGDB::RemoteGDB(System *_system, int _port)
@@ -221,3 +224,5 @@
output = it->second;
return true;
}
+
+} // namespace gem5
diff --git a/src/arch/mips/remote_gdb.hh b/src/arch/mips/remote_gdb.hh
index 8fb54f7..6a38956 100644
--- a/src/arch/mips/remote_gdb.hh
+++ b/src/arch/mips/remote_gdb.hh
@@ -34,6 +34,9 @@
#include "base/bitfield.hh"
#include "base/remote_gdb.hh"
+namespace gem5
+{
+
class System;
class ThreadContext;
@@ -88,5 +91,6 @@
};
} // namespace MipsISA
+} // namespace gem5
#endif /* __ARCH_MIPS_REMOTE_GDB_H__ */
diff --git a/src/arch/mips/se_workload.cc b/src/arch/mips/se_workload.cc
index 580eb40..75e1ac1 100644
--- a/src/arch/mips/se_workload.cc
+++ b/src/arch/mips/se_workload.cc
@@ -27,6 +27,9 @@
#include "arch/mips/se_workload.hh"
+namespace gem5
+{
+
namespace MipsISA
{
@@ -35,3 +38,4 @@
};
} // namespace MipsISA
+} // namespace gem5
diff --git a/src/arch/mips/se_workload.hh b/src/arch/mips/se_workload.hh
index 489f1d1..52b620e 100644
--- a/src/arch/mips/se_workload.hh
+++ b/src/arch/mips/se_workload.hh
@@ -35,24 +35,27 @@
#include "sim/syscall_abi.hh"
#include "sim/syscall_desc.hh"
+namespace gem5
+{
+
namespace MipsISA
{
-class SEWorkload : public ::SEWorkload
+class SEWorkload : public gem5::SEWorkload
{
public:
using Params = MipsSEWorkloadParams;
- SEWorkload(const Params &p) : ::SEWorkload(p) {}
+ SEWorkload(const Params &p) : gem5::SEWorkload(p) {}
void
setSystem(System *sys) override
{
- ::SEWorkload::setSystem(sys);
+ gem5::SEWorkload::setSystem(sys);
gdb = BaseRemoteGDB::build<RemoteGDB>(system);
}
- ::loader::Arch getArch() const override { return ::loader::Mips; }
+ loader::Arch getArch() const override { return loader::Mips; }
struct SyscallABI : public GenericSyscallABI64
{
@@ -90,5 +93,6 @@
};
} // namespace guest_abi
+} // namespace gem5
#endif // __ARCH_MIPS_SE_WORKLOAD_HH__
diff --git a/src/arch/mips/stacktrace.hh b/src/arch/mips/stacktrace.hh
index 8612e06..449945f 100644
--- a/src/arch/mips/stacktrace.hh
+++ b/src/arch/mips/stacktrace.hh
@@ -31,6 +31,9 @@
#include "cpu/profile.hh"
+namespace gem5
+{
+
namespace MipsISA
{
@@ -40,6 +43,7 @@
void trace(ThreadContext *tc, bool is_call) override {};
};
-}
+} // namespace MipsISA
+} // namespace gem5
#endif // __ARCH_MIPS_STACKTRACE_HH__
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index 5373ba9..4294529 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -46,6 +46,9 @@
#include "params/MipsTLB.hh"
#include "sim/process.hh"
+namespace gem5
+{
+
using namespace MipsISA;
///////////////////////////////////////////////////////////////////////
@@ -255,3 +258,5 @@
return *pte;
}
+
+} // namespace gem5
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 36c294b..193ed0c 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -40,6 +40,9 @@
#include "params/MipsTLB.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class ThreadContext;
/* MIPS does not distinguish between a DTLB and an ITLB -> unified TLB
@@ -103,8 +106,7 @@
ThreadContext *tc, Mode mode) const override;
};
-}
-
-
+} // namespace MipsISA
+} // namespace gem5
#endif // __MIPS_MEMORY_HH__
diff --git a/src/arch/mips/types.hh b/src/arch/mips/types.hh
index 35c77c3..1091936 100644
--- a/src/arch/mips/types.hh
+++ b/src/arch/mips/types.hh
@@ -33,6 +33,9 @@
#include "arch/mips/pcstate.hh"
+namespace gem5
+{
+
namespace MipsISA
{
@@ -162,4 +165,6 @@
};
} // namespace MipsISA
+} // namespace gem5
+
#endif
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index fe41249..c878980 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -39,6 +39,9 @@
#include "cpu/thread_context.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
using namespace MipsISA;
namespace MipsISA {
@@ -207,3 +210,4 @@
}
} // namespace MipsISA
+} // namespace gem5
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 8d35529..b72b3f4 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -38,6 +38,9 @@
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+namespace gem5
+{
+
class ThreadContext;
namespace MipsISA {
@@ -74,7 +77,7 @@
return (addr + PageBytes - 1) & ~(PageBytes - 1);
}
-};
-
+} // namespace MipsISA
+} // namespace gem5
#endif
diff --git a/src/arch/mips/vecregs.hh b/src/arch/mips/vecregs.hh
index 752f4c0..0c8b86a 100644
--- a/src/arch/mips/vecregs.hh
+++ b/src/arch/mips/vecregs.hh
@@ -33,17 +33,21 @@
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
+namespace gem5
+{
+
namespace MipsISA
{
// Not applicable to MIPS
-using VecElem = ::DummyVecElem;
-using VecRegContainer = ::DummyVecRegContainer;
-constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
+using VecElem = ::gem5::DummyVecElem;
+using VecRegContainer = ::gem5::DummyVecRegContainer;
+constexpr unsigned NumVecElemPerVecReg = ::gem5::DummyNumVecElemPerVecReg;
// Not applicable to MIPS
-using VecPredRegContainer = ::DummyVecPredRegContainer;
+using VecPredRegContainer = ::gem5::DummyVecPredRegContainer;
} // namespace MipsISA
+} // namespace gem5
#endif
diff --git a/src/arch/null/locked_mem.hh b/src/arch/null/locked_mem.hh
index 8af3fdb..db53a70 100644
--- a/src/arch/null/locked_mem.hh
+++ b/src/arch/null/locked_mem.hh
@@ -49,11 +49,15 @@
#include "arch/generic/locked_mem.hh"
+namespace gem5
+{
+
namespace NullISA
{
using namespace GenericISA::locked_mem;
} // namespace NullISA
+} // namespace gem5
#endif
diff --git a/src/arch/null/page_size.hh b/src/arch/null/page_size.hh
index ee6c7c4..79b574e 100644
--- a/src/arch/null/page_size.hh
+++ b/src/arch/null/page_size.hh
@@ -40,10 +40,14 @@
#include "base/types.hh"
+namespace gem5
+{
+
namespace NullISA
{
const Addr PageShift = 12;
const Addr PageBytes = 1ULL << PageShift;
-}
+} // namespace NullISA
+} // namespace gem5
#endif //__ARCH_NULL_PAGE_SIZE_HH__
diff --git a/src/arch/null/pcstate.hh b/src/arch/null/pcstate.hh
index 9a8295e..5b790bb 100644
--- a/src/arch/null/pcstate.hh
+++ b/src/arch/null/pcstate.hh
@@ -40,11 +40,15 @@
#include "arch/generic/types.hh"
+namespace gem5
+{
+
namespace NullISA
{
typedef GenericISA::UPCState<4> PCState;
-}
+} // namespace NullISA
+} // namespace gem5
#endif // __ARCH_NULL_TYPES_HH__
diff --git a/src/arch/null/remote_gdb.hh b/src/arch/null/remote_gdb.hh
index cef2338..db18c69 100644
--- a/src/arch/null/remote_gdb.hh
+++ b/src/arch/null/remote_gdb.hh
@@ -40,6 +40,9 @@
#include "base/types.hh"
+namespace gem5
+{
+
class ThreadContext;
class BaseRemoteGDB
@@ -54,4 +57,6 @@
virtual ~BaseRemoteGDB() {}
};
+} // namespace gem5
+
#endif // __ARCH_NULL_REMOTE_GDB_H__
diff --git a/src/arch/null/utility.hh b/src/arch/null/utility.hh
index 82b9be6..fc02986 100644
--- a/src/arch/null/utility.hh
+++ b/src/arch/null/utility.hh
@@ -41,6 +41,9 @@
#include "base/types.hh"
#include "cpu/thread_context.hh"
+namespace gem5
+{
+
namespace NullISA
{
@@ -50,6 +53,7 @@
return 0;
}
-}
+} // namespace NullISA
+} // namespace gem5
#endif // __ARCH_NULL_UTILITY_HH__
diff --git a/src/arch/null/vecregs.hh b/src/arch/null/vecregs.hh
index 1f4f7ec..dcb2091 100644
--- a/src/arch/null/vecregs.hh
+++ b/src/arch/null/vecregs.hh
@@ -44,17 +44,21 @@
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
+namespace gem5
+{
+
namespace NullISA
{
// Not applicable to null
-using VecElem = ::DummyVecElem;
-using VecRegContainer = ::DummyVecRegContainer;
-constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
+using VecElem = ::gem5::DummyVecElem;
+using VecRegContainer = ::gem5::DummyVecRegContainer;
+constexpr unsigned NumVecElemPerVecReg = ::gem5::DummyNumVecElemPerVecReg;
// Not applicable to null
-using VecPredRegContainer = ::DummyVecPredRegContainer;
+using VecPredRegContainer = ::gem5::DummyVecPredRegContainer;
-}
+} // namespace NullISA
+} // namespace gem5
#endif // __ARCH_NULL_VECREGS_HH__
diff --git a/src/arch/power/PowerISA.py b/src/arch/power/PowerISA.py
index 81abd9c..d6146ca 100644
--- a/src/arch/power/PowerISA.py
+++ b/src/arch/power/PowerISA.py
@@ -37,5 +37,5 @@
class PowerISA(BaseISA):
type = 'PowerISA'
- cxx_class = 'PowerISA::ISA'
+ cxx_class = 'gem5::PowerISA::ISA'
cxx_header = "arch/power/isa.hh"
diff --git a/src/arch/power/PowerInterrupts.py b/src/arch/power/PowerInterrupts.py
index 443e7ae..2ee91e3 100644
--- a/src/arch/power/PowerInterrupts.py
+++ b/src/arch/power/PowerInterrupts.py
@@ -28,5 +28,5 @@
class PowerInterrupts(BaseInterrupts):
type = 'PowerInterrupts'
- cxx_class = 'PowerISA::Interrupts'
+ cxx_class = 'gem5::PowerISA::Interrupts'
cxx_header = 'arch/power/interrupts.hh'
diff --git a/src/arch/power/PowerMMU.py b/src/arch/power/PowerMMU.py
index 1d966bb..db9673d 100644
--- a/src/arch/power/PowerMMU.py
+++ b/src/arch/power/PowerMMU.py
@@ -40,7 +40,7 @@
class PowerMMU(BaseMMU):
type = 'PowerMMU'
- cxx_class = 'PowerISA::MMU'
+ cxx_class = 'gem5::PowerISA::MMU'
cxx_header = 'arch/power/mmu.hh'
itb = PowerTLB()
dtb = PowerTLB()
diff --git a/src/arch/power/PowerSeWorkload.py b/src/arch/power/PowerSeWorkload.py
index 2d3d3cb..ef7bbb5 100644
--- a/src/arch/power/PowerSeWorkload.py
+++ b/src/arch/power/PowerSeWorkload.py
@@ -30,13 +30,13 @@
class PowerSEWorkload(SEWorkload):
type = 'PowerSEWorkload'
cxx_header = "arch/power/se_workload.hh"
- cxx_class = 'PowerISA::SEWorkload'
+ cxx_class = 'gem5::PowerISA::SEWorkload'
abstract = True
class PowerEmuLinux(PowerSEWorkload):
type = 'PowerEmuLinux'
cxx_header = "arch/power/linux/se_workload.hh"
- cxx_class = 'PowerISA::EmuLinux'
+ cxx_class = 'gem5::PowerISA::EmuLinux'
@classmethod
def _is_compatible_with(cls, obj):
diff --git a/src/arch/power/PowerTLB.py b/src/arch/power/PowerTLB.py
index 7f9a271..39f0a44 100644
--- a/src/arch/power/PowerTLB.py
+++ b/src/arch/power/PowerTLB.py
@@ -33,6 +33,6 @@
class PowerTLB(BaseTLB):
type = 'PowerTLB'
- cxx_class = 'PowerISA::TLB'
+ cxx_class = 'gem5::PowerISA::TLB'
cxx_header = 'arch/power/tlb.hh'
size = Param.Int(64, "TLB size")
diff --git a/src/arch/power/decoder.cc b/src/arch/power/decoder.cc
index cc2a2bf..e2a56c1 100644
--- a/src/arch/power/decoder.cc
+++ b/src/arch/power/decoder.cc
@@ -28,9 +28,13 @@
#include "arch/power/decoder.hh"
+namespace gem5
+{
+
namespace PowerISA
{
GenericISA::BasicDecodeCache<Decoder, ExtMachInst> Decoder::defaultCache;
-}
+} // namespace PowerISA
+} // namespace gem5
diff --git a/src/arch/power/decoder.hh b/src/arch/power/decoder.hh
index eb67ed0..4e0c92b 100644
--- a/src/arch/power/decoder.hh
+++ b/src/arch/power/decoder.hh
@@ -35,6 +35,9 @@
#include "cpu/static_inst.hh"
#include "debug/Decode.hh"
+namespace gem5
+{
+
namespace PowerISA
{
@@ -114,5 +117,6 @@
};
} // namespace PowerISA
+} // namespace gem5
#endif // __ARCH_POWER_DECODER_HH__
diff --git a/src/arch/power/faults.hh b/src/arch/power/faults.hh
index 806f958..edfcc8f 100644
--- a/src/arch/power/faults.hh
+++ b/src/arch/power/faults.hh
@@ -32,6 +32,9 @@
#include "sim/faults.hh"
+namespace gem5
+{
+
namespace PowerISA
{
@@ -93,5 +96,6 @@
};
} // namespace PowerISA
+} // namespace gem5
#endif // __ARCH_POWER_FAULTS_HH__
diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc
index cb769cd..ca52d83 100644
--- a/src/arch/power/insts/branch.cc
+++ b/src/arch/power/insts/branch.cc
@@ -31,6 +31,9 @@
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh"
+namespace gem5
+{
+
using namespace PowerISA;
const std::string &
@@ -168,3 +171,5 @@
return ss.str();
}
+
+} // namespace gem5
diff --git a/src/arch/power/insts/branch.hh b/src/arch/power/insts/branch.hh
index e4f63e8..5c5982c 100644
--- a/src/arch/power/insts/branch.hh
+++ b/src/arch/power/insts/branch.hh
@@ -31,6 +31,9 @@
#include "arch/power/insts/static_inst.hh"
+namespace gem5
+{
+
namespace PowerISA
{
@@ -192,5 +195,6 @@
};
} // namespace PowerISA
+} // namespace gem5
#endif //__ARCH_POWER_INSTS_BRANCH_HH__
diff --git a/src/arch/power/insts/condition.cc b/src/arch/power/insts/condition.cc
index 0178473..4cb0df2 100644
--- a/src/arch/power/insts/condition.cc
+++ b/src/arch/power/insts/condition.cc
@@ -28,6 +28,9 @@
#include "arch/power/insts/condition.hh"
+namespace gem5
+{
+
using namespace PowerISA;
std::string
@@ -57,3 +60,5 @@
return ss.str();
}
+
+} // namespace gem5
diff --git a/src/arch/power/insts/condition.hh b/src/arch/power/insts/condition.hh
index deaaa51..a082bdd 100644
--- a/src/arch/power/insts/condition.hh
+++ b/src/arch/power/insts/condition.hh
@@ -32,6 +32,9 @@
#include "arch/power/insts/static_inst.hh"
#include "base/cprintf.hh"
+namespace gem5
+{
+
namespace PowerISA
{
@@ -82,5 +85,6 @@
};
} // namespace PowerISA
+} // namespace gem5
#endif //__ARCH_POWER_INSTS_CONDITION_HH__
diff --git a/src/arch/power/insts/floating.cc b/src/arch/power/insts/floating.cc
index 6a53d3c..83924e6 100644
--- a/src/arch/power/insts/floating.cc
+++ b/src/arch/power/insts/floating.cc
@@ -28,6 +28,9 @@
#include "arch/power/insts/floating.hh"
+namespace gem5
+{
+
using namespace PowerISA;
std::string
@@ -56,3 +59,5 @@
return ss.str();
}
+
+} // namespace gem5
diff --git a/src/arch/power/insts/floating.hh b/src/arch/power/insts/floating.hh
index ef06901..cc50236 100644
--- a/src/arch/power/insts/floating.hh
+++ b/src/arch/power/insts/floating.hh
@@ -33,6 +33,9 @@
#include "base/bitfield.hh"
#include "base/cprintf.hh"
+namespace gem5
+{
+
namespace PowerISA
{
@@ -148,5 +151,6 @@
};
} // namespace PowerISA
+} // namespace gem5
#endif //__ARCH_POWER_INSTS_FLOATING_HH__
diff --git a/src/arch/power/insts/integer.cc b/src/arch/power/insts/integer.cc
index 18a72ab..7798d40 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -28,6 +28,9 @@
#include "arch/power/insts/integer.hh"
+namespace gem5
+{
+
using namespace PowerISA;
std::string
@@ -920,3 +923,5 @@
return ss.str();
}
+
+} // namespace gem5
diff --git a/src/arch/power/insts/integer.hh b/src/arch/power/insts/integer.hh
index 600fdf4..2e34876 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -34,6 +34,9 @@
#include "base/bitfield.hh"
#include "base/cprintf.hh"
+namespace gem5
+{
+
namespace PowerISA
{
@@ -790,5 +793,6 @@
};
} // namespace PowerISA
+} // namespace gem5
#endif //__ARCH_POWER_INSTS_INTEGER_HH__
diff --git a/src/arch/power/insts/mem.cc b/src/arch/power/insts/mem.cc
index a2954f8..7e44fd8 100644
--- a/src/arch/power/insts/mem.cc
+++ b/src/arch/power/insts/mem.cc
@@ -30,6 +30,9 @@
#include "base/loader/symtab.hh"
+namespace gem5
+{
+
using namespace PowerISA;
std::string
@@ -158,7 +161,6 @@
return ss.str();
}
-
std::string
MemIndexOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
@@ -219,3 +221,5 @@
return ss.str();
}
+
+} // namespace gem5
diff --git a/src/arch/power/insts/mem.hh b/src/arch/power/insts/mem.hh
index ddb36bb..6fcfb12 100644
--- a/src/arch/power/insts/mem.hh
+++ b/src/arch/power/insts/mem.hh
@@ -31,6 +31,9 @@
#include "arch/power/insts/static_inst.hh"
+namespace gem5
+{
+
namespace PowerISA
{
@@ -115,5 +118,6 @@
};
} // namespace PowerISA
+} // namespace gem5
#endif //__ARCH_POWER_INSTS_MEM_HH__
diff --git a/src/arch/power/insts/misc.cc b/src/arch/power/insts/misc.cc
index ec3a939..645bb99 100644
--- a/src/arch/power/insts/misc.cc
+++ b/src/arch/power/insts/misc.cc
@@ -28,6 +28,9 @@
#include "arch/power/insts/misc.hh"
+namespace gem5
+{
+
using namespace PowerISA;
std::string
@@ -56,3 +59,5 @@
return ss.str();
}
+
+} // namespace gem5
diff --git a/src/arch/power/insts/misc.hh b/src/arch/power/insts/misc.hh
index 8cf9afc..e1b8fe6 100644
--- a/src/arch/power/insts/misc.hh
+++ b/src/arch/power/insts/misc.hh
@@ -31,6 +31,9 @@
#include "arch/power/insts/static_inst.hh"
+namespace gem5
+{
+
namespace PowerISA
{
@@ -47,5 +50,6 @@
};
} // namespace PowerISA
+} // namespace gem5
#endif //__ARCH_POWER_INSTS_MISC_HH__
diff --git a/src/arch/power/insts/static_inst.cc b/src/arch/power/insts/static_inst.cc
index d10c861..90df775 100644
--- a/src/arch/power/insts/static_inst.cc
+++ b/src/arch/power/insts/static_inst.cc
@@ -31,6 +31,9 @@
#include "cpu/reg_class.hh"
+namespace gem5
+{
+
using namespace PowerISA;
void
@@ -68,3 +71,5 @@
return ss.str();
}
+
+} // namespace gem5
diff --git a/src/arch/power/insts/static_inst.hh b/src/arch/power/insts/static_inst.hh
index 9eb87a1..54ef589 100644
--- a/src/arch/power/insts/static_inst.hh
+++ b/src/arch/power/insts/static_inst.hh
@@ -33,6 +33,9 @@
#include "base/trace.hh"
#include "cpu/static_inst.hh"
+namespace gem5
+{
+
namespace PowerISA
{
@@ -86,5 +89,6 @@
};
} // namespace PowerISA
+} // namespace gem5
#endif //__ARCH_POWER_INSTS_STATICINST_HH__
diff --git a/src/arch/power/interrupts.hh b/src/arch/power/interrupts.hh
index f5d571d..81c82c6 100644
--- a/src/arch/power/interrupts.hh
+++ b/src/arch/power/interrupts.hh
@@ -33,6 +33,9 @@
#include "base/logging.hh"
#include "params/PowerInterrupts.hh"
+namespace gem5
+{
+
class BaseCPU;
class ThreadContext;
@@ -84,6 +87,6 @@
};
} // namespace PowerISA
+} // namespace gem5
#endif // __ARCH_POWER_INTERRUPT_HH__
-
diff --git a/src/arch/power/isa.cc b/src/arch/power/isa.cc
index 56c25bb..086369f 100644
--- a/src/arch/power/isa.cc
+++ b/src/arch/power/isa.cc
@@ -43,6 +43,9 @@
#include "cpu/thread_context.hh"
#include "params/PowerISA.hh"
+namespace gem5
+{
+
namespace PowerISA
{
@@ -75,4 +78,5 @@
tc->pcState(src->pcState());
}
-}
+} // namespace PowerISA
+} // namespace gem5
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index 927cdeb..784f368 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -37,6 +37,9 @@
#include "cpu/reg_class.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
struct PowerISAParams;
class ThreadContext;
class Checkpoint;
@@ -140,5 +143,6 @@
};
} // namespace PowerISA
+} // namespace gem5
#endif // __ARCH_POWER_ISA_HH__
diff --git a/src/arch/power/isa/includes.isa b/src/arch/power/isa/includes.isa
index b50f15d..e9b950b 100644
--- a/src/arch/power/isa/includes.isa
+++ b/src/arch/power/isa/includes.isa
@@ -46,6 +46,7 @@
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
+using namespace gem5;
using namespace PowerISA;
}};
@@ -59,6 +60,7 @@
#include "base/cprintf.hh"
#include "cpu/thread_context.hh"
+using namespace gem5;
using namespace PowerISA;
}};
@@ -76,6 +78,7 @@
#include "mem/packet_access.hh"
#include "sim/sim_exit.hh"
+using namespace gem5;
using namespace PowerISA;
}};
diff --git a/src/arch/power/linux/linux.hh b/src/arch/power/linux/linux.hh
index 5279c67..cdb1cda 100644
--- a/src/arch/power/linux/linux.hh
+++ b/src/arch/power/linux/linux.hh
@@ -34,6 +34,9 @@
#include "kern/linux/linux.hh"
+namespace gem5
+{
+
/*
* This works for a 2.6.15 kernel.
*/
@@ -213,4 +216,6 @@
}
};
+} // namespace gem5
+
#endif // __ARCH_POWER_LINUX_LINUX_HH__
diff --git a/src/arch/power/linux/se_workload.cc b/src/arch/power/linux/se_workload.cc
index c699b62..75eb210 100644
--- a/src/arch/power/linux/se_workload.cc
+++ b/src/arch/power/linux/se_workload.cc
@@ -38,6 +38,9 @@
#include "cpu/thread_context.hh"
#include "sim/syscall_emul.hh"
+namespace gem5
+{
+
namespace
{
@@ -448,3 +451,4 @@
};
} // namespace PowerISA
+} // namespace gem5
diff --git a/src/arch/power/linux/se_workload.hh b/src/arch/power/linux/se_workload.hh
index d8012ff..93d9c1e 100644
--- a/src/arch/power/linux/se_workload.hh
+++ b/src/arch/power/linux/se_workload.hh
@@ -35,6 +35,9 @@
#include "params/PowerEmuLinux.hh"
#include "sim/syscall_desc.hh"
+namespace gem5
+{
+
namespace PowerISA
{
@@ -53,5 +56,6 @@
};
} // namespace PowerISA
+} // namespace gem5
#endif // __ARCH_POWER_LINUX_SE_WORKLOAD_HH__
diff --git a/src/arch/power/locked_mem.hh b/src/arch/power/locked_mem.hh
index 5838490..b225914 100644
--- a/src/arch/power/locked_mem.hh
+++ b/src/arch/power/locked_mem.hh
@@ -39,11 +39,15 @@
#include "arch/generic/locked_mem.hh"
+namespace gem5
+{
+
namespace PowerISA
{
using namespace GenericISA::locked_mem;
} // namespace PowerISA
+} // namespace gem5
#endif // __ARCH_POWER_LOCKED_MEM_HH__
diff --git a/src/arch/power/mmu.hh b/src/arch/power/mmu.hh
index eb04f98..8507e4e 100644
--- a/src/arch/power/mmu.hh
+++ b/src/arch/power/mmu.hh
@@ -42,6 +42,9 @@
#include "params/PowerMMU.hh"
+namespace gem5
+{
+
namespace PowerISA {
class MMU : public BaseMMU
@@ -53,5 +56,6 @@
};
} // namespace PowerISA
+} // namespace gem5
#endif // __ARCH_POWER_MMU_HH__
diff --git a/src/arch/power/page_size.hh b/src/arch/power/page_size.hh
index 690b846..0a4060f 100644
--- a/src/arch/power/page_size.hh
+++ b/src/arch/power/page_size.hh
@@ -33,6 +33,9 @@
#include "base/types.hh"
+namespace gem5
+{
+
namespace PowerISA
{
@@ -40,5 +43,6 @@
const Addr PageBytes = 1ULL << PageShift;
} // namespace PowerISA
+} // namespace gem5
#endif // __ARCH_POWER_PAGE_SIZE_HH__
diff --git a/src/arch/power/pagetable.cc b/src/arch/power/pagetable.cc
index 8e181c0..a0b608c 100644
--- a/src/arch/power/pagetable.cc
+++ b/src/arch/power/pagetable.cc
@@ -33,6 +33,9 @@
#include "sim/serialize.hh"
+namespace gem5
+{
+
namespace PowerISA
{
@@ -75,3 +78,4 @@
}
} // namespace PowerISA
+} // namespace gem5
diff --git a/src/arch/power/pagetable.hh b/src/arch/power/pagetable.hh
index 6f0f40b..ea83216 100644
--- a/src/arch/power/pagetable.hh
+++ b/src/arch/power/pagetable.hh
@@ -35,6 +35,9 @@
#include "base/types.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
namespace PowerISA
{
@@ -84,6 +87,6 @@
};
} // namespace PowerISA
+} // namespace gem5
#endif // __ARCH_POWER_PAGETABLE_H__
-
diff --git a/src/arch/power/pcstate.hh b/src/arch/power/pcstate.hh
index 1d3cd27..9553c73 100644
--- a/src/arch/power/pcstate.hh
+++ b/src/arch/power/pcstate.hh
@@ -31,11 +31,15 @@
#include "arch/generic/types.hh"
+namespace gem5
+{
+
namespace PowerISA
{
typedef GenericISA::SimplePCState<4> PCState;
-}
+} // namespace PowerISA
+} // namespace gem5
#endif // __ARCH_POWER_PCSTATE_HH__
diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc
index 050dff3..a9a28b3 100644
--- a/src/arch/power/process.cc
+++ b/src/arch/power/process.cc
@@ -45,6 +45,9 @@
#include "sim/syscall_return.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace PowerISA;
PowerProcess::PowerProcess(
@@ -278,3 +281,5 @@
//Align the "stack_min" to a page boundary.
memState->setStackMin(roundDown(stack_min, pageSize));
}
+
+} // namespace gem5
diff --git a/src/arch/power/process.hh b/src/arch/power/process.hh
index b603281..210bce2 100644
--- a/src/arch/power/process.hh
+++ b/src/arch/power/process.hh
@@ -32,6 +32,9 @@
#include "sim/process.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Loader, loader);
namespace loader
{
@@ -49,5 +52,6 @@
void argsInit(int intSize, int pageSize);
};
-#endif // __POWER_PROCESS_HH__
+} // namespace gem5
+#endif // __POWER_PROCESS_HH__
diff --git a/src/arch/power/regs/float.hh b/src/arch/power/regs/float.hh
index c6e872d..9464101 100644
--- a/src/arch/power/regs/float.hh
+++ b/src/arch/power/regs/float.hh
@@ -29,6 +29,9 @@
#ifndef __ARCH_POWER_REGS_FLOAT_HH__
#define __ARCH_POWER_REGS_FLOAT_HH__
+namespace gem5
+{
+
namespace PowerISA
{
@@ -36,5 +39,6 @@
const int NumFloatRegs = NumFloatArchRegs;
} // namespace PowerISA
+} // namespace gem5
#endif // __ARCH_POWER_REGS_FLOAT_HH__
diff --git a/src/arch/power/regs/int.hh b/src/arch/power/regs/int.hh
index f66be59..27acb62 100644
--- a/src/arch/power/regs/int.hh
+++ b/src/arch/power/regs/int.hh
@@ -29,6 +29,9 @@
#ifndef __ARCH_POWER_REGS_INT_HH__
#define __ARCH_POWER_REGS_INT_HH__
+namespace gem5
+{
+
namespace PowerISA
{
@@ -65,5 +68,6 @@
};
} // namespace PowerISA
+} // namespace gem5
#endif // __ARCH_POWER_REGS_INT_HH__
diff --git a/src/arch/power/regs/misc.hh b/src/arch/power/regs/misc.hh
index 1665e28..7659180 100644
--- a/src/arch/power/regs/misc.hh
+++ b/src/arch/power/regs/misc.hh
@@ -31,6 +31,9 @@
#include "base/bitunion.hh"
+namespace gem5
+{
+
namespace PowerISA
{
@@ -97,5 +100,6 @@
EndBitUnion(Fpscr)
} // namespace PowerISA
+} // namespace gem5
#endif // __ARCH_POWER_MISCREGS_HH__
diff --git a/src/arch/power/remote_gdb.cc b/src/arch/power/remote_gdb.cc
index 860a233..886a840 100644
--- a/src/arch/power/remote_gdb.cc
+++ b/src/arch/power/remote_gdb.cc
@@ -143,6 +143,9 @@
#include "mem/page_table.hh"
#include "sim/byteswap.hh"
+namespace gem5
+{
+
using namespace PowerISA;
RemoteGDB::RemoteGDB(System *_system, int _port)
@@ -229,3 +232,5 @@
output = it->second;
return true;
}
+
+} // namespace gem5
diff --git a/src/arch/power/remote_gdb.hh b/src/arch/power/remote_gdb.hh
index ab5037e..fa21df5 100644
--- a/src/arch/power/remote_gdb.hh
+++ b/src/arch/power/remote_gdb.hh
@@ -37,6 +37,9 @@
#include "arch/power/remote_gdb.hh"
#include "base/remote_gdb.hh"
+namespace gem5
+{
+
namespace PowerISA
{
@@ -87,5 +90,6 @@
};
} // namespace PowerISA
+} // namespace gem5
#endif /* __ARCH_POWER_REMOTE_GDB_H__ */
diff --git a/src/arch/power/se_workload.cc b/src/arch/power/se_workload.cc
index 40179f1..4177fc0 100644
--- a/src/arch/power/se_workload.cc
+++ b/src/arch/power/se_workload.cc
@@ -27,6 +27,9 @@
#include "arch/power/se_workload.hh"
+namespace gem5
+{
+
namespace PowerISA
{
@@ -40,3 +43,4 @@
};
} // namespace PowerISA
+} // namespace gem5
diff --git a/src/arch/power/se_workload.hh b/src/arch/power/se_workload.hh
index ad7896b..1c9e485 100644
--- a/src/arch/power/se_workload.hh
+++ b/src/arch/power/se_workload.hh
@@ -36,23 +36,26 @@
#include "sim/syscall_abi.hh"
#include "sim/syscall_desc.hh"
+namespace gem5
+{
+
namespace PowerISA
{
-class SEWorkload : public ::SEWorkload
+class SEWorkload : public gem5::SEWorkload
{
public:
using Params = PowerSEWorkloadParams;
- SEWorkload(const Params &p) : ::SEWorkload(p) {}
+ SEWorkload(const Params &p) : gem5::SEWorkload(p) {}
void
setSystem(System *sys) override
{
- ::SEWorkload::setSystem(sys);
+ gem5::SEWorkload::setSystem(sys);
gdb = BaseRemoteGDB::build<RemoteGDB>(system);
}
- ::loader::Arch getArch() const override { return ::loader::Power; }
+ loader::Arch getArch() const override { return loader::Power; }
struct SyscallABI : public GenericSyscallABI64
{
@@ -87,5 +90,6 @@
};
} // namespace guest_abi
+} // namespace gem5
#endif // __ARCH_POWER_SE_WORKLOAD_HH__
diff --git a/src/arch/power/stacktrace.hh b/src/arch/power/stacktrace.hh
index 729daf1..d63f191 100644
--- a/src/arch/power/stacktrace.hh
+++ b/src/arch/power/stacktrace.hh
@@ -34,6 +34,9 @@
#include "base/logging.hh"
#include "cpu/profile.hh"
+namespace gem5
+{
+
namespace PowerISA
{
@@ -48,5 +51,6 @@
};
} // namespace PowerISA
+} // namespace gem5
#endif // __ARCH_POWER_STACKTRACE_HH__
diff --git a/src/arch/power/tlb.cc b/src/arch/power/tlb.cc
index 410b12c..f559d59 100644
--- a/src/arch/power/tlb.cc
+++ b/src/arch/power/tlb.cc
@@ -47,6 +47,9 @@
#include "sim/full_system.hh"
#include "sim/process.hh"
+namespace gem5
+{
+
using namespace PowerISA;
///////////////////////////////////////////////////////////////////////
@@ -276,3 +279,5 @@
return *pte;
}
+
+} // namespace gem5
diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh
index 4cc7c98..5d21fdc 100644
--- a/src/arch/power/tlb.hh
+++ b/src/arch/power/tlb.hh
@@ -40,6 +40,9 @@
#include "mem/request.hh"
#include "params/PowerTLB.hh"
+namespace gem5
+{
+
class ThreadContext;
namespace PowerISA {
@@ -159,5 +162,6 @@
};
} // namespace PowerISA
+} // namespace gem5
#endif // __ARCH_POWER_TLB_HH__
diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh
index c7ff900..1385367 100644
--- a/src/arch/power/types.hh
+++ b/src/arch/power/types.hh
@@ -34,6 +34,9 @@
#include "arch/power/pcstate.hh"
#include "base/bitunion.hh"
+namespace gem5
+{
+
namespace PowerISA
{
@@ -101,18 +104,19 @@
// typedef int RegContextParam;
// typedef int RegContextVal;
-} // PowerISA namespace
+} // namespace PowerISA
+} // namespace gem5
namespace std {
template<>
-struct hash<PowerISA::ExtMachInst> : public hash<uint32_t>
+struct hash<gem5::PowerISA::ExtMachInst> : public hash<uint32_t>
{
- size_t operator()(const PowerISA::ExtMachInst &emi) const {
+ size_t operator()(const gem5::PowerISA::ExtMachInst &emi) const {
return hash<uint32_t>::operator()((uint32_t)emi);
};
};
-}
+} // namespace std
#endif // __ARCH_POWER_TYPES_HH__
diff --git a/src/arch/power/vecregs.hh b/src/arch/power/vecregs.hh
index 974e0ef..a0100af 100644
--- a/src/arch/power/vecregs.hh
+++ b/src/arch/power/vecregs.hh
@@ -34,17 +34,21 @@
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
+namespace gem5
+{
+
namespace PowerISA
{
// Not applicable to Power
-using VecElem = ::DummyVecElem;
-using VecRegContainer = ::DummyVecRegContainer;
-constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
+using VecElem = ::gem5::DummyVecElem;
+using VecRegContainer = ::gem5::DummyVecRegContainer;
+constexpr unsigned NumVecElemPerVecReg = ::gem5::DummyNumVecElemPerVecReg;
// Not applicable to Power
-using VecPredRegContainer = ::DummyVecPredRegContainer;
+using VecPredRegContainer = ::gem5::DummyVecPredRegContainer;
} // namespace PowerISA
+} // namespace gem5
#endif // __ARCH_POWER_VECREGS_HH__
diff --git a/src/arch/riscv/PMAChecker.py b/src/arch/riscv/PMAChecker.py
index 12b1ca3..22424eb 100644
--- a/src/arch/riscv/PMAChecker.py
+++ b/src/arch/riscv/PMAChecker.py
@@ -42,4 +42,6 @@
class PMAChecker(SimObject):
type = 'PMAChecker'
cxx_header = 'arch/riscv/pma_checker.hh'
+ cxx_class = 'gem5::PMAChecker'
+
uncacheable = VectorParam.AddrRange([], "Uncacheable address ranges")
diff --git a/src/arch/riscv/PMP.py b/src/arch/riscv/PMP.py
index 8628bd6..9a86c2f 100644
--- a/src/arch/riscv/PMP.py
+++ b/src/arch/riscv/PMP.py
@@ -31,5 +31,7 @@
class PMP(SimObject):
type = 'PMP'
cxx_header = 'arch/riscv/pmp.hh'
+ cxx_class = 'gem5::PMP'
+
pmp_entries = Param.Int(16, "Maximum PMP Entries Supported")
diff --git a/src/arch/riscv/RiscvFsWorkload.py b/src/arch/riscv/RiscvFsWorkload.py
index 1a2d868..f92945e 100644
--- a/src/arch/riscv/RiscvFsWorkload.py
+++ b/src/arch/riscv/RiscvFsWorkload.py
@@ -34,16 +34,18 @@
class RiscvBareMetal(Workload):
type = 'RiscvBareMetal'
- cxx_class = 'RiscvISA::BareMetal'
+ cxx_class = 'gem5::RiscvISA::BareMetal'
cxx_header = 'arch/riscv/bare_metal/fs_workload.hh'
+
bootloader = Param.String("File, that contains the bootloader code")
bare_metal = Param.Bool(True, "Using Bare Metal Application?")
reset_vect = Param.Addr(0x0, 'Reset vector')
class RiscvLinux(KernelWorkload):
type = 'RiscvLinux'
- cxx_class = 'RiscvISA::FsLinux'
+ cxx_class = 'gem5::RiscvISA::FsLinux'
cxx_header = 'arch/riscv/linux/fs_workload.hh'
+
dtb_filename = Param.String("",
"File that contains the Device Tree Blob. Don't use DTB if empty.")
dtb_addr = Param.Addr(0x87e00000, "DTB address")
diff --git a/src/arch/riscv/RiscvISA.py b/src/arch/riscv/RiscvISA.py
index 3869174..a54dcfd 100644
--- a/src/arch/riscv/RiscvISA.py
+++ b/src/arch/riscv/RiscvISA.py
@@ -42,5 +42,5 @@
class RiscvISA(BaseISA):
type = 'RiscvISA'
- cxx_class = 'RiscvISA::ISA'
+ cxx_class = 'gem5::RiscvISA::ISA'
cxx_header = "arch/riscv/isa.hh"
diff --git a/src/arch/riscv/RiscvInterrupts.py b/src/arch/riscv/RiscvInterrupts.py
index c3ad370..ce0ef01 100644
--- a/src/arch/riscv/RiscvInterrupts.py
+++ b/src/arch/riscv/RiscvInterrupts.py
@@ -31,5 +31,5 @@
class RiscvInterrupts(BaseInterrupts):
type = 'RiscvInterrupts'
- cxx_class = 'RiscvISA::Interrupts'
+ cxx_class = 'gem5::RiscvISA::Interrupts'
cxx_header = 'arch/riscv/interrupts.hh'
diff --git a/src/arch/riscv/RiscvMMU.py b/src/arch/riscv/RiscvMMU.py
index f4fca6e..78fa7f5 100644
--- a/src/arch/riscv/RiscvMMU.py
+++ b/src/arch/riscv/RiscvMMU.py
@@ -44,8 +44,9 @@
class RiscvMMU(BaseMMU):
type = 'RiscvMMU'
- cxx_class = 'RiscvISA::MMU'
+ cxx_class = 'gem5::RiscvISA::MMU'
cxx_header = 'arch/riscv/mmu.hh'
+
itb = RiscvTLB()
dtb = RiscvTLB()
pma_checker = Param.PMAChecker(PMAChecker(), "PMA Checker")
diff --git a/src/arch/riscv/RiscvSeWorkload.py b/src/arch/riscv/RiscvSeWorkload.py
index c4f61bf..f14244f 100644
--- a/src/arch/riscv/RiscvSeWorkload.py
+++ b/src/arch/riscv/RiscvSeWorkload.py
@@ -30,13 +30,13 @@
class RiscvSEWorkload(SEWorkload):
type = 'RiscvSEWorkload'
cxx_header = "arch/riscv/se_workload.hh"
- cxx_class = 'RiscvISA::SEWorkload'
+ cxx_class = 'gem5::RiscvISA::SEWorkload'
abstract = True
class RiscvEmuLinux(RiscvSEWorkload):
type = 'RiscvEmuLinux'
cxx_header = "arch/riscv/linux/se_workload.hh"
- cxx_class = 'RiscvISA::EmuLinux'
+ cxx_class = 'gem5::RiscvISA::EmuLinux'
@classmethod
def _is_compatible_with(cls, obj):
diff --git a/src/arch/riscv/RiscvTLB.py b/src/arch/riscv/RiscvTLB.py
index d66d870..0cbce35 100644
--- a/src/arch/riscv/RiscvTLB.py
+++ b/src/arch/riscv/RiscvTLB.py
@@ -36,8 +36,9 @@
class RiscvPagetableWalker(ClockedObject):
type = 'RiscvPagetableWalker'
- cxx_class = 'RiscvISA::Walker'
+ cxx_class = 'gem5::RiscvISA::Walker'
cxx_header = 'arch/riscv/pagetable_walker.hh'
+
port = RequestPort("Port for the hardware table walker")
system = Param.System(Parent.any, "system object")
num_squash_per_cycle = Param.Unsigned(4,
@@ -48,8 +49,9 @@
class RiscvTLB(BaseTLB):
type = 'RiscvTLB'
- cxx_class = 'RiscvISA::TLB'
+ cxx_class = 'gem5::RiscvISA::TLB'
cxx_header = 'arch/riscv/tlb.hh'
+
size = Param.Int(64, "TLB size")
walker = Param.RiscvPagetableWalker(\
RiscvPagetableWalker(), "page table walker")
diff --git a/src/arch/riscv/bare_metal/fs_workload.cc b/src/arch/riscv/bare_metal/fs_workload.cc
index b9fb3a3..83f5411 100644
--- a/src/arch/riscv/bare_metal/fs_workload.cc
+++ b/src/arch/riscv/bare_metal/fs_workload.cc
@@ -34,6 +34,9 @@
#include "sim/system.hh"
#include "sim/workload.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -71,3 +74,4 @@
}
} // namespace RiscvISA
+} // namespace gem5
diff --git a/src/arch/riscv/bare_metal/fs_workload.hh b/src/arch/riscv/bare_metal/fs_workload.hh
index 0bcda8f..875910a 100644
--- a/src/arch/riscv/bare_metal/fs_workload.hh
+++ b/src/arch/riscv/bare_metal/fs_workload.hh
@@ -33,6 +33,9 @@
#include "params/RiscvBareMetal.hh"
#include "sim/workload.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -84,5 +87,6 @@
};
} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_BARE_METAL_FS_WORKLOAD_HH__
diff --git a/src/arch/riscv/decoder.cc b/src/arch/riscv/decoder.cc
index 8f128b0..ac7e228 100644
--- a/src/arch/riscv/decoder.cc
+++ b/src/arch/riscv/decoder.cc
@@ -32,6 +32,9 @@
#include "base/bitfield.hh"
#include "debug/Decode.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -109,4 +112,5 @@
return decode(emi, nextPC.instAddr());
}
-}
+} // namespace RiscvISA
+} // namespace gem5
diff --git a/src/arch/riscv/decoder.hh b/src/arch/riscv/decoder.hh
index 932c4f2..8f5083b 100644
--- a/src/arch/riscv/decoder.hh
+++ b/src/arch/riscv/decoder.hh
@@ -38,6 +38,9 @@
#include "cpu/static_inst.hh"
#include "debug/Decode.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -83,5 +86,6 @@
};
} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_DECODER_HH__
diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index ef3f3b7..b7fb509 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -42,6 +42,9 @@
#include "sim/full_system.hh"
#include "sim/workload.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -205,3 +208,4 @@
}
} // namespace RiscvISA
+} // namespace gem5
diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index c185f8b..38c5638 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -38,6 +38,9 @@
#include "cpu/null_static_inst.hh"
#include "sim/faults.hh"
+namespace gem5
+{
+
class ThreadContext;
namespace RiscvISA
@@ -250,5 +253,6 @@
};
} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_FAULTS_HH__
diff --git a/src/arch/riscv/idle_event.cc b/src/arch/riscv/idle_event.cc
index 88256b9..f361f44 100644
--- a/src/arch/riscv/idle_event.cc
+++ b/src/arch/riscv/idle_event.cc
@@ -30,6 +30,9 @@
#include "cpu/thread_context.hh"
+namespace gem5
+{
+
using namespace RiscvISA;
void
@@ -37,3 +40,5 @@
{
fatal("Idle Start Event Not Defined for RISCV ISA ");
}
+
+} // namespace gem5
diff --git a/src/arch/riscv/idle_event.hh b/src/arch/riscv/idle_event.hh
index ba1e542..c0e5e9a 100644
--- a/src/arch/riscv/idle_event.hh
+++ b/src/arch/riscv/idle_event.hh
@@ -31,6 +31,9 @@
#include "cpu/pc_event.hh"
+namespace gem5
+{
+
class IdleStartEvent : public PCEvent
{
public:
@@ -40,4 +43,6 @@
virtual void process(ThreadContext *tc);
};
+} // namespace gem5
+
#endif // __KERN_RISCV_IDLE_EVENT_HH__
diff --git a/src/arch/riscv/insts/amo.cc b/src/arch/riscv/insts/amo.cc
index 55521fb..45a703a 100644
--- a/src/arch/riscv/insts/amo.cc
+++ b/src/arch/riscv/insts/amo.cc
@@ -37,6 +37,9 @@
#include "cpu/exec_context.hh"
#include "cpu/static_inst.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -144,4 +147,5 @@
return ss.str();
}
-}
+} // namespace RiscvISA
+} // namespace gem5
diff --git a/src/arch/riscv/insts/amo.hh b/src/arch/riscv/insts/amo.hh
index d032735..9c73c1f 100644
--- a/src/arch/riscv/insts/amo.hh
+++ b/src/arch/riscv/insts/amo.hh
@@ -36,6 +36,9 @@
#include "arch/riscv/insts/static_inst.hh"
#include "cpu/static_inst.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -131,6 +134,7 @@
std::function<void(T*,T)> op;
};
-}
+} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_INSTS_AMO_HH__
diff --git a/src/arch/riscv/insts/compressed.cc b/src/arch/riscv/insts/compressed.cc
index 2468382..eb04f1f 100644
--- a/src/arch/riscv/insts/compressed.cc
+++ b/src/arch/riscv/insts/compressed.cc
@@ -35,6 +35,9 @@
#include "arch/riscv/utility.hh"
#include "cpu/static_inst.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -48,4 +51,5 @@
return ss.str();
}
-}
+} // namespace RiscvISA
+} // namespace gem5
diff --git a/src/arch/riscv/insts/compressed.hh b/src/arch/riscv/insts/compressed.hh
index 01a612e..aabe6df 100644
--- a/src/arch/riscv/insts/compressed.hh
+++ b/src/arch/riscv/insts/compressed.hh
@@ -35,6 +35,9 @@
#include "arch/riscv/insts/static_inst.hh"
#include "cpu/static_inst.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -50,6 +53,7 @@
Addr pc, const loader::SymbolTable *symtab) const override;
};
-}
+} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_INSTS_COMPRESSED_HH__
diff --git a/src/arch/riscv/insts/mem.cc b/src/arch/riscv/insts/mem.cc
index a4336c9..36d6985 100644
--- a/src/arch/riscv/insts/mem.cc
+++ b/src/arch/riscv/insts/mem.cc
@@ -37,6 +37,9 @@
#include "arch/riscv/utility.hh"
#include "cpu/static_inst.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -58,4 +61,5 @@
return ss.str();
}
-}
+} // namespace RiscvISA
+} // namespace gem5
diff --git a/src/arch/riscv/insts/mem.hh b/src/arch/riscv/insts/mem.hh
index 0d8733e..8e95c6b 100644
--- a/src/arch/riscv/insts/mem.hh
+++ b/src/arch/riscv/insts/mem.hh
@@ -36,6 +36,9 @@
#include "cpu/exec_context.hh"
#include "cpu/static_inst.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -68,6 +71,7 @@
Addr pc, const loader::SymbolTable *symtab) const override;
};
-}
+} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_INST_MEM_HH__
diff --git a/src/arch/riscv/insts/pseudo.hh b/src/arch/riscv/insts/pseudo.hh
index 56962f0..5be53e3 100644
--- a/src/arch/riscv/insts/pseudo.hh
+++ b/src/arch/riscv/insts/pseudo.hh
@@ -33,6 +33,9 @@
#include "arch/riscv/insts/static_inst.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -48,6 +51,7 @@
}
};
-}
+} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_INSTS_PSEUDO_HH__
diff --git a/src/arch/riscv/insts/standard.cc b/src/arch/riscv/insts/standard.cc
index 43f6bc7..14e8fe2 100644
--- a/src/arch/riscv/insts/standard.cc
+++ b/src/arch/riscv/insts/standard.cc
@@ -38,6 +38,9 @@
#include "arch/riscv/utility.hh"
#include "cpu/static_inst.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -84,4 +87,5 @@
return mnemonic;
}
-}
+} // namespace RiscvISA
+} // namespace gem5
diff --git a/src/arch/riscv/insts/standard.hh b/src/arch/riscv/insts/standard.hh
index 5b6728a..93e6a4f 100644
--- a/src/arch/riscv/insts/standard.hh
+++ b/src/arch/riscv/insts/standard.hh
@@ -39,6 +39,9 @@
#include "cpu/exec_context.hh"
#include "cpu/static_inst.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -122,6 +125,7 @@
Addr pc, const loader::SymbolTable *symtab) const override;
};
-}
+} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_STANDARD_INST_HH__
diff --git a/src/arch/riscv/insts/static_inst.cc b/src/arch/riscv/insts/static_inst.cc
index b10fe70..de40f67 100644
--- a/src/arch/riscv/insts/static_inst.cc
+++ b/src/arch/riscv/insts/static_inst.cc
@@ -32,6 +32,9 @@
#include "arch/riscv/types.hh"
#include "cpu/static_inst.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -46,3 +49,4 @@
}
} // namespace RiscvISA
+} // namespace gem5
diff --git a/src/arch/riscv/insts/static_inst.hh b/src/arch/riscv/insts/static_inst.hh
index 1c9c616..867f9a4 100644
--- a/src/arch/riscv/insts/static_inst.hh
+++ b/src/arch/riscv/insts/static_inst.hh
@@ -37,6 +37,9 @@
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -131,6 +134,7 @@
void advancePC(PCState &pcState) const override;
};
-}
+} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_STATIC_INST_HH__
diff --git a/src/arch/riscv/insts/unknown.hh b/src/arch/riscv/insts/unknown.hh
index 9c851ce..30cec98 100644
--- a/src/arch/riscv/insts/unknown.hh
+++ b/src/arch/riscv/insts/unknown.hh
@@ -39,6 +39,9 @@
#include "cpu/exec_context.hh"
#include "cpu/static_inst.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -68,6 +71,7 @@
}
};
-}
+} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_UNKNOWN_INST_HH__
diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh
index 41906cc..dcd88b1 100644
--- a/src/arch/riscv/interrupts.hh
+++ b/src/arch/riscv/interrupts.hh
@@ -41,6 +41,9 @@
#include "params/RiscvInterrupts.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class BaseCPU;
class ThreadContext;
@@ -174,5 +177,6 @@
};
} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_INTERRUPT_HH__
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 2ac3e9f..162d956 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -50,6 +50,9 @@
#include "sim/core.hh"
#include "sim/pseudo_inst.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -482,4 +485,5 @@
UNSERIALIZE_CONTAINER(miscRegFile);
}
-}
+} // namespace RiscvISA
+} // namespace gem5
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index ec852cf..3597310 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -40,6 +40,9 @@
#include "arch/riscv/types.hh"
#include "base/types.hh"
+namespace gem5
+{
+
struct RiscvISAParams;
class Checkpoint;
@@ -98,5 +101,6 @@
};
} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_ISA_HH__
diff --git a/src/arch/riscv/isa/includes.isa b/src/arch/riscv/isa/includes.isa
index 2f97f15..6ffa277 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -74,6 +74,7 @@
#include "mem/request.hh"
#include "sim/full_system.hh"
+using namespace gem5;
using namespace RiscvISA;
}};
@@ -105,5 +106,6 @@
#include "sim/sim_exit.hh"
#include "sim/system.hh"
+using namespace gem5;
using namespace RiscvISA;
}};
diff --git a/src/arch/riscv/linux/fs_workload.cc b/src/arch/riscv/linux/fs_workload.cc
index e6b1b9b..2e92245 100644
--- a/src/arch/riscv/linux/fs_workload.cc
+++ b/src/arch/riscv/linux/fs_workload.cc
@@ -35,6 +35,9 @@
#include "sim/kernel_workload.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -73,3 +76,4 @@
}
} // namespace RiscvISA
+} // namespace gem5
diff --git a/src/arch/riscv/linux/fs_workload.hh b/src/arch/riscv/linux/fs_workload.hh
index d891349..f85ec16 100644
--- a/src/arch/riscv/linux/fs_workload.hh
+++ b/src/arch/riscv/linux/fs_workload.hh
@@ -33,6 +33,9 @@
#include "params/RiscvLinux.hh"
#include "sim/kernel_workload.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -53,5 +56,6 @@
};
} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_LINUX_FS_WORKLOAD_HH__
diff --git a/src/arch/riscv/linux/linux.hh b/src/arch/riscv/linux/linux.hh
index 801dd8f..0e38df3 100644
--- a/src/arch/riscv/linux/linux.hh
+++ b/src/arch/riscv/linux/linux.hh
@@ -34,6 +34,9 @@
#include "arch/riscv/utility.hh"
#include "kern/linux/linux.hh"
+namespace gem5
+{
+
class RiscvLinux : public Linux
{
public:
@@ -380,4 +383,6 @@
}
};
+} // namespace gem5
+
#endif
diff --git a/src/arch/riscv/linux/se_workload.cc b/src/arch/riscv/linux/se_workload.cc
index 09f4758..18627a7 100644
--- a/src/arch/riscv/linux/se_workload.cc
+++ b/src/arch/riscv/linux/se_workload.cc
@@ -38,6 +38,9 @@
#include "cpu/thread_context.hh"
#include "sim/syscall_emul.hh"
+namespace gem5
+{
+
namespace
{
@@ -783,3 +786,4 @@
};
} // namespace RiscvISA
+} // namespace gem5
diff --git a/src/arch/riscv/linux/se_workload.hh b/src/arch/riscv/linux/se_workload.hh
index 862d33a..6d722ef 100644
--- a/src/arch/riscv/linux/se_workload.hh
+++ b/src/arch/riscv/linux/se_workload.hh
@@ -35,6 +35,9 @@
#include "params/RiscvEmuLinux.hh"
#include "sim/syscall_desc.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -57,5 +60,6 @@
};
} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_LINUX_SE_WORKLOAD_HH__
diff --git a/src/arch/riscv/locked_mem.cc b/src/arch/riscv/locked_mem.cc
index 957cffb..1c57534 100644
--- a/src/arch/riscv/locked_mem.cc
+++ b/src/arch/riscv/locked_mem.cc
@@ -4,7 +4,11 @@
#include "base/types.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
std::unordered_map<int, std::stack<Addr>> locked_addrs;
-}
+} // namespace RiscvISA
+} // namespace gem5
diff --git a/src/arch/riscv/locked_mem.hh b/src/arch/riscv/locked_mem.hh
index 44f2e3a..53f7137 100644
--- a/src/arch/riscv/locked_mem.hh
+++ b/src/arch/riscv/locked_mem.hh
@@ -56,6 +56,9 @@
#include "mem/packet.hh"
#include "mem/request.hh"
+namespace gem5
+{
+
/*
* ISA-specific helper functions for locked memory accesses.
*/
@@ -139,5 +142,6 @@
}
} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_LOCKED_MEM_HH__
diff --git a/src/arch/riscv/mmu.hh b/src/arch/riscv/mmu.hh
index 3e58829..52b0380 100644
--- a/src/arch/riscv/mmu.hh
+++ b/src/arch/riscv/mmu.hh
@@ -45,6 +45,9 @@
#include "params/RiscvMMU.hh"
+namespace gem5
+{
+
namespace RiscvISA {
class MMU : public BaseMMU
@@ -85,5 +88,6 @@
};
} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_MMU_HH__
diff --git a/src/arch/riscv/page_size.hh b/src/arch/riscv/page_size.hh
index e0ba3a4..e5ea527 100644
--- a/src/arch/riscv/page_size.hh
+++ b/src/arch/riscv/page_size.hh
@@ -44,12 +44,16 @@
#include "base/types.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
const Addr PageShift = 12;
const Addr PageBytes = 1ULL << PageShift;
-}
+} // namespace RiscvISA
+} // namespace gem5
#endif //__ARCH_RISCV_PAGE_SIZE_HH__
diff --git a/src/arch/riscv/pagetable.cc b/src/arch/riscv/pagetable.cc
index 38776c3..b2901e9 100644
--- a/src/arch/riscv/pagetable.cc
+++ b/src/arch/riscv/pagetable.cc
@@ -32,6 +32,9 @@
#include "sim/serialize.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -57,4 +60,5 @@
UNSERIALIZE_SCALAR(lruSeq);
}
-}
+} // namespace RiscvISA
+} // namespace gem5
diff --git a/src/arch/riscv/pagetable.hh b/src/arch/riscv/pagetable.hh
index d3c123e..06a054f 100644
--- a/src/arch/riscv/pagetable.hh
+++ b/src/arch/riscv/pagetable.hh
@@ -37,6 +37,9 @@
#include "base/types.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
namespace RiscvISA {
BitUnion64(SATP)
@@ -109,6 +112,7 @@
void unserialize(CheckpointIn &cp) override;
};
-};
-#endif // __ARCH_RISCV_PAGETABLE_H__
+} // namespace RiscvISA
+} // namespace gem5
+#endif // __ARCH_RISCV_PAGETABLE_H__
diff --git a/src/arch/riscv/pagetable_walker.cc b/src/arch/riscv/pagetable_walker.cc
index 0a0c719..e6a5766 100644
--- a/src/arch/riscv/pagetable_walker.cc
+++ b/src/arch/riscv/pagetable_walker.cc
@@ -63,6 +63,9 @@
#include "mem/packet_access.hh"
#include "mem/request.hh"
+namespace gem5
+{
+
namespace RiscvISA {
Fault
@@ -610,4 +613,5 @@
return walker->tlb->createPagefault(entry.vaddr, mode);
}
-} /* end namespace RiscvISA */
+} // namespace RiscvISA
+} // namespace gem5
diff --git a/src/arch/riscv/pagetable_walker.hh b/src/arch/riscv/pagetable_walker.hh
index 7ef18a8..8db9b80 100644
--- a/src/arch/riscv/pagetable_walker.hh
+++ b/src/arch/riscv/pagetable_walker.hh
@@ -52,6 +52,9 @@
#include "sim/faults.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
class ThreadContext;
namespace RiscvISA
@@ -209,6 +212,8 @@
{
}
};
-}
+
+} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_PAGE_TABLE_WALKER_HH__
diff --git a/src/arch/riscv/pcstate.hh b/src/arch/riscv/pcstate.hh
index 720f291..bc60a07 100644
--- a/src/arch/riscv/pcstate.hh
+++ b/src/arch/riscv/pcstate.hh
@@ -44,6 +44,9 @@
#include "arch/generic/types.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -74,6 +77,7 @@
}
};
-}
+} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_PCSTATE_HH__
diff --git a/src/arch/riscv/pma_checker.cc b/src/arch/riscv/pma_checker.cc
index 15c5cf9..a64b387 100644
--- a/src/arch/riscv/pma_checker.cc
+++ b/src/arch/riscv/pma_checker.cc
@@ -44,6 +44,9 @@
#include "params/PMAChecker.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
PMAChecker::PMAChecker(const Params ¶ms) :
SimObject(params),
uncacheable(params.uncacheable.begin(), params.uncacheable.end())
@@ -87,3 +90,5 @@
{
uncacheable = old->uncacheable;
}
+
+} // namespace gem5
diff --git a/src/arch/riscv/pma_checker.hh b/src/arch/riscv/pma_checker.hh
index 298d4a0..08e8051 100644
--- a/src/arch/riscv/pma_checker.hh
+++ b/src/arch/riscv/pma_checker.hh
@@ -44,6 +44,9 @@
#include "params/PMAChecker.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
/**
* Based on the RISC-V ISA privileged specifications
* V1.11, there is no implementation guidelines on the
@@ -78,4 +81,6 @@
void takeOverFrom(PMAChecker *old);
};
+} // namespace gem5
+
#endif // __ARCH_RISCV_PMA_CHECKER_HH__
diff --git a/src/arch/riscv/pmp.cc b/src/arch/riscv/pmp.cc
index af93a14..bc8ded0 100644
--- a/src/arch/riscv/pmp.cc
+++ b/src/arch/riscv/pmp.cc
@@ -41,6 +41,9 @@
#include "params/PMP.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
PMP::PMP(const Params ¶ms) :
SimObject(params),
pmpEntries(params.pmp_entries),
@@ -264,3 +267,5 @@
return this_range;
}
}
+
+} // namespace gem5
diff --git a/src/arch/riscv/pmp.hh b/src/arch/riscv/pmp.hh
index aceed05..33d4976 100644
--- a/src/arch/riscv/pmp.hh
+++ b/src/arch/riscv/pmp.hh
@@ -42,6 +42,9 @@
* PMP header file.
*/
+namespace gem5
+{
+
/**
* This class helps to implement RISCV's physical memory
* protection (pmp) primitive.
@@ -188,4 +191,6 @@
};
+} // namespace gem5
+
#endif // __ARCH_RISCV_PMP_HH__
diff --git a/src/arch/riscv/pra_constants.hh b/src/arch/riscv/pra_constants.hh
index ab61498..5285256 100644
--- a/src/arch/riscv/pra_constants.hh
+++ b/src/arch/riscv/pra_constants.hh
@@ -32,6 +32,9 @@
#include "arch/riscv/types.hh"
#include "base/bitunion.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -324,5 +327,6 @@
EndBitUnion(TagLoReg)
} // namespace RiscvISA
+} // namespace gem5
#endif
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index fd014cd..ce34e3b 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -55,6 +55,9 @@
#include "sim/syscall_return.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace RiscvISA;
RiscvProcess::RiscvProcess(const ProcessParams ¶ms,
@@ -246,3 +249,5 @@
memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
}
+
+} // namespace gem5
diff --git a/src/arch/riscv/process.hh b/src/arch/riscv/process.hh
index 25299ae..ca0a050 100644
--- a/src/arch/riscv/process.hh
+++ b/src/arch/riscv/process.hh
@@ -37,6 +37,9 @@
#include "sim/process.hh"
#include "sim/syscall_abi.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Loader, loader);
namespace loader
{
@@ -74,4 +77,6 @@
void initState() override;
};
+} // namespace gem5
+
#endif // __RISCV_PROCESS_HH__
diff --git a/src/arch/riscv/reg_abi.cc b/src/arch/riscv/reg_abi.cc
index 25aee6f..977bdff 100644
--- a/src/arch/riscv/reg_abi.cc
+++ b/src/arch/riscv/reg_abi.cc
@@ -27,9 +27,13 @@
#include "arch/riscv/reg_abi.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
const std::vector<int> RegABI64::ArgumentRegs = {10, 11, 12, 13, 14, 15, 16};
} // namespace RiscvISA
+} // namespace gem5
diff --git a/src/arch/riscv/reg_abi.hh b/src/arch/riscv/reg_abi.hh
index 492c117..91881e9 100644
--- a/src/arch/riscv/reg_abi.hh
+++ b/src/arch/riscv/reg_abi.hh
@@ -32,6 +32,9 @@
#include "sim/syscall_abi.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -42,5 +45,6 @@
};
} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_REG_ABI_HH__
diff --git a/src/arch/riscv/regs/float.hh b/src/arch/riscv/regs/float.hh
index 2d5d654..37b94e2 100644
--- a/src/arch/riscv/regs/float.hh
+++ b/src/arch/riscv/regs/float.hh
@@ -55,6 +55,9 @@
#include "base/bitfield.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -100,6 +103,7 @@
"ft8", "ft9", "ft10", "ft11"
};
-}
+} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_REGS_FLOAT_HH__
diff --git a/src/arch/riscv/regs/int.hh b/src/arch/riscv/regs/int.hh
index 5ed6ba9..ef8f141 100644
--- a/src/arch/riscv/regs/int.hh
+++ b/src/arch/riscv/regs/int.hh
@@ -49,6 +49,9 @@
#include <string>
#include <vector>
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -77,6 +80,7 @@
"t3", "t4", "t5", "t6"
};
-}
+} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_REGS_INT_HH__
diff --git a/src/arch/riscv/regs/misc.hh b/src/arch/riscv/regs/misc.hh
index da72fae..5bfcbe1 100644
--- a/src/arch/riscv/regs/misc.hh
+++ b/src/arch/riscv/regs/misc.hh
@@ -54,6 +54,9 @@
#include "base/bitunion.hh"
#include "base/types.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -657,6 +660,7 @@
{CSR_MIP, MI_MASK}
};
-}
+} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_REGS_MISC_HH__
diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc
index b8549e2..db581b5 100644
--- a/src/arch/riscv/remote_gdb.cc
+++ b/src/arch/riscv/remote_gdb.cc
@@ -150,6 +150,9 @@
#include "mem/page_table.hh"
#include "sim/full_system.hh"
+namespace gem5
+{
+
using namespace RiscvISA;
RemoteGDB::RemoteGDB(System *_system, int _port)
@@ -488,3 +491,5 @@
{
return ®Cache;
}
+
+} // namespace gem5
diff --git a/src/arch/riscv/remote_gdb.hh b/src/arch/riscv/remote_gdb.hh
index 565a773..40fe821 100644
--- a/src/arch/riscv/remote_gdb.hh
+++ b/src/arch/riscv/remote_gdb.hh
@@ -39,6 +39,9 @@
#include "arch/riscv/regs/int.hh"
#include "base/remote_gdb.hh"
+namespace gem5
+{
+
class System;
class ThreadContext;
@@ -161,5 +164,6 @@
};
} // namespace RiscvISA
+} // namespace gem5
#endif /* __ARCH_RISCV_REMOTE_GDB_H__ */
diff --git a/src/arch/riscv/se_workload.hh b/src/arch/riscv/se_workload.hh
index 5bca1bc..5152c58 100644
--- a/src/arch/riscv/se_workload.hh
+++ b/src/arch/riscv/se_workload.hh
@@ -35,24 +35,27 @@
#include "sim/se_workload.hh"
#include "sim/syscall_abi.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
-class SEWorkload : public ::SEWorkload
+class SEWorkload : public gem5::SEWorkload
{
public:
using Params = RiscvSEWorkloadParams;
- SEWorkload(const Params &p) : ::SEWorkload(p) {}
+ SEWorkload(const Params &p) : gem5::SEWorkload(p) {}
void
setSystem(System *sys) override
{
- ::SEWorkload::setSystem(sys);
+ gem5::SEWorkload::setSystem(sys);
gdb = BaseRemoteGDB::build<RemoteGDB>(system);
}
- ::loader::Arch getArch() const override { return ::loader::Riscv64; }
+ loader::Arch getArch() const override { return loader::Riscv64; }
//FIXME RISCV needs to handle 64 bit arguments in its 32 bit ISA.
using SyscallABI = RegABI64;
@@ -84,5 +87,6 @@
};
} // namespace guest_abi
+} // namespace gem5
#endif // __ARCH_RISCV_SE_WORKLOAD_HH__
diff --git a/src/arch/riscv/stacktrace.hh b/src/arch/riscv/stacktrace.hh
index 34a608b..d59085b 100644
--- a/src/arch/riscv/stacktrace.hh
+++ b/src/arch/riscv/stacktrace.hh
@@ -34,6 +34,9 @@
#include "base/logging.hh"
#include "cpu/profile.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -48,5 +51,6 @@
};
} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_STACKTRACE_HH__
diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index 1ec848e..d7d441e 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -54,6 +54,9 @@
#include "sim/process.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace RiscvISA;
///////////////////////////////////////////////////////////////////////
@@ -532,3 +535,5 @@
{
return &walker->getPort("port");
}
+
+} // namespace gem5
diff --git a/src/arch/riscv/tlb.hh b/src/arch/riscv/tlb.hh
index 365465a..b8a3631 100644
--- a/src/arch/riscv/tlb.hh
+++ b/src/arch/riscv/tlb.hh
@@ -45,6 +45,9 @@
#include "params/RiscvTLB.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class ThreadContext;
/* To maintain compatibility with other architectures, we'll
@@ -147,6 +150,7 @@
Translation *translation, Mode mode, bool &delayed);
};
-}
+} // namespace RiscvISA
+} // namespace gem5
#endif // __RISCV_MEMORY_HH__
diff --git a/src/arch/riscv/types.hh b/src/arch/riscv/types.hh
index 146d234..f06fe3e 100644
--- a/src/arch/riscv/types.hh
+++ b/src/arch/riscv/types.hh
@@ -44,12 +44,16 @@
#include "arch/riscv/pcstate.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
typedef uint32_t MachInst;
typedef uint64_t ExtMachInst;
-}
+} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_TYPES_HH__
diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh
index bae341e..d1355fc 100644
--- a/src/arch/riscv/utility.hh
+++ b/src/arch/riscv/utility.hh
@@ -56,6 +56,9 @@
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
@@ -129,5 +132,6 @@
}
} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_UTILITY_HH__
diff --git a/src/arch/riscv/vecregs.hh b/src/arch/riscv/vecregs.hh
index f809520..51fd244 100644
--- a/src/arch/riscv/vecregs.hh
+++ b/src/arch/riscv/vecregs.hh
@@ -51,17 +51,21 @@
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
+namespace gem5
+{
+
namespace RiscvISA
{
// Not applicable to RISC-V
-using VecElem = ::DummyVecElem;
-using VecRegContainer = ::DummyVecRegContainer;
-constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
+using VecElem = ::gem5::DummyVecElem;
+using VecRegContainer = ::gem5::DummyVecRegContainer;
+constexpr unsigned NumVecElemPerVecReg = ::gem5::DummyNumVecElemPerVecReg;
// Not applicable to RISC-V
-using VecPredRegContainer = ::DummyVecPredRegContainer;
+using VecPredRegContainer = ::gem5::DummyVecPredRegContainer;
-}
+} // namespace RiscvISA
+} // namespace gem5
#endif // __ARCH_RISCV_VECREGS_HH__
diff --git a/src/arch/sparc/SparcFsWorkload.py b/src/arch/sparc/SparcFsWorkload.py
index ffc3f2b..0d6bb54 100644
--- a/src/arch/sparc/SparcFsWorkload.py
+++ b/src/arch/sparc/SparcFsWorkload.py
@@ -31,4 +31,4 @@
class SparcFsWorkload(Workload):
type = 'SparcFsWorkload'
cxx_header = 'arch/sparc/fs_workload.hh'
- cxx_class = 'SparcISA::FsWorkload'
+ cxx_class = 'gem5::SparcISA::FsWorkload'
diff --git a/src/arch/sparc/SparcISA.py b/src/arch/sparc/SparcISA.py
index 235fdcc..88ea301 100644
--- a/src/arch/sparc/SparcISA.py
+++ b/src/arch/sparc/SparcISA.py
@@ -37,5 +37,5 @@
class SparcISA(BaseISA):
type = 'SparcISA'
- cxx_class = 'SparcISA::ISA'
+ cxx_class = 'gem5::SparcISA::ISA'
cxx_header = "arch/sparc/isa.hh"
diff --git a/src/arch/sparc/SparcInterrupts.py b/src/arch/sparc/SparcInterrupts.py
index 4bacfe0..00d6f84 100644
--- a/src/arch/sparc/SparcInterrupts.py
+++ b/src/arch/sparc/SparcInterrupts.py
@@ -28,5 +28,5 @@
class SparcInterrupts(BaseInterrupts):
type = 'SparcInterrupts'
- cxx_class = 'SparcISA::Interrupts'
+ cxx_class = 'gem5::SparcISA::Interrupts'
cxx_header = 'arch/sparc/interrupts.hh'
diff --git a/src/arch/sparc/SparcMMU.py b/src/arch/sparc/SparcMMU.py
index 16f98f8..72aea5f 100644
--- a/src/arch/sparc/SparcMMU.py
+++ b/src/arch/sparc/SparcMMU.py
@@ -42,7 +42,7 @@
class SparcMMU(BaseMMU):
type = 'SparcMMU'
- cxx_class = 'SparcISA::MMU'
+ cxx_class = 'gem5::SparcISA::MMU'
cxx_header = 'arch/sparc/mmu.hh'
itb = SparcTLB()
dtb = SparcTLB()
diff --git a/src/arch/sparc/SparcNativeTrace.py b/src/arch/sparc/SparcNativeTrace.py
index c2a6414..6437763 100644
--- a/src/arch/sparc/SparcNativeTrace.py
+++ b/src/arch/sparc/SparcNativeTrace.py
@@ -31,5 +31,5 @@
class SparcNativeTrace(NativeTrace):
type = 'SparcNativeTrace'
- cxx_class = 'Trace::SparcNativeTrace'
+ cxx_class = 'gem5::Trace::SparcNativeTrace'
cxx_header = 'arch/sparc/nativetrace.hh'
diff --git a/src/arch/sparc/SparcSeWorkload.py b/src/arch/sparc/SparcSeWorkload.py
index 75327ed..700d0b8 100644
--- a/src/arch/sparc/SparcSeWorkload.py
+++ b/src/arch/sparc/SparcSeWorkload.py
@@ -30,13 +30,13 @@
class SparcSEWorkload(SEWorkload):
type = 'SparcSEWorkload'
cxx_header = "arch/sparc/se_workload.hh"
- cxx_class = 'SparcISA::SEWorkload'
+ cxx_class = 'gem5::SparcISA::SEWorkload'
abstract = True
class SparcEmuLinux(SparcSEWorkload):
type = 'SparcEmuLinux'
cxx_header = "arch/sparc/linux/se_workload.hh"
- cxx_class = 'SparcISA::EmuLinux'
+ cxx_class = 'gem5::SparcISA::EmuLinux'
@classmethod
def _is_compatible_with(cls, obj):
diff --git a/src/arch/sparc/SparcTLB.py b/src/arch/sparc/SparcTLB.py
index 6878bef..87a74f0 100644
--- a/src/arch/sparc/SparcTLB.py
+++ b/src/arch/sparc/SparcTLB.py
@@ -31,6 +31,6 @@
class SparcTLB(BaseTLB):
type = 'SparcTLB'
- cxx_class = 'SparcISA::TLB'
+ cxx_class = 'gem5::SparcISA::TLB'
cxx_header = 'arch/sparc/tlb.hh'
size = Param.Int(64, "TLB size")
diff --git a/src/arch/sparc/asi.cc b/src/arch/sparc/asi.cc
index 699484c..ffdb8e4 100644
--- a/src/arch/sparc/asi.cc
+++ b/src/arch/sparc/asi.cc
@@ -28,6 +28,9 @@
#include "arch/sparc/asi.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -312,4 +315,5 @@
asi == ASI_SPARC_ERROR_STATUS_REG;
}
-}
+} // namespace SparcISA
+} // namespace gem5
diff --git a/src/arch/sparc/asi.hh b/src/arch/sparc/asi.hh
index 3afa172..4ebc163 100644
--- a/src/arch/sparc/asi.hh
+++ b/src/arch/sparc/asi.hh
@@ -29,6 +29,9 @@
#ifndef __ARCH_SPARC_ASI_HH__
#define __ARCH_SPARC_ASI_HH__
+namespace gem5
+{
+
namespace SparcISA
{
@@ -272,4 +275,6 @@
bool asiIsSparcError(ASI);
};
+} // namespace gem5
+
#endif // __ARCH_SPARC_ASI_HH__
diff --git a/src/arch/sparc/decoder.cc b/src/arch/sparc/decoder.cc
index 6df388c..4025041 100644
--- a/src/arch/sparc/decoder.cc
+++ b/src/arch/sparc/decoder.cc
@@ -28,9 +28,13 @@
#include "arch/sparc/decoder.hh"
+namespace gem5
+{
+
namespace SparcISA
{
GenericISA::BasicDecodeCache<Decoder, ExtMachInst> Decoder::defaultCache;
-}
+} // namespace SparcISA
+} // namespace gem5
diff --git a/src/arch/sparc/decoder.hh b/src/arch/sparc/decoder.hh
index 7a3669b..72fe5df 100644
--- a/src/arch/sparc/decoder.hh
+++ b/src/arch/sparc/decoder.hh
@@ -35,6 +35,9 @@
#include "cpu/static_inst.hh"
#include "debug/Decode.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -131,5 +134,6 @@
};
} // namespace SparcISA
+} // namespace gem5
#endif // __ARCH_SPARC_DECODER_HH__
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index d65ac6a..047acb2 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -44,6 +44,9 @@
#include "sim/full_system.hh"
#include "sim/process.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -828,4 +831,4 @@
}
} // namespace SparcISA
-
+} // namespace gem5
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index 814475f..df09dc4 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -35,6 +35,9 @@
// The design of the "name" and "vect" functions is in sim/faults.hh
+namespace gem5
+{
+
namespace SparcISA
{
@@ -361,5 +364,6 @@
RegVal TL);
} // namespace SparcISA
+} // namespace gem5
#endif // __SPARC_FAULTS_HH__
diff --git a/src/arch/sparc/fs_workload.cc b/src/arch/sparc/fs_workload.cc
index 813e728..7d7a407 100644
--- a/src/arch/sparc/fs_workload.cc
+++ b/src/arch/sparc/fs_workload.cc
@@ -32,6 +32,9 @@
#include "params/SparcFsWorkload.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -50,3 +53,4 @@
}
} // namespace SparcISA
+} // namespace gem5
diff --git a/src/arch/sparc/fs_workload.hh b/src/arch/sparc/fs_workload.hh
index e3c3f5b..06f02cf 100644
--- a/src/arch/sparc/fs_workload.hh
+++ b/src/arch/sparc/fs_workload.hh
@@ -34,6 +34,9 @@
#include "params/SparcFsWorkload.hh"
#include "sim/workload.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -76,5 +79,6 @@
};
} // namespace SparcISA
+} // namespace gem5
#endif // __ARCH_SPARC_FS_WORKLOAD_HH__
diff --git a/src/arch/sparc/handlers.hh b/src/arch/sparc/handlers.hh
index 2086f9c..04990b4 100644
--- a/src/arch/sparc/handlers.hh
+++ b/src/arch/sparc/handlers.hh
@@ -32,6 +32,9 @@
#include "arch/sparc/types.hh"
#include "sim/byteswap.hh"
+namespace gem5
+{
+
namespace SparcISA {
// We only use 19 instructions for the trap handlers, but there would be
@@ -184,4 +187,6 @@
};
} // namespace SparcISA
+} // namespace gem5
+
#endif // __ARCH_SPARC_HANDLERS_HH__
diff --git a/src/arch/sparc/insts/blockmem.cc b/src/arch/sparc/insts/blockmem.cc
index 6b1d8ee..3206cce 100644
--- a/src/arch/sparc/insts/blockmem.cc
+++ b/src/arch/sparc/insts/blockmem.cc
@@ -28,6 +28,9 @@
#include "arch/sparc/insts/blockmem.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -84,4 +87,5 @@
return response.str();
}
-}
+} // namespace SparcISA
+} // namespace gem5
diff --git a/src/arch/sparc/insts/blockmem.hh b/src/arch/sparc/insts/blockmem.hh
index 5f7a883..5ae5558 100644
--- a/src/arch/sparc/insts/blockmem.hh
+++ b/src/arch/sparc/insts/blockmem.hh
@@ -31,6 +31,9 @@
#include "arch/sparc/insts/micro.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -84,6 +87,7 @@
const int32_t imm;
};
-}
+} // namespace SparcISA
+} // namespace gem5
#endif // __ARCH_SPARC_INSTS_BLOCKMEM_HH__
diff --git a/src/arch/sparc/insts/branch.cc b/src/arch/sparc/insts/branch.cc
index f3fae55..84861cc 100644
--- a/src/arch/sparc/insts/branch.cc
+++ b/src/arch/sparc/insts/branch.cc
@@ -33,6 +33,9 @@
// Branch instructions
//
+namespace gem5
+{
+
namespace SparcISA
{
@@ -95,4 +98,5 @@
return response.str();
}
-}
+} // namespace SparcISA
+} // namespace gem5
diff --git a/src/arch/sparc/insts/branch.hh b/src/arch/sparc/insts/branch.hh
index 68a1220..0b777f7 100644
--- a/src/arch/sparc/insts/branch.hh
+++ b/src/arch/sparc/insts/branch.hh
@@ -31,6 +31,9 @@
#include "arch/sparc/insts/static_inst.hh"
+namespace gem5
+{
+
////////////////////////////////////////////////////////////////////
//
// Branch instructions
@@ -113,6 +116,7 @@
int32_t imm;
};
-}
+} // namespace SparcISA
+} // namespace gem5
#endif // __ARCH_SPARC_INSTS_BRANCH_HH__
diff --git a/src/arch/sparc/insts/integer.cc b/src/arch/sparc/insts/integer.cc
index 8ed0d89..cff8eca 100644
--- a/src/arch/sparc/insts/integer.cc
+++ b/src/arch/sparc/insts/integer.cc
@@ -28,6 +28,9 @@
#include "arch/sparc/insts/integer.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -119,4 +122,5 @@
return response.str();
}
-}
+} // namespace SparcISA
+} // namespace gem5
diff --git a/src/arch/sparc/insts/integer.hh b/src/arch/sparc/insts/integer.hh
index ae3f629..b558113 100644
--- a/src/arch/sparc/insts/integer.hh
+++ b/src/arch/sparc/insts/integer.hh
@@ -31,6 +31,9 @@
#include "arch/sparc/insts/static_inst.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -124,6 +127,7 @@
Addr pc, const loader::SymbolTable *symtab) const override;
};
-}
+} // namespace SparcISA
+} // namespace gem5
#endif // __ARCH_SPARCH_INSTS_INTEGER_HH__
diff --git a/src/arch/sparc/insts/mem.cc b/src/arch/sparc/insts/mem.cc
index 60cfc59..7fba721 100644
--- a/src/arch/sparc/insts/mem.cc
+++ b/src/arch/sparc/insts/mem.cc
@@ -28,6 +28,9 @@
#include "arch/sparc/insts/mem.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -87,4 +90,5 @@
return response.str();
}
-}
+} // namespace SparcISA
+} // namespace gem5
diff --git a/src/arch/sparc/insts/mem.hh b/src/arch/sparc/insts/mem.hh
index 53c664c..0c3aacb 100644
--- a/src/arch/sparc/insts/mem.hh
+++ b/src/arch/sparc/insts/mem.hh
@@ -31,6 +31,9 @@
#include "arch/sparc/insts/static_inst.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -69,6 +72,7 @@
const int32_t imm;
};
-}
+} // namespace SparcISA
+} // namespace gem5
#endif // __ARCH_SPARC_INSTS_MEM_HH__
diff --git a/src/arch/sparc/insts/micro.cc b/src/arch/sparc/insts/micro.cc
index 2652a90..c9bf601 100644
--- a/src/arch/sparc/insts/micro.cc
+++ b/src/arch/sparc/insts/micro.cc
@@ -28,6 +28,9 @@
#include "arch/sparc/insts/micro.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -40,4 +43,5 @@
return response.str();
}
-}
+} // namespace SparcISA
+} // namespace gem5
diff --git a/src/arch/sparc/insts/micro.hh b/src/arch/sparc/insts/micro.hh
index 33d0f87..2d89189 100644
--- a/src/arch/sparc/insts/micro.hh
+++ b/src/arch/sparc/insts/micro.hh
@@ -31,6 +31,9 @@
#include "arch/sparc/insts/static_inst.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -119,6 +122,7 @@
}
};
-}
+} // namespace SparcISA
+} // namespace gem5
#endif // __ARCH_SPARC_INSTS_MICRO_HH__
diff --git a/src/arch/sparc/insts/nop.hh b/src/arch/sparc/insts/nop.hh
index d9feb98..0aad703 100644
--- a/src/arch/sparc/insts/nop.hh
+++ b/src/arch/sparc/insts/nop.hh
@@ -31,6 +31,9 @@
#include "arch/sparc/insts/static_inst.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -68,6 +71,7 @@
}
};
-}
+} // namespace SparcISA
+} // namespace gem5
#endif // __ARCH_SPARC_INSTS_NOP_HH__
diff --git a/src/arch/sparc/insts/priv.cc b/src/arch/sparc/insts/priv.cc
index 015b74b..2bfb7dc 100644
--- a/src/arch/sparc/insts/priv.cc
+++ b/src/arch/sparc/insts/priv.cc
@@ -29,6 +29,9 @@
#include "arch/sparc/insts/priv.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -95,4 +98,5 @@
return response.str();
}
-}
+} // namespace SparcISA
+} // namespace gem5
diff --git a/src/arch/sparc/insts/priv.hh b/src/arch/sparc/insts/priv.hh
index a152dda..5e35e89 100644
--- a/src/arch/sparc/insts/priv.hh
+++ b/src/arch/sparc/insts/priv.hh
@@ -32,6 +32,9 @@
#include "arch/sparc/insts/static_inst.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -108,6 +111,7 @@
char const *regName;
};
-}
+} // namespace SparcISA
+} // namespace gem5
#endif //__ARCH_SPARC_INSTS_PRIV_HH__
diff --git a/src/arch/sparc/insts/static_inst.cc b/src/arch/sparc/insts/static_inst.cc
index 2fdb79f..2b35783 100644
--- a/src/arch/sparc/insts/static_inst.cc
+++ b/src/arch/sparc/insts/static_inst.cc
@@ -33,6 +33,9 @@
#include "arch/sparc/regs/misc.hh"
#include "base/bitunion.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -372,4 +375,5 @@
"condition code %d", condition);
}
-}
+} // namespace SparcISA
+} // namespace gem5
diff --git a/src/arch/sparc/insts/static_inst.hh b/src/arch/sparc/insts/static_inst.hh
index 51b0305..5b67b80 100644
--- a/src/arch/sparc/insts/static_inst.hh
+++ b/src/arch/sparc/insts/static_inst.hh
@@ -37,6 +37,9 @@
#include "cpu/exec_context.hh"
#include "cpu/static_inst.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -128,6 +131,7 @@
}
};
-}
+} // namespace SparcISA
+} // namespace gem5
#endif //__ARCH_SPARC_INSTS_STATIC_INST_HH__
diff --git a/src/arch/sparc/insts/trap.cc b/src/arch/sparc/insts/trap.cc
index caa3c75..7e7c0b7 100644
--- a/src/arch/sparc/insts/trap.cc
+++ b/src/arch/sparc/insts/trap.cc
@@ -28,6 +28,9 @@
#include "arch/sparc/insts/trap.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -45,4 +48,5 @@
return response.str();
}
-}
+} // namespace SparcISA
+} // namespace gem5
diff --git a/src/arch/sparc/insts/trap.hh b/src/arch/sparc/insts/trap.hh
index b38ea0e..fbe2dc1 100644
--- a/src/arch/sparc/insts/trap.hh
+++ b/src/arch/sparc/insts/trap.hh
@@ -36,6 +36,9 @@
#include "arch/sparc/insts/static_inst.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -72,6 +75,7 @@
}
};
-}
+} // namespace SparcISA
+} // namespace gem5
#endif // __ARCH_SPARC_INSTS_TRAP_HH__
diff --git a/src/arch/sparc/insts/unimp.hh b/src/arch/sparc/insts/unimp.hh
index 6b1e9a4..e8694d9 100644
--- a/src/arch/sparc/insts/unimp.hh
+++ b/src/arch/sparc/insts/unimp.hh
@@ -35,6 +35,9 @@
#include "arch/sparc/insts/static_inst.hh"
#include "base/cprintf.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -114,6 +117,7 @@
}
};
-}
+} // namespace SparcISA
+} // namespace gem5
#endif // __ARCH_SPARC_INSTS_UNIMP_HH__
diff --git a/src/arch/sparc/insts/unknown.hh b/src/arch/sparc/insts/unknown.hh
index da2b3ee..813acf1 100644
--- a/src/arch/sparc/insts/unknown.hh
+++ b/src/arch/sparc/insts/unknown.hh
@@ -31,6 +31,9 @@
#include "arch/sparc/insts/static_inst.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -61,6 +64,7 @@
};
-}
+} // namespace SparcISA
+} // namespace gem5
#endif // __ARCH_SPARC_INSTS_UNKNOWN_HH__
diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh
index 76885b5..b544b3b 100644
--- a/src/arch/sparc/interrupts.hh
+++ b/src/arch/sparc/interrupts.hh
@@ -37,6 +37,9 @@
#include "params/SparcInterrupts.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -251,6 +254,8 @@
UNSERIALIZE_SCALAR(intStatus);
}
};
-} // namespace SPARC_ISA
+
+} // namespace SparcISA
+} // namespace gem5
#endif // __ARCH_SPARC_INTERRUPT_HH__
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index 8d0e873..ed43abd 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -43,6 +43,9 @@
#include "debug/Timer.hh"
#include "params/SparcISA.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -940,4 +943,5 @@
}
}
-}
+} // namespace SparcISA
+} // namespace gem5
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 3c2202a..4d2b15c 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -40,6 +40,9 @@
#include "cpu/reg_class.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class Checkpoint;
class EventManager;
struct SparcISAParams;
@@ -238,6 +241,8 @@
ISA(const Params &p);
};
-}
+
+} // namespace SparcISA
+} // namespace gem5
#endif
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index 1dade27..c561056 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -66,6 +66,7 @@
#include "cpu/thread_context.hh" // for Jump::branchTarget()
#include "mem/packet.hh"
+using namespace gem5;
using namespace SparcISA;
}};
@@ -86,6 +87,7 @@
#include "sim/pseudo_inst.hh"
#include "sim/sim_exit.hh"
+using namespace gem5;
using namespace SparcISA;
}};
diff --git a/src/arch/sparc/linux/linux.hh b/src/arch/sparc/linux/linux.hh
index 184226c..134a8e5 100644
--- a/src/arch/sparc/linux/linux.hh
+++ b/src/arch/sparc/linux/linux.hh
@@ -37,6 +37,9 @@
#include "cpu/thread_context.hh"
#include "kern/linux/linux.hh"
+namespace gem5
+{
+
class SparcLinux : public Linux
{
public:
@@ -289,4 +292,6 @@
static const unsigned TGT_RLIMIT_NOFILE = 6;
};
+} // namespace gem5
+
#endif
diff --git a/src/arch/sparc/linux/se_workload.cc b/src/arch/sparc/linux/se_workload.cc
index 57961c9..64386f4 100644
--- a/src/arch/sparc/linux/se_workload.cc
+++ b/src/arch/sparc/linux/se_workload.cc
@@ -36,6 +36,9 @@
#include "cpu/thread_context.hh"
#include "sim/syscall_desc.hh"
+namespace gem5
+{
+
namespace
{
@@ -137,3 +140,4 @@
}
} // namespace SparcISA
+} // namespace gem5
diff --git a/src/arch/sparc/linux/se_workload.hh b/src/arch/sparc/linux/se_workload.hh
index 8c0401d..01ab9b7 100644
--- a/src/arch/sparc/linux/se_workload.hh
+++ b/src/arch/sparc/linux/se_workload.hh
@@ -34,6 +34,9 @@
#include "params/SparcEmuLinux.hh"
#include "sim/syscall_desc.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -61,5 +64,6 @@
};
} // namespace SparcISA
+} // namespace gem5
#endif // __ARCH_SPARC_LINUX_SE_WORKLOAD_HH__
diff --git a/src/arch/sparc/linux/syscalls.cc b/src/arch/sparc/linux/syscalls.cc
index 17cc705..d00580f 100644
--- a/src/arch/sparc/linux/syscalls.cc
+++ b/src/arch/sparc/linux/syscalls.cc
@@ -30,6 +30,9 @@
#include "sim/syscall_desc.hh"
#include "sim/syscall_emul.hh"
+namespace gem5
+{
+
class Process;
class ThreadContext;
@@ -670,3 +673,4 @@
};
} // namespace SparcISA
+} // namespace gem5
diff --git a/src/arch/sparc/locked_mem.hh b/src/arch/sparc/locked_mem.hh
index eaa6bb9..de19d61 100644
--- a/src/arch/sparc/locked_mem.hh
+++ b/src/arch/sparc/locked_mem.hh
@@ -37,11 +37,15 @@
#include "arch/generic/locked_mem.hh"
+namespace gem5
+{
+
namespace SparcISA
{
using namespace GenericISA::locked_mem;
} // namespace SparcISA
+} // namespace gem5
#endif
diff --git a/src/arch/sparc/mmu.hh b/src/arch/sparc/mmu.hh
index f784015..c9bb539 100644
--- a/src/arch/sparc/mmu.hh
+++ b/src/arch/sparc/mmu.hh
@@ -43,6 +43,9 @@
#include "params/SparcMMU.hh"
+namespace gem5
+{
+
namespace SparcISA {
class MMU : public BaseMMU
@@ -70,5 +73,6 @@
};
} // namespace SparcISA
+} // namespace gem5
#endif // __ARCH_SPARC_MMU_HH__
diff --git a/src/arch/sparc/nativetrace.cc b/src/arch/sparc/nativetrace.cc
index da279ef..752e316 100644
--- a/src/arch/sparc/nativetrace.cc
+++ b/src/arch/sparc/nativetrace.cc
@@ -33,6 +33,9 @@
#include "params/SparcNativeTrace.hh"
#include "sim/byteswap.hh"
+namespace gem5
+{
+
namespace Trace {
static const char *intRegNames[SparcISA::NumIntArchRegs] = {
@@ -86,3 +89,4 @@
}
} // namespace Trace
+} // namespace gem5
diff --git a/src/arch/sparc/nativetrace.hh b/src/arch/sparc/nativetrace.hh
index 26e5dfa..3a9d178 100644
--- a/src/arch/sparc/nativetrace.hh
+++ b/src/arch/sparc/nativetrace.hh
@@ -32,6 +32,9 @@
#include "base/types.hh"
#include "cpu/nativetrace.hh"
+namespace gem5
+{
+
class ThreadContext;
namespace Trace {
@@ -46,5 +49,6 @@
};
} // namespace Trace
+} // namespace gem5
#endif // __CPU_NATIVETRACE_HH__
diff --git a/src/arch/sparc/page_size.hh b/src/arch/sparc/page_size.hh
index e3c9b68..a0946db 100644
--- a/src/arch/sparc/page_size.hh
+++ b/src/arch/sparc/page_size.hh
@@ -31,12 +31,16 @@
#include "base/types.hh"
+namespace gem5
+{
+
namespace SparcISA
{
const Addr PageShift = 13;
const Addr PageBytes = 1ULL << PageShift;
-}
+} // namespace SparcISA
+} // namespace gem5
#endif // __ARCH_SPARC_PAGE_SIZE_HH__
diff --git a/src/arch/sparc/pagetable.cc b/src/arch/sparc/pagetable.cc
index fe42c09..0f9a10b 100644
--- a/src/arch/sparc/pagetable.cc
+++ b/src/arch/sparc/pagetable.cc
@@ -30,6 +30,9 @@
#include "sim/serialize.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -72,3 +75,5 @@
}
+
+} // namespace gem5
diff --git a/src/arch/sparc/pagetable.hh b/src/arch/sparc/pagetable.hh
index 6af2e27..2d2ca2e 100644
--- a/src/arch/sparc/pagetable.hh
+++ b/src/arch/sparc/pagetable.hh
@@ -36,6 +36,9 @@
#include "base/types.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -276,6 +279,6 @@
};
} // namespace SparcISA
+} // namespace gem5
#endif // __ARCH_SPARC_PAGE_TABLE_HH__
-
diff --git a/src/arch/sparc/pcstate.hh b/src/arch/sparc/pcstate.hh
index fea9339..4431b38 100644
--- a/src/arch/sparc/pcstate.hh
+++ b/src/arch/sparc/pcstate.hh
@@ -31,11 +31,15 @@
#include "arch/generic/types.hh"
+namespace gem5
+{
+
namespace SparcISA
{
typedef GenericISA::DelaySlotUPCState<4> PCState;
-}
+} // namespace SparcISA
+} // namespace gem5
-#endif
+#endif // __ARCH_SPARC_PCSTATE_HH__
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index e28fb19..e774b95 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -47,6 +47,9 @@
#include "sim/syscall_return.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace SparcISA;
SparcProcess::SparcProcess(const ProcessParams ¶ms,
@@ -387,3 +390,5 @@
initVirtMem->writeBlob(spillStart,
spillHandler32, sizeof(MachInst) * numSpillInsts);
}
+
+} // namespace gem5
diff --git a/src/arch/sparc/process.hh b/src/arch/sparc/process.hh
index 84519ff..70dccb4 100644
--- a/src/arch/sparc/process.hh
+++ b/src/arch/sparc/process.hh
@@ -38,6 +38,9 @@
#include "mem/page_table.hh"
#include "sim/process.hh"
+namespace gem5
+{
+
class SparcProcess : public Process
{
protected:
@@ -131,4 +134,6 @@
void argsInit(int intSize, int pageSize);
};
+} // namespace gem5
+
#endif // __SPARC_PROCESS_HH__
diff --git a/src/arch/sparc/pseudo_inst_abi.hh b/src/arch/sparc/pseudo_inst_abi.hh
index 2bcbef2..12e4ca1 100644
--- a/src/arch/sparc/pseudo_inst_abi.hh
+++ b/src/arch/sparc/pseudo_inst_abi.hh
@@ -32,6 +32,9 @@
#include "cpu/thread_context.hh"
#include "sim/guest_abi.hh"
+namespace gem5
+{
+
struct SparcPseudoInstABI
{
using State = int;
@@ -66,5 +69,6 @@
};
} // namespace guest_abi
+} // namespace gem5
#endif // __ARCH_SPARC_PSEUDO_INST_ABI_HH__
diff --git a/src/arch/sparc/regs/float.hh b/src/arch/sparc/regs/float.hh
index 7cae8cd..3588090 100644
--- a/src/arch/sparc/regs/float.hh
+++ b/src/arch/sparc/regs/float.hh
@@ -29,6 +29,9 @@
#ifndef __ARCH_SPARC_REGS_FLOAT_HH__
#define __ARCH_SPARC_REGS_FLOAT_HH__
+namespace gem5
+{
+
namespace SparcISA
{
@@ -36,5 +39,6 @@
const int NumFloatArchRegs = NumFloatRegs;
} // namespace SparcISA
+} // namespace gem5
#endif
diff --git a/src/arch/sparc/regs/int.hh b/src/arch/sparc/regs/int.hh
index d5c82ae..06048fc 100644
--- a/src/arch/sparc/regs/int.hh
+++ b/src/arch/sparc/regs/int.hh
@@ -31,6 +31,9 @@
#include "arch/sparc/sparc_traits.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -76,5 +79,6 @@
const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
} // namespace SparcISA
+} // namespace gem5
#endif
diff --git a/src/arch/sparc/regs/misc.hh b/src/arch/sparc/regs/misc.hh
index 5c9706f..1620c60 100644
--- a/src/arch/sparc/regs/misc.hh
+++ b/src/arch/sparc/regs/misc.hh
@@ -32,6 +32,9 @@
#include "base/bitunion.hh"
#include "base/types.hh"
+namespace gem5
+{
+
namespace SparcISA
{
enum MiscRegIndex
@@ -169,6 +172,7 @@
const int NumMiscRegs = MISCREG_NUMMISCREGS;
-}
+} // namespace SparcISA
+} // namespace gem5
#endif
diff --git a/src/arch/sparc/remote_gdb.cc b/src/arch/sparc/remote_gdb.cc
index f59a418..83ef55b 100644
--- a/src/arch/sparc/remote_gdb.cc
+++ b/src/arch/sparc/remote_gdb.cc
@@ -143,6 +143,9 @@
#include "sim/process.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace SparcISA;
RemoteGDB::RemoteGDB(System *_system, int _port)
@@ -247,3 +250,5 @@
return ®Cache64;
}
}
+
+} // namespace gem5
diff --git a/src/arch/sparc/remote_gdb.hh b/src/arch/sparc/remote_gdb.hh
index d6abf32..7129ecd 100644
--- a/src/arch/sparc/remote_gdb.hh
+++ b/src/arch/sparc/remote_gdb.hh
@@ -34,6 +34,9 @@
#include "base/remote_gdb.hh"
+namespace gem5
+{
+
class System;
class ThreadContext;
@@ -109,5 +112,6 @@
BaseGdbRegCache *gdbRegs();
};
} // namespace SparcISA
+} // namespace gem5
#endif /* __ARCH_SPARC_REMOTE_GDB_H__ */
diff --git a/src/arch/sparc/se_workload.cc b/src/arch/sparc/se_workload.cc
index b651b05..88bbaf0 100644
--- a/src/arch/sparc/se_workload.cc
+++ b/src/arch/sparc/se_workload.cc
@@ -34,6 +34,9 @@
#include "base/logging.hh"
#include "cpu/thread_context.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -136,3 +139,4 @@
}
} // namespace SparcISA
+} // namespace gem5
diff --git a/src/arch/sparc/se_workload.hh b/src/arch/sparc/se_workload.hh
index 9c1c777..f821aef 100644
--- a/src/arch/sparc/se_workload.hh
+++ b/src/arch/sparc/se_workload.hh
@@ -38,18 +38,21 @@
#include "sim/se_workload.hh"
#include "sim/syscall_abi.hh"
+namespace gem5
+{
+
namespace SparcISA
{
-class SEWorkload : public ::SEWorkload
+class SEWorkload : public gem5::SEWorkload
{
public:
- using ::SEWorkload::SEWorkload;
+ using gem5::SEWorkload::SEWorkload;
void
setSystem(System *sys) override
{
- ::SEWorkload::setSystem(sys);
+ gem5::SEWorkload::setSystem(sys);
gdb = BaseRemoteGDB::build<RemoteGDB>(system);
}
@@ -132,5 +135,6 @@
};
} // namespace guest_abi
+} // namespace gem5
#endif // __ARCH_SPARC_SE_WORKLOAD_HH__
diff --git a/src/arch/sparc/solaris/solaris.cc b/src/arch/sparc/solaris/solaris.cc
index 2866666..d05fb49 100644
--- a/src/arch/sparc/solaris/solaris.cc
+++ b/src/arch/sparc/solaris/solaris.cc
@@ -31,6 +31,9 @@
#include <fcntl.h>
#include <sys/mman.h>
+namespace gem5
+{
+
// open(2) flags translation table
const std::map<int, int> SparcSolaris::openFlagTable = {
#ifdef _MSC_VER
@@ -90,3 +93,5 @@
{ TGT_MAP_ANONYMOUS, MAP_ANONYMOUS },
{ TGT_MAP_FIXED, MAP_FIXED },
};
+
+} // namespace gem5
diff --git a/src/arch/sparc/solaris/solaris.hh b/src/arch/sparc/solaris/solaris.hh
index 59d3db4..a90d6eb 100644
--- a/src/arch/sparc/solaris/solaris.hh
+++ b/src/arch/sparc/solaris/solaris.hh
@@ -34,6 +34,9 @@
#include "kern/solaris/solaris.hh"
#include "sim/byteswap.hh"
+namespace gem5
+{
+
class SparcSolaris : public Solaris
{
public:
@@ -79,4 +82,6 @@
static const unsigned TGT_MAP_FIXED = 0x00010;
};
+} // namespace gem5
+
#endif
diff --git a/src/arch/sparc/sparc_traits.hh b/src/arch/sparc/sparc_traits.hh
index e53f514..7755216 100644
--- a/src/arch/sparc/sparc_traits.hh
+++ b/src/arch/sparc/sparc_traits.hh
@@ -29,6 +29,9 @@
#ifndef __ARCH_SPARC_SPARC_TRAITS_HH__
#define __ARCH_SPARC_SPARC_TRAITS_HH__
+namespace gem5
+{
+
namespace SparcISA
{
// Max trap levels
@@ -39,6 +42,8 @@
// Number of register windows, can legally be 3 to 32
const int NWindows = 8;
-}
+
+} // namespace SparcISA
+} // namespace gem5
#endif // __ARCH_SPARC_SPARC_TRAITS_HH__
diff --git a/src/arch/sparc/stacktrace.hh b/src/arch/sparc/stacktrace.hh
index a40859d..f4e3a56 100644
--- a/src/arch/sparc/stacktrace.hh
+++ b/src/arch/sparc/stacktrace.hh
@@ -31,6 +31,9 @@
#include "cpu/profile.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -44,6 +47,7 @@
}
};
-}
+} // namespace SparcISA
+} // namespace gem5
#endif // __ARCH_SPARC_STACKTRACE_HH__
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 6bbd8cd..9ffab09 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -50,6 +50,9 @@
#include "sim/process.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
/* @todo remove some of the magic constants. -- ali
* */
namespace SparcISA {
@@ -1506,3 +1509,4 @@
}
} // namespace SparcISA
+} // namespace gem5
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 522b543..e40a30b 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -36,6 +36,9 @@
#include "mem/request.hh"
#include "params/SparcTLB.hh"
+namespace gem5
+{
+
class ThreadContext;
class Packet;
@@ -200,6 +203,7 @@
ASI cacheAsi[2];
};
-}
+} // namespace SparcISA
+} // namespace gem5
#endif // __ARCH_SPARC_TLB_HH__
diff --git a/src/arch/sparc/tlb_map.hh b/src/arch/sparc/tlb_map.hh
index cb31a17..8b9f320 100644
--- a/src/arch/sparc/tlb_map.hh
+++ b/src/arch/sparc/tlb_map.hh
@@ -33,6 +33,9 @@
#include "arch/sparc/pagetable.hh"
+namespace gem5
+{
+
namespace SparcISA
{
@@ -162,6 +165,7 @@
};
-};
+} // namespace SparcISA
+} // namespace gem5
#endif // __ARCH_SPARC_TLB_MAP_HH__
diff --git a/src/arch/sparc/types.hh b/src/arch/sparc/types.hh
index 3999cde..9e233d1 100644
--- a/src/arch/sparc/types.hh
+++ b/src/arch/sparc/types.hh
@@ -32,12 +32,16 @@
#include "arch/sparc/pcstate.hh"
#include "base/types.hh"
+namespace gem5
+{
+
namespace SparcISA
{
typedef uint32_t MachInst;
typedef uint64_t ExtMachInst;
-}
+} // namespace SparcISA
+} // namespace gem5
#endif
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 42e0bf5..3f5372a 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -37,6 +37,9 @@
#include "debug/Timer.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace SparcISA;
@@ -373,3 +376,4 @@
}
}
+} // namespace gem5
diff --git a/src/arch/sparc/vecregs.hh b/src/arch/sparc/vecregs.hh
index 480b26d..bb5c038 100644
--- a/src/arch/sparc/vecregs.hh
+++ b/src/arch/sparc/vecregs.hh
@@ -32,17 +32,21 @@
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
+namespace gem5
+{
+
namespace SparcISA
{
// Not applicable to SPARC
-using VecElem = ::DummyVecElem;
-using VecRegContainer = ::DummyVecRegContainer;
-constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
+using VecElem = ::gem5::DummyVecElem;
+using VecRegContainer = ::gem5::DummyVecRegContainer;
+constexpr unsigned NumVecElemPerVecReg = ::gem5::DummyNumVecElemPerVecReg;
// Not applicable to SPARC
-using VecPredRegContainer = ::DummyVecPredRegContainer;
+using VecPredRegContainer = ::gem5::DummyVecPredRegContainer;
} // namespace SparcISA
+} // namespace gem5
#endif
diff --git a/src/arch/x86/X86FsWorkload.py b/src/arch/x86/X86FsWorkload.py
index 1a4248f..a049203 100644
--- a/src/arch/x86/X86FsWorkload.py
+++ b/src/arch/x86/X86FsWorkload.py
@@ -44,7 +44,7 @@
class X86FsWorkload(KernelWorkload):
type = 'X86FsWorkload'
cxx_header = 'arch/x86/fs_workload.hh'
- cxx_class = 'X86ISA::FsWorkload'
+ cxx_class = 'gem5::X86ISA::FsWorkload'
smbios_table = Param.X86SMBiosSMBiosTable(
X86SMBiosSMBiosTable(), 'table of smbios/dmi information')
@@ -60,7 +60,7 @@
class X86FsLinux(X86FsWorkload):
type = 'X86FsLinux'
cxx_header = 'arch/x86/linux/fs_workload.hh'
- cxx_class = 'X86ISA::FsLinux'
+ cxx_class = 'gem5::X86ISA::FsLinux'
e820_table = Param.X86E820Table(
X86E820Table(), 'E820 map of physical memory')
diff --git a/src/arch/x86/X86ISA.py b/src/arch/x86/X86ISA.py
index 1503f5f..ea27bf8 100644
--- a/src/arch/x86/X86ISA.py
+++ b/src/arch/x86/X86ISA.py
@@ -38,7 +38,7 @@
class X86ISA(BaseISA):
type = 'X86ISA'
- cxx_class = 'X86ISA::ISA'
+ cxx_class = 'gem5::X86ISA::ISA'
cxx_header = "arch/x86/isa.hh"
vendor_string = Param.String("M5 Simulator",
diff --git a/src/arch/x86/X86LocalApic.py b/src/arch/x86/X86LocalApic.py
index 39004d2..baf4216 100644
--- a/src/arch/x86/X86LocalApic.py
+++ b/src/arch/x86/X86LocalApic.py
@@ -46,7 +46,7 @@
class X86LocalApic(BaseInterrupts):
type = 'X86LocalApic'
- cxx_class = 'X86ISA::Interrupts'
+ cxx_class = 'gem5::X86ISA::Interrupts'
cxx_header = 'arch/x86/interrupts.hh'
int_requestor = RequestPort("Port for sending interrupt messages")
diff --git a/src/arch/x86/X86MMU.py b/src/arch/x86/X86MMU.py
index fc77d5b..bc24d9a 100644
--- a/src/arch/x86/X86MMU.py
+++ b/src/arch/x86/X86MMU.py
@@ -40,7 +40,7 @@
class X86MMU(BaseMMU):
type = 'X86MMU'
- cxx_class = 'X86ISA::MMU'
+ cxx_class = 'gem5::X86ISA::MMU'
cxx_header = 'arch/x86/mmu.hh'
itb = X86TLB()
dtb = X86TLB()
diff --git a/src/arch/x86/X86NativeTrace.py b/src/arch/x86/X86NativeTrace.py
index d30afba..1be9c94 100644
--- a/src/arch/x86/X86NativeTrace.py
+++ b/src/arch/x86/X86NativeTrace.py
@@ -31,5 +31,5 @@
class X86NativeTrace(NativeTrace):
type = 'X86NativeTrace'
- cxx_class = 'Trace::X86NativeTrace'
+ cxx_class = 'gem5::Trace::X86NativeTrace'
cxx_header = 'arch/x86/nativetrace.hh'
diff --git a/src/arch/x86/X86SeWorkload.py b/src/arch/x86/X86SeWorkload.py
index 0dfec53..4a70e01 100644
--- a/src/arch/x86/X86SeWorkload.py
+++ b/src/arch/x86/X86SeWorkload.py
@@ -30,7 +30,7 @@
class X86EmuLinux(SEWorkload):
type = 'X86EmuLinux'
cxx_header = "arch/x86/linux/se_workload.hh"
- cxx_class = 'X86ISA::EmuLinux'
+ cxx_class = 'gem5::X86ISA::EmuLinux'
@classmethod
def _is_compatible_with(cls, obj):
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index d9dd980..8abc93c 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -41,8 +41,9 @@
class X86PagetableWalker(ClockedObject):
type = 'X86PagetableWalker'
- cxx_class = 'X86ISA::Walker'
+ cxx_class = 'gem5::X86ISA::Walker'
cxx_header = 'arch/x86/pagetable_walker.hh'
+
port = RequestPort("Port for the hardware table walker")
system = Param.System(Parent.any, "system object")
num_squash_per_cycle = Param.Unsigned(4,
@@ -50,8 +51,9 @@
class X86TLB(BaseTLB):
type = 'X86TLB'
- cxx_class = 'X86ISA::TLB'
+ cxx_class = 'gem5::X86ISA::TLB'
cxx_header = 'arch/x86/tlb.hh'
+
size = Param.Unsigned(64, "TLB size")
system = Param.System(Parent.any, "system object")
walker = Param.X86PagetableWalker(\
diff --git a/src/arch/x86/bios/ACPI.py b/src/arch/x86/bios/ACPI.py
index 5dfcb4d..c20096f 100644
--- a/src/arch/x86/bios/ACPI.py
+++ b/src/arch/x86/bios/ACPI.py
@@ -40,7 +40,7 @@
# contents as appropriate for that type of table.
class X86ACPISysDescTable(SimObject):
type = 'X86ACPISysDescTable'
- cxx_class = 'X86ISA::ACPI::SysDescTable'
+ cxx_class = 'gem5::X86ISA::ACPI::SysDescTable'
cxx_header = 'arch/x86/bios/acpi.hh'
abstract = True
@@ -55,14 +55,14 @@
class X86ACPIRSDT(X86ACPISysDescTable):
type = 'X86ACPIRSDT'
- cxx_class = 'X86ISA::ACPI::RSDT'
+ cxx_class = 'gem5::X86ISA::ACPI::RSDT'
cxx_header = 'arch/x86/bios/acpi.hh'
entries = VectorParam.X86ACPISysDescTable([], 'system description tables')
class X86ACPIXSDT(X86ACPISysDescTable):
type = 'X86ACPIXSDT'
- cxx_class = 'X86ISA::ACPI::XSDT'
+ cxx_class = 'gem5::X86ISA::ACPI::XSDT'
cxx_header = 'arch/x86/bios/acpi.hh'
entries = VectorParam.X86ACPISysDescTable([], 'system description tables')
@@ -70,13 +70,13 @@
class X86ACPIMadtRecord(SimObject):
type = 'X86ACPIMadtRecord'
- cxx_class = 'X86ISA::ACPI::MADT::Record'
+ cxx_class = 'gem5::X86ISA::ACPI::MADT::Record'
cxx_header = 'arch/x86/bios/acpi.hh'
abstract = True
class X86ACPIMadt(X86ACPISysDescTable):
type = 'X86ACPIMadt'
- cxx_class = 'X86ISA::ACPI::MADT::MADT'
+ cxx_class = 'gem5::X86ISA::ACPI::MADT::MADT'
cxx_header = 'arch/x86/bios/acpi.hh'
local_apic_address = Param.UInt32(0, 'Address of the local apic')
@@ -86,7 +86,7 @@
class X86ACPIMadtLAPIC(X86ACPIMadtRecord):
type = 'X86ACPIMadtLAPIC'
cxx_header = 'arch/x86/bios/acpi.hh'
- cxx_class = 'X86ISA::ACPI::MADT::LAPIC'
+ cxx_class = 'gem5::X86ISA::ACPI::MADT::LAPIC'
acpi_processor_id = Param.UInt8(0, 'ACPI Processor ID')
apic_id = Param.UInt8(0, 'APIC ID')
@@ -95,7 +95,7 @@
class X86ACPIMadtIOAPIC(X86ACPIMadtRecord):
type = 'X86ACPIMadtIOAPIC'
cxx_header = 'arch/x86/bios/acpi.hh'
- cxx_class = 'X86ISA::ACPI::MADT::IOAPIC'
+ cxx_class = 'gem5::X86ISA::ACPI::MADT::IOAPIC'
id = Param.UInt8(0, 'I/O APIC ID')
address = Param.Addr(0, 'I/O APIC Address')
@@ -104,7 +104,7 @@
class X86ACPIMadtIntSourceOverride(X86ACPIMadtRecord):
type = 'X86ACPIMadtIntSourceOverride'
cxx_header = 'arch/x86/bios/acpi.hh'
- cxx_class = 'X86ISA::ACPI::MADT::IntSourceOverride'
+ cxx_class = 'gem5::X86ISA::ACPI::MADT::IntSourceOverride'
bus_source = Param.UInt8(0, 'Bus Source')
irq_source = Param.UInt8(0, 'IRQ Source')
@@ -114,7 +114,7 @@
class X86ACPIMadtNMI(X86ACPIMadtRecord):
type = 'X86ACPIMadtNMI'
cxx_header = 'arch/x86/bios/acpi.hh'
- cxx_class = 'X86ISA::ACPI::MADT::NMI'
+ cxx_class = 'gem5::X86ISA::ACPI::MADT::NMI'
acpi_processor_id = Param.UInt8(0, 'ACPI Processor ID')
flags = Param.UInt16(0, 'Flags')
@@ -123,14 +123,14 @@
class X86ACPIMadtLAPICOverride(X86ACPIMadtRecord):
type = 'X86ACPIMadtLAPICOverride'
cxx_header = 'arch/x86/bios/acpi.hh'
- cxx_class = 'X86ISA::ACPI::MADT::LAPICOverride'
+ cxx_class = 'gem5::X86ISA::ACPI::MADT::LAPICOverride'
address = Param.Addr(0, '64-bit Physical Address of Local APIC')
# Root System Description Pointer Structure
class X86ACPIRSDP(SimObject):
type = 'X86ACPIRSDP'
- cxx_class = 'X86ISA::ACPI::RSDP'
+ cxx_class = 'gem5::X86ISA::ACPI::RSDP'
cxx_header = 'arch/x86/bios/acpi.hh'
oem_id = Param.String('', 'string identifying the oem')
diff --git a/src/arch/x86/bios/E820.py b/src/arch/x86/bios/E820.py
index bed6990..222e4a4 100644
--- a/src/arch/x86/bios/E820.py
+++ b/src/arch/x86/bios/E820.py
@@ -38,7 +38,7 @@
class X86E820Entry(SimObject):
type = 'X86E820Entry'
- cxx_class = 'X86ISA::E820Entry'
+ cxx_class = 'gem5::X86ISA::E820Entry'
cxx_header = 'arch/x86/bios/e820.hh'
addr = Param.Addr(0, 'address of the beginning of the region')
@@ -47,7 +47,7 @@
class X86E820Table(SimObject):
type = 'X86E820Table'
- cxx_class = 'X86ISA::E820Table'
+ cxx_class = 'gem5::X86ISA::E820Table'
cxx_header = 'arch/x86/bios/e820.hh'
entries = VectorParam.X86E820Entry('entries for the e820 table')
diff --git a/src/arch/x86/bios/IntelMP.py b/src/arch/x86/bios/IntelMP.py
index 0d9a641..18bd487 100644
--- a/src/arch/x86/bios/IntelMP.py
+++ b/src/arch/x86/bios/IntelMP.py
@@ -38,7 +38,7 @@
class X86IntelMPFloatingPointer(SimObject):
type = 'X86IntelMPFloatingPointer'
- cxx_class = 'X86ISA::intelmp::FloatingPointer'
+ cxx_class = 'gem5::X86ISA::intelmp::FloatingPointer'
cxx_header = 'arch/x86/bios/intelmp.hh'
# The minor revision of the spec to support. The major version is assumed
@@ -51,7 +51,7 @@
class X86IntelMPConfigTable(SimObject):
type = 'X86IntelMPConfigTable'
- cxx_class = 'X86ISA::intelmp::ConfigTable'
+ cxx_class = 'gem5::X86ISA::intelmp::ConfigTable'
cxx_header = 'arch/x86/bios/intelmp.hh'
spec_rev = Param.UInt8(4, 'minor revision of the MP spec supported')
@@ -79,19 +79,19 @@
class X86IntelMPBaseConfigEntry(SimObject):
type = 'X86IntelMPBaseConfigEntry'
- cxx_class = 'X86ISA::intelmp::BaseConfigEntry'
+ cxx_class = 'gem5::X86ISA::intelmp::BaseConfigEntry'
cxx_header = 'arch/x86/bios/intelmp.hh'
abstract = True
class X86IntelMPExtConfigEntry(SimObject):
type = 'X86IntelMPExtConfigEntry'
- cxx_class = 'X86ISA::intelmp::ExtConfigEntry'
+ cxx_class = 'gem5::X86ISA::intelmp::ExtConfigEntry'
cxx_header = 'arch/x86/bios/intelmp.hh'
abstract = True
class X86IntelMPProcessor(X86IntelMPBaseConfigEntry):
type = 'X86IntelMPProcessor'
- cxx_class = 'X86ISA::intelmp::Processor'
+ cxx_class = 'gem5::X86ISA::intelmp::Processor'
cxx_header = 'arch/x86/bios/intelmp.hh'
local_apic_id = Param.UInt8(0, 'local APIC id')
@@ -108,7 +108,7 @@
class X86IntelMPBus(X86IntelMPBaseConfigEntry):
type = 'X86IntelMPBus'
- cxx_class = 'X86ISA::intelmp::Bus'
+ cxx_class = 'gem5::X86ISA::intelmp::Bus'
cxx_header = 'arch/x86/bios/intelmp.hh'
bus_id = Param.UInt8(0, 'bus id assigned by the bios')
@@ -121,7 +121,7 @@
class X86IntelMPIOAPIC(X86IntelMPBaseConfigEntry):
type = 'X86IntelMPIOAPIC'
- cxx_class = 'X86ISA::intelmp::IOAPIC'
+ cxx_class = 'gem5::X86ISA::intelmp::IOAPIC'
cxx_header = 'arch/x86/bios/intelmp.hh'
id = Param.UInt8(0, 'id of this APIC')
@@ -152,7 +152,7 @@
class X86IntelMPIOIntAssignment(X86IntelMPBaseConfigEntry):
type = 'X86IntelMPIOIntAssignment'
- cxx_class = 'X86ISA::intelmp::IOIntAssignment'
+ cxx_class = 'gem5::X86ISA::intelmp::IOIntAssignment'
cxx_header = 'arch/x86/bios/intelmp.hh'
interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt')
@@ -172,7 +172,7 @@
class X86IntelMPLocalIntAssignment(X86IntelMPBaseConfigEntry):
type = 'X86IntelMPLocalIntAssignment'
- cxx_class = 'X86ISA::intelmp::LocalIntAssignment'
+ cxx_class = 'gem5::X86ISA::intelmp::LocalIntAssignment'
cxx_header = 'arch/x86/bios/intelmp.hh'
interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt')
@@ -198,7 +198,7 @@
class X86IntelMPAddrSpaceMapping(X86IntelMPExtConfigEntry):
type = 'X86IntelMPAddrSpaceMapping'
- cxx_class = 'X86ISA::intelmp::AddrSpaceMapping'
+ cxx_class = 'gem5::X86ISA::intelmp::AddrSpaceMapping'
cxx_header = 'arch/x86/bios/intelmp.hh'
bus_id = Param.UInt8(0, 'id of the bus the address space is mapped to')
@@ -209,7 +209,7 @@
class X86IntelMPBusHierarchy(X86IntelMPExtConfigEntry):
type = 'X86IntelMPBusHierarchy'
- cxx_class = 'X86ISA::intelmp::BusHierarchy'
+ cxx_class = 'gem5::X86ISA::intelmp::BusHierarchy'
cxx_header = 'arch/x86/bios/intelmp.hh'
bus_id = Param.UInt8(0, 'id of the bus being described')
@@ -224,7 +224,7 @@
class X86IntelMPCompatAddrSpaceMod(X86IntelMPExtConfigEntry):
type = 'X86IntelMPCompatAddrSpaceMod'
- cxx_class = 'X86ISA::intelmp::CompatAddrSpaceMod'
+ cxx_class = 'gem5::X86ISA::intelmp::CompatAddrSpaceMod'
cxx_header = 'arch/x86/bios/intelmp.hh'
bus_id = Param.UInt8(0, 'id of the bus being described')
diff --git a/src/arch/x86/bios/SMBios.py b/src/arch/x86/bios/SMBios.py
index 24d28e3..67abc3e 100644
--- a/src/arch/x86/bios/SMBios.py
+++ b/src/arch/x86/bios/SMBios.py
@@ -38,7 +38,7 @@
class X86SMBiosSMBiosStructure(SimObject):
type = 'X86SMBiosSMBiosStructure'
- cxx_class = 'X86ISA::smbios::SMBiosStructure'
+ cxx_class = 'gem5::X86ISA::smbios::SMBiosStructure'
cxx_header = 'arch/x86/bios/smbios.hh'
abstract = True
@@ -91,7 +91,7 @@
class X86SMBiosBiosInformation(X86SMBiosSMBiosStructure):
type = 'X86SMBiosBiosInformation'
- cxx_class = 'X86ISA::smbios::BiosInformation'
+ cxx_class = 'gem5::X86ISA::smbios::BiosInformation'
cxx_header = 'arch/x86/bios/smbios.hh'
vendor = Param.String("", "vendor name string")
@@ -114,7 +114,7 @@
class X86SMBiosSMBiosTable(SimObject):
type = 'X86SMBiosSMBiosTable'
- cxx_class = 'X86ISA::smbios::SMBiosTable'
+ cxx_class = 'gem5::X86ISA::smbios::SMBiosTable'
cxx_header = 'arch/x86/bios/smbios.hh'
major_version = Param.UInt8(2, "major version number")
diff --git a/src/arch/x86/bios/acpi.cc b/src/arch/x86/bios/acpi.cc
index 9a5d32e..f2dbcfb 100644
--- a/src/arch/x86/bios/acpi.cc
+++ b/src/arch/x86/bios/acpi.cc
@@ -47,6 +47,9 @@
#include "sim/byteswap.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -331,3 +334,4 @@
} // namespace ACPI
} // namespace X86ISA
+} // namespace gem5
diff --git a/src/arch/x86/bios/acpi.hh b/src/arch/x86/bios/acpi.hh
index fa6fa10..f6d94ee 100644
--- a/src/arch/x86/bios/acpi.hh
+++ b/src/arch/x86/bios/acpi.hh
@@ -59,6 +59,9 @@
#include "params/X86ACPIXSDT.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class PortProxy;
namespace X86ISA
@@ -359,5 +362,6 @@
} // namespace ACPI
} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_BIOS_E820_HH__
diff --git a/src/arch/x86/bios/e820.cc b/src/arch/x86/bios/e820.cc
index 51c6b9d..9e5f29b 100644
--- a/src/arch/x86/bios/e820.cc
+++ b/src/arch/x86/bios/e820.cc
@@ -40,6 +40,9 @@
#include "mem/port_proxy.hh"
#include "sim/byteswap.hh"
+namespace gem5
+{
+
using namespace X86ISA;
template<class T>
@@ -68,3 +71,5 @@
writeVal(entries[i]->type, proxy, addr);
}
}
+
+} // namespace gem5
diff --git a/src/arch/x86/bios/e820.hh b/src/arch/x86/bios/e820.hh
index 0c59adf..acf578a 100644
--- a/src/arch/x86/bios/e820.hh
+++ b/src/arch/x86/bios/e820.hh
@@ -45,6 +45,9 @@
#include "params/X86E820Table.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class PortProxy;
namespace X86ISA
@@ -75,6 +78,8 @@
void writeTo(PortProxy& proxy, Addr countAddr, Addr addr);
};
-}
+
+} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_BIOS_E820_HH__
diff --git a/src/arch/x86/bios/intelmp.cc b/src/arch/x86/bios/intelmp.cc
index 3d8bc68..78d3fcd 100644
--- a/src/arch/x86/bios/intelmp.cc
+++ b/src/arch/x86/bios/intelmp.cc
@@ -62,6 +62,9 @@
#include "params/X86IntelMPBusHierarchy.hh"
#include "params/X86IntelMPCompatAddrSpaceMod.hh"
+namespace gem5
+{
+
const char X86ISA::intelmp::FloatingPointer::signature[] = "_MP_";
template<class T>
@@ -393,3 +396,5 @@
if (p.add)
mod |= 1;
}
+
+} // namespace gem5
diff --git a/src/arch/x86/bios/intelmp.hh b/src/arch/x86/bios/intelmp.hh
index 48ba4bb..19f2f7a 100644
--- a/src/arch/x86/bios/intelmp.hh
+++ b/src/arch/x86/bios/intelmp.hh
@@ -50,6 +50,9 @@
#include "enums/X86IntelMPTriggerMode.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class PortProxy;
// Config entry types
@@ -310,8 +313,8 @@
CompatAddrSpaceMod(const Params &p);
};
-} //IntelMP
-
-} //X86ISA
+} // namespace intelmp
+} // namespace X86ISA
+} // namespace gem5
#endif
diff --git a/src/arch/x86/bios/smbios.cc b/src/arch/x86/bios/smbios.cc
index bd5210c..ec30950 100644
--- a/src/arch/x86/bios/smbios.cc
+++ b/src/arch/x86/bios/smbios.cc
@@ -47,6 +47,9 @@
#include "params/X86SMBiosSMBiosTable.hh"
#include "sim/byteswap.hh"
+namespace gem5
+{
+
const char X86ISA::smbios::SMBiosTable::SMBiosHeader::anchorString[] = "_SM_";
const uint8_t X86ISA::smbios::SMBiosTable::
SMBiosHeader::formattedArea[] = {0,0,0,0,0};
@@ -319,3 +322,5 @@
intChecksum = -intChecksum;
proxy.writeBlob(addr + 0x15, &intChecksum, 1);
}
+
+} // namespace gem5
diff --git a/src/arch/x86/bios/smbios.hh b/src/arch/x86/bios/smbios.hh
index b3c4cf9..dc38676 100644
--- a/src/arch/x86/bios/smbios.hh
+++ b/src/arch/x86/bios/smbios.hh
@@ -50,6 +50,9 @@
#include "enums/ExtCharacteristic.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class PortProxy;
struct X86SMBiosBiosInformationParams;
struct X86SMBiosSMBiosStructureParams;
@@ -227,7 +230,8 @@
Addr &headerSize, Addr &structSize);
};
-} //SMBios
-} //X86ISA
+} // namespace smbios
+} // namespace X86ISA
+} // namespace gem5
#endif
diff --git a/src/arch/x86/cpuid.cc b/src/arch/x86/cpuid.cc
index 84ad7bd..9d1390d 100644
--- a/src/arch/x86/cpuid.cc
+++ b/src/arch/x86/cpuid.cc
@@ -32,6 +32,9 @@
#include "base/bitfield.hh"
#include "cpu/thread_context.hh"
+namespace gem5
+{
+
namespace X86ISA {
enum StandardCpuidFunction
{
@@ -186,3 +189,4 @@
return true;
}
} // namespace X86ISA
+} // namespace gem5
diff --git a/src/arch/x86/cpuid.hh b/src/arch/x86/cpuid.hh
index 8ff4693..5c1a8cc 100644
--- a/src/arch/x86/cpuid.hh
+++ b/src/arch/x86/cpuid.hh
@@ -31,6 +31,9 @@
#include "base/types.hh"
+namespace gem5
+{
+
class ThreadContext;
namespace X86ISA
@@ -57,6 +60,8 @@
bool doCpuid(ThreadContext * tc, uint32_t function,
uint32_t index, CpuidResult &result);
+
} // namespace X86ISA
+} // namespace gem5
#endif
diff --git a/src/arch/x86/decoder.cc b/src/arch/x86/decoder.cc
index 95b80a8..015a504 100644
--- a/src/arch/x86/decoder.cc
+++ b/src/arch/x86/decoder.cc
@@ -35,6 +35,9 @@
#include "debug/Decode.hh"
#include "debug/Decoder.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -740,4 +743,5 @@
return microcodeRom.fetchMicroop(micropc, curMacroop);
}
-}
+} // namespace X86ISA
+} // namespace gem5
diff --git a/src/arch/x86/decoder.hh b/src/arch/x86/decoder.hh
index b43cf34..39fdab9 100644
--- a/src/arch/x86/decoder.hh
+++ b/src/arch/x86/decoder.hh
@@ -45,6 +45,9 @@
#include "cpu/static_inst.hh"
#include "debug/Decoder.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -345,5 +348,6 @@
};
} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_DECODER_HH__
diff --git a/src/arch/x86/decoder_tables.cc b/src/arch/x86/decoder_tables.cc
index e470800..b1154e7 100644
--- a/src/arch/x86/decoder_tables.cc
+++ b/src/arch/x86/decoder_tables.cc
@@ -38,6 +38,9 @@
#include "arch/x86/decoder.hh"
#include "arch/x86/types.hh"
+namespace gem5
+{
+
namespace X86ISA
{
const uint8_t CS = CSOverride;
@@ -283,4 +286,5 @@
/* E */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* F */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0
};
-}
+} // namespace X86ISA
+} // namespace gem5
diff --git a/src/arch/x86/emulenv.cc b/src/arch/x86/emulenv.cc
index 0c19925..bfca1e5 100644
--- a/src/arch/x86/emulenv.cc
+++ b/src/arch/x86/emulenv.cc
@@ -41,6 +41,9 @@
#include "base/logging.hh"
+namespace gem5
+{
+
using namespace X86ISA;
void EmulEnv::doModRM(const ExtMachInst & machInst)
@@ -118,3 +121,5 @@
if (segFromInst)
seg = (SegmentRegIndex)(segFromInst - 1);
}
+
+} // namespace gem5
diff --git a/src/arch/x86/emulenv.hh b/src/arch/x86/emulenv.hh
index b76c0ed..ad14747 100644
--- a/src/arch/x86/emulenv.hh
+++ b/src/arch/x86/emulenv.hh
@@ -42,6 +42,9 @@
#include "arch/x86/regs/segment.hh"
#include "arch/x86/types.hh"
+namespace gem5
+{
+
namespace X86ISA
{
struct EmulEnv
@@ -68,6 +71,8 @@
void doModRM(const ExtMachInst & machInst);
void setSeg(const ExtMachInst & machInst);
};
-}
+
+} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_TYPES_HH__
diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
index b1eea90..d925bd7 100644
--- a/src/arch/x86/faults.cc
+++ b/src/arch/x86/faults.cc
@@ -50,6 +50,9 @@
#include "sim/full_system.hh"
#include "sim/process.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -318,3 +321,4 @@
}
} // namespace X86ISA
+} // namespace gem5
diff --git a/src/arch/x86/faults.hh b/src/arch/x86/faults.hh
index 9b6d488..3ce702d 100644
--- a/src/arch/x86/faults.hh
+++ b/src/arch/x86/faults.hh
@@ -46,6 +46,9 @@
#include "cpu/null_static_inst.hh"
#include "sim/faults.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -377,5 +380,6 @@
};
} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_FAULTS_HH__
diff --git a/src/arch/x86/fs_workload.cc b/src/arch/x86/fs_workload.cc
index 8fa564d..dd71222 100644
--- a/src/arch/x86/fs_workload.cc
+++ b/src/arch/x86/fs_workload.cc
@@ -48,6 +48,9 @@
#include "params/X86FsWorkload.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -395,3 +398,4 @@
}
} // namespace X86ISA
+} // namespace gem5
diff --git a/src/arch/x86/fs_workload.hh b/src/arch/x86/fs_workload.hh
index fc554b4..6c2038f 100644
--- a/src/arch/x86/fs_workload.hh
+++ b/src/arch/x86/fs_workload.hh
@@ -49,6 +49,9 @@
#include "params/X86FsWorkload.hh"
#include "sim/kernel_workload.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -105,5 +108,6 @@
};
} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_FS_WORKLOAD_HH__
diff --git a/src/arch/x86/insts/badmicroop.cc b/src/arch/x86/insts/badmicroop.cc
index 4e8633b..516173c 100644
--- a/src/arch/x86/insts/badmicroop.cc
+++ b/src/arch/x86/insts/badmicroop.cc
@@ -40,6 +40,9 @@
#include "arch/generic/debugfaults.hh"
#include "arch/x86/generated/decoder.hh"
+namespace gem5
+{
+
namespace {
static X86ISA::ExtMachInst dummyMachInst;
@@ -59,3 +62,4 @@
new GenericISA::M5PanicFault("Invalid microop!"));
} // namespace X86ISA
+} // namespace gem5
diff --git a/src/arch/x86/insts/badmicroop.hh b/src/arch/x86/insts/badmicroop.hh
index 5b04073..b1aa6ad 100644
--- a/src/arch/x86/insts/badmicroop.hh
+++ b/src/arch/x86/insts/badmicroop.hh
@@ -40,11 +40,15 @@
#include "cpu/static_inst_fwd.hh"
+namespace gem5
+{
+
namespace X86ISA
{
extern const StaticInstPtr badMicroop;
} // namespace X86ISA
+} // namespace gem5
#endif //__ARCH_X86_INSTS_BADMICROOP_HH__
diff --git a/src/arch/x86/insts/macroop.hh b/src/arch/x86/insts/macroop.hh
index 7e3b890..36718f7 100644
--- a/src/arch/x86/insts/macroop.hh
+++ b/src/arch/x86/insts/macroop.hh
@@ -43,6 +43,9 @@
#include "arch/x86/emulenv.hh"
#include "arch/x86/types.hh"
+namespace gem5
+{
+
namespace X86ISA
{
// Base class for combinationally generated macroops
@@ -101,6 +104,8 @@
return env;
}
};
-}
+
+} // namespace X86ISA
+} // namespace gem5
#endif //__ARCH_X86_INSTS_MACROOP_HH__
diff --git a/src/arch/x86/insts/microdebug.hh b/src/arch/x86/insts/microdebug.hh
index 6c4e5d2..488ed14 100644
--- a/src/arch/x86/insts/microdebug.hh
+++ b/src/arch/x86/insts/microdebug.hh
@@ -30,6 +30,9 @@
#include "arch/x86/insts/microop.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -65,5 +68,6 @@
};
} // namespace X86ISA
+} // namespace gem5
#endif //__ARCH_X86_INSTS_MICRODEBUG_HH__
diff --git a/src/arch/x86/insts/microfpop.hh b/src/arch/x86/insts/microfpop.hh
index 3cd92cf..3c9f5b8 100644
--- a/src/arch/x86/insts/microfpop.hh
+++ b/src/arch/x86/insts/microfpop.hh
@@ -40,6 +40,9 @@
#include "arch/x86/insts/microop.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -62,6 +65,7 @@
const RegIndex foldOBit;
};
-}
+} // namespace X86ISA
+} // namespace gem5
#endif //__ARCH_X86_INSTS_MICROFPOP_HH__
diff --git a/src/arch/x86/insts/microldstop.hh b/src/arch/x86/insts/microldstop.hh
index 8ce458b..e38341b 100644
--- a/src/arch/x86/insts/microldstop.hh
+++ b/src/arch/x86/insts/microldstop.hh
@@ -48,6 +48,9 @@
#include "mem/request.hh"
#include "sim/faults.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -155,6 +158,7 @@
{}
};
-}
+} // namespace X86ISA
+} // namespace gem5
#endif //__ARCH_X86_INSTS_MICROLDSTOP_HH__
diff --git a/src/arch/x86/insts/micromediaop.hh b/src/arch/x86/insts/micromediaop.hh
index 330a930..8c0b5ce 100644
--- a/src/arch/x86/insts/micromediaop.hh
+++ b/src/arch/x86/insts/micromediaop.hh
@@ -31,6 +31,9 @@
#include "arch/x86/insts/microop.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -84,6 +87,7 @@
static constexpr uint8_t dataSize = 0;
};
-}
+} // namespace X86ISA
+} // namespace gem5
#endif //__ARCH_X86_INSTS_MICROMEDIAOP_HH__
diff --git a/src/arch/x86/insts/microop.cc b/src/arch/x86/insts/microop.cc
index b9be362..12b5f94 100644
--- a/src/arch/x86/insts/microop.cc
+++ b/src/arch/x86/insts/microop.cc
@@ -39,6 +39,9 @@
#include "arch/x86/regs/misc.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -130,4 +133,5 @@
return pcs;
}
-}
+} // namespace X86ISA
+} // namespace gem5
diff --git a/src/arch/x86/insts/microop.hh b/src/arch/x86/insts/microop.hh
index e3a2a56..c59c5b9 100644
--- a/src/arch/x86/insts/microop.hh
+++ b/src/arch/x86/insts/microop.hh
@@ -41,6 +41,9 @@
#include "arch/x86/insts/static_inst.hh"
#include "base/compiler.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -157,6 +160,7 @@
{}
};
-}
+} // namespace X86ISA
+} // namespace gem5
#endif //__ARCH_X86_INSTS_MICROOP_HH__
diff --git a/src/arch/x86/insts/microop_args.hh b/src/arch/x86/insts/microop_args.hh
index 5e7f7c4..8ec836e 100644
--- a/src/arch/x86/insts/microop_args.hh
+++ b/src/arch/x86/insts/microop_args.hh
@@ -42,6 +42,9 @@
#include "cpu/reg_class.hh"
#include "sim/faults.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -375,6 +378,7 @@
}
};
-}
+} // namespace X86ISA
+} // namespace gem5
#endif //__ARCH_X86_INSTS_MICROOP_ARGS_HH__
diff --git a/src/arch/x86/insts/microregop.cc b/src/arch/x86/insts/microregop.cc
index 63cdf50..2c8721e 100644
--- a/src/arch/x86/insts/microregop.cc
+++ b/src/arch/x86/insts/microregop.cc
@@ -43,6 +43,9 @@
#include "base/condcodes.hh"
#include "debug/X86.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -75,4 +78,5 @@
return flags;
}
-}
+} // namespace X86ISA
+} // namespace gem5
diff --git a/src/arch/x86/insts/microregop.hh b/src/arch/x86/insts/microregop.hh
index 70676df..979fd20 100644
--- a/src/arch/x86/insts/microregop.hh
+++ b/src/arch/x86/insts/microregop.hh
@@ -41,6 +41,9 @@
#include "arch/x86/insts/microop.hh"
#include "arch/x86/insts/microop_args.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -70,6 +73,7 @@
template <typename ...Operands>
using RegOpT = InstOperands<RegOpBase, Operands...>;
-}
+} // namespace X86ISA
+} // namespace gem5
#endif //__ARCH_X86_INSTS_MICROREGOP_HH__
diff --git a/src/arch/x86/insts/microspecop.hh b/src/arch/x86/insts/microspecop.hh
index ed78024..942bfd7 100644
--- a/src/arch/x86/insts/microspecop.hh
+++ b/src/arch/x86/insts/microspecop.hh
@@ -31,6 +31,9 @@
#include "arch/x86/insts/microop.hh"
#include "cpu/exec_context.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -54,5 +57,6 @@
};
} // namespace X86ISA
+} // namespace gem5
#endif //__ARCH_X86_INSTS_MICROSPECOP_HH__
diff --git a/src/arch/x86/insts/static_inst.cc b/src/arch/x86/insts/static_inst.cc
index 6c90d50..01e62f1 100644
--- a/src/arch/x86/insts/static_inst.cc
+++ b/src/arch/x86/insts/static_inst.cc
@@ -41,6 +41,9 @@
#include "arch/x86/regs/segment.hh"
#include "cpu/reg_class.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -297,4 +300,5 @@
return ss.str();
}
-}
+} // namespace X86ISA
+} // namespace gem5
diff --git a/src/arch/x86/insts/static_inst.hh b/src/arch/x86/insts/static_inst.hh
index 92489dc..3b2b9f6 100644
--- a/src/arch/x86/insts/static_inst.hh
+++ b/src/arch/x86/insts/static_inst.hh
@@ -43,6 +43,9 @@
#include "cpu/static_inst.hh"
#include "debug/X86.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -208,6 +211,8 @@
return retPC;
}
};
-}
+
+} // namespace X86ISA
+} // namespace gem5
#endif //__ARCH_X86_INSTS_STATICINST_HH__
diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index 9dee310..80ed3a6 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -63,6 +63,9 @@
#include "sim/full_system.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
int
divideFromConf(uint32_t conf)
{
@@ -779,3 +782,5 @@
if (triggerTimerInterrupt())
setReg(APIC_INITIAL_COUNT, readReg(APIC_INITIAL_COUNT));
}
+
+} // namespace gem5
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index 79a959a..7557b22 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -61,6 +61,9 @@
#include "params/X86LocalApic.hh"
#include "sim/eventq.hh"
+namespace gem5
+{
+
class ThreadContext;
class BaseCPU;
@@ -301,5 +304,6 @@
};
} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_INTERRUPTS_HH__
diff --git a/src/arch/x86/intmessage.hh b/src/arch/x86/intmessage.hh
index 690532e..e775e2a 100644
--- a/src/arch/x86/intmessage.hh
+++ b/src/arch/x86/intmessage.hh
@@ -38,6 +38,9 @@
#include "mem/packet_access.hh"
#include "mem/request.hh"
+namespace gem5
+{
+
namespace X86ISA
{
BitUnion32(TriggerIntMessage)
@@ -84,6 +87,8 @@
Addr addr = x86InterruptAddress(id, TriggerIntOffset);
return buildIntPacket(addr, message);
}
-}
+
+} // namespace X86ISA
+} // namespace gem5
#endif
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index e5a37de..085420e 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -39,6 +39,9 @@
#include "params/X86ISA.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -485,4 +488,5 @@
return vendorString;
}
-}
+} // namespace X86ISA
+} // namespace gem5
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 6358d27..eb4890c 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -38,6 +38,9 @@
#include "base/types.hh"
#include "cpu/reg_class.hh"
+namespace gem5
+{
+
class ThreadContext;
struct X86ISAParams;
@@ -119,6 +122,7 @@
std::string getVendorString() const;
};
-}
+} // namespace X86ISA
+} // namespace gem5
#endif
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 0136624..fe28516e 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -69,6 +69,7 @@
#include "mem/packet.hh"
#include "sim/faults.hh"
+using namespace gem5;
using X86ISA::GpRegIndex;
using X86ISA::FpRegIndex;
using X86ISA::CtrlRegIndex;
@@ -96,6 +97,7 @@
#include "mem/packet.hh"
#include "sim/full_system.hh"
+using namespace gem5;
using namespace X86ISA;
}};
@@ -123,6 +125,7 @@
#include "sim/pseudo_inst.hh"
#include "sim/sim_exit.hh"
+using namespace gem5;
using namespace X86ISA;
}};
diff --git a/src/arch/x86/ldstflags.hh b/src/arch/x86/ldstflags.hh
index 408d057..95f0dd6 100644
--- a/src/arch/x86/ldstflags.hh
+++ b/src/arch/x86/ldstflags.hh
@@ -42,6 +42,9 @@
#include "base/compiler.hh"
#include "mem/request.hh"
+namespace gem5
+{
+
/**
* This is exposed globally, independent of the ISA.
*/
@@ -55,6 +58,7 @@
AddrSizeFlagBit = 2,
StoreCheck = 4
};
-}
+} // namespace X86ISA
+} // namespace gem5
#endif //__ARCH_X86_LDSTFLAGS_HH__
diff --git a/src/arch/x86/linux/fs_workload.cc b/src/arch/x86/linux/fs_workload.cc
index 4f3dce4..f3c1b87 100644
--- a/src/arch/x86/linux/fs_workload.cc
+++ b/src/arch/x86/linux/fs_workload.cc
@@ -45,6 +45,9 @@
#include "sim/byteswap.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -127,3 +130,4 @@
}
} // namespace X86ISA
+} // namespace gem5
diff --git a/src/arch/x86/linux/fs_workload.hh b/src/arch/x86/linux/fs_workload.hh
index 5601a83..af4ab3d 100644
--- a/src/arch/x86/linux/fs_workload.hh
+++ b/src/arch/x86/linux/fs_workload.hh
@@ -42,6 +42,9 @@
#include "arch/x86/fs_workload.hh"
#include "params/X86FsLinux.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -58,5 +61,6 @@
};
} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_LINUX_FS_WORKLOAD_HH__
diff --git a/src/arch/x86/linux/linux.hh b/src/arch/x86/linux/linux.hh
index 391e418..9d1563a 100644
--- a/src/arch/x86/linux/linux.hh
+++ b/src/arch/x86/linux/linux.hh
@@ -46,6 +46,9 @@
#include "sim/guest_abi.hh"
#include "sim/syscall_return.hh"
+namespace gem5
+{
+
class X86Linux : public Linux
{
public:
@@ -371,4 +374,6 @@
} tgt_sysinfo;
};
+} // namespace gem5
+
#endif
diff --git a/src/arch/x86/linux/se_workload.cc b/src/arch/x86/linux/se_workload.cc
index 1bb7d2c..a00f2b9 100644
--- a/src/arch/x86/linux/se_workload.cc
+++ b/src/arch/x86/linux/se_workload.cc
@@ -52,6 +52,9 @@
#include "sim/syscall_desc.hh"
#include "sim/syscall_emul.hh"
+namespace gem5
+{
+
namespace
{
@@ -169,3 +172,4 @@
}
} // namespace X86ISA
+} // namespace gem5
diff --git a/src/arch/x86/linux/se_workload.hh b/src/arch/x86/linux/se_workload.hh
index 85c2cb3..02a4dc2 100644
--- a/src/arch/x86/linux/se_workload.hh
+++ b/src/arch/x86/linux/se_workload.hh
@@ -47,6 +47,9 @@
#include "sim/syscall_abi.hh"
#include "sim/syscall_desc.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -64,7 +67,7 @@
gdb = BaseRemoteGDB::build<RemoteGDB>(system);
}
- ::loader::Arch getArch() const override { return ::loader::X86_64; }
+ loader::Arch getArch() const override { return loader::X86_64; }
void syscall(ThreadContext *tc) override;
void event(ThreadContext *tc) override;
@@ -113,5 +116,6 @@
};
} // namespace guest_abi
+} // namespace gem5
#endif // __ARCH_X86_LINUX_SE_WORKLOAD_HH__
diff --git a/src/arch/x86/linux/syscall_tbl32.cc b/src/arch/x86/linux/syscall_tbl32.cc
index db70151..112719c 100644
--- a/src/arch/x86/linux/syscall_tbl32.cc
+++ b/src/arch/x86/linux/syscall_tbl32.cc
@@ -32,6 +32,9 @@
#include "arch/x86/linux/syscalls.hh"
#include "sim/syscall_emul.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -371,3 +374,4 @@
};
} // namespace X86ISA
+} // namespace gem5
diff --git a/src/arch/x86/linux/syscall_tbl64.cc b/src/arch/x86/linux/syscall_tbl64.cc
index 7231595..e1eed18 100644
--- a/src/arch/x86/linux/syscall_tbl64.cc
+++ b/src/arch/x86/linux/syscall_tbl64.cc
@@ -32,6 +32,9 @@
#include "arch/x86/linux/syscalls.hh"
#include "sim/syscall_emul.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -361,3 +364,4 @@
};
} // namespace X86ISA
+} // namespace gem5
diff --git a/src/arch/x86/linux/syscalls.cc b/src/arch/x86/linux/syscalls.cc
index 194235d..bd5d571 100644
--- a/src/arch/x86/linux/syscalls.cc
+++ b/src/arch/x86/linux/syscalls.cc
@@ -37,6 +37,9 @@
#include "sim/syscall_desc.hh"
#include "sim/syscall_emul.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -170,3 +173,4 @@
}
} // namespace X86ISA
+} // namespace gem5
diff --git a/src/arch/x86/linux/syscalls.hh b/src/arch/x86/linux/syscalls.hh
index 3d0cc5d..91d57f5 100644
--- a/src/arch/x86/linux/syscalls.hh
+++ b/src/arch/x86/linux/syscalls.hh
@@ -33,6 +33,9 @@
#include "sim/se_workload.hh"
#include "sim/syscall_emul.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -63,5 +66,6 @@
VPtr<UserDesc32> userDesc);
} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_LINUX_SYSCALLS_HH__
diff --git a/src/arch/x86/locked_mem.hh b/src/arch/x86/locked_mem.hh
index adea8b7..73959b3 100644
--- a/src/arch/x86/locked_mem.hh
+++ b/src/arch/x86/locked_mem.hh
@@ -37,11 +37,15 @@
#include "arch/generic/locked_mem.hh"
+namespace gem5
+{
+
namespace X86ISA
{
using namespace GenericISA::locked_mem;
} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_LOCKEDMEM_HH__
diff --git a/src/arch/x86/memhelpers.hh b/src/arch/x86/memhelpers.hh
index 35dfac6..9ba4af8 100644
--- a/src/arch/x86/memhelpers.hh
+++ b/src/arch/x86/memhelpers.hh
@@ -37,6 +37,9 @@
#include "sim/byteswap.hh"
#include "sim/insttracer.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -254,6 +257,7 @@
return fault;
}
-}
+} // namespace X86ISA
+} // namespace gem5
#endif
diff --git a/src/arch/x86/microcode_rom.hh b/src/arch/x86/microcode_rom.hh
index 4f7952a..31693cf 100644
--- a/src/arch/x86/microcode_rom.hh
+++ b/src/arch/x86/microcode_rom.hh
@@ -33,6 +33,9 @@
#include "arch/x86/emulenv.hh"
#include "cpu/static_inst.hh"
+namespace gem5
+{
+
namespace X86ISAInst
{
@@ -74,7 +77,7 @@
using X86ISAInst::MicrocodeRom;
-}
-
+} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_MICROCODE_ROM_HH__
diff --git a/src/arch/x86/mmu.hh b/src/arch/x86/mmu.hh
index 70afea3..3f53863 100644
--- a/src/arch/x86/mmu.hh
+++ b/src/arch/x86/mmu.hh
@@ -43,6 +43,9 @@
#include "params/X86MMU.hh"
+namespace gem5
+{
+
namespace X86ISA {
class MMU : public BaseMMU
@@ -67,5 +70,6 @@
};
} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_MMU_HH__
diff --git a/src/arch/x86/nativetrace.cc b/src/arch/x86/nativetrace.cc
index c6251fc..9e357a8 100644
--- a/src/arch/x86/nativetrace.cc
+++ b/src/arch/x86/nativetrace.cc
@@ -35,6 +35,9 @@
#include "params/X86NativeTrace.hh"
#include "sim/byteswap.hh"
+namespace gem5
+{
+
namespace Trace {
void
@@ -185,3 +188,4 @@
}
} // namespace Trace
+} // namespace gem5
diff --git a/src/arch/x86/nativetrace.hh b/src/arch/x86/nativetrace.hh
index 245b0fc..295be72 100644
--- a/src/arch/x86/nativetrace.hh
+++ b/src/arch/x86/nativetrace.hh
@@ -32,6 +32,9 @@
#include "base/types.hh"
#include "cpu/nativetrace.hh"
+namespace gem5
+{
+
class ThreadContext;
namespace Trace {
@@ -85,5 +88,6 @@
};
} // namespace Trace
+} // namespace gem5
#endif // __ARCH_X86_NATIVETRACE_HH__
diff --git a/src/arch/x86/page_size.hh b/src/arch/x86/page_size.hh
index aceadd0..9ff1e7b 100644
--- a/src/arch/x86/page_size.hh
+++ b/src/arch/x86/page_size.hh
@@ -40,10 +40,14 @@
#include "base/types.hh"
+namespace gem5
+{
+
namespace X86ISA
{
const Addr PageShift = 12;
const Addr PageBytes = 1ULL << PageShift;
-}
+} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_PAGE_SIZE_HH__
diff --git a/src/arch/x86/pagetable.cc b/src/arch/x86/pagetable.cc
index 1ccc9b8..20d446d 100644
--- a/src/arch/x86/pagetable.cc
+++ b/src/arch/x86/pagetable.cc
@@ -42,6 +42,9 @@
#include "arch/x86/page_size.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -89,4 +92,5 @@
UNSERIALIZE_SCALAR(lruSeq);
}
-}
+} // namespace X86ISA
+} // namespace gem5
diff --git a/src/arch/x86/pagetable.hh b/src/arch/x86/pagetable.hh
index d56a8dd..1621f46 100644
--- a/src/arch/x86/pagetable.hh
+++ b/src/arch/x86/pagetable.hh
@@ -48,6 +48,9 @@
#include "mem/port_proxy.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
class ThreadContext;
namespace X86ISA
@@ -196,6 +199,8 @@
PageTableEntry pte;
Addr entryAddr;
};
-}
+
+} // namespace X86ISA
+} // namespace gem5
#endif
diff --git a/src/arch/x86/pagetable_walker.cc b/src/arch/x86/pagetable_walker.cc
index 4b7b88c..ab28f1a 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -62,6 +62,9 @@
#include "mem/packet_access.hh"
#include "mem/request.hh"
+namespace gem5
+{
+
namespace X86ISA {
Fault
@@ -735,4 +738,5 @@
m5reg.cpl == 3, false);
}
-/* end namespace X86ISA */ }
+} // namespace X86ISA
+} // namespace gem5
diff --git a/src/arch/x86/pagetable_walker.hh b/src/arch/x86/pagetable_walker.hh
index 4cf4bb3..42d0609 100644
--- a/src/arch/x86/pagetable_walker.hh
+++ b/src/arch/x86/pagetable_walker.hh
@@ -49,6 +49,9 @@
#include "sim/faults.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
class ThreadContext;
namespace X86ISA
@@ -205,5 +208,8 @@
{
}
};
-}
+
+} // namespace X86ISA
+} // namespace gem5
+
#endif // __ARCH_X86_PAGE_TABLE_WALKER_HH__
diff --git a/src/arch/x86/pcstate.hh b/src/arch/x86/pcstate.hh
index 8ad2d97..dd2dded 100644
--- a/src/arch/x86/pcstate.hh
+++ b/src/arch/x86/pcstate.hh
@@ -41,6 +41,9 @@
#include "arch/generic/types.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -108,6 +111,7 @@
}
};
-}
+} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_PCSTATE_HH__
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index a35d063..a50b3bf 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -66,6 +66,9 @@
#include "sim/syscall_return.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace X86ISA;
template class MultiLevelPageTable<LongModePTE<47, 39>,
@@ -1027,3 +1030,5 @@
X86Process::clone(old_tc, new_tc, p, flags);
((I386Process*)p)->vsyscallPage = vsyscallPage;
}
+
+} // namespace gem5
diff --git a/src/arch/x86/process.hh b/src/arch/x86/process.hh
index 0724029..e29a03b 100644
--- a/src/arch/x86/process.hh
+++ b/src/arch/x86/process.hh
@@ -46,6 +46,9 @@
#include "sim/aux_vector.hh"
#include "sim/process.hh"
+namespace gem5
+{
+
class SyscallDesc;
namespace X86ISA
@@ -171,6 +174,7 @@
Process *process, RegVal flags) override;
};
-}
+} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_PROCESS_HH__
diff --git a/src/arch/x86/pseudo_inst_abi.hh b/src/arch/x86/pseudo_inst_abi.hh
index deec0b5..456a18e 100644
--- a/src/arch/x86/pseudo_inst_abi.hh
+++ b/src/arch/x86/pseudo_inst_abi.hh
@@ -38,6 +38,9 @@
#include "arch/x86/regs/int.hh"
#include "sim/guest_abi.hh"
+namespace gem5
+{
+
struct X86PseudoInstABI
{
using State = int;
@@ -83,3 +86,4 @@
};
} // namespace guest_abi
+} // namespace gem5
diff --git a/src/arch/x86/regs/apic.hh b/src/arch/x86/regs/apic.hh
index b299abe..e5f5af1 100644
--- a/src/arch/x86/regs/apic.hh
+++ b/src/arch/x86/regs/apic.hh
@@ -31,6 +31,9 @@
#include "base/bitunion.hh"
+namespace gem5
+{
+
namespace X86ISA
{
enum ApicRegIndex
@@ -100,6 +103,8 @@
BitUnion32(InterruptCommandRegHigh)
Bitfield<31, 24> destination;
EndBitUnion(InterruptCommandRegHigh)
-}
+
+} // namespace X86ISA
+} // namespace gem5
#endif
diff --git a/src/arch/x86/regs/ccr.hh b/src/arch/x86/regs/ccr.hh
index e360a17..0a68e06 100644
--- a/src/arch/x86/regs/ccr.hh
+++ b/src/arch/x86/regs/ccr.hh
@@ -40,6 +40,9 @@
#include "arch/x86/x86_traits.hh"
+namespace gem5
+{
+
namespace X86ISA
{
enum CCRegIndex
@@ -52,6 +55,7 @@
NUM_CCREGS
};
-}
+} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_CCREGS_HH__
diff --git a/src/arch/x86/regs/float.hh b/src/arch/x86/regs/float.hh
index 963c111..bd98567 100644
--- a/src/arch/x86/regs/float.hh
+++ b/src/arch/x86/regs/float.hh
@@ -41,6 +41,9 @@
#include "arch/x86/x86_traits.hh"
#include "base/bitunion.hh"
+namespace gem5
+{
+
namespace X86ISA
{
enum FloatRegIndex
@@ -153,6 +156,8 @@
// Add 8 for the indices that are mapped over the fp stack
const int NumFloatRegs =
NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs + 8;
-}
+
+} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_FLOATREGS_HH__
diff --git a/src/arch/x86/regs/int.hh b/src/arch/x86/regs/int.hh
index 8c95d05..37bbe93 100644
--- a/src/arch/x86/regs/int.hh
+++ b/src/arch/x86/regs/int.hh
@@ -43,6 +43,9 @@
#include "base/logging.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
namespace X86ISA
{
BitUnion64(X86IntReg)
@@ -184,6 +187,8 @@
}
const int NumIntRegs = NUM_INTREGS;
-}
+
+} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_INTREGS_HH__
diff --git a/src/arch/x86/regs/misc.hh b/src/arch/x86/regs/misc.hh
index 496ab64..89997dc 100644
--- a/src/arch/x86/regs/misc.hh
+++ b/src/arch/x86/regs/misc.hh
@@ -49,6 +49,9 @@
#undef CR2
#undef CR3
+namespace gem5
+{
+
namespace X86ISA
{
enum CondFlagBit
@@ -1054,6 +1057,8 @@
Bitfield<11> enable;
Bitfield<8> bsp;
EndBitUnion(LocalApicBase)
-}
+
+} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_INTREGS_HH__
diff --git a/src/arch/x86/regs/msr.cc b/src/arch/x86/regs/msr.cc
index b12074b..6d9a520 100644
--- a/src/arch/x86/regs/msr.cc
+++ b/src/arch/x86/regs/msr.cc
@@ -28,6 +28,9 @@
#include "arch/x86/regs/msr.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -156,3 +159,4 @@
}
} // namespace X86ISA
+} // namespace gem5
diff --git a/src/arch/x86/regs/msr.hh b/src/arch/x86/regs/msr.hh
index 33390da..b9ce737 100644
--- a/src/arch/x86/regs/msr.hh
+++ b/src/arch/x86/regs/msr.hh
@@ -34,6 +34,9 @@
#include "arch/x86/regs/misc.hh"
#include "base/types.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -62,5 +65,6 @@
bool msrAddrToIndex(MiscRegIndex ®Num, Addr addr);
} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_REG_MSR_HH__
diff --git a/src/arch/x86/regs/segment.hh b/src/arch/x86/regs/segment.hh
index 2b0db15..714bc2e 100644
--- a/src/arch/x86/regs/segment.hh
+++ b/src/arch/x86/regs/segment.hh
@@ -38,6 +38,9 @@
#ifndef __ARCH_X86_SEGMENTREGS_HH__
#define __ARCH_X86_SEGMENTREGS_HH__
+namespace gem5
+{
+
namespace X86ISA
{
enum SegmentRegIndex
@@ -61,6 +64,7 @@
NUM_SEGMENTREGS
};
-}
+} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_SEGMENTREGS_HH__
diff --git a/src/arch/x86/remote_gdb.cc b/src/arch/x86/remote_gdb.cc
index 7570370..91a431b 100644
--- a/src/arch/x86/remote_gdb.cc
+++ b/src/arch/x86/remote_gdb.cc
@@ -61,6 +61,9 @@
#include "sim/full_system.hh"
#include "sim/workload.hh"
+namespace gem5
+{
+
using namespace X86ISA;
RemoteGDB::RemoteGDB(System *_system, int _port) :
@@ -233,3 +236,5 @@
if (r.gs != context->readMiscRegNoEffect(MISCREG_GS))
warn("Remote gdb: Ignoring update to GS.\n");
}
+
+} // namespace gem5
diff --git a/src/arch/x86/remote_gdb.hh b/src/arch/x86/remote_gdb.hh
index 3d5909f..62176a5 100644
--- a/src/arch/x86/remote_gdb.hh
+++ b/src/arch/x86/remote_gdb.hh
@@ -46,6 +46,9 @@
#include "base/compiler.hh"
#include "base/remote_gdb.hh"
+namespace gem5
+{
+
class System;
class ThreadContext;
@@ -146,6 +149,8 @@
RemoteGDB(System *system, int _port);
BaseGdbRegCache *gdbRegs();
};
+
} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_REMOTEGDB_HH__
diff --git a/src/arch/x86/se_workload.hh b/src/arch/x86/se_workload.hh
index 1a6ba2a..49ddf20 100644
--- a/src/arch/x86/se_workload.hh
+++ b/src/arch/x86/se_workload.hh
@@ -30,6 +30,9 @@
#include "base/types.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -45,5 +48,6 @@
const Addr MMIORegionPhysAddr = 0xffff0000;
} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_SE_WORKLOAD_HH__
diff --git a/src/arch/x86/stacktrace.hh b/src/arch/x86/stacktrace.hh
index 8fa3b65..2ca5501 100644
--- a/src/arch/x86/stacktrace.hh
+++ b/src/arch/x86/stacktrace.hh
@@ -31,6 +31,9 @@
#include "cpu/profile.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -41,5 +44,6 @@
};
} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_STACKTRACE_HH__
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 90e43b9..3f05792 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -57,6 +57,9 @@
#include "sim/process.hh"
#include "sim/pseudo_inst.hh"
+namespace gem5
+{
+
namespace X86ISA {
TLB::TLB(const Params &p)
@@ -575,3 +578,4 @@
}
} // namespace X86ISA
+} // namespace gem5
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 738a703..4d83cc7 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -48,6 +48,9 @@
#include "params/X86TLB.hh"
#include "sim/stats.hh"
+namespace gem5
+{
+
class ThreadContext;
namespace X86ISA
@@ -169,6 +172,8 @@
*/
Port *getTableWalkerPort() override;
};
-}
+
+} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_TLB_HH__
diff --git a/src/arch/x86/types.cc b/src/arch/x86/types.cc
index 5806623..258f902 100644
--- a/src/arch/x86/types.cc
+++ b/src/arch/x86/types.cc
@@ -30,6 +30,9 @@
#include "sim/serialize.hh"
+namespace gem5
+{
+
using namespace X86ISA;
template <>
@@ -105,3 +108,5 @@
paramIn(cp, name + ".mode", temp8);
machInst.mode = temp8;
}
+
+} // namespace gem5
diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh
index ce03de2..a2c2771 100644
--- a/src/arch/x86/types.hh
+++ b/src/arch/x86/types.hh
@@ -46,6 +46,9 @@
#include "base/bitunion.hh"
#include "base/cprintf.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -287,16 +290,27 @@
return true;
}
-}
+} // namespace X86ISA
+
+// These two functions allow ExtMachInst to be used with SERIALIZE_SCALAR
+// and UNSERIALIZE_SCALAR.
+template <>
+void paramOut(CheckpointOut &cp, const std::string &name,
+ const X86ISA::ExtMachInst &machInst);
+template <>
+void paramIn(CheckpointIn &cp, const std::string &name,
+ X86ISA::ExtMachInst &machInst);
+
+} // namespace gem5
namespace std
{
template<>
-struct hash<X86ISA::ExtMachInst>
+struct hash<gem5::X86ISA::ExtMachInst>
{
size_t
- operator()(const X86ISA::ExtMachInst &emi) const
+ operator()(const gem5::X86ISA::ExtMachInst &emi) const
{
return (((uint64_t)emi.legacy << 48) |
((uint64_t)emi.rex << 40) |
@@ -312,15 +326,6 @@
};
};
-}
-
-// These two functions allow ExtMachInst to be used with SERIALIZE_SCALAR
-// and UNSERIALIZE_SCALAR.
-template <>
-void paramOut(CheckpointOut &cp, const std::string &name,
- const X86ISA::ExtMachInst &machInst);
-template <>
-void paramIn(CheckpointIn &cp, const std::string &name,
- X86ISA::ExtMachInst &machInst);
+} // namespace std
#endif // __ARCH_X86_TYPES_HH__
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index e3add56..6b31d55 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -48,6 +48,9 @@
#include "cpu/base.hh"
#include "fputils/fp80.h"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -166,3 +169,4 @@
}
} // namespace X86_ISA
+} // namespace gem5
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 0c0b1c0..94a0a4b 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -42,6 +42,9 @@
#include "cpu/thread_context.hh"
#include "sim/full_system.hh"
+namespace gem5
+{
+
namespace X86ISA
{
/**
@@ -134,6 +137,8 @@
* @param value Double precision float to store.
*/
void storeFloat80(void *mem, double value);
-}
+
+} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_UTILITY_HH__
diff --git a/src/arch/x86/vecregs.hh b/src/arch/x86/vecregs.hh
index 43f58bf..578360b 100644
--- a/src/arch/x86/vecregs.hh
+++ b/src/arch/x86/vecregs.hh
@@ -46,17 +46,21 @@
#include "arch/x86/regs/int.hh"
#include "arch/x86/regs/misc.hh"
+namespace gem5
+{
+
namespace X86ISA
{
// Not applicable to x86
-using VecElem = ::DummyVecElem;
-using VecRegContainer = ::DummyVecRegContainer;
-constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
+using VecElem = ::gem5::DummyVecElem;
+using VecRegContainer = ::gem5::DummyVecRegContainer;
+constexpr unsigned NumVecElemPerVecReg = ::gem5::DummyNumVecElemPerVecReg;
// Not applicable to x86
-using VecPredRegContainer = ::DummyVecPredRegContainer;
+using VecPredRegContainer = ::gem5::DummyVecPredRegContainer;
} // namespace X86ISA
+} // namespace gem5
#endif // __ARCH_X86_VECREGS_HH__
diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh
index 37496a6..9e98820 100644
--- a/src/arch/x86/x86_traits.hh
+++ b/src/arch/x86/x86_traits.hh
@@ -42,6 +42,9 @@
#include "base/types.hh"
+namespace gem5
+{
+
namespace X86ISA
{
const int NumMicroIntRegs = 16;
@@ -94,6 +97,8 @@
assert(addr < PhysAddrAPICRangeSize);
return PhysAddrPrefixInterrupts | (id * PhysAddrAPICRangeSize) | addr;
}
-}
+
+} // namespace X86ISA
+} // namespace gem5
#endif //__ARCH_X86_X86TRAITS_HH__
diff --git a/src/base/addr_range.hh b/src/base/addr_range.hh
index 405d8ba..6531a0b 100644
--- a/src/base/addr_range.hh
+++ b/src/base/addr_range.hh
@@ -50,6 +50,9 @@
#include "base/logging.hh"
#include "base/types.hh"
+namespace gem5
+{
+
/**
* The AddrRange class encapsulates an address range, and supports a
* number of tests to check if two ranges intersect, if a range
@@ -658,4 +661,6 @@
RangeSize(Addr start, Addr size)
{ return AddrRange(start, start + size); }
+} // namespace gem5
+
#endif // __BASE_ADDR_RANGE_HH__
diff --git a/src/base/addr_range.test.cc b/src/base/addr_range.test.cc
index 0abd517..00cf251 100644
--- a/src/base/addr_range.test.cc
+++ b/src/base/addr_range.test.cc
@@ -43,6 +43,8 @@
#include "base/addr_range.hh"
#include "base/bitfield.hh"
+using namespace gem5;
+
TEST(AddrRangeTest, ValidRange)
{
AddrRange r;
diff --git a/src/base/addr_range_map.hh b/src/base/addr_range_map.hh
index 57784b4..c953231 100644
--- a/src/base/addr_range_map.hh
+++ b/src/base/addr_range_map.hh
@@ -50,6 +50,9 @@
#include "base/addr_range.hh"
#include "base/types.hh"
+namespace gem5
+{
+
/**
* The AddrRangeMap uses an STL map to implement an interval tree for
* address decoding. The value stored is a template type and can be
@@ -334,4 +337,6 @@
mutable std::list<iterator> cache;
};
+} // namespace gem5
+
#endif //__BASE_ADDR_RANGE_MAP_HH__
diff --git a/src/base/addr_range_map.test.cc b/src/base/addr_range_map.test.cc
index 74f6bff..a2d2b56 100644
--- a/src/base/addr_range_map.test.cc
+++ b/src/base/addr_range_map.test.cc
@@ -44,6 +44,8 @@
#include "base/addr_range_map.hh"
+using namespace gem5;
+
// Converted from legacy unit test framework
TEST(AddrRangeMapTest, LegacyTests)
{
diff --git a/src/base/amo.hh b/src/base/amo.hh
index 23be57d..81bf069 100644
--- a/src/base/amo.hh
+++ b/src/base/amo.hh
@@ -37,6 +37,9 @@
#include <functional>
#include <memory>
+namespace gem5
+{
+
struct AtomicOpFunctor
{
/**
@@ -238,4 +241,6 @@
*/
typedef std::unique_ptr<AtomicOpFunctor> AtomicOpFunctorPtr;
+} // namespace gem5
+
#endif // __BASE_AMO_HH__
diff --git a/src/base/amo.test.cc b/src/base/amo.test.cc
index e1a56c1..10e5540 100644
--- a/src/base/amo.test.cc
+++ b/src/base/amo.test.cc
@@ -35,6 +35,8 @@
#include "base/amo.hh"
+using namespace gem5;
+
void
multiply2Op(int *b, int a)
{
diff --git a/src/base/atomicio.cc b/src/base/atomicio.cc
index 7dca8fb..6705c8a 100644
--- a/src/base/atomicio.cc
+++ b/src/base/atomicio.cc
@@ -31,6 +31,9 @@
#include <cerrno>
#include <cstdio>
+namespace gem5
+{
+
ssize_t
atomic_read(int fd, void *s, size_t n)
{
@@ -88,3 +91,5 @@
return pos;
}
+
+} // namespace gem5
diff --git a/src/base/atomicio.hh b/src/base/atomicio.hh
index 572ca18..44e3431 100644
--- a/src/base/atomicio.hh
+++ b/src/base/atomicio.hh
@@ -31,6 +31,9 @@
#include <unistd.h>
+namespace gem5
+{
+
// These functions keep reading/writing, if possible, until all data
// has been transferred. Basically, try again when there's no error,
// but there is data left also retry on EINTR.
@@ -63,4 +66,6 @@
*/
#define STATIC_ERR(m) STATIC_MSG(STDERR_FILENO, m)
+} // namespace gem5
+
#endif // __BASE_ATOMICIO_HH__
diff --git a/src/base/atomicio.test.cc b/src/base/atomicio.test.cc
index 1801d2c..0b5aa50 100644
--- a/src/base/atomicio.test.cc
+++ b/src/base/atomicio.test.cc
@@ -42,6 +42,8 @@
#include "base/atomicio.hh"
+using namespace gem5;
+
/*
* This will test reading from a file with a buffer capable of storing the
* entirity of the file.
diff --git a/src/base/barrier.hh b/src/base/barrier.hh
index eabe434..9ed6cd8 100644
--- a/src/base/barrier.hh
+++ b/src/base/barrier.hh
@@ -40,6 +40,9 @@
#include <condition_variable>
+namespace gem5
+{
+
class Barrier
{
private:
@@ -77,4 +80,6 @@
}
};
+} // namespace gem5
+
#endif // __BASE_BARRIER_HH__
diff --git a/src/base/bitfield.cc b/src/base/bitfield.cc
index 47055df..720292b 100644
--- a/src/base/bitfield.cc
+++ b/src/base/bitfield.cc
@@ -37,6 +37,9 @@
#include "base/bitfield.hh"
+namespace gem5
+{
+
/** Lookup table used for High Speed bit reversing */
const uint8_t reverseBitsLookUpTable[] =
{
@@ -63,3 +66,5 @@
0x0F, 0x8F, 0x4F, 0xCF, 0x2F, 0xAF, 0x6F, 0xEF, 0x1F, 0x9F, 0x5F, 0xDF,
0x3F, 0xBF, 0x7F, 0xFF
};
+
+} // namespace gem5
diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh
index 888b365..30cc952 100644
--- a/src/base/bitfield.hh
+++ b/src/base/bitfield.hh
@@ -46,6 +46,9 @@
#include <cstdint>
#include <type_traits>
+namespace gem5
+{
+
extern const uint8_t reverseBitsLookUpTable[];
/**
@@ -408,4 +411,6 @@
return value ? __builtin_ctzll(value) : 64;
}
+} // namespace gem5
+
#endif // __BASE_BITFIELD_HH__
diff --git a/src/base/bitfield.test.cc b/src/base/bitfield.test.cc
index c2ef8d2..516e751 100644
--- a/src/base/bitfield.test.cc
+++ b/src/base/bitfield.test.cc
@@ -39,6 +39,8 @@
#include "base/bitfield.hh"
+using namespace gem5;
+
/*
* The following tests the "mask(N)" function. It is assumed that the mask
* returned is a 64 bit value with the N LSBs set to one.
diff --git a/src/base/bitunion.hh b/src/base/bitunion.hh
index a4eb354..d062443 100644
--- a/src/base/bitunion.hh
+++ b/src/base/bitunion.hh
@@ -38,6 +38,9 @@
#include "base/compiler.hh"
#include "sim/serialize_handlers.hh"
+namespace gem5
+{
+
// The following implements the BitUnion system of defining bitfields
//on top of an underlying class. This is done through the pervasive use of
//both named and unnamed unions which all contain the same actual storage.
@@ -402,14 +405,14 @@
//overhead.
#define __BitUnion(type, name) \
class BitfieldUnderlyingClasses##name : \
- public bitfield_backend::BitfieldTypes<type> \
+ public gem5::bitfield_backend::BitfieldTypes<type> \
{ \
protected: \
typedef type __StorageType; \
- friend bitfield_backend::BitUnionBaseType< \
- bitfield_backend::BitUnionOperators< \
+ friend gem5::bitfield_backend::BitUnionBaseType< \
+ gem5::bitfield_backend::BitUnionOperators< \
BitfieldUnderlyingClasses##name> >; \
- friend bitfield_backend::BitUnionBaseType< \
+ friend gem5::bitfield_backend::BitUnionBaseType< \
BitfieldUnderlyingClasses##name>; \
public: \
union { \
@@ -426,7 +429,7 @@
#define EndBitUnion(name) \
}; \
}; \
- typedef bitfield_backend::BitUnionOperators< \
+ typedef gem5::bitfield_backend::BitUnionOperators< \
BitfieldUnderlyingClasses##name> name;
//This sets up a bitfield which has other bitfields nested inside of it. The
@@ -537,21 +540,6 @@
template <typename T>
using BitUnionBaseType = typename bitfield_backend::BitUnionBaseType<T>::Type;
-
-//An STL style hash structure for hashing BitUnions based on their base type.
-namespace std
-{
- template <typename T>
- struct hash<BitUnionType<T> > : public hash<BitUnionBaseType<T> >
- {
- size_t
- operator() (const BitUnionType<T> &val) const
- {
- return hash<BitUnionBaseType<T> >::operator()(val);
- }
- };
-} // namespace std
-
namespace bitfield_backend
{
template<typename T>
@@ -622,4 +610,20 @@
}
};
+} // namespace gem5
+
+//An STL style hash structure for hashing BitUnions based on their base type.
+namespace std
+{
+ template <typename T>
+ struct hash<gem5::BitUnionType<T>> : public hash<gem5::BitUnionBaseType<T>>
+ {
+ size_t
+ operator() (const gem5::BitUnionType<T> &val) const
+ {
+ return hash<gem5::BitUnionBaseType<T> >::operator()(val);
+ }
+ };
+} // namespace std
+
#endif // __BASE_BITUNION_HH__
diff --git a/src/base/bitunion.test.cc b/src/base/bitunion.test.cc
index ced108b..ee12be7 100644
--- a/src/base/bitunion.test.cc
+++ b/src/base/bitunion.test.cc
@@ -34,6 +34,8 @@
#include "base/bitunion.hh"
#include "base/cprintf.hh"
+using namespace gem5;
+
namespace {
BitUnion64(SixtyFour)
diff --git a/src/base/bmpwriter.cc b/src/base/bmpwriter.cc
index 121d1bf..2bb8aef 100644
--- a/src/base/bmpwriter.cc
+++ b/src/base/bmpwriter.cc
@@ -41,6 +41,9 @@
#include "base/logging.hh"
+namespace gem5
+{
+
const char* BmpWriter::_imgExtension = "bmp";
// bitmap class ctor
@@ -105,4 +108,4 @@
bmp.flush();
}
-
+} // namespace gem5
diff --git a/src/base/bmpwriter.hh b/src/base/bmpwriter.hh
index 4d75861..a014228 100644
--- a/src/base/bmpwriter.hh
+++ b/src/base/bmpwriter.hh
@@ -47,6 +47,9 @@
* @file Declaration of a class that writes a frame buffer to a bitmap
*/
+namespace gem5
+{
+
// write frame buffer into a bitmap picture
class BmpWriter : public ImgWriter
{
@@ -129,6 +132,6 @@
const CompleteV1Header getCompleteHeader() const;
};
+} // namespace gem5
#endif // __BASE_BITMAP_HH__
-
diff --git a/src/base/callback.hh b/src/base/callback.hh
index bedbba3..84d7ce9 100644
--- a/src/base/callback.hh
+++ b/src/base/callback.hh
@@ -32,6 +32,9 @@
#include <functional>
#include <list>
+namespace gem5
+{
+
class CallbackQueue : public std::list<std::function<void()>>
{
public:
@@ -50,4 +53,6 @@
}
};
+} // namespace gem5
+
#endif // __BASE_CALLBACK_HH__
diff --git a/src/base/cast.hh b/src/base/cast.hh
index 5b2e671..cdc3c62 100644
--- a/src/base/cast.hh
+++ b/src/base/cast.hh
@@ -31,6 +31,9 @@
#include <cassert>
+namespace gem5
+{
+
// This is designed for situations where we have a pointer to a base
// type, but in all cases when we cast it to a derived type, we know
// by construction that it should work correctly.
@@ -63,4 +66,6 @@
#endif
+} // namespace gem5
+
#endif // __BASE_CAST_HH__
diff --git a/src/base/channel_addr.cc b/src/base/channel_addr.cc
index c061f49..9cc155a 100644
--- a/src/base/channel_addr.cc
+++ b/src/base/channel_addr.cc
@@ -39,6 +39,9 @@
#include "base/logging.hh"
+namespace gem5
+{
+
ChannelAddrRange::ChannelAddrRange(AddrRange ch_range, Addr start, Addr end)
: ChannelAddrRange(ChannelAddr(ch_range, start),
ChannelAddr(ch_range, end))
@@ -59,3 +62,5 @@
{
return out << (ChannelAddr::Type)addr;
}
+
+} // namespace gem5
diff --git a/src/base/channel_addr.hh b/src/base/channel_addr.hh
index ad32d04..cb9d0eb 100644
--- a/src/base/channel_addr.hh
+++ b/src/base/channel_addr.hh
@@ -42,6 +42,9 @@
#include "base/addr_range.hh"
+namespace gem5
+{
+
/**
* Class holding a guest address in a contiguous channel-local address
* space.
@@ -192,25 +195,28 @@
ChannelAddr _end;
};
+/**
+ * @ingroup api_channel_addr
+ */
+std::ostream &operator<<(std::ostream &out, const gem5::ChannelAddr &addr);
+
+} // namespace gem5
+
namespace std
{
template<>
- struct hash<ChannelAddr>
+ struct hash<gem5::ChannelAddr>
{
- typedef ChannelAddr argument_type;
+ typedef gem5::ChannelAddr argument_type;
typedef std::size_t result_type;
result_type
- operator()(argument_type const &a) const noexcept {
- return std::hash<ChannelAddr::Type>{}(
+ operator()(argument_type const &a) const noexcept
+ {
+ return std::hash<gem5::ChannelAddr::Type>{}(
static_cast<argument_type::Type>(a));
}
};
}
-/**
- * @ingroup api_channel_addr
- */
-std::ostream &operator<<(std::ostream &out, const ChannelAddr &addr);
-
#endif // __BASE_CHANNEL_ADDR_HH__
diff --git a/src/base/channel_addr.test.cc b/src/base/channel_addr.test.cc
index 01aa8b7..4481369 100644
--- a/src/base/channel_addr.test.cc
+++ b/src/base/channel_addr.test.cc
@@ -39,6 +39,8 @@
#include "base/channel_addr.hh"
+using namespace gem5;
+
/* Default range should be invalid */
TEST(ChannelAddrRange, DefaultInvalid)
{
diff --git a/src/base/chunk_generator.hh b/src/base/chunk_generator.hh
index e95f4fd..4293941 100644
--- a/src/base/chunk_generator.hh
+++ b/src/base/chunk_generator.hh
@@ -40,6 +40,9 @@
#include "base/intmath.hh"
#include "base/types.hh"
+namespace gem5
+{
+
/**
* This class takes an arbitrary memory region (address/length pair)
* and generates a series of appropriately (e.g. block- or page-)
@@ -195,4 +198,6 @@
}
};
+} // namespace gem5
+
#endif // __BASE_CHUNK_GENERATOR_HH__
diff --git a/src/base/chunk_generator.test.cc b/src/base/chunk_generator.test.cc
index f5d7048..bd9b906 100644
--- a/src/base/chunk_generator.test.cc
+++ b/src/base/chunk_generator.test.cc
@@ -30,6 +30,7 @@
#include "chunk_generator.hh"
+using namespace gem5;
/*
* A test to ensure the object is in a sane state after initialization.
diff --git a/src/base/circlebuf.hh b/src/base/circlebuf.hh
index 77a05d7..edd3bbf 100644
--- a/src/base/circlebuf.hh
+++ b/src/base/circlebuf.hh
@@ -46,6 +46,9 @@
#include "base/logging.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
/**
* Circular buffer backed by a vector.
*
@@ -283,4 +286,6 @@
param.write(temp.cbegin(), temp.size());
}
+} // namespace gem5
+
#endif // __BASE_CIRCLEBUF_HH__
diff --git a/src/base/circlebuf.test.cc b/src/base/circlebuf.test.cc
index 2e1f6bd..02fe396 100644
--- a/src/base/circlebuf.test.cc
+++ b/src/base/circlebuf.test.cc
@@ -43,6 +43,7 @@
#include "base/circlebuf.hh"
using testing::ElementsAreArray;
+using namespace gem5;
const char data[] = {
0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
diff --git a/src/base/circular_queue.hh b/src/base/circular_queue.hh
index 5425633..859d12e 100644
--- a/src/base/circular_queue.hh
+++ b/src/base/circular_queue.hh
@@ -45,6 +45,9 @@
#include <type_traits>
#include <vector>
+namespace gem5
+{
+
/** Circular queue.
* Circular queue implemented in a standard vector. All indices are
* monotonically increasing, and modulo is used at access time to alias them
@@ -589,4 +592,6 @@
iterator getIterator(size_t idx) { return iterator(this, idx); }
};
+} // namespace gem5
+
#endif /* __BASE_CIRCULARQUEUE_HH__ */
diff --git a/src/base/circular_queue.test.cc b/src/base/circular_queue.test.cc
index ffbdce2..0196aa4 100644
--- a/src/base/circular_queue.test.cc
+++ b/src/base/circular_queue.test.cc
@@ -39,6 +39,8 @@
#include "base/circular_queue.hh"
+using namespace gem5;
+
/** Testing that once instantiated with a fixed size,
* the queue is still empty */
TEST(CircularQueueTest, Empty)
diff --git a/src/base/condcodes.hh b/src/base/condcodes.hh
index b15fec0..4e998dc 100644
--- a/src/base/condcodes.hh
+++ b/src/base/condcodes.hh
@@ -31,6 +31,9 @@
#include "base/bitfield.hh"
+namespace gem5
+{
+
/**
* Calculate the carry flag from an addition. This should work even when
* a carry value is also added in.
@@ -151,4 +154,6 @@
return !(dest & mask(width));
}
+} // namespace gem5
+
#endif // __BASE_CONDCODE_HH__
diff --git a/src/base/condcodes.test.cc b/src/base/condcodes.test.cc
index 8b02dbd..62f8c88 100644
--- a/src/base/condcodes.test.cc
+++ b/src/base/condcodes.test.cc
@@ -30,6 +30,8 @@
#include "base/condcodes.hh"
+using namespace gem5;
+
/*
* Add 0x80 + 0x80 to get 0x100. findCarry should report a carry flag after
* this operation.
diff --git a/src/base/cprintf.cc b/src/base/cprintf.cc
index 24a2d00..327b735 100644
--- a/src/base/cprintf.cc
+++ b/src/base/cprintf.cc
@@ -34,6 +34,9 @@
#include "base/compiler.hh"
+namespace gem5
+{
+
namespace cp
{
@@ -313,3 +316,4 @@
}
} // namespace cp
+} // namespace gem5
diff --git a/src/base/cprintf.hh b/src/base/cprintf.hh
index 34fd304..a34af4c 100644
--- a/src/base/cprintf.hh
+++ b/src/base/cprintf.hh
@@ -37,6 +37,9 @@
#include "base/cprintf_formats.hh"
+namespace gem5
+{
+
namespace cp {
struct Print
@@ -185,4 +188,6 @@
return csprintf(format.c_str(), args...);
}
+} // namespace gem5
+
#endif // __CPRINTF_HH__
diff --git a/src/base/cprintf.test.cc b/src/base/cprintf.test.cc
index a64a52b..761258c 100644
--- a/src/base/cprintf.test.cc
+++ b/src/base/cprintf.test.cc
@@ -34,6 +34,8 @@
#include "base/cprintf.hh"
+using namespace gem5;
+
#define CPRINTF_TEST(...) \
do { \
std::stringstream ss; \
diff --git a/src/base/cprintf_formats.hh b/src/base/cprintf_formats.hh
index a7c221d..02ba496 100644
--- a/src/base/cprintf_formats.hh
+++ b/src/base/cprintf_formats.hh
@@ -33,6 +33,9 @@
#include <ostream>
#include <sstream>
+namespace gem5
+{
+
namespace cp
{
@@ -388,5 +391,6 @@
}
} // namespace cp
+} // namespace gem5
#endif // __CPRINTF_FORMATS_HH__
diff --git a/src/base/cprintftime.cc b/src/base/cprintftime.cc
index a09c4cb..abd20fe 100644
--- a/src/base/cprintftime.cc
+++ b/src/base/cprintftime.cc
@@ -36,6 +36,9 @@
#include "base/cprintf.hh"
+namespace gem5
+{
+
volatile int stop = false;
void
@@ -87,3 +90,5 @@
return 0;
}
+
+} // namespace gem5
diff --git a/src/base/crc.hh b/src/base/crc.hh
index b2b6c14..9baf0ead 100644
--- a/src/base/crc.hh
+++ b/src/base/crc.hh
@@ -40,6 +40,9 @@
#include "base/bitfield.hh"
+namespace gem5
+{
+
/**
* Evaluate the CRC32 of the first size bytes of a data buffer,
* using a specific polynomium and an initial value.
@@ -78,4 +81,6 @@
return reverseBits(crc);
}
+} // namespace gem5
+
#endif // __BASE_CRC_HH__
diff --git a/src/base/date.cc b/src/base/date.cc
index bec3490..bf830af 100644
--- a/src/base/date.cc
+++ b/src/base/date.cc
@@ -26,7 +26,12 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+namespace gem5
+{
+
/**
* @ingroup api_base_utils
*/
const char *compileDate = __DATE__ " " __TIME__;
+
+} // namespace gem5
diff --git a/src/base/debug.cc b/src/base/debug.cc
index 34bc4f4..74107fe 100644
--- a/src/base/debug.cc
+++ b/src/base/debug.cc
@@ -49,6 +49,9 @@
#include "base/cprintf.hh"
#include "base/logging.hh"
+namespace gem5
+{
+
namespace Debug {
//
@@ -178,3 +181,5 @@
ccprintf(os, "%s\n", f->name());
}
}
+
+} // namespace gem5
diff --git a/src/base/debug.hh b/src/base/debug.hh
index 19c42c2..c678a25 100644
--- a/src/base/debug.hh
+++ b/src/base/debug.hh
@@ -48,7 +48,8 @@
#include <string>
#include <vector>
-#include "base/compiler.hh"
+namespace gem5
+{
namespace Debug {
@@ -156,4 +157,6 @@
"Replace DTRACE(x) with Debug::x.")
/** @} */ // end of api_trace
+} // namespace gem5
+
#endif // __BASE_DEBUG_HH__
diff --git a/src/base/debug.test.cc b/src/base/debug.test.cc
index b0f3a5d..81eb6b7 100644
--- a/src/base/debug.test.cc
+++ b/src/base/debug.test.cc
@@ -31,6 +31,8 @@
#include "base/debug.hh"
#include "base/gtest/logging.hh"
+using namespace gem5;
+
/** Test assignment of names and descriptions. */
TEST(DebugFlagTest, NameDesc)
{
diff --git a/src/base/fiber.cc b/src/base/fiber.cc
index e414bd2..0b7a6e2 100644
--- a/src/base/fiber.cc
+++ b/src/base/fiber.cc
@@ -48,6 +48,9 @@
#include "base/logging.hh"
+namespace gem5
+{
+
namespace
{
@@ -181,3 +184,5 @@
Fiber *Fiber::currentFiber() { return _currentFiber; }
Fiber *Fiber::primaryFiber() { return &_primaryFiber; }
+
+} // namespace gem5
diff --git a/src/base/fiber.hh b/src/base/fiber.hh
index be8937f..5a9acf2 100644
--- a/src/base/fiber.hh
+++ b/src/base/fiber.hh
@@ -50,6 +50,9 @@
#include "config/have_valgrind.hh"
+namespace gem5
+{
+
/**
* This class represents a fiber, which is a light weight sort of thread which
* is cooperatively scheduled and runs sequentially with other fibers, swapping
@@ -163,4 +166,6 @@
void createContext();
};
+} // namespace gem5
+
#endif // __BASE_FIBER_HH__
diff --git a/src/base/fiber.test.cc b/src/base/fiber.test.cc
index 5a16760..c14aad4 100644
--- a/src/base/fiber.test.cc
+++ b/src/base/fiber.test.cc
@@ -45,6 +45,8 @@
#include "base/fiber.hh"
+using namespace gem5;
+
/** This test is checking if the "started" member has its expected
* value before and after the fiber runs. In the test an empty fiber
* is used since we are just interested on the _started member and
diff --git a/src/base/filters/BloomFilters.py b/src/base/filters/BloomFilters.py
index 4808b19..02d2052 100644
--- a/src/base/filters/BloomFilters.py
+++ b/src/base/filters/BloomFilters.py
@@ -32,7 +32,7 @@
type = 'BloomFilterBase'
abstract = True
cxx_header = "base/filters/base.hh"
- cxx_class = 'bloom_filter::Base'
+ cxx_class = 'gem5::bloom_filter::Base'
size = Param.Int(4096, "Number of entries in the filter")
@@ -45,7 +45,7 @@
class BloomFilterBlock(BloomFilterBase):
type = 'BloomFilterBlock'
- cxx_class = 'bloom_filter::Block'
+ cxx_class = 'gem5::bloom_filter::Block'
cxx_header = "base/filters/block_bloom_filter.hh"
masks_lsbs = VectorParam.Unsigned([Self.offset_bits,
@@ -55,7 +55,7 @@
class BloomFilterMultiBitSel(BloomFilterBase):
type = 'BloomFilterMultiBitSel'
- cxx_class = 'bloom_filter::MultiBitSel'
+ cxx_class = 'gem5::bloom_filter::MultiBitSel'
cxx_header = "base/filters/multi_bit_sel_bloom_filter.hh"
num_hashes = Param.Int(4, "Number of hashes")
@@ -65,17 +65,17 @@
class BloomFilterBulk(BloomFilterMultiBitSel):
type = 'BloomFilterBulk'
- cxx_class = 'bloom_filter::Bulk'
+ cxx_class = 'gem5::bloom_filter::Bulk'
cxx_header = "base/filters/bulk_bloom_filter.hh"
class BloomFilterH3(BloomFilterMultiBitSel):
type = 'BloomFilterH3'
- cxx_class = 'bloom_filter::H3'
+ cxx_class = 'gem5::bloom_filter::H3'
cxx_header = "base/filters/h3_bloom_filter.hh"
class BloomFilterMulti(BloomFilterBase):
type = 'BloomFilterMulti'
- cxx_class = 'bloom_filter::Multi'
+ cxx_class = 'gem5::bloom_filter::Multi'
cxx_header = "base/filters/multi_bloom_filter.hh"
# The base filter should not be used, since this filter is the combination
@@ -93,7 +93,7 @@
class BloomFilterPerfect(BloomFilterBase):
type = 'BloomFilterPerfect'
- cxx_class = 'bloom_filter::Perfect'
+ cxx_class = 'gem5::bloom_filter::Perfect'
cxx_header = "base/filters/perfect_bloom_filter.hh"
# The base filter is not needed. Use a dummy value.
diff --git a/src/base/filters/base.hh b/src/base/filters/base.hh
index 7ab9663..f2b9fce 100644
--- a/src/base/filters/base.hh
+++ b/src/base/filters/base.hh
@@ -39,6 +39,9 @@
#include "params/BloomFilterBase.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(BloomFilter, bloom_filter);
namespace bloom_filter
{
@@ -150,5 +153,6 @@
};
} // namespace bloom_filter
+} // namespace gem5
#endif // __BASE_FILTERS_BASE_HH__
diff --git a/src/base/filters/block_bloom_filter.cc b/src/base/filters/block_bloom_filter.cc
index 13447b1..e1ae116 100644
--- a/src/base/filters/block_bloom_filter.cc
+++ b/src/base/filters/block_bloom_filter.cc
@@ -33,6 +33,9 @@
#include "base/logging.hh"
#include "params/BloomFilterBlock.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(BloomFilter, bloom_filter);
namespace bloom_filter
{
@@ -92,3 +95,4 @@
}
} // namespace bloom_filter
+} // namespace gem5
diff --git a/src/base/filters/block_bloom_filter.hh b/src/base/filters/block_bloom_filter.hh
index ba1a88c..0375d30 100644
--- a/src/base/filters/block_bloom_filter.hh
+++ b/src/base/filters/block_bloom_filter.hh
@@ -34,6 +34,9 @@
#include "base/filters/base.hh"
+namespace gem5
+{
+
struct BloomFilterBlockParams;
GEM5_DEPRECATED_NAMESPACE(BloomFilter, bloom_filter);
@@ -71,5 +74,6 @@
};
} // namespace bloom_filter
+} // namespace gem5
#endif // __BASE_FILTERS_BLOCK_BLOOM_FILTER_HH__
diff --git a/src/base/filters/bulk_bloom_filter.cc b/src/base/filters/bulk_bloom_filter.cc
index fb47b9d..3a2ac58 100644
--- a/src/base/filters/bulk_bloom_filter.cc
+++ b/src/base/filters/bulk_bloom_filter.cc
@@ -35,6 +35,9 @@
#include "base/logging.hh"
#include "params/BloomFilterBulk.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(BloomFilter, bloom_filter);
namespace bloom_filter
{
@@ -98,3 +101,4 @@
}
} // namespace bloom_filter
+} // namespace gem5
diff --git a/src/base/filters/bulk_bloom_filter.hh b/src/base/filters/bulk_bloom_filter.hh
index c87d6ae..985fcb3 100644
--- a/src/base/filters/bulk_bloom_filter.hh
+++ b/src/base/filters/bulk_bloom_filter.hh
@@ -32,6 +32,9 @@
#include "base/filters/multi_bit_sel_bloom_filter.hh"
+namespace gem5
+{
+
struct BloomFilterBulkParams;
GEM5_DEPRECATED_NAMESPACE(BloomFilter, bloom_filter);
@@ -66,5 +69,6 @@
};
} // namespace bloom_filter
+} // namespace gem5
#endif // __BASE_FILTERS_BULK_BLOOM_FILTER_HH__
diff --git a/src/base/filters/h3_bloom_filter.cc b/src/base/filters/h3_bloom_filter.cc
index 65a4583..e1aeba7 100644
--- a/src/base/filters/h3_bloom_filter.cc
+++ b/src/base/filters/h3_bloom_filter.cc
@@ -35,6 +35,9 @@
#include "base/logging.hh"
#include "params/BloomFilterH3.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(BloomFilter, bloom_filter);
namespace bloom_filter
{
@@ -392,3 +395,4 @@
}
} // namespace bloom_filter
+} // namespace gem5
diff --git a/src/base/filters/h3_bloom_filter.hh b/src/base/filters/h3_bloom_filter.hh
index 65f9553..a60c212 100644
--- a/src/base/filters/h3_bloom_filter.hh
+++ b/src/base/filters/h3_bloom_filter.hh
@@ -32,6 +32,9 @@
#include "base/filters/multi_bit_sel_bloom_filter.hh"
+namespace gem5
+{
+
struct BloomFilterH3Params;
GEM5_DEPRECATED_NAMESPACE(BloomFilter, bloom_filter);
@@ -53,5 +56,6 @@
};
} // namespace bloom_filter
+} // namespace gem5
#endif // __BASE_FILTERS_H3_BLOOM_FILTER_HH__
diff --git a/src/base/filters/multi_bit_sel_bloom_filter.cc b/src/base/filters/multi_bit_sel_bloom_filter.cc
index 282a105..4bb3d08 100644
--- a/src/base/filters/multi_bit_sel_bloom_filter.cc
+++ b/src/base/filters/multi_bit_sel_bloom_filter.cc
@@ -35,6 +35,9 @@
#include "base/logging.hh"
#include "params/BloomFilterMultiBitSel.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(BloomFilter, bloom_filter);
namespace bloom_filter
{
@@ -96,4 +99,5 @@
}
} // namespace bloom_filter
+} // namespace gem5
diff --git a/src/base/filters/multi_bit_sel_bloom_filter.hh b/src/base/filters/multi_bit_sel_bloom_filter.hh
index 46b02eb..8c5b34c 100644
--- a/src/base/filters/multi_bit_sel_bloom_filter.hh
+++ b/src/base/filters/multi_bit_sel_bloom_filter.hh
@@ -32,6 +32,9 @@
#include "base/filters/base.hh"
+namespace gem5
+{
+
struct BloomFilterMultiBitSelParams;
GEM5_DEPRECATED_NAMESPACE(BloomFilter, bloom_filter);
@@ -78,5 +81,6 @@
};
} // namespace bloom_filter
+} // namespace gem5
#endif // __BASE_FILTERS_MULTI_BIT_SEL_BLOOM_FILTER_HH__
diff --git a/src/base/filters/multi_bloom_filter.cc b/src/base/filters/multi_bloom_filter.cc
index 36dfd21..401d844 100644
--- a/src/base/filters/multi_bloom_filter.cc
+++ b/src/base/filters/multi_bloom_filter.cc
@@ -32,6 +32,9 @@
#include "base/logging.hh"
#include "params/BloomFilterMulti.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(BloomFilter, bloom_filter);
namespace bloom_filter
{
@@ -112,3 +115,4 @@
}
} // namespace bloom_filter
+} // namespace gem5
diff --git a/src/base/filters/multi_bloom_filter.hh b/src/base/filters/multi_bloom_filter.hh
index b346573..ec9838a 100644
--- a/src/base/filters/multi_bloom_filter.hh
+++ b/src/base/filters/multi_bloom_filter.hh
@@ -34,6 +34,9 @@
#include "base/filters/base.hh"
+namespace gem5
+{
+
struct BloomFilterMultiParams;
GEM5_DEPRECATED_NAMESPACE(BloomFilter, bloom_filter);
@@ -66,5 +69,6 @@
};
} // namespace bloom_filter
+} // namespace gem5
#endif // __BASE_FILTERS_MULTI_BLOOM_FILTER_HH__
diff --git a/src/base/filters/perfect_bloom_filter.cc b/src/base/filters/perfect_bloom_filter.cc
index 91119be..0424ddc 100644
--- a/src/base/filters/perfect_bloom_filter.cc
+++ b/src/base/filters/perfect_bloom_filter.cc
@@ -30,6 +30,9 @@
#include "params/BloomFilterPerfect.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(BloomFilter, bloom_filter);
namespace bloom_filter
{
@@ -81,3 +84,4 @@
}
} // namespace bloom_filter
+} // namespace gem5
diff --git a/src/base/filters/perfect_bloom_filter.hh b/src/base/filters/perfect_bloom_filter.hh
index 79d7120..65ef015 100644
--- a/src/base/filters/perfect_bloom_filter.hh
+++ b/src/base/filters/perfect_bloom_filter.hh
@@ -33,6 +33,9 @@
#include "base/filters/base.hh"
+namespace gem5
+{
+
struct BloomFilterPerfectParams;
GEM5_DEPRECATED_NAMESPACE(BloomFilter, bloom_filter);
@@ -62,5 +65,6 @@
};
} // namespace bloom_filter
+} // namespace gem5
#endif // __BASE_FILTERS_PERFECT_BLOOM_FILTER_HH__
diff --git a/src/base/flags.hh b/src/base/flags.hh
index 0544380..4f7a52e 100644
--- a/src/base/flags.hh
+++ b/src/base/flags.hh
@@ -32,6 +32,9 @@
#include <type_traits>
+namespace gem5
+{
+
/**
* Wrapper that groups a few flag bits under the same undelying container.
*
@@ -142,4 +145,6 @@
/** @} */ // end of api_flags
};
+} // namespace gem5
+
#endif // __BASE_FLAGS_HH__
diff --git a/src/base/flags.test.cc b/src/base/flags.test.cc
index 08031b9..98957d1 100644
--- a/src/base/flags.test.cc
+++ b/src/base/flags.test.cc
@@ -33,6 +33,8 @@
#include "base/flags.hh"
+using namespace gem5;
+
/** Test default zero-initialized constructor. */
TEST(FlagsTest, ConstructorZero)
{
diff --git a/src/base/framebuffer.cc b/src/base/framebuffer.cc
index 3fec3ff..2fe7fbd 100644
--- a/src/base/framebuffer.cc
+++ b/src/base/framebuffer.cc
@@ -41,6 +41,9 @@
#include "base/bitfield.hh"
+namespace gem5
+{
+
const FrameBuffer FrameBuffer::dummy(320, 240);
FrameBuffer::FrameBuffer(unsigned width, unsigned height)
@@ -125,3 +128,5 @@
reinterpret_cast<const Bytef *>(pixels.data()),
area() * sizeof(Pixel));
}
+
+} // namespace gem5
diff --git a/src/base/framebuffer.hh b/src/base/framebuffer.hh
index faf01ed..2f64499 100644
--- a/src/base/framebuffer.hh
+++ b/src/base/framebuffer.hh
@@ -51,6 +51,9 @@
#include "base/types.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
/**
* Internal gem5 representation of a frame buffer
*
@@ -198,4 +201,6 @@
unsigned _height;
};
+} // namespace gem5
+
#endif // __BASE_FRAMEBUFFER_HH__
diff --git a/src/base/gtest/cur_tick_fake.hh b/src/base/gtest/cur_tick_fake.hh
index 5afe2a3..9ba1ab4 100644
--- a/src/base/gtest/cur_tick_fake.hh
+++ b/src/base/gtest/cur_tick_fake.hh
@@ -29,7 +29,8 @@
#include "base/types.hh"
#include "sim/cur_tick.hh"
-namespace {
+namespace gem5
+{
class GTestTickHandler
{
@@ -45,4 +46,4 @@
void setCurTick(Tick tick) { *Gem5Internal::_curTickPtr = tick; }
};
-} // anonymous namespace
+} // namespace gem5
diff --git a/src/base/gtest/logging.cc b/src/base/gtest/logging.cc
index 68fb187..ab66258 100644
--- a/src/base/gtest/logging.cc
+++ b/src/base/gtest/logging.cc
@@ -27,6 +27,9 @@
#include "base/gtest/logging.hh"
+namespace gem5
+{
+
thread_local GTestLogOutput gtestLogOutput;
GTestLogOutput::EventHook::EventHook(GTestLogOutput &_stream) : stream(_stream)
@@ -45,3 +48,5 @@
// Clear out the stream at the start of each test.
stream.str("");
}
+
+} // namespace gem5
diff --git a/src/base/gtest/logging.hh b/src/base/gtest/logging.hh
index 3889e30..12d4e5a 100644
--- a/src/base/gtest/logging.hh
+++ b/src/base/gtest/logging.hh
@@ -29,6 +29,9 @@
#include <sstream>
+namespace gem5
+{
+
class GTestLogOutput : public std::ostringstream
{
private:
@@ -54,3 +57,5 @@
};
extern thread_local GTestLogOutput gtestLogOutput;
+
+} // namespace gem5
diff --git a/src/base/gtest/logging_mock.cc b/src/base/gtest/logging_mock.cc
index 572d057..101374e 100644
--- a/src/base/gtest/logging_mock.cc
+++ b/src/base/gtest/logging_mock.cc
@@ -31,6 +31,9 @@
#include "base/logging.hh"
+namespace gem5
+{
+
namespace {
// This custom exception type will help prevent fatal exceptions from being
@@ -108,3 +111,5 @@
static GTestLogger* hack_logger = new GTestLogger("hack: ");
return *hack_logger;
}
+
+} // namespace gem5
diff --git a/src/base/hostinfo.cc b/src/base/hostinfo.cc
index 0e11f3f..2b2ea64 100644
--- a/src/base/hostinfo.cc
+++ b/src/base/hostinfo.cc
@@ -39,6 +39,9 @@
#include "base/logging.hh"
#include "base/str.hh"
+namespace gem5
+{
+
#ifndef __APPLE__
uint64_t
procInfo(const char *filename, const char *target)
@@ -92,3 +95,5 @@
return procInfo("/proc/self/status", "VmSize:");
#endif
}
+
+} // namespace gem5
diff --git a/src/base/hostinfo.hh b/src/base/hostinfo.hh
index d8a8910..3998ad6 100644
--- a/src/base/hostinfo.hh
+++ b/src/base/hostinfo.hh
@@ -31,6 +31,9 @@
#include <cstdint>
+namespace gem5
+{
+
/**
* Determine the simulator process' total virtual memory usage.
*
@@ -38,4 +41,6 @@
*/
uint64_t memUsage();
+} // namespace gem5
+
#endif // __HOSTINFO_HH__
diff --git a/src/base/imgwriter.cc b/src/base/imgwriter.cc
index 47cbcb1..c9bc289 100644
--- a/src/base/imgwriter.cc
+++ b/src/base/imgwriter.cc
@@ -46,6 +46,9 @@
#endif
+namespace gem5
+{
+
std::unique_ptr<ImgWriter>
createImgWriter(enums::ImageFormat type, const FrameBuffer *fb)
{
@@ -69,3 +72,5 @@
return std::unique_ptr<BmpWriter>(new BmpWriter(fb));
}
}
+
+} // namespace gem5
diff --git a/src/base/imgwriter.hh b/src/base/imgwriter.hh
index 0eb30a7..37ad650 100644
--- a/src/base/imgwriter.hh
+++ b/src/base/imgwriter.hh
@@ -45,6 +45,9 @@
#include "enums/ImageFormat.hh"
+namespace gem5
+{
+
// write frame buffer to an image
class ImgWriter
{
@@ -87,4 +90,6 @@
std::unique_ptr<ImgWriter>
createImgWriter(enums::ImageFormat type, const FrameBuffer *fb);
+} // namespace gem5
+
#endif //__BASE_IMGWRITER_HH__
diff --git a/src/base/inet.cc b/src/base/inet.cc
index f8fe944..ca83fa4 100644
--- a/src/base/inet.cc
+++ b/src/base/inet.cc
@@ -50,6 +50,9 @@
#include "base/logging.hh"
#include "base/types.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Net, networking);
namespace networking
{
@@ -410,3 +413,4 @@
}
} // namespace networking
+} // namespace gem5
diff --git a/src/base/inet.hh b/src/base/inet.hh
index 3a2f4c4..3897f63 100644
--- a/src/base/inet.hh
+++ b/src/base/inet.hh
@@ -65,6 +65,9 @@
#include "dnet/blob.h"
#include "dnet/rand.h"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Net, networking);
namespace networking
{
@@ -831,5 +834,6 @@
int hsplit(const EthPacketPtr &ptr);
} // namespace networking
+} // namespace gem5
#endif // __BASE_INET_HH__
diff --git a/src/base/inifile.cc b/src/base/inifile.cc
index b5f73a4..8c0662d 100644
--- a/src/base/inifile.cc
+++ b/src/base/inifile.cc
@@ -36,6 +36,9 @@
#include "base/str.hh"
+namespace gem5
+{
+
IniFile::IniFile()
{}
@@ -366,3 +369,5 @@
cb(pair.first, pair.second->getValue());
}
}
+
+} // namespace gem5
diff --git a/src/base/inifile.hh b/src/base/inifile.hh
index ae6dc45..72f1df7 100644
--- a/src/base/inifile.hh
+++ b/src/base/inifile.hh
@@ -42,6 +42,9 @@
* @todo Change comments to match documentation style.
*/
+namespace gem5
+{
+
///
/// This class represents the contents of a ".ini" file.
///
@@ -216,4 +219,6 @@
void visitSection(const std::string §ionName, VisitSectionCallback cb);
};
+} // namespace gem5
+
#endif // __INIFILE_HH__
diff --git a/src/base/inifile.test.cc b/src/base/inifile.test.cc
index 73d7ab7..3cf8899 100644
--- a/src/base/inifile.test.cc
+++ b/src/base/inifile.test.cc
@@ -38,6 +38,8 @@
#include "base/inifile.hh"
+using namespace gem5;
+
namespace {
std::istringstream iniFile(R"ini_file(
diff --git a/src/base/intmath.hh b/src/base/intmath.hh
index 78d0795..5ce5b5b 100644
--- a/src/base/intmath.hh
+++ b/src/base/intmath.hh
@@ -48,6 +48,9 @@
#include "base/bitfield.hh"
+namespace gem5
+{
+
/**
* @ingroup api_base_utils
*/
@@ -295,4 +298,6 @@
return ctz32(value);
}
+} // namespace gem5
+
#endif // __BASE_INTMATH_HH__
diff --git a/src/base/intmath.test.cc b/src/base/intmath.test.cc
index e42a9a8..8182f7d 100644
--- a/src/base/intmath.test.cc
+++ b/src/base/intmath.test.cc
@@ -42,6 +42,8 @@
#include "base/intmath.hh"
+using namespace gem5;
+
TEST(IntmathTest, isPowerOf2)
{
EXPECT_TRUE(isPowerOf2(1));
diff --git a/src/base/loader/dtb_file.cc b/src/base/loader/dtb_file.cc
index db657d3..f89b1ae 100644
--- a/src/base/loader/dtb_file.cc
+++ b/src/base/loader/dtb_file.cc
@@ -37,6 +37,9 @@
#include "libfdt.h"
#include "sim/byteswap.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Loader, loader);
namespace loader
{
@@ -158,3 +161,4 @@
}
} // namespace loader
+} // namespace gem5
diff --git a/src/base/loader/dtb_file.hh b/src/base/loader/dtb_file.hh
index 1bc2ccd..f0a211f 100644
--- a/src/base/loader/dtb_file.hh
+++ b/src/base/loader/dtb_file.hh
@@ -32,6 +32,9 @@
#include "base/compiler.hh"
#include "base/loader/image_file.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Loader, loader);
namespace loader
{
@@ -73,5 +76,6 @@
};
} // namespace loader
+} // namespace gem5
#endif //__BASE_LOADER_DTB_FILE_HH__
diff --git a/src/base/loader/elf_object.cc b/src/base/loader/elf_object.cc
index e7fba63..28721f5 100644
--- a/src/base/loader/elf_object.cc
+++ b/src/base/loader/elf_object.cc
@@ -58,6 +58,9 @@
#include "gelf.h"
#include "sim/byteswap.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Loader, loader);
namespace loader
{
@@ -433,3 +436,4 @@
}
} // namespace loader
+} // namespace gem5
diff --git a/src/base/loader/elf_object.hh b/src/base/loader/elf_object.hh
index 7e7b739..6159b35 100644
--- a/src/base/loader/elf_object.hh
+++ b/src/base/loader/elf_object.hh
@@ -48,6 +48,9 @@
#include "base/loader/object_file.hh"
#include "gelf.h"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Loader, loader);
namespace loader
{
@@ -134,5 +137,6 @@
void setInterpDir(const std::string &dirname);
} // namespace loader
+} // namespace gem5
#endif // __BASE_LOADER_ELF_OBJECT_HH__
diff --git a/src/base/loader/image_file.hh b/src/base/loader/image_file.hh
index 0d87c5e..194c956 100644
--- a/src/base/loader/image_file.hh
+++ b/src/base/loader/image_file.hh
@@ -36,6 +36,9 @@
#include "base/loader/image_file_data.hh"
#include "base/loader/memory_image.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Loader, loader);
namespace loader
{
@@ -52,5 +55,6 @@
};
} // namespace loader
+} // namespace gem5
#endif // __BASE_LOADER_IMAGE_FILE_HH__
diff --git a/src/base/loader/image_file_data.cc b/src/base/loader/image_file_data.cc
index dc6cb90..f99c5f3 100644
--- a/src/base/loader/image_file_data.cc
+++ b/src/base/loader/image_file_data.cc
@@ -39,6 +39,9 @@
#include "base/logging.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Loader, loader);
namespace loader
{
@@ -131,3 +134,4 @@
}
} // namespace loader
+} // namespace gem5
diff --git a/src/base/loader/image_file_data.hh b/src/base/loader/image_file_data.hh
index 681dfa6..d02c499 100644
--- a/src/base/loader/image_file_data.hh
+++ b/src/base/loader/image_file_data.hh
@@ -35,6 +35,9 @@
#include "base/compiler.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Loader, loader);
namespace loader
{
@@ -58,5 +61,6 @@
typedef std::shared_ptr<ImageFileData> ImageFileDataPtr;
} // namespace loader
+} // namespace gem5
#endif // __BASE_LOADER_IMAGE_FILE_DATA_HH__
diff --git a/src/base/loader/image_file_data.test.cc b/src/base/loader/image_file_data.test.cc
index 2ab4bf1..7e04a05c 100644
--- a/src/base/loader/image_file_data.test.cc
+++ b/src/base/loader/image_file_data.test.cc
@@ -35,6 +35,7 @@
#include "base/loader/image_file_data.hh"
#include "base/loader/small_image_file.test.hh"
+using namespace gem5;
using namespace loader;
TEST(ImageFileDataTest, SimpleImage)
diff --git a/src/base/loader/memory_image.cc b/src/base/loader/memory_image.cc
index 83b6c91..5537f28 100644
--- a/src/base/loader/memory_image.cc
+++ b/src/base/loader/memory_image.cc
@@ -29,6 +29,9 @@
#include "base/loader/memory_image.hh"
#include "mem/port_proxy.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Loader, loader);
namespace loader
{
@@ -65,3 +68,4 @@
}
} // namespace loader
+} // namespace gem5
diff --git a/src/base/loader/memory_image.hh b/src/base/loader/memory_image.hh
index 0752045..2c56f4c 100644
--- a/src/base/loader/memory_image.hh
+++ b/src/base/loader/memory_image.hh
@@ -41,6 +41,9 @@
#include "base/logging.hh"
#include "base/types.hh"
+namespace gem5
+{
+
class PortProxy;
GEM5_DEPRECATED_NAMESPACE(Loader, loader);
@@ -168,5 +171,6 @@
}
} // namespace loader
+} // namespace gem5
#endif // __BASE_LOADER_MEMORY_IMAGE_HH__
diff --git a/src/base/loader/object_file.cc b/src/base/loader/object_file.cc
index 3778a8a..2566853 100644
--- a/src/base/loader/object_file.cc
+++ b/src/base/loader/object_file.cc
@@ -33,6 +33,9 @@
#include "base/loader/raw_image.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Loader, loader);
namespace loader
{
@@ -130,3 +133,4 @@
}
} // namespace loader
+} // namespace gem5
diff --git a/src/base/loader/object_file.hh b/src/base/loader/object_file.hh
index 5e767de..1079f16 100644
--- a/src/base/loader/object_file.hh
+++ b/src/base/loader/object_file.hh
@@ -40,6 +40,9 @@
#include "base/types.hh"
#include "enums/ByteOrder.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Loader, loader);
namespace loader
{
@@ -134,5 +137,6 @@
ObjectFile *createObjectFile(const std::string &fname, bool raw=false);
} // namespace loader
+} // namespace gem5
#endif // __BASE_LOADER_OBJECT_FILE_HH__
diff --git a/src/base/loader/raw_image.hh b/src/base/loader/raw_image.hh
index 7dcbf88..7321ea4 100644
--- a/src/base/loader/raw_image.hh
+++ b/src/base/loader/raw_image.hh
@@ -32,6 +32,9 @@
#include "base/compiler.hh"
#include "base/loader/object_file.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Loader, loader);
namespace loader
{
@@ -53,5 +56,6 @@
};
} // namespace loader
+} // namespace gem5
#endif // __BASE_LOADER_RAW_IMAGE_HH__
diff --git a/src/base/loader/small_image_file.test.hh b/src/base/loader/small_image_file.test.hh
index f880d75..bce850a 100644
--- a/src/base/loader/small_image_file.test.hh
+++ b/src/base/loader/small_image_file.test.hh
@@ -31,6 +31,9 @@
#include <cstdint>
+namespace gem5
+{
+
/**
* This image file contains the text "This is a test image.\n" 31 times.
*/
@@ -136,4 +139,6 @@
0xc9, 0x58, 0x6c, 0x4e, 0xaa, 0x02, 0x00, 0x00
};
+} // namespace gem5
+
#endif // __SMALL_IMAGE_FILE_HH__
diff --git a/src/base/loader/symtab.cc b/src/base/loader/symtab.cc
index 32b7d00..f2f54e9 100644
--- a/src/base/loader/symtab.cc
+++ b/src/base/loader/symtab.cc
@@ -34,6 +34,9 @@
#include "base/logging.hh"
#include "base/str.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Loader, loader);
namespace loader
{
@@ -121,3 +124,4 @@
}
} // namespace loader
+} // namespace gem5
diff --git a/src/base/loader/symtab.hh b/src/base/loader/symtab.hh
index 3e287c2..200accc 100644
--- a/src/base/loader/symtab.hh
+++ b/src/base/loader/symtab.hh
@@ -41,6 +41,9 @@
#include "base/types.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Loader, loader);
namespace loader
{
@@ -390,5 +393,6 @@
extern SymbolTable debugSymbolTable;
} // namespace loader
+} // namespace gem5
#endif // __BASE_LOADER_SYMTAB_HH__
diff --git a/src/base/logging.cc b/src/base/logging.cc
index f96d101..b871fcf 100644
--- a/src/base/logging.cc
+++ b/src/base/logging.cc
@@ -44,6 +44,9 @@
#include "base/hostinfo.hh"
+namespace gem5
+{
+
namespace {
class ExitLogger : public Logger
@@ -107,3 +110,5 @@
static Logger* hack_logger = new Logger("hack: ");
return *hack_logger;
}
+
+} // namespace gem5
diff --git a/src/base/logging.hh b/src/base/logging.hh
index 050f2c6..56396f8 100644
--- a/src/base/logging.hh
+++ b/src/base/logging.hh
@@ -48,6 +48,9 @@
#include "base/compiler.hh"
#include "base/cprintf.hh"
+namespace gem5
+{
+
class Logger
{
public:
@@ -137,7 +140,7 @@
#define base_message(logger, ...) \
- logger.print(::Logger::Loc(__FILE__, __LINE__), __VA_ARGS__)
+ logger.print(::gem5::Logger::Loc(__FILE__, __LINE__), __VA_ARGS__)
/*
* Only print the message the first time this expression is
@@ -171,7 +174,7 @@
*
* @ingroup api_logger
*/
-#define panic(...) exit_message(::Logger::getPanic(), __VA_ARGS__)
+#define panic(...) exit_message(::gem5::Logger::getPanic(), __VA_ARGS__)
/**
* This implements a cprintf based fatal() function. fatal() should
@@ -183,7 +186,7 @@
*
* @ingroup api_logger
*/
-#define fatal(...) exit_message(::Logger::getFatal(), __VA_ARGS__)
+#define fatal(...) exit_message(::gem5::Logger::getFatal(), __VA_ARGS__)
/**
* Conditional panic macro that checks the supplied condition and only panics
@@ -201,7 +204,7 @@
do { \
if (GEM5_UNLIKELY(cond)) { \
panic("panic condition " # cond " occurred: %s", \
- csprintf(__VA_ARGS__)); \
+ ::gem5::csprintf(__VA_ARGS__)); \
} \
} while (0)
@@ -223,7 +226,7 @@
do { \
if (GEM5_UNLIKELY(cond)) { \
fatal("fatal condition " # cond " occurred: %s", \
- csprintf(__VA_ARGS__)); \
+ ::gem5::csprintf(__VA_ARGS__)); \
} \
} while (0)
@@ -239,13 +242,16 @@
* @ingroup api_logger
* @{
*/
-#define warn(...) base_message(::Logger::getWarn(), __VA_ARGS__)
-#define inform(...) base_message(::Logger::getInfo(), __VA_ARGS__)
-#define hack(...) base_message(::Logger::getHack(), __VA_ARGS__)
+#define warn(...) base_message(::gem5::Logger::getWarn(), __VA_ARGS__)
+#define inform(...) base_message(::gem5::Logger::getInfo(), __VA_ARGS__)
+#define hack(...) base_message(::gem5::Logger::getHack(), __VA_ARGS__)
-#define warn_once(...) base_message_once(::Logger::getWarn(), __VA_ARGS__)
-#define inform_once(...) base_message_once(::Logger::getInfo(), __VA_ARGS__)
-#define hack_once(...) base_message_once(::Logger::getHack(), __VA_ARGS__)
+#define warn_once(...) \
+ base_message_once(::gem5::Logger::getWarn(), __VA_ARGS__)
+#define inform_once(...) \
+ base_message_once(::gem5::Logger::getInfo(), __VA_ARGS__)
+#define hack_once(...) \
+ base_message_once(::gem5::Logger::getHack(), __VA_ARGS__)
/** @} */ // end of api_logger
/**
@@ -295,8 +301,12 @@
#define chatty_assert(cond, ...) \
do { \
if (GEM5_UNLIKELY(!(cond))) \
- panic("assert(" # cond ") failed: %s", csprintf(__VA_ARGS__)); \
+ panic("assert(" # cond ") failed: %s", \
+ ::gem5::csprintf(__VA_ARGS__)); \
} while (0)
#endif // NDEBUG
/** @} */ // end of api_logger
+
+} // namespace gem5
+
#endif // __BASE_LOGGING_HH__
diff --git a/src/base/logging.test.cc b/src/base/logging.test.cc
index 3f16070..31b363d 100644
--- a/src/base/logging.test.cc
+++ b/src/base/logging.test.cc
@@ -32,6 +32,8 @@
#include "base/gtest/logging.hh"
#include "base/logging.hh"
+using namespace gem5;
+
/** Temporarily redirects cerr to gtestLogOutput. */
class LoggingFixture : public ::testing::Test
{
diff --git a/src/base/match.cc b/src/base/match.cc
index 8fff25d..9c85833 100644
--- a/src/base/match.cc
+++ b/src/base/match.cc
@@ -31,6 +31,9 @@
#include "base/str.hh"
+namespace gem5
+{
+
ObjectMatch::ObjectMatch()
{
}
@@ -113,3 +116,4 @@
return to_return;
}
+} // namespace gem5
diff --git a/src/base/match.hh b/src/base/match.hh
index 48d79c4..36c5ad2 100644
--- a/src/base/match.hh
+++ b/src/base/match.hh
@@ -37,6 +37,9 @@
#include <string>
#include <vector>
+namespace gem5
+{
+
/**
* ObjectMatch contains a vector of expressions. ObjectMatch can then be
* queried, via ObjectMatch.match(std::string), to check if a string matches
@@ -69,5 +72,6 @@
}
};
-#endif // __BASE_MATCH_HH__
+} // namespace gem5
+#endif // __BASE_MATCH_HH__
diff --git a/src/base/match.test.cc b/src/base/match.test.cc
index 2091281..d1e493f 100644
--- a/src/base/match.test.cc
+++ b/src/base/match.test.cc
@@ -30,6 +30,8 @@
#include "base/match.hh"
+using namespace gem5;
+
TEST(MatchTest, Add)
{
/*
diff --git a/src/base/named.hh b/src/base/named.hh
index b0ddbd7..5695929 100644
--- a/src/base/named.hh
+++ b/src/base/named.hh
@@ -31,6 +31,9 @@
#include <string>
+namespace gem5
+{
+
/** Interface for things with names. This is useful when using DPRINTF. */
class Named
{
@@ -44,4 +47,6 @@
virtual std::string name() const { return _name; }
};
+} // namespace gem5
+
#endif // __BASE_NAMED_HH__
diff --git a/src/base/named.test.cc b/src/base/named.test.cc
index 3cc6951..3d790c0 100644
--- a/src/base/named.test.cc
+++ b/src/base/named.test.cc
@@ -30,6 +30,8 @@
#include "base/named.hh"
+using namespace gem5;
+
/** Test if a Named instance has the name it is assigned. */
TEST(NamedTest, Name)
{
diff --git a/src/base/output.cc b/src/base/output.cc
index aeafb9d..01651c7 100644
--- a/src/base/output.cc
+++ b/src/base/output.cc
@@ -56,6 +56,9 @@
#include "base/logging.hh"
+namespace gem5
+{
+
OutputDirectory simout;
@@ -344,3 +347,5 @@
}
}
}
+
+} // namespace gem5
diff --git a/src/base/output.hh b/src/base/output.hh
index 82959eb..78ae00b 100644
--- a/src/base/output.hh
+++ b/src/base/output.hh
@@ -48,6 +48,9 @@
#include "base/compiler.hh"
+namespace gem5
+{
+
class OutputDirectory;
class OutputStream
@@ -301,4 +304,6 @@
extern OutputDirectory simout;
+} // namespace gem5
+
#endif // __BASE_OUTPUT_HH__
diff --git a/src/base/pixel.cc b/src/base/pixel.cc
index c21d0f1..5e7b0f0 100644
--- a/src/base/pixel.cc
+++ b/src/base/pixel.cc
@@ -41,6 +41,9 @@
#include "base/bitfield.hh"
+namespace gem5
+{
+
const PixelConverter PixelConverter::rgba8888_le(4, 0, 8, 16, 8, 8, 8);
const PixelConverter PixelConverter::rgba8888_be(4, 0, 8, 16, 8, 8, 8,
ByteOrder::big);
@@ -64,7 +67,7 @@
PixelConverter::Channel::Channel(unsigned _offset, unsigned width)
: offset(_offset),
- mask(::mask(width)),
+ mask(gem5::mask(width)),
factor(255.0 / mask)
{
}
@@ -96,3 +99,5 @@
p[i] = (word >> (8 * (length - i - 1))) & 0xFF;
}
}
+
+} // namespace gem5
diff --git a/src/base/pixel.hh b/src/base/pixel.hh
index 639909c..a33924d 100644
--- a/src/base/pixel.hh
+++ b/src/base/pixel.hh
@@ -49,6 +49,9 @@
#include "base/types.hh"
#include "sim/byteswap.hh"
+namespace gem5
+{
+
/**
* Internal gem5 representation of a Pixel.
*/
@@ -228,4 +231,6 @@
return os;
}
+} // namespace gem5
+
#endif // __BASE_PIXEL_HH__
diff --git a/src/base/pixel.test.cc b/src/base/pixel.test.cc
index 34fa7ca..d5f25de 100644
--- a/src/base/pixel.test.cc
+++ b/src/base/pixel.test.cc
@@ -39,6 +39,8 @@
#include "base/pixel.hh"
+using namespace gem5;
+
static Pixel pixel_red(0xff, 0x00, 0x00);
static Pixel pixel_green(0x00, 0xff, 0x00);
static Pixel pixel_blue(0x00, 0x00, 0xff);
diff --git a/src/base/pngwriter.cc b/src/base/pngwriter.cc
index 680b988..8797c4c 100644
--- a/src/base/pngwriter.cc
+++ b/src/base/pngwriter.cc
@@ -51,6 +51,9 @@
#include "base/logging.hh"
+namespace gem5
+{
+
const char* PngWriter::_imgExtension = "png";
/**
@@ -172,3 +175,4 @@
png_write_end(pngPtr, NULL);
}
+} // namespace gem5
diff --git a/src/base/pngwriter.hh b/src/base/pngwriter.hh
index 7163482..e7d6144 100644
--- a/src/base/pngwriter.hh
+++ b/src/base/pngwriter.hh
@@ -46,6 +46,9 @@
#include "base/framebuffer.hh"
#include "base/imgwriter.hh"
+namespace gem5
+{
+
/** Image writer implementing support for PNG */
class PngWriter : public ImgWriter
{
@@ -105,4 +108,6 @@
static const char* _imgExtension;
};
+} // namespace gem5
+
#endif // __BASE_PNG_HH__
diff --git a/src/base/pollevent.cc b/src/base/pollevent.cc
index 7691ba6..a18a5b7 100644
--- a/src/base/pollevent.cc
+++ b/src/base/pollevent.cc
@@ -50,6 +50,9 @@
#include "sim/eventq.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
PollQueue pollQueue;
/////////////////////////////////////////////////////
@@ -248,3 +251,5 @@
getEventQueue(0)->wakeup();
}
}
+
+} // namespace gem5
diff --git a/src/base/pollevent.hh b/src/base/pollevent.hh
index 1930bb3..d4f80e3 100644
--- a/src/base/pollevent.hh
+++ b/src/base/pollevent.hh
@@ -36,6 +36,9 @@
#include "sim/core.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
class PollQueue;
class PollEvent : public Serializable
@@ -110,4 +113,6 @@
*/
extern PollQueue pollQueue;
+} // namespace gem5
+
#endif // __BASE_POLLEVENT_HH__
diff --git a/src/base/printable.hh b/src/base/printable.hh
index f79843e..8e86ff2 100644
--- a/src/base/printable.hh
+++ b/src/base/printable.hh
@@ -36,6 +36,9 @@
#include <ostream>
#include <string>
+namespace gem5
+{
+
/**
* Abstract base class for objects which support being printed
* to a stream for debugging. Primarily used to support PrintReq
@@ -52,4 +55,6 @@
const std::string &prefix = "") const = 0;
};
+} // namespace gem5
+
#endif // __PRINTABLE_HH__
diff --git a/src/base/random.cc b/src/base/random.cc
index 63f4b7f..0315b6e 100644
--- a/src/base/random.cc
+++ b/src/base/random.cc
@@ -45,6 +45,9 @@
#include "base/logging.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
Random::Random()
{
// default random seed
@@ -94,3 +97,5 @@
}
Random random_mt;
+
+} // namespace gem5
diff --git a/src/base/random.hh b/src/base/random.hh
index 0ef2b6f..9a3d696 100644
--- a/src/base/random.hh
+++ b/src/base/random.hh
@@ -53,6 +53,9 @@
#include "base/types.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
class Checkpoint;
class Random : public Serializable
@@ -121,4 +124,6 @@
*/
extern Random random_mt;
+} // namespace gem5
+
#endif // __BASE_RANDOM_HH__
diff --git a/src/base/refcnt.hh b/src/base/refcnt.hh
index 43a2a36..b9546d3 100644
--- a/src/base/refcnt.hh
+++ b/src/base/refcnt.hh
@@ -49,6 +49,9 @@
* Classes for managing reference counted objects.
*/
+namespace gem5
+{
+
/**
* Derive from RefCounted if you want to enable reference counting of
* this class. If you want to use automatic reference counting, you
@@ -311,4 +314,6 @@
return l != r.get();
}
+} // namespace gem5
+
#endif // __BASE_REFCNT_HH__
diff --git a/src/base/refcnt.test.cc b/src/base/refcnt.test.cc
index 791cfc2..1d62602 100644
--- a/src/base/refcnt.test.cc
+++ b/src/base/refcnt.test.cc
@@ -35,6 +35,8 @@
#include "base/refcnt.hh"
+using namespace gem5;
+
namespace {
class TestRC;
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index 8ec8641..f2ecfcc 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -155,6 +155,9 @@
#include "sim/full_system.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
static const char GDBStart = '$';
static const char GDBEnd = '#';
static const char GDBGoodP = '+';
@@ -1305,3 +1308,5 @@
return true;
}
+
+} // namespace gem5
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index ce39869..eb0661d 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -66,6 +66,9 @@
* https://sourceware.org/gdb/current/onlinedocs/gdb/Remote-Protocol.html
*/
+namespace gem5
+{
+
class System;
class ThreadContext;
@@ -410,4 +413,6 @@
write(addr, sizeof(T), (const char *)&data);
}
+} // namespace gem5
+
#endif /* __REMOTE_GDB_H__ */
diff --git a/src/base/sat_counter.hh b/src/base/sat_counter.hh
index cf60fdc..6644b05 100644
--- a/src/base/sat_counter.hh
+++ b/src/base/sat_counter.hh
@@ -47,6 +47,9 @@
#include "base/logging.hh"
#include "base/types.hh"
+namespace gem5
+{
+
/**
* Implements an n bit saturating counter and provides methods to
* increment, decrement, and read it.
@@ -340,4 +343,6 @@
[[deprecated("Use SatCounter8 (or variants) instead")]]
typedef SatCounter8 SatCounter;
+} // namespace gem5
+
#endif // __BASE_SAT_COUNTER_HH__
diff --git a/src/base/sat_counter.test.cc b/src/base/sat_counter.test.cc
index 02b6a87..07a01c7 100644
--- a/src/base/sat_counter.test.cc
+++ b/src/base/sat_counter.test.cc
@@ -34,6 +34,8 @@
#include "base/gtest/logging.hh"
#include "base/sat_counter.hh"
+using namespace gem5;
+
/**
* Test that an error is triggered when the number of bits exceeds the
* counter's capacity.
diff --git a/src/base/socket.cc b/src/base/socket.cc
index abe5ddf..fa61ea4 100644
--- a/src/base/socket.cc
+++ b/src/base/socket.cc
@@ -43,6 +43,9 @@
#include "base/types.hh"
#include "sim/byteswap.hh"
+namespace gem5
+{
+
bool ListenSocket::listeningDisabled = false;
bool ListenSocket::anyListening = false;
@@ -157,3 +160,5 @@
return sfd;
}
+
+} // namespace gem5
diff --git a/src/base/socket.hh b/src/base/socket.hh
index 4b42674..b9b257c 100644
--- a/src/base/socket.hh
+++ b/src/base/socket.hh
@@ -29,6 +29,9 @@
#ifndef __SOCKET_HH__
#define __SOCKET_HH__
+namespace gem5
+{
+
class ListenSocket
{
protected:
@@ -74,4 +77,6 @@
/** @} */ // end of api_socket
};
+} // namespace gem5
+
#endif //__SOCKET_HH__
diff --git a/src/base/socket.test.cc b/src/base/socket.test.cc
index c08adc2..a267f8c 100644
--- a/src/base/socket.test.cc
+++ b/src/base/socket.test.cc
@@ -34,6 +34,8 @@
static const int TestPort1 = 7893;
static const int TestPort2 = 7894;
+using namespace gem5;
+
/*
* Socket.test tests socket.cc. It should be noted that some features of
* socket.cc have not been fully tested due to interaction with system-calls.
diff --git a/src/base/statistics.cc b/src/base/statistics.cc
index 3a709d5..c4782f6 100644
--- a/src/base/statistics.cc
+++ b/src/base/statistics.cc
@@ -50,6 +50,9 @@
#include "base/logging.hh"
#include "sim/root.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
{
@@ -330,3 +333,5 @@
{
statistics::dump();
}
+
+} // namespace gem5
diff --git a/src/base/statistics.hh b/src/base/statistics.hh
index 6a7e23e..1afdd74 100644
--- a/src/base/statistics.hh
+++ b/src/base/statistics.hh
@@ -86,6 +86,9 @@
#include "base/str.hh"
#include "base/types.hh"
+namespace gem5
+{
+
/* A namespace for all of the Statistics */
GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
@@ -2942,4 +2945,6 @@
void debugDumpStats();
+} // namespace gem5
+
#endif // __BASE_STATISTICS_HH__
diff --git a/src/base/stats/group.cc b/src/base/stats/group.cc
index a66c487..b31efc9 100644
--- a/src/base/stats/group.cc
+++ b/src/base/stats/group.cc
@@ -44,6 +44,9 @@
#include "base/trace.hh"
#include "debug/Stats.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
{
@@ -187,3 +190,4 @@
}
} // namespace statistics
+} // namespace gem5
diff --git a/src/base/stats/group.hh b/src/base/stats/group.hh
index 91b6d8a..bd1183e 100644
--- a/src/base/stats/group.hh
+++ b/src/base/stats/group.hh
@@ -45,6 +45,9 @@
#include "base/compiler.hh"
#include "base/stats/units.hh"
+namespace gem5
+{
+
/**
* Convenience macro to add a stat to a statistics group.
*
@@ -219,5 +222,6 @@
};
} // namespace statistics
+} // namespace gem5
#endif // __BASE_STATS_GROUP_HH__
diff --git a/src/base/stats/hdf5.cc b/src/base/stats/hdf5.cc
index 3246bb4..0dca54f 100644
--- a/src/base/stats/hdf5.cc
+++ b/src/base/stats/hdf5.cc
@@ -40,6 +40,9 @@
#include "base/logging.hh"
#include "base/stats/info.hh"
+namespace gem5
+{
+
/**
* Check if all strings in a container are empty.
*/
@@ -323,3 +326,4 @@
}
}; // namespace statistics
+} // namespace gem5
diff --git a/src/base/stats/hdf5.hh b/src/base/stats/hdf5.hh
index cd6caf8..7fa9999 100644
--- a/src/base/stats/hdf5.hh
+++ b/src/base/stats/hdf5.hh
@@ -50,6 +50,9 @@
#include "base/stats/output.hh"
#include "base/stats/types.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
{
@@ -156,5 +159,6 @@
bool desc = true, bool formulas = true);
} // namespace statistics
+} // namespace gem5
#endif // __BASE_STATS_HDF5_HH__
diff --git a/src/base/stats/info.cc b/src/base/stats/info.cc
index de1fb7f..f7512d2 100644
--- a/src/base/stats/info.cc
+++ b/src/base/stats/info.cc
@@ -50,6 +50,9 @@
#include "base/logging.hh"
#include "base/str.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
{
@@ -214,3 +217,4 @@
}
} // namespace statistics
+} // namespace gem5
diff --git a/src/base/stats/info.hh b/src/base/stats/info.hh
index 0e7e398..f8dfce7 100644
--- a/src/base/stats/info.hh
+++ b/src/base/stats/info.hh
@@ -34,12 +34,15 @@
#include "base/stats/types.hh"
#include "base/stats/units.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
{
typedef uint16_t FlagsType;
-typedef ::Flags<FlagsType> Flags;
+typedef gem5::Flags<FlagsType> Flags;
/** Nothing extra to print. */
const FlagsType none = 0x0000;
@@ -269,5 +272,6 @@
NameMapType &nameMap();
} // namespace statistics
+} // namespace gem5
#endif // __BASE_STATS_INFO_HH__
diff --git a/src/base/stats/output.hh b/src/base/stats/output.hh
index 9c8dcd5..39b0804 100644
--- a/src/base/stats/output.hh
+++ b/src/base/stats/output.hh
@@ -46,6 +46,9 @@
#include "base/compiler.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
{
@@ -80,5 +83,6 @@
};
} // namespace statistics
+} // namespace gem5
#endif // __BASE_STATS_OUTPUT_HH__
diff --git a/src/base/stats/storage.cc b/src/base/stats/storage.cc
index 9ffa280..6b32dc5 100644
--- a/src/base/stats/storage.cc
+++ b/src/base/stats/storage.cc
@@ -43,6 +43,9 @@
#include <cmath>
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
{
@@ -225,3 +228,4 @@
}
} // namespace statistics
+} // namespace gem5
diff --git a/src/base/stats/storage.hh b/src/base/stats/storage.hh
index 1ce6fe7..d0c60a1 100644
--- a/src/base/stats/storage.hh
+++ b/src/base/stats/storage.hh
@@ -41,6 +41,9 @@
// For curTick().
#include "sim/core.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
{
@@ -782,5 +785,6 @@
};
} // namespace statistics
+} // namespace gem5
#endif // __BASE_STATS_STORAGE_HH__
diff --git a/src/base/stats/storage.test.cc b/src/base/stats/storage.test.cc
index c744c27..3726f6a 100644
--- a/src/base/stats/storage.test.cc
+++ b/src/base/stats/storage.test.cc
@@ -35,6 +35,8 @@
#include "base/gtest/logging.hh"
#include "base/stats/storage.hh"
+using namespace gem5;
+
// Instantiate the fake class to have a valid curTick of 0
GTestTickHandler tickHandler;
diff --git a/src/base/stats/text.cc b/src/base/stats/text.cc
index 8791e45..828f551 100644
--- a/src/base/stats/text.cc
+++ b/src/base/stats/text.cc
@@ -57,6 +57,9 @@
#include "base/stats/info.hh"
#include "base/str.hh"
+namespace gem5
+{
+
namespace
{
@@ -392,7 +395,7 @@
}
}
- if (flags.isSet(::statistics::total)) {
+ if (flags.isSet(statistics::total)) {
print.pdf = Nan;
print.cdf = Nan;
print.name = base + "total";
@@ -690,7 +693,7 @@
std::vector<std::string> total_subname;
total_subname.push_back("total");
- if (info.flags.isSet(::statistics::total) && (info.x > 1)) {
+ if (info.flags.isSet(statistics::total) && (info.x > 1)) {
print.name = statName(info.name);
print.subnames = total_subname;
print.desc = info.desc;
@@ -815,3 +818,4 @@
}
} // namespace statistics
+} // namespace gem5
diff --git a/src/base/stats/text.hh b/src/base/stats/text.hh
index 547c198..4bbe3ea 100644
--- a/src/base/stats/text.hh
+++ b/src/base/stats/text.hh
@@ -50,6 +50,9 @@
#include "base/stats/output.hh"
#include "base/stats/types.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
{
@@ -105,5 +108,6 @@
Output *initText(const std::string &filename, bool desc, bool spaces);
} // namespace statistics
+} // namespace gem5
#endif // __BASE_STATS_TEXT_HH__
diff --git a/src/base/stats/types.hh b/src/base/stats/types.hh
index df485bc..e6d5232 100644
--- a/src/base/stats/types.hh
+++ b/src/base/stats/types.hh
@@ -36,6 +36,9 @@
#include "base/compiler.hh"
#include "base/types.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
{
@@ -58,5 +61,6 @@
typedef unsigned int off_type;
} // namespace statistics
+} // namespace gem5
#endif // __BASE_STATS_TYPES_HH__
diff --git a/src/base/stats/units.hh b/src/base/stats/units.hh
index 718a68f..42ebb56 100644
--- a/src/base/stats/units.hh
+++ b/src/base/stats/units.hh
@@ -34,6 +34,9 @@
#include "base/compiler.hh"
#include "base/cprintf.hh"
+namespace gem5
+{
+
/**
* Convenience macros to declare the unit of a stat.
*/
@@ -372,7 +375,7 @@
};
} // namespace units
-
} // namespace statistics
+} // namespace gem5
#endif // __BASE_STATS_UNITS_HH__
diff --git a/src/base/stats/units.test.cc b/src/base/stats/units.test.cc
index db9c27b..dc4b475 100644
--- a/src/base/stats/units.test.cc
+++ b/src/base/stats/units.test.cc
@@ -31,6 +31,8 @@
#include "base/stats/units.hh"
+using namespace gem5;
+
TEST(StatsUnitsTest, Cycle)
{
statistics::units::Cycle *unit = statistics::units::Cycle::get();
diff --git a/src/base/stl_helpers.hh b/src/base/stl_helpers.hh
index 793bf77..47b817a 100644
--- a/src/base/stl_helpers.hh
+++ b/src/base/stl_helpers.hh
@@ -39,7 +39,9 @@
GEM5_DEPRECATED_NAMESPACE(m5, gem5);
namespace gem5
{
-namespace stl_helpers {
+
+namespace stl_helpers
+{
template <typename T, typename Enabled=void>
struct IsHelpedContainer : public std::false_type {};
diff --git a/src/base/str.cc b/src/base/str.cc
index bc404c9..4be50a2 100644
--- a/src/base/str.cc
+++ b/src/base/str.cc
@@ -31,6 +31,9 @@
#include <string>
#include <vector>
+namespace gem5
+{
+
bool
split_first(const std::string &s, std::string &lhs, std::string &rhs, char c)
{
@@ -98,3 +101,5 @@
v.push_back(s.substr(first));
}
+
+} // namespace gem5
diff --git a/src/base/str.hh b/src/base/str.hh
index d91761d..94cf1f2 100644
--- a/src/base/str.hh
+++ b/src/base/str.hh
@@ -42,6 +42,9 @@
#include "base/logging.hh"
+namespace gem5
+{
+
inline void
eat_lead_white(std::string &s)
{
@@ -261,5 +264,6 @@
return (s.compare(0, prefix.size(), prefix) == 0);
}
+} // namespace gem5
#endif //__BASE_STR_HH__
diff --git a/src/base/str.test.cc b/src/base/str.test.cc
index d3cbc3d..f999c98 100644
--- a/src/base/str.test.cc
+++ b/src/base/str.test.cc
@@ -41,6 +41,8 @@
#include "base/str.hh"
+using namespace gem5;
+
/*
* str.cc has "eat_lead_white", "eat_end_white", and "eat_white" fucntions to
* remove leading and trailing whitespace. The following tests verify this
diff --git a/src/base/temperature.cc b/src/base/temperature.cc
index b1d9c9a..d82b6d7 100644
--- a/src/base/temperature.cc
+++ b/src/base/temperature.cc
@@ -37,6 +37,9 @@
#include "base/temperature.hh"
+namespace gem5
+{
+
Temperature
Temperature::fromKelvin(double _value)
{
@@ -67,3 +70,5 @@
out << temp.value << "K";
return out;
}
+
+} // namespace gem5
diff --git a/src/base/temperature.hh b/src/base/temperature.hh
index bcb5199..ae8a44a 100644
--- a/src/base/temperature.hh
+++ b/src/base/temperature.hh
@@ -40,6 +40,9 @@
#include <ostream>
+namespace gem5
+{
+
/**
* The class stores temperatures in Kelvin and provides helper methods
* to convert to/from Celsius.
@@ -172,5 +175,6 @@
return Temperature(lhs.value / rhs);
}
+} // namespace gem5
#endif // __BASE_TEMPERATURE_HH__
diff --git a/src/base/temperature.test.cc b/src/base/temperature.test.cc
index 1d7b048..d4cbabe 100644
--- a/src/base/temperature.test.cc
+++ b/src/base/temperature.test.cc
@@ -41,6 +41,8 @@
#include "base/temperature.hh"
+using namespace gem5;
+
TEST(TemperatureTest, Constructor)
{
Temperature temp;
diff --git a/src/base/time.cc b/src/base/time.cc
index 080c43d..ea9ff84 100644
--- a/src/base/time.cc
+++ b/src/base/time.cc
@@ -38,6 +38,9 @@
#include "sim/core.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
void
Time::_set(bool monotonic)
{
@@ -179,3 +182,4 @@
return ret;
}
+} // namespace gem5
diff --git a/src/base/time.hh b/src/base/time.hh
index 2067080..493f97d 100644
--- a/src/base/time.hh
+++ b/src/base/time.hh
@@ -42,6 +42,9 @@
#include "base/types.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
class Time
{
protected:
@@ -265,4 +268,6 @@
time_t mkutctime(struct tm *time);
+} // namespace gem5
+
#endif // __BASE_TIME_HH__
diff --git a/src/base/trace.cc b/src/base/trace.cc
index 0137ad7..982bac4 100644
--- a/src/base/trace.cc
+++ b/src/base/trace.cc
@@ -45,13 +45,17 @@
#include "debug/FmtTicksOff.hh"
#include "sim/backtrace.hh"
-const std::string &name()
+const std::string &
+name()
{
static const std::string default_name("global");
return default_name;
}
+namespace gem5
+{
+
namespace Trace
{
@@ -167,3 +171,4 @@
}
} // namespace Trace
+} // namespace gem5
diff --git a/src/base/trace.hh b/src/base/trace.hh
index 9e3984f..a69eda5 100644
--- a/src/base/trace.hh
+++ b/src/base/trace.hh
@@ -43,6 +43,14 @@
#include "base/types.hh"
#include "sim/core.hh"
+// Return the global context name "global". This function gets called when
+// the DPRINTF macros are used in a context without a visible name() function
+// @todo This should be moved to the gem5 namespace
+const std::string &name();
+
+namespace gem5
+{
+
namespace Trace {
/** Debug logging base class. Handles formatting and outputting
@@ -141,10 +149,6 @@
const std::string &operator()() const { return str; }
};
-// Return the global context name "global". This function gets called when
-// the DPRINTF macros are used in a context without a visible name() function
-const std::string &name();
-
/**
* DPRINTF is a debugging trace facility that allows one to
* selectively enable tracing statements. To use DPRINTF, there must
@@ -174,48 +178,50 @@
*/
#define DDUMP(x, data, count) do { \
- if (GEM5_UNLIKELY(TRACING_ON && Debug::x)) \
- Trace::getDebugLogger()->dump( \
- curTick(), name(), data, count, #x); \
+ if (GEM5_UNLIKELY(TRACING_ON && ::gem5::Debug::x)) \
+ ::gem5::Trace::getDebugLogger()->dump( \
+ ::gem5::curTick(), name(), data, count, #x); \
} while (0)
#define DPRINTF(x, ...) do { \
- if (GEM5_UNLIKELY(TRACING_ON && Debug::x)) { \
- Trace::getDebugLogger()->dprintf_flag( \
- curTick(), name(), #x, __VA_ARGS__); \
+ if (GEM5_UNLIKELY(TRACING_ON && ::gem5::Debug::x)) { \
+ ::gem5::Trace::getDebugLogger()->dprintf_flag( \
+ ::gem5::curTick(), name(), #x, __VA_ARGS__); \
} \
} while (0)
#define DPRINTFS(x, s, ...) do { \
- if (GEM5_UNLIKELY(TRACING_ON && Debug::x)) { \
- Trace::getDebugLogger()->dprintf_flag( \
- curTick(), (s)->name(), #x, __VA_ARGS__); \
+ if (GEM5_UNLIKELY(TRACING_ON && ::gem5::Debug::x)) { \
+ ::gem5::Trace::getDebugLogger()->dprintf_flag( \
+ ::gem5::curTick(), (s)->name(), #x, __VA_ARGS__); \
} \
} while (0)
#define DPRINTFR(x, ...) do { \
- if (GEM5_UNLIKELY(TRACING_ON && Debug::x)) { \
- Trace::getDebugLogger()->dprintf_flag( \
- (Tick)-1, std::string(), #x, __VA_ARGS__); \
+ if (GEM5_UNLIKELY(TRACING_ON && ::gem5::Debug::x)) { \
+ ::gem5::Trace::getDebugLogger()->dprintf_flag( \
+ (::gem5::Tick)-1, std::string(), #x, __VA_ARGS__); \
} \
} while (0)
#define DPRINTFV(x, ...) do { \
if (GEM5_UNLIKELY(TRACING_ON && (x))) { \
- Trace::getDebugLogger()->dprintf_flag( \
- curTick(), name(), x.name(), __VA_ARGS__); \
+ ::gem5::Trace::getDebugLogger()->dprintf_flag( \
+ ::gem5::curTick(), name(), x.name(), __VA_ARGS__); \
} \
} while (0)
#define DPRINTFN(...) do { \
if (TRACING_ON) { \
- Trace::getDebugLogger()->dprintf(curTick(), name(), __VA_ARGS__); \
+ ::gem5::Trace::getDebugLogger()->dprintf( \
+ ::gem5::curTick(), name(), __VA_ARGS__); \
} \
} while (0)
#define DPRINTFNR(...) do { \
if (TRACING_ON) { \
- Trace::getDebugLogger()->dprintf((Tick)-1, "", __VA_ARGS__); \
+ ::gem5::Trace::getDebugLogger()->dprintf( \
+ (::gem5::Tick)-1, "", __VA_ARGS__); \
} \
} while (0)
@@ -223,12 +229,14 @@
GEM5_DEPRECATED_MACRO_STMT(DPRINTF_UNCONDITIONAL, \
do { \
if (TRACING_ON) { \
- Trace::getDebugLogger()->dprintf_flag( \
- curTick(), name(), #x, __VA_ARGS__); \
+ ::gem5::Trace::getDebugLogger()->dprintf_flag( \
+ ::gem5::curTick(), name(), #x, __VA_ARGS__); \
} \
} while (0), \
"Use DPRINTFN or DPRINTF with a debug flag instead.")
/** @} */ // end of api_trace
+} // namespace gem5
+
#endif // __BASE_TRACE_HH__
diff --git a/src/base/trace.test.cc b/src/base/trace.test.cc
index 45e6f6c..885783e 100644
--- a/src/base/trace.test.cc
+++ b/src/base/trace.test.cc
@@ -36,6 +36,8 @@
#include "base/named.hh"
#include "base/trace.hh"
+using namespace gem5;
+
// In test SetGetLogger this logger will be assigned to be the one returned
// by Tracer::getDebugLogger(). All tests before that test should assume
// that getDebugLogger() returns a cerr-based logger, and all tests after
@@ -46,11 +48,14 @@
// Instantiate the mock class to have a valid curTick of 0
GTestTickHandler tickHandler;
+namespace gem5
+{
namespace Debug {
/** Debug flag used for the tests in this file. */
SimpleFlag TraceTestDebugFlag("TraceTestDebugFlag",
"Exclusive debug flag for the trace tests");
}
+} // namespace gem5
/** @return The ostream as a std::string. */
std::string
diff --git a/src/base/trie.hh b/src/base/trie.hh
index 9e21a67..80ffbc0 100644
--- a/src/base/trie.hh
+++ b/src/base/trie.hh
@@ -37,6 +37,9 @@
#include "base/logging.hh"
#include "base/types.hh"
+namespace gem5
+{
+
/**
* A trie is a tree-based data structure used for data retrieval. It uses
* bits masked from the msb of the key to to determine a value's location,
@@ -393,4 +396,6 @@
}
};
+} // namespace gem5
+
#endif
diff --git a/src/base/trie.test.cc b/src/base/trie.test.cc
index ec50852..0a19efa 100644
--- a/src/base/trie.test.cc
+++ b/src/base/trie.test.cc
@@ -35,6 +35,8 @@
#include "base/trie.hh"
#include "base/types.hh"
+using namespace gem5;
+
namespace {
static inline uint32_t *ptr(uintptr_t val)
diff --git a/src/base/types.cc b/src/base/types.cc
index 3191b4c..628303e 100644
--- a/src/base/types.cc
+++ b/src/base/types.cc
@@ -28,6 +28,9 @@
#include "base/types.hh"
+namespace gem5
+{
+
std::ostream&
operator<<(std::ostream &out, const Cycles & cycles)
{
@@ -35,3 +38,4 @@
return out;
}
+} // namespace gem5
diff --git a/src/base/types.hh b/src/base/types.hh
index 5f4c741..9a59053 100644
--- a/src/base/types.hh
+++ b/src/base/types.hh
@@ -43,6 +43,9 @@
#include <ostream>
#include <stdexcept>
+namespace gem5
+{
+
/** Statistics counter type. Not much excuse for not using a 64-bit
* integer here, but if you're desperate and only run short
* simulations you could make this 32 bits.
@@ -256,4 +259,6 @@
// we just create an alias.
constexpr decltype(nullptr) NoFault = nullptr;
+} // namespace gem5
+
#endif // __BASE_TYPES_HH__
diff --git a/src/base/types.test.cc b/src/base/types.test.cc
index c05747b..ca4d00a 100644
--- a/src/base/types.test.cc
+++ b/src/base/types.test.cc
@@ -41,6 +41,8 @@
#include "base/types.hh"
+using namespace gem5;
+
/*
* The following test the Cycles class. Cycles is a wrapper for uint64_t.
* It overloads most commonly used operators.
diff --git a/src/base/uncontended_mutex.hh b/src/base/uncontended_mutex.hh
index 721712f..99e2cb2 100644
--- a/src/base/uncontended_mutex.hh
+++ b/src/base/uncontended_mutex.hh
@@ -32,6 +32,9 @@
#include <condition_variable>
#include <mutex>
+namespace gem5
+{
+
/*
* The std::mutex implementation is slower than expected because of many mode
* checking and legacy support.
@@ -115,4 +118,6 @@
}
};
+} // namespace gem5
+
#endif // __BASE_UNCONTENDED_MUTEX_HH__
diff --git a/src/base/uncontended_mutex.test.cc b/src/base/uncontended_mutex.test.cc
index 6ce929b..4df3f71 100644
--- a/src/base/uncontended_mutex.test.cc
+++ b/src/base/uncontended_mutex.test.cc
@@ -32,6 +32,8 @@
#include "base/uncontended_mutex.hh"
+using namespace gem5;
+
TEST(UncontendedMutex, Lock)
{
int data = 0;
diff --git a/src/base/version.cc b/src/base/version.cc
index 8fb6926..6e4f3a7 100644
--- a/src/base/version.cc
+++ b/src/base/version.cc
@@ -26,8 +26,12 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+namespace gem5
+{
+
/**
* @ingroup api_base_utils
*/
const char *gem5Version = "[DEVELOP-FOR-V21.01]";
+} // namespace gem5
diff --git a/src/base/vnc/Vnc.py b/src/base/vnc/Vnc.py
index 1b0457c..8421d34 100644
--- a/src/base/vnc/Vnc.py
+++ b/src/base/vnc/Vnc.py
@@ -41,6 +41,7 @@
class VncInput(SimObject):
type = 'VncInput'
cxx_header = "base/vnc/vncinput.hh"
+ cxx_class = 'gem5::VncInput'
frame_capture = Param.Bool(False, "capture changed frames to files")
img_format = Param.ImageFormat(
"Auto", "Format of the dumped Framebuffer"
@@ -49,5 +50,6 @@
class VncServer(VncInput):
type = 'VncServer'
cxx_header = "base/vnc/vncserver.hh"
+ cxx_class = 'gem5::VncServer'
port = Param.TcpPort(5900, "listen port")
number = Param.Int(0, "vnc client number")
diff --git a/src/base/vnc/vncinput.cc b/src/base/vnc/vncinput.cc
index b07e0ca..f9bdb91 100644
--- a/src/base/vnc/vncinput.cc
+++ b/src/base/vnc/vncinput.cc
@@ -49,6 +49,9 @@
#include "base/trace.hh"
#include "debug/VNC.hh"
+namespace gem5
+{
+
VncInput::VncInput(const Params &p)
: SimObject(p), keyboard(NULL), mouse(NULL),
fb(&FrameBuffer::dummy),
@@ -131,3 +134,5 @@
++captureCurrentFrame;
}
+
+} // namespace gem5
diff --git a/src/base/vnc/vncinput.hh b/src/base/vnc/vncinput.hh
index 7970c8e..a687ff6 100644
--- a/src/base/vnc/vncinput.hh
+++ b/src/base/vnc/vncinput.hh
@@ -50,6 +50,9 @@
#include "params/VncInput.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class OutputDirectory;
/**
@@ -241,4 +244,7 @@
/** Captures the current frame buffer to a file */
void captureFrameBuffer();
};
+
+} // namespace gem5
+
#endif
diff --git a/src/base/vnc/vncserver.cc b/src/base/vnc/vncserver.cc
index 7ecd3f9..41aafe5 100644
--- a/src/base/vnc/vncserver.cc
+++ b/src/base/vnc/vncserver.cc
@@ -69,6 +69,9 @@
#include "sim/byteswap.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
const PixelConverter VncServer::pixelConverter(
4, // 4 bytes / pixel
16, 8, 0, // R in [23, 16], G in [15, 8], B in [7, 0]
@@ -729,3 +732,5 @@
detach();
}
}
+
+} // namespace gem5
diff --git a/src/base/vnc/vncserver.hh b/src/base/vnc/vncserver.hh
index 8452329..091cb4d 100644
--- a/src/base/vnc/vncserver.hh
+++ b/src/base/vnc/vncserver.hh
@@ -56,6 +56,9 @@
* Declaration of a VNC server
*/
+namespace gem5
+{
+
class VncServer : public VncInput
{
public:
@@ -316,4 +319,6 @@
void frameBufferResized() override;
};
+} // namespace gem5
+
#endif
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index acd1db1..fb5cbe6 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -89,6 +89,7 @@
type = 'BaseCPU'
abstract = True
cxx_header = "cpu/base.hh"
+ cxx_class = 'gem5::BaseCPU'
cxx_exports = [
PyBindMethod("switchOut"),
diff --git a/src/cpu/CPUTracers.py b/src/cpu/CPUTracers.py
index 786606d..653c2ce 100644
--- a/src/cpu/CPUTracers.py
+++ b/src/cpu/CPUTracers.py
@@ -30,17 +30,17 @@
class ExeTracer(InstTracer):
type = 'ExeTracer'
- cxx_class = 'Trace::ExeTracer'
+ cxx_class = 'gem5::Trace::ExeTracer'
cxx_header = "cpu/exetrace.hh"
class IntelTrace(InstTracer):
type = 'IntelTrace'
- cxx_class = 'Trace::IntelTrace'
+ cxx_class = 'gem5::Trace::IntelTrace'
cxx_header = "cpu/inteltrace.hh"
class NativeTrace(ExeTracer):
abstract = True
type = 'NativeTrace'
- cxx_class = 'Trace::NativeTrace'
+ cxx_class = 'gem5::Trace::NativeTrace'
cxx_header = 'cpu/nativetrace.hh'
diff --git a/src/cpu/CheckerCPU.py b/src/cpu/CheckerCPU.py
index d08d86a..14c98c2 100644
--- a/src/cpu/CheckerCPU.py
+++ b/src/cpu/CheckerCPU.py
@@ -33,6 +33,8 @@
type = 'CheckerCPU'
abstract = True
cxx_header = "cpu/checker/cpu.hh"
+ cxx_class = 'gem5::CheckerCPU'
+
exitOnError = Param.Bool(False, "Exit on an error")
updateOnError = Param.Bool(False,
"Update the checker with the main CPU's state on an error")
diff --git a/src/cpu/DummyChecker.py b/src/cpu/DummyChecker.py
index 3f3808e..5687f7d 100644
--- a/src/cpu/DummyChecker.py
+++ b/src/cpu/DummyChecker.py
@@ -39,3 +39,4 @@
class DummyChecker(CheckerCPU):
type = 'DummyChecker'
cxx_header = 'cpu/dummy_checker.hh'
+ cxx_class = 'gem5::DummyChecker'
diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py
index d5ca453..c5ba1e7 100644
--- a/src/cpu/FuncUnit.py
+++ b/src/cpu/FuncUnit.py
@@ -60,6 +60,8 @@
class OpDesc(SimObject):
type = 'OpDesc'
cxx_header = "cpu/func_unit.hh"
+ cxx_class = 'gem5::OpDesc'
+
opClass = Param.OpClass("type of operation")
opLat = Param.Cycles(1, "cycles until result is available")
pipelined = Param.Bool(True, "set to true when the functional unit for"
@@ -68,5 +70,7 @@
class FUDesc(SimObject):
type = 'FUDesc'
cxx_header = "cpu/func_unit.hh"
+ cxx_class = 'gem5::FUDesc'
+
count = Param.Int("number of these FU's available")
opList = VectorParam.OpDesc("operation classes for this FU type")
diff --git a/src/cpu/InstPBTrace.py b/src/cpu/InstPBTrace.py
index 6f40f3a..e26a6ca 100644
--- a/src/cpu/InstPBTrace.py
+++ b/src/cpu/InstPBTrace.py
@@ -31,6 +31,6 @@
class InstPBTrace(InstTracer):
type = 'InstPBTrace'
- cxx_class = 'Trace::InstPBTrace'
+ cxx_class = 'gem5::Trace::InstPBTrace'
cxx_header = 'cpu/inst_pb_trace.hh'
file_name = Param.String("Instruction trace output file")
diff --git a/src/cpu/TimingExpr.py b/src/cpu/TimingExpr.py
index 02c4452..9c45097 100644
--- a/src/cpu/TimingExpr.py
+++ b/src/cpu/TimingExpr.py
@@ -46,12 +46,14 @@
class TimingExpr(SimObject):
type = 'TimingExpr'
cxx_header = 'cpu/timing_expr.hh'
+ cxx_class = 'gem5::TimingExpr'
abstract = True;
class TimingExprLiteral(TimingExpr):
"""Literal 64 bit unsigned value"""
type = 'TimingExprLiteral'
cxx_header = 'cpu/timing_expr.hh'
+ cxx_class = 'gem5::TimingExprLiteral'
value = Param.UInt64("literal value")
@@ -67,6 +69,7 @@
"""Find the source register number from the current inst"""
type = 'TimingExprSrcReg'
cxx_header = 'cpu/timing_expr.hh'
+ cxx_class = 'gem5::TimingExprSrcReg'
# index = Param.Unsigned("index into inst src regs")
index = Param.Unsigned("index into inst src regs")
@@ -79,6 +82,7 @@
"""Read an architectural register"""
type = 'TimingExprReadIntReg'
cxx_header = 'cpu/timing_expr.hh'
+ cxx_class = 'gem5::TimingExprReadIntReg'
reg = Param.TimingExpr("register raw index to read")
@@ -90,6 +94,7 @@
"""Block of declarations"""
type = 'TimingExprLet'
cxx_header = 'cpu/timing_expr.hh'
+ cxx_class = 'gem5::TimingExprLet'
defns = VectorParam.TimingExpr("expressions for bindings")
expr = Param.TimingExpr("body expression")
@@ -103,6 +108,7 @@
"""Value of a bound sub-expression"""
type = 'TimingExprRef'
cxx_header = 'cpu/timing_expr.hh'
+ cxx_class = 'gem5::TimingExprRef'
index = Param.Unsigned("expression index")
@@ -134,6 +140,7 @@
"""Unary operator"""
type = 'TimingExprUn'
cxx_header = 'cpu/timing_expr.hh'
+ cxx_class = 'gem5::TimingExprUn'
op = Param.TimingExprOp("operator")
arg = Param.TimingExpr("expression")
@@ -147,6 +154,7 @@
"""Binary operator"""
type = 'TimingExprBin'
cxx_header = 'cpu/timing_expr.hh'
+ cxx_class = 'gem5::TimingExprBin'
op = Param.TimingExprOp("operator")
left = Param.TimingExpr("LHS expression")
@@ -162,6 +170,7 @@
"""If-then-else operator"""
type = 'TimingExprIf'
cxx_header = 'cpu/timing_expr.hh'
+ cxx_class = 'gem5::TimingExprIf'
cond = Param.TimingExpr("condition expression")
trueExpr = Param.TimingExpr("true expression")
diff --git a/src/cpu/activity.cc b/src/cpu/activity.cc
index 2c8df0e..f10b1ce 100644
--- a/src/cpu/activity.cc
+++ b/src/cpu/activity.cc
@@ -33,6 +33,9 @@
#include "cpu/timebuf.hh"
#include "debug/Activity.hh"
+namespace gem5
+{
+
ActivityRecorder::ActivityRecorder(const std::string &name, int num_stages,
int longest_latency, int activity)
: _name(name), activityBuffer(longest_latency, 0),
@@ -163,3 +166,5 @@
assert(count == activityCount);
}
+
+} // namespace gem5
diff --git a/src/cpu/activity.hh b/src/cpu/activity.hh
index decc544..9c74cc2 100644
--- a/src/cpu/activity.hh
+++ b/src/cpu/activity.hh
@@ -32,6 +32,9 @@
#include "base/trace.hh"
#include "cpu/timebuf.hh"
+namespace gem5
+{
+
/**
* ActivityRecorder helper class that informs the CPU if it can switch
* over to being idle or not. It works by having a time buffer as
@@ -135,4 +138,6 @@
bool *stageActive;
};
+} // namespace gem5
+
#endif // __CPU_ACTIVITY_HH__
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 1267e0b..f27489c 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -71,6 +71,9 @@
// Hack
#include "sim/stat_control.hh"
+namespace gem5
+{
+
std::unique_ptr<BaseCPU::GlobalStats> BaseCPU::globalStats;
std::vector<BaseCPU *> BaseCPU::cpuList;
@@ -726,8 +729,8 @@
}
-BaseCPU::GlobalStats::GlobalStats(::statistics::Group *parent)
- : ::statistics::Group(parent),
+BaseCPU::GlobalStats::GlobalStats(statistics::Group *parent)
+ : statistics::Group(parent),
ADD_STAT(simInsts, statistics::units::Count::get(),
"Number of instructions simulated"),
ADD_STAT(simOps, statistics::units::Count::get(),
@@ -764,3 +767,5 @@
hostInstRate = simInsts / hostSeconds;
hostOpRate = simOps / hostSeconds;
}
+
+} // namespace gem5
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index e274cfa..724da06 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -62,6 +62,9 @@
#include "sim/system.hh"
#include "debug/Mwait.hh"
+namespace gem5
+{
+
class BaseCPU;
struct BaseCPUParams;
class CheckerCPU;
@@ -148,13 +151,13 @@
/** Global CPU statistics that are merged into the Root object. */
struct GlobalStats : public statistics::Group
{
- GlobalStats(::statistics::Group *parent);
+ GlobalStats(statistics::Group *parent);
- ::statistics::Value simInsts;
- ::statistics::Value simOps;
+ statistics::Value simInsts;
+ statistics::Value simOps;
- ::statistics::Formula hostInstRate;
- ::statistics::Formula hostOpRate;
+ statistics::Formula hostInstRate;
+ statistics::Formula hostOpRate;
};
/**
@@ -620,6 +623,8 @@
EventFunctionWrapper enterPwrGatingEvent;
};
+} // namespace gem5
+
#endif // THE_ISA == NULL_ISA
#endif // __CPU_BASE_HH__
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index a6e60a0..f41d179 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -52,6 +52,9 @@
#include "params/CheckerCPU.hh"
#include "sim/full_system.hh"
+namespace gem5
+{
+
void
CheckerCPU::init()
{
@@ -373,3 +376,5 @@
curTick(), thread->pcState());
panic("Checker found an error!");
}
+
+} // namespace gem5
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index b6c3747..aebf522 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -60,6 +60,9 @@
#include "params/CheckerCPU.hh"
#include "sim/eventq.hh"
+namespace gem5
+{
+
class ThreadContext;
class Request;
@@ -603,4 +606,6 @@
void dumpInsts();
};
+} // namespace gem5
+
#endif // __CPU_CHECKER_CPU_HH__
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 6684502..22ce514 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -59,6 +59,9 @@
#include "sim/sim_object.hh"
#include "sim/stats.hh"
+namespace gem5
+{
+
template <class DynInstPtr>
void
Checker<DynInstPtr>::advancePC(const Fault &fault)
@@ -700,4 +703,6 @@
}
+} // namespace gem5
+
#endif//__CPU_CHECKER_CPU_IMPL_HH__
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 9b65097..30056d7 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -49,6 +49,9 @@
#include "cpu/thread_context.hh"
#include "debug/Checker.hh"
+namespace gem5
+{
+
namespace TheISA
{
class Decoder;
@@ -523,4 +526,6 @@
};
+} // namespace gem5
+
#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
diff --git a/src/cpu/decode_cache.hh b/src/cpu/decode_cache.hh
index acaa8ca..4e5631a 100644
--- a/src/cpu/decode_cache.hh
+++ b/src/cpu/decode_cache.hh
@@ -35,6 +35,9 @@
#include "base/compiler.hh"
#include "cpu/static_inst_fwd.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(DecodeCache, decode_cache);
namespace decode_cache
{
@@ -134,5 +137,6 @@
};
} // namespace decode_cache
+} // namespace gem5
#endif // __CPU_DECODE_CACHE_HH__
diff --git a/src/cpu/dummy_checker.hh b/src/cpu/dummy_checker.hh
index 37d31af..db78952 100644
--- a/src/cpu/dummy_checker.hh
+++ b/src/cpu/dummy_checker.hh
@@ -41,6 +41,9 @@
#include "cpu/checker/cpu.hh"
#include "params/DummyChecker.hh"
+namespace gem5
+{
+
/**
* Specific non-templated derived class used for SimObject configuration.
*/
@@ -58,4 +61,6 @@
}
};
+} // namespace gem5
+
#endif // __CPU_DUMMY_CHECKER_HH__
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index e8164ec..66b43b1 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -51,6 +51,9 @@
#include "cpu/translation.hh"
#include "mem/request.hh"
+namespace gem5
+{
+
/**
* The ExecContext is an abstract base class the provides the
* interface used by the ISA to manipulate the state of the CPU model.
@@ -300,4 +303,6 @@
/** @} */
};
+} // namespace gem5
+
#endif // __CPU_EXEC_CONTEXT_HH__
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 9a6b1e7..2ac6d32 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -52,6 +52,9 @@
#include "debug/FmtTicksOff.hh"
#include "enums/OpClass.hh"
+namespace gem5
+{
+
namespace Trace {
void
@@ -176,3 +179,4 @@
}
} // namespace Trace
+} // namespace gem5
diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh
index 33ba457..5c93f15 100644
--- a/src/cpu/exetrace.hh
+++ b/src/cpu/exetrace.hh
@@ -37,6 +37,9 @@
#include "params/ExeTracer.hh"
#include "sim/insttracer.hh"
+namespace gem5
+{
+
class ThreadContext;
namespace Trace {
@@ -77,5 +80,6 @@
};
} // namespace Trace
+} // namespace gem5
#endif // __CPU_EXETRACE_HH__
diff --git a/src/cpu/func_unit.cc b/src/cpu/func_unit.cc
index 7d979bc..fd25e04 100644
--- a/src/cpu/func_unit.cc
+++ b/src/cpu/func_unit.cc
@@ -32,6 +32,9 @@
#include "base/logging.hh"
+namespace gem5
+{
+
////////////////////////////////////////////////////////////////////////////
//
// The funciton unit
@@ -92,3 +95,5 @@
{
return pipelined[capability];
}
+
+} // namespace gem5
diff --git a/src/cpu/func_unit.hh b/src/cpu/func_unit.hh
index 42bf0fe..7d30bd8 100644
--- a/src/cpu/func_unit.hh
+++ b/src/cpu/func_unit.hh
@@ -39,6 +39,9 @@
#include "params/OpDesc.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
////////////////////////////////////////////////////////////////////////////
//
// The SimObjects we use to get the FU information into the simulator
@@ -118,4 +121,6 @@
bool isPipelined(OpClass capability);
};
+} // namespace gem5
+
#endif // __FU_POOL_HH__
diff --git a/src/cpu/inst_pb_trace.cc b/src/cpu/inst_pb_trace.cc
index 3f61ae5..e6b58fa 100644
--- a/src/cpu/inst_pb_trace.cc
+++ b/src/cpu/inst_pb_trace.cc
@@ -47,6 +47,9 @@
#include "proto/inst.pb.h"
#include "sim/core.hh"
+namespace gem5
+{
+
namespace Trace {
ProtoOutputStream *InstPBTrace::traceStream;
@@ -174,3 +177,4 @@
}
} // namespace Trace
+} // namespace gem5
diff --git a/src/cpu/inst_pb_trace.hh b/src/cpu/inst_pb_trace.hh
index 5984a30..173538a 100644
--- a/src/cpu/inst_pb_trace.hh
+++ b/src/cpu/inst_pb_trace.hh
@@ -46,12 +46,15 @@
#include "proto/protoio.hh"
#include "sim/insttracer.hh"
-class ThreadContext;
-
namespace ProtoMessage {
class Inst;
}
+namespace gem5
+{
+
+class ThreadContext;
+
namespace Trace {
/**
@@ -132,5 +135,8 @@
friend class InstPBTraceRecord;
};
+
} // namespace Trace
+} // namespace gem5
+
#endif // __CPU_INST_PB_TRACE_HH__
diff --git a/src/cpu/inst_res.hh b/src/cpu/inst_res.hh
index 21ed297..f58bf88 100644
--- a/src/cpu/inst_res.hh
+++ b/src/cpu/inst_res.hh
@@ -43,6 +43,9 @@
#include "arch/generic/types.hh"
#include "arch/generic/vec_reg.hh"
+namespace gem5
+{
+
class InstResult
{
public:
@@ -202,4 +205,6 @@
/** @} */
};
+} // namespace gem5
+
#endif // __CPU_INST_RES_HH__
diff --git a/src/cpu/inst_seq.hh b/src/cpu/inst_seq.hh
index 3dec3ce..77dd629 100644
--- a/src/cpu/inst_seq.hh
+++ b/src/cpu/inst_seq.hh
@@ -31,6 +31,9 @@
#include "base/types.hh"
+namespace gem5
+{
+
// inst sequence type, used to order instructions in the ready list,
// if this rolls over the ready list order temporarily will get messed
// up, but execution will continue and complete correctly
@@ -39,4 +42,6 @@
// inst tag type, used to tag an operation instance in the IQ
typedef unsigned int InstTag;
+} // namespace gem5
+
#endif // __STD_TYPES_HH__
diff --git a/src/cpu/inteltrace.cc b/src/cpu/inteltrace.cc
index 469cc98..6491ee8 100644
--- a/src/cpu/inteltrace.cc
+++ b/src/cpu/inteltrace.cc
@@ -33,6 +33,9 @@
#include "cpu/exetrace.hh"
#include "cpu/static_inst.hh"
+namespace gem5
+{
+
namespace Trace {
void
@@ -50,3 +53,4 @@
}
} // namespace Trace
+} // namespace gem5
diff --git a/src/cpu/inteltrace.hh b/src/cpu/inteltrace.hh
index 6b4fdb1..0f09c9f 100644
--- a/src/cpu/inteltrace.hh
+++ b/src/cpu/inteltrace.hh
@@ -37,6 +37,9 @@
#include "params/IntelTrace.hh"
#include "sim/insttracer.hh"
+namespace gem5
+{
+
namespace Trace {
class IntelTraceRecord : public InstRecord
@@ -73,5 +76,6 @@
};
} // namespace Trace
+} // namespace gem5
#endif // __CPU_INTELTRACE_HH__
diff --git a/src/cpu/kvm/BaseKvmCPU.py b/src/cpu/kvm/BaseKvmCPU.py
index 169854b..58cb00b 100644
--- a/src/cpu/kvm/BaseKvmCPU.py
+++ b/src/cpu/kvm/BaseKvmCPU.py
@@ -43,6 +43,7 @@
class BaseKvmCPU(BaseCPU):
type = 'BaseKvmCPU'
cxx_header = "cpu/kvm/base.hh"
+ cxx_class = 'gem5::BaseKvmCPU'
abstract = True
@cxxMethod
diff --git a/src/cpu/kvm/KvmVM.py b/src/cpu/kvm/KvmVM.py
index 1bd71d3..29a90a4 100644
--- a/src/cpu/kvm/KvmVM.py
+++ b/src/cpu/kvm/KvmVM.py
@@ -41,6 +41,7 @@
class KvmVM(SimObject):
type = 'KvmVM'
cxx_header = "cpu/kvm/vm.hh"
+ cxx_class = 'gem5::KvmVM'
coalescedMMIO = \
VectorParam.AddrRange([], "memory ranges for coalesced MMIO")
diff --git a/src/cpu/kvm/X86KvmCPU.py b/src/cpu/kvm/X86KvmCPU.py
index fce70fd..8bb48e8 100644
--- a/src/cpu/kvm/X86KvmCPU.py
+++ b/src/cpu/kvm/X86KvmCPU.py
@@ -32,6 +32,7 @@
class X86KvmCPU(BaseKvmCPU):
type = 'X86KvmCPU'
cxx_header = "cpu/kvm/x86_cpu.hh"
+ cxx_class = 'gem5::X86KvmCPU'
cxx_exports = [
PyBindMethod("dumpFpuRegs"),
diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index fbf3a72..17575ed 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -59,6 +59,9 @@
/* Used by some KVM macros */
#define PAGE_SIZE pageSize
+namespace gem5
+{
+
BaseKvmCPU::BaseKvmCPU(const BaseKvmCPUParams ¶ms)
: BaseCPU(params),
vm(*params.system->getKvmVM()),
@@ -1363,3 +1366,5 @@
activeInstPeriod = period;
}
+
+} // namespace gem5
diff --git a/src/cpu/kvm/base.hh b/src/cpu/kvm/base.hh
index 070985d..e5b047e 100644
--- a/src/cpu/kvm/base.hh
+++ b/src/cpu/kvm/base.hh
@@ -62,6 +62,9 @@
struct kvm_run;
struct kvm_sregs;
+namespace gem5
+{
+
// forward declarations
class ThreadContext;
struct BaseKvmCPUParams;
@@ -808,4 +811,6 @@
Counter ctrInsts;
};
+} // namespace gem5
+
#endif
diff --git a/src/cpu/kvm/device.cc b/src/cpu/kvm/device.cc
index ace6018..d73b278 100644
--- a/src/cpu/kvm/device.cc
+++ b/src/cpu/kvm/device.cc
@@ -46,6 +46,9 @@
#include "base/logging.hh"
+namespace gem5
+{
+
KvmDevice::KvmDevice(int _fd)
: fd(_fd)
{
@@ -124,3 +127,4 @@
return ::ioctl(fd, request, p1);
}
+} // namespace gem5
diff --git a/src/cpu/kvm/device.hh b/src/cpu/kvm/device.hh
index 3409a55..b823010 100644
--- a/src/cpu/kvm/device.hh
+++ b/src/cpu/kvm/device.hh
@@ -40,6 +40,9 @@
#include <cstdint>
+namespace gem5
+{
+
/**
* KVM device wrapper
*
@@ -121,4 +124,6 @@
int fd;
};
+} // namespace gem5
+
#endif // __CPU_KVM_DEVICE_HH__
diff --git a/src/cpu/kvm/perfevent.cc b/src/cpu/kvm/perfevent.cc
index 177bbe6..f9c317d 100644
--- a/src/cpu/kvm/perfevent.cc
+++ b/src/cpu/kvm/perfevent.cc
@@ -51,6 +51,9 @@
#include "base/logging.hh"
#include "perfevent.hh"
+namespace gem5
+{
+
PerfKvmCounterConfig::PerfKvmCounterConfig(uint32_t type, uint64_t config)
{
memset(&attr, 0, sizeof(attr));
@@ -253,3 +256,5 @@
}
} while (_size);
}
+
+} // namespace gem5
diff --git a/src/cpu/kvm/perfevent.hh b/src/cpu/kvm/perfevent.hh
index 307db92..70a246f 100644
--- a/src/cpu/kvm/perfevent.hh
+++ b/src/cpu/kvm/perfevent.hh
@@ -45,6 +45,9 @@
#include "config/have_perf_attr_exclude_host.hh"
+namespace gem5
+{
+
/**
* PerfEvent counter configuration.
*/
@@ -378,4 +381,6 @@
long pageSize;
};
+} // namespace gem5
+
#endif
diff --git a/src/cpu/kvm/timer.cc b/src/cpu/kvm/timer.cc
index 538fd56..af78c73 100644
--- a/src/cpu/kvm/timer.cc
+++ b/src/cpu/kvm/timer.cc
@@ -58,6 +58,9 @@
#define sigev_notify_thread_id _sigev_un._tid
#endif
+namespace gem5
+{
+
static pid_t
sysGettid()
{
@@ -195,3 +198,5 @@
{
return ticksFromHostCycles(MIN_HOST_CYCLES);
}
+
+} // namespace gem5
diff --git a/src/cpu/kvm/timer.hh b/src/cpu/kvm/timer.hh
index 0f69849..72a2c0f 100644
--- a/src/cpu/kvm/timer.hh
+++ b/src/cpu/kvm/timer.hh
@@ -43,6 +43,9 @@
#include "cpu/kvm/perfevent.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
/**
* Timer functions to interrupt VM execution after a number of
* simulation ticks. The timer allows scaling of the host time to take
@@ -247,4 +250,6 @@
PerfKvmCounter &hwOverflow;
};
+} // namespace gem5
+
#endif
diff --git a/src/cpu/kvm/vm.cc b/src/cpu/kvm/vm.cc
index 13f774e..f1fdeec 100644
--- a/src/cpu/kvm/vm.cc
+++ b/src/cpu/kvm/vm.cc
@@ -53,6 +53,9 @@
#include "params/KvmVM.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
namespace
{
@@ -588,3 +591,5 @@
return ::ioctl(vmFD, request, p1);
}
+
+} // namespace gem5
diff --git a/src/cpu/kvm/vm.hh b/src/cpu/kvm/vm.hh
index d033bb6..2eb1909 100644
--- a/src/cpu/kvm/vm.hh
+++ b/src/cpu/kvm/vm.hh
@@ -49,6 +49,9 @@
struct kvm_msr_list;
struct kvm_vcpu_init;
+namespace gem5
+{
+
// forward declarations
struct KvmVMParams;
class BaseKvmCPU;
@@ -554,4 +557,6 @@
uint32_t maxMemorySlot;
};
+} // namespace gem5
+
#endif
diff --git a/src/cpu/kvm/x86_cpu.cc b/src/cpu/kvm/x86_cpu.cc
index 8b2b578..6b4e2ef 100644
--- a/src/cpu/kvm/x86_cpu.cc
+++ b/src/cpu/kvm/x86_cpu.cc
@@ -48,6 +48,9 @@
#include "debug/KvmIO.hh"
#include "debug/KvmInt.hh"
+namespace gem5
+{
+
using namespace X86ISA;
#define MSR_TSC 0x10
@@ -1623,3 +1626,5 @@
if (ioctl(KVM_SET_VCPU_EVENTS, (void *)&events) == -1)
panic("KVM: Failed to set guest debug registers\n");
}
+
+} // namespace gem5
diff --git a/src/cpu/kvm/x86_cpu.hh b/src/cpu/kvm/x86_cpu.hh
index 19743f4..69390a8 100644
--- a/src/cpu/kvm/x86_cpu.hh
+++ b/src/cpu/kvm/x86_cpu.hh
@@ -42,6 +42,9 @@
struct kvm_xcrs;
struct kvm_xsave;
+namespace gem5
+{
+
/**
* x86 implementation of a KVM-based hardware virtualized CPU.
*/
@@ -259,4 +262,6 @@
/** @} */
};
+} // namespace gem5
+
#endif
diff --git a/src/cpu/minor/MinorCPU.py b/src/cpu/minor/MinorCPU.py
index e9003bd..5b360ca 100644
--- a/src/cpu/minor/MinorCPU.py
+++ b/src/cpu/minor/MinorCPU.py
@@ -53,6 +53,7 @@
type = 'MinorOpClass'
cxx_header = "cpu/minor/func_unit.hh"
+ cxx_class = 'gem5::MinorOpClass'
opClass = Param.OpClass("op class to match")
@@ -61,6 +62,7 @@
type = 'MinorOpClassSet'
cxx_header = "cpu/minor/func_unit.hh"
+ cxx_class = 'gem5::MinorOpClassSet'
opClasses = VectorParam.MinorOpClass([], "op classes to be matched."
" An empty list means any class")
@@ -68,6 +70,7 @@
class MinorFUTiming(SimObject):
type = 'MinorFUTiming'
cxx_header = "cpu/minor/func_unit.hh"
+ cxx_class = 'gem5::MinorFUTiming'
mask = Param.UInt64(0, "mask for testing ExtMachInst")
match = Param.UInt64(0, "match value for testing ExtMachInst:"
@@ -101,6 +104,7 @@
class MinorFU(SimObject):
type = 'MinorFU'
cxx_header = "cpu/minor/func_unit.hh"
+ cxx_class = 'gem5::MinorFU'
opClasses = Param.MinorOpClassSet(MinorOpClassSet(), "type of operations"
" allowed on this functional unit")
@@ -116,6 +120,7 @@
class MinorFUPool(SimObject):
type = 'MinorFUPool'
cxx_header = "cpu/minor/func_unit.hh"
+ cxx_class = 'gem5::MinorFUPool'
funcUnits = VectorParam.MinorFU("functional units")
@@ -182,6 +187,7 @@
class MinorCPU(BaseCPU):
type = 'MinorCPU'
cxx_header = "cpu/minor/cpu.hh"
+ cxx_class = 'gem5::MinorCPU'
@classmethod
def memory_mode(cls):
diff --git a/src/cpu/minor/activity.cc b/src/cpu/minor/activity.cc
index 0980eba..f78e927 100644
--- a/src/cpu/minor/activity.cc
+++ b/src/cpu/minor/activity.cc
@@ -41,6 +41,9 @@
#include "cpu/minor/trace.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -65,3 +68,4 @@
}
} // namespace minor
+} // namespace gem5
diff --git a/src/cpu/minor/activity.hh b/src/cpu/minor/activity.hh
index 7deba3d..b942217 100644
--- a/src/cpu/minor/activity.hh
+++ b/src/cpu/minor/activity.hh
@@ -47,6 +47,9 @@
#include "cpu/activity.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -67,5 +70,6 @@
};
} // namespace minor
+} // namespace gem5
#endif /* __CPU_MINOR_ACTIVITY_HH__ */
diff --git a/src/cpu/minor/buffers.hh b/src/cpu/minor/buffers.hh
index 686329c..648ec49 100644
--- a/src/cpu/minor/buffers.hh
+++ b/src/cpu/minor/buffers.hh
@@ -56,6 +56,9 @@
#include "cpu/minor/trace.hh"
#include "cpu/timebuf.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -656,5 +659,6 @@
};
} // namespace minor
+} // namespace gem5
#endif /* __CPU_MINOR_BUFFERS_HH__ */
diff --git a/src/cpu/minor/cpu.cc b/src/cpu/minor/cpu.cc
index 31de890..713acc5 100644
--- a/src/cpu/minor/cpu.cc
+++ b/src/cpu/minor/cpu.cc
@@ -44,6 +44,9 @@
#include "debug/MinorCPU.hh"
#include "debug/Quiesce.hh"
+namespace gem5
+{
+
MinorCPU::MinorCPU(const MinorCPUParams ¶ms) :
BaseCPU(params),
threadPolicy(params.threadPolicy),
@@ -338,3 +341,5 @@
return ret;
}
+
+} // namespace gem5
diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh
index 306d5e5..57b73b7 100644
--- a/src/cpu/minor/cpu.hh
+++ b/src/cpu/minor/cpu.hh
@@ -52,6 +52,9 @@
#include "enums/ThreadPolicy.hh"
#include "params/MinorCPU.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -199,4 +202,6 @@
EventFunctionWrapper *fetchEventWrapper;
};
+} // namespace gem5
+
#endif /* __CPU_MINOR_CPU_HH__ */
diff --git a/src/cpu/minor/decode.cc b/src/cpu/minor/decode.cc
index 1398d03..ab908e0 100644
--- a/src/cpu/minor/decode.cc
+++ b/src/cpu/minor/decode.cc
@@ -42,6 +42,9 @@
#include "cpu/minor/pipeline.hh"
#include "debug/Decode.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -350,3 +353,4 @@
}
} // namespace minor
+} // namespace gem5
diff --git a/src/cpu/minor/decode.hh b/src/cpu/minor/decode.hh
index 17a7db4..8e20e8b 100644
--- a/src/cpu/minor/decode.hh
+++ b/src/cpu/minor/decode.hh
@@ -53,6 +53,9 @@
#include "cpu/minor/dyn_inst.hh"
#include "cpu/minor/pipe_data.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -162,5 +165,6 @@
};
} // namespace minor
+} // namespace gem5
#endif /* __CPU_MINOR_DECODE_HH__ */
diff --git a/src/cpu/minor/dyn_inst.cc b/src/cpu/minor/dyn_inst.cc
index fd28661..4fe2f5a 100644
--- a/src/cpu/minor/dyn_inst.cc
+++ b/src/cpu/minor/dyn_inst.cc
@@ -48,6 +48,9 @@
#include "debug/MinorExecute.hh"
#include "enums/OpClass.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -243,3 +246,4 @@
}
} // namespace minor
+} // namespace gem5
diff --git a/src/cpu/minor/dyn_inst.hh b/src/cpu/minor/dyn_inst.hh
index b61e769..d71ccec 100644
--- a/src/cpu/minor/dyn_inst.hh
+++ b/src/cpu/minor/dyn_inst.hh
@@ -59,6 +59,9 @@
#include "sim/faults.hh"
#include "sim/insttracer.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -296,5 +299,6 @@
std::ostream &operator <<(std::ostream &os, const MinorDynInst &inst);
} // namespace minor
+} // namespace gem5
#endif /* __CPU_MINOR_DYN_INST_HH__ */
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 261db67..d68c359 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -56,6 +56,9 @@
#include "mem/request.hh"
#include "debug/MinorExecute.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -67,7 +70,7 @@
* separates that interface from other classes such as Pipeline, MinorCPU
* and DynMinorInst and makes it easier to see what state is accessed by it.
*/
-class ExecContext : public ::ExecContext
+class ExecContext : public gem5::ExecContext
{
public:
MinorCPU &cpu;
@@ -405,5 +408,6 @@
};
} // namespace minor
+} // namespace gem5
#endif /* __CPU_MINOR_EXEC_CONTEXT_HH__ */
diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index 5059e4f..39a652d 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -53,6 +53,9 @@
#include "debug/MinorTrace.hh"
#include "debug/PCEvent.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -1898,3 +1901,4 @@
}
} // namespace minor
+} // namespace gem5
diff --git a/src/cpu/minor/execute.hh b/src/cpu/minor/execute.hh
index 1facfae..56966ba 100644
--- a/src/cpu/minor/execute.hh
+++ b/src/cpu/minor/execute.hh
@@ -56,6 +56,9 @@
#include "cpu/minor/pipe_data.hh"
#include "cpu/minor/scoreboard.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -361,5 +364,6 @@
};
} // namespace minor
+} // namespace gem5
#endif /* __CPU_MINOR_EXECUTE_HH__ */
diff --git a/src/cpu/minor/fetch1.cc b/src/cpu/minor/fetch1.cc
index b80cec5..2fd6eb0 100644
--- a/src/cpu/minor/fetch1.cc
+++ b/src/cpu/minor/fetch1.cc
@@ -50,6 +50,9 @@
#include "debug/Fetch.hh"
#include "debug/MinorTrace.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -774,3 +777,4 @@
}
} // namespace minor
+} // namespace gem5
diff --git a/src/cpu/minor/fetch1.hh b/src/cpu/minor/fetch1.hh
index e668a6f..c29a4af 100644
--- a/src/cpu/minor/fetch1.hh
+++ b/src/cpu/minor/fetch1.hh
@@ -54,6 +54,9 @@
#include "cpu/minor/pipe_data.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -411,5 +414,6 @@
};
} // namespace minor
+} // namespace gem5
#endif /* __CPU_MINOR_FETCH1_HH__ */
diff --git a/src/cpu/minor/fetch2.cc b/src/cpu/minor/fetch2.cc
index 52d6ad7..e588e21 100644
--- a/src/cpu/minor/fetch2.cc
+++ b/src/cpu/minor/fetch2.cc
@@ -49,6 +49,9 @@
#include "debug/Fetch.hh"
#include "debug/MinorTrace.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -650,3 +653,4 @@
}
} // namespace minor
+} // namespace gem5
diff --git a/src/cpu/minor/fetch2.hh b/src/cpu/minor/fetch2.hh
index 4ffeb56..09b7867 100644
--- a/src/cpu/minor/fetch2.hh
+++ b/src/cpu/minor/fetch2.hh
@@ -54,6 +54,9 @@
#include "cpu/pred/bpred_unit.hh"
#include "params/MinorCPU.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -229,5 +232,6 @@
};
} // namespace minor
+} // namespace gem5
#endif /* __CPU_MINOR_FETCH2_HH__ */
diff --git a/src/cpu/minor/func_unit.cc b/src/cpu/minor/func_unit.cc
index 150eaf3..17b7a0e 100644
--- a/src/cpu/minor/func_unit.cc
+++ b/src/cpu/minor/func_unit.cc
@@ -46,6 +46,9 @@
#include "debug/MinorTiming.hh"
#include "enums/OpClass.hh"
+namespace gem5
+{
+
MinorOpClassSet::MinorOpClassSet(const MinorOpClassSetParams ¶ms) :
SimObject(params),
opClasses(params.opClasses),
@@ -211,3 +214,4 @@
}
} // namespace minor
+} // namespace gem5
diff --git a/src/cpu/minor/func_unit.hh b/src/cpu/minor/func_unit.hh
index 7eb4438..9400f91 100644
--- a/src/cpu/minor/func_unit.hh
+++ b/src/cpu/minor/func_unit.hh
@@ -61,6 +61,9 @@
#include "sim/clocked_object.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
/** Boxing for MinorOpClass to get around a build problem with C++11 but
* also allow for future additions to op class checking */
class MinorOpClass : public SimObject
@@ -270,5 +273,6 @@
};
} // namespace minor
+} // namespace gem5
#endif /* __CPU_MINOR_FUNC_UNIT_HH__ */
diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index fbc4eba..f0e88f2 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -51,6 +51,9 @@
#include "debug/Activity.hh"
#include "debug/MinorMem.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -1796,3 +1799,4 @@
}
} // namespace minor
+} // namespace gem5
diff --git a/src/cpu/minor/lsq.hh b/src/cpu/minor/lsq.hh
index fb4dda6..d4cdc40 100644
--- a/src/cpu/minor/lsq.hh
+++ b/src/cpu/minor/lsq.hh
@@ -55,6 +55,9 @@
#include "cpu/minor/trace.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -744,5 +747,6 @@
Packet::SenderState *sender_state = NULL, PacketDataPtr data = NULL);
} // namespace minor
+} // namespace gem5
#endif /* __CPU_MINOR_NEW_LSQ_HH__ */
diff --git a/src/cpu/minor/pipe_data.cc b/src/cpu/minor/pipe_data.cc
index d035e49..5a3ec8c 100644
--- a/src/cpu/minor/pipe_data.cc
+++ b/src/cpu/minor/pipe_data.cc
@@ -37,6 +37,9 @@
#include "cpu/minor/pipe_data.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -286,3 +289,4 @@
}
} // namespace minor
+} // namespace gem5
diff --git a/src/cpu/minor/pipe_data.hh b/src/cpu/minor/pipe_data.hh
index fd9748e..f16af27 100644
--- a/src/cpu/minor/pipe_data.hh
+++ b/src/cpu/minor/pipe_data.hh
@@ -54,6 +54,9 @@
#include "cpu/minor/dyn_inst.hh"
#include "cpu/base.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -290,5 +293,6 @@
};
} // namespace minor
+} // namespace gem5
#endif /* __CPU_MINOR_PIPE_DATA_HH__ */
diff --git a/src/cpu/minor/pipeline.cc b/src/cpu/minor/pipeline.cc
index ad1d810..db936e4 100644
--- a/src/cpu/minor/pipeline.cc
+++ b/src/cpu/minor/pipeline.cc
@@ -48,6 +48,9 @@
#include "debug/MinorTrace.hh"
#include "debug/Quiesce.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -256,3 +259,4 @@
}
} // namespace minor
+} // namespace gem5
diff --git a/src/cpu/minor/pipeline.hh b/src/cpu/minor/pipeline.hh
index 5f31c66..f2eab5d 100644
--- a/src/cpu/minor/pipeline.hh
+++ b/src/cpu/minor/pipeline.hh
@@ -54,6 +54,9 @@
#include "params/MinorCPU.hh"
#include "sim/ticked_object.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -140,5 +143,6 @@
};
} // namespace minor
+} // namespace gem5
#endif /* __CPU_MINOR_PIPELINE_HH__ */
diff --git a/src/cpu/minor/scoreboard.cc b/src/cpu/minor/scoreboard.cc
index 235264d..af359ef 100644
--- a/src/cpu/minor/scoreboard.cc
+++ b/src/cpu/minor/scoreboard.cc
@@ -41,6 +41,9 @@
#include "debug/MinorScoreboard.hh"
#include "debug/MinorTiming.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -307,3 +310,4 @@
}
} // namespace minor
+} // namespace gem5
diff --git a/src/cpu/minor/scoreboard.hh b/src/cpu/minor/scoreboard.hh
index 3e865db..a928444 100644
--- a/src/cpu/minor/scoreboard.hh
+++ b/src/cpu/minor/scoreboard.hh
@@ -53,6 +53,9 @@
#include "cpu/minor/trace.hh"
#include "cpu/reg_class.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -159,5 +162,6 @@
};
} // namespace minor
+} // namespace gem5
#endif /* __CPU_MINOR_SCOREBOARD_HH__ */
diff --git a/src/cpu/minor/stats.cc b/src/cpu/minor/stats.cc
index 5d884dc..3c68f14 100644
--- a/src/cpu/minor/stats.cc
+++ b/src/cpu/minor/stats.cc
@@ -37,6 +37,9 @@
#include "cpu/minor/stats.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -79,3 +82,4 @@
}
} // namespace minor
+} // namespace gem5
diff --git a/src/cpu/minor/stats.hh b/src/cpu/minor/stats.hh
index a38891f..ed5f953 100644
--- a/src/cpu/minor/stats.hh
+++ b/src/cpu/minor/stats.hh
@@ -48,6 +48,9 @@
#include "cpu/base.hh"
#include "sim/ticked_object.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -82,5 +85,6 @@
};
} // namespace minor
+} // namespace gem5
#endif /* __CPU_MINOR_STATS_HH__ */
diff --git a/src/cpu/minor/trace.hh b/src/cpu/minor/trace.hh
index a41c2db..8a98764 100644
--- a/src/cpu/minor/trace.hh
+++ b/src/cpu/minor/trace.hh
@@ -54,6 +54,9 @@
#include "base/trace.hh"
#include "debug/MinorTrace.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
@@ -85,5 +88,6 @@
}
} // namespace minor
+} // namespace gem5
#endif /* __CPU_MINOR_TRACE_HH__ */
diff --git a/src/cpu/nativetrace.cc b/src/cpu/nativetrace.cc
index 49870ea..0686bca 100644
--- a/src/cpu/nativetrace.cc
+++ b/src/cpu/nativetrace.cc
@@ -33,6 +33,9 @@
#include "debug/GDBMisc.hh"
#include "params/NativeTrace.hh"
+namespace gem5
+{
+
namespace Trace {
NativeTrace::NativeTrace(const Params &p)
@@ -61,3 +64,4 @@
}
} // namespace Trace
+} // namespace gem5
diff --git a/src/cpu/nativetrace.hh b/src/cpu/nativetrace.hh
index b04b915..c6730dc 100644
--- a/src/cpu/nativetrace.hh
+++ b/src/cpu/nativetrace.hh
@@ -39,6 +39,9 @@
#include "cpu/exetrace.hh"
#include "cpu/static_inst.hh"
+namespace gem5
+{
+
class ThreadContext;
namespace Trace {
@@ -115,5 +118,6 @@
};
} // namespace Trace
+} // namespace gem5
#endif // __CPU_NATIVETRACE_HH__
diff --git a/src/cpu/nop_static_inst.cc b/src/cpu/nop_static_inst.cc
index be76109..8baf948 100644
--- a/src/cpu/nop_static_inst.cc
+++ b/src/cpu/nop_static_inst.cc
@@ -30,6 +30,9 @@
#include "cpu/static_inst.hh"
+namespace gem5
+{
+
namespace
{
@@ -61,3 +64,5 @@
}
StaticInstPtr nopStaticInstPtr = new NopStaticInst;
+
+} // namespace gem5
diff --git a/src/cpu/nop_static_inst.hh b/src/cpu/nop_static_inst.hh
index 9397f85..1c744cd 100644
--- a/src/cpu/nop_static_inst.hh
+++ b/src/cpu/nop_static_inst.hh
@@ -30,7 +30,12 @@
#include "cpu/static_inst_fwd.hh"
+namespace gem5
+{
+
/// Pointer to a statically allocated generic "nop" instruction object.
extern StaticInstPtr nopStaticInstPtr;
+} // namespace gem5
+
#endif // __CPU_NOP_STATIC_INST_HH__
diff --git a/src/cpu/null_static_inst.cc b/src/cpu/null_static_inst.cc
index b9011c7..53f2767 100644
--- a/src/cpu/null_static_inst.cc
+++ b/src/cpu/null_static_inst.cc
@@ -30,4 +30,9 @@
#include "cpu/static_inst.hh"
+namespace gem5
+{
+
const StaticInstPtr nullStaticInstPtr;
+
+} // namespace gem5
diff --git a/src/cpu/null_static_inst.hh b/src/cpu/null_static_inst.hh
index 361c566..a941fbd 100644
--- a/src/cpu/null_static_inst.hh
+++ b/src/cpu/null_static_inst.hh
@@ -30,7 +30,12 @@
#include "cpu/static_inst_fwd.hh"
+namespace gem5
+{
+
/// Statically allocated null StaticInstPtr.
extern const StaticInstPtr nullStaticInstPtr;
+} // namespace gem5
+
#endif // __CPU_NULL_STATIC_INST_HH__
diff --git a/src/cpu/o3/FUPool.py b/src/cpu/o3/FUPool.py
index 1f36717..e9d606e 100644
--- a/src/cpu/o3/FUPool.py
+++ b/src/cpu/o3/FUPool.py
@@ -43,7 +43,7 @@
class FUPool(SimObject):
type = 'FUPool'
- cxx_class = 'o3::FUPool'
+ cxx_class = 'gem5::o3::FUPool'
cxx_header = "cpu/o3/fu_pool.hh"
FUList = VectorParam.FUDesc("list of FU's for this pool")
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 301b216..fb1a9dc 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -56,7 +56,7 @@
class O3CPU(BaseCPU):
type = 'O3CPU'
- cxx_class = 'o3::CPU'
+ cxx_class = 'gem5::o3::CPU'
cxx_header = 'cpu/o3/dyn_inst.hh'
@classmethod
diff --git a/src/cpu/o3/O3Checker.py b/src/cpu/o3/O3Checker.py
index 638b41d..c343cd6 100644
--- a/src/cpu/o3/O3Checker.py
+++ b/src/cpu/o3/O3Checker.py
@@ -29,5 +29,5 @@
class O3Checker(CheckerCPU):
type = 'O3Checker'
- cxx_class = 'o3::Checker'
+ cxx_class = 'gem5::o3::Checker'
cxx_header = 'cpu/o3/checker.hh'
diff --git a/src/cpu/o3/checker.cc b/src/cpu/o3/checker.cc
index 50de2dd..926fcbf 100644
--- a/src/cpu/o3/checker.cc
+++ b/src/cpu/o3/checker.cc
@@ -42,5 +42,10 @@
#include "cpu/checker/cpu_impl.hh"
+namespace gem5
+{
+
template
class Checker<o3::DynInstPtr>;
+
+} // namespace gem5
diff --git a/src/cpu/o3/checker.hh b/src/cpu/o3/checker.hh
index ed880d2..29423f7 100644
--- a/src/cpu/o3/checker.hh
+++ b/src/cpu/o3/checker.hh
@@ -44,16 +44,19 @@
#include "cpu/checker/cpu.hh"
#include "cpu/o3/dyn_inst.hh"
+namespace gem5
+{
+
namespace o3
{
/**
* Specific non-templated derived class used for SimObject configuration.
*/
-class Checker : public ::Checker<DynInstPtr>
+class Checker : public gem5::Checker<DynInstPtr>
{
public:
- Checker(const Params &p) : ::Checker<DynInstPtr>(p)
+ Checker(const Params &p) : gem5::Checker<DynInstPtr>(p)
{
// The checker should check all instructions executed by the main
// cpu and therefore any parameters for early exit don't make much
@@ -64,5 +67,6 @@
};
} // namespace o3
+} // namespace gem5
#endif // __CPU_O3_CHECKER_HH__
diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh
index e4c3a20..013ef99 100644
--- a/src/cpu/o3/comm.hh
+++ b/src/cpu/o3/comm.hh
@@ -51,6 +51,9 @@
#include "cpu/o3/limits.hh"
#include "sim/faults.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -223,5 +226,6 @@
};
} // namespace o3
+} // namespace gem5
#endif //__CPU_O3_COMM_HH__
diff --git a/src/cpu/o3/commit.cc b/src/cpu/o3/commit.cc
index 23265d4..9d70647 100644
--- a/src/cpu/o3/commit.cc
+++ b/src/cpu/o3/commit.cc
@@ -68,6 +68,9 @@
#include "sim/faults.hh"
#include "sim/full_system.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -1536,3 +1539,4 @@
}
} // namespace o3
+} // namespace gem5
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 6c4e780..bcb7c23 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -56,6 +56,9 @@
#include "enums/CommitPolicy.hh"
#include "sim/probe/probe.hh"
+namespace gem5
+{
+
struct O3CPUParams;
namespace o3
@@ -517,5 +520,6 @@
};
} // namespace o3
+} // namespace gem5
#endif // __CPU_O3_COMMIT_HH__
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 873ba01..1c6a9f3 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -61,6 +61,9 @@
#include "sim/stat_control.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
struct BaseCPUParams;
namespace o3
@@ -320,7 +323,7 @@
}
}
- ::ThreadContext *tc;
+ gem5::ThreadContext *tc;
// Setup the TC that will serve as the interface to the threads/CPU.
auto *o3_tc = new ThreadContext;
@@ -734,7 +737,7 @@
DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
// Will change now that the PC and thread state is internal to the CPU
// and not in the ThreadContext.
- ::ThreadContext *src_tc;
+ gem5::ThreadContext *src_tc;
if (FullSystem)
src_tc = system->threads[tid];
else
@@ -769,7 +772,7 @@
//Set PC/NPC/NNPC
pcState(src_tc->pcState(), tid);
- src_tc->setStatus(::ThreadContext::Active);
+ src_tc->setStatus(gem5::ThreadContext::Active);
activateContext(tid);
@@ -938,7 +941,7 @@
if (!isCpuDrained()) {
// If a thread is suspended, wake it up so it can be drained
for (auto t : threadContexts) {
- if (t->status() == ::ThreadContext::Suspended){
+ if (t->status() == gem5::ThreadContext::Suspended){
DPRINTF(Drain, "Currently suspended so activate %i \n",
t->threadId());
t->activate();
@@ -1055,7 +1058,7 @@
_status = Idle;
for (ThreadID i = 0; i < thread.size(); i++) {
- if (thread[i]->status() == ::ThreadContext::Active) {
+ if (thread[i]->status() == gem5::ThreadContext::Active) {
DPRINTF(Drain, "Activating thread: %i\n", i);
activateThread(i);
_status = Running;
@@ -1610,7 +1613,7 @@
void
CPU::wakeup(ThreadID tid)
{
- if (thread[tid]->status() != ::ThreadContext::Suspended)
+ if (thread[tid]->status() != gem5::ThreadContext::Suspended)
return;
wakeCPU();
@@ -1654,7 +1657,7 @@
DPRINTF(O3CPU, "Thread %d is inserted to exitingThreads list\n", tid);
// the thread trying to exit can't be already halted
- assert(tcBase(tid)->status() != ::ThreadContext::Halted);
+ assert(tcBase(tid)->status() != gem5::ThreadContext::Halted);
// make sure the thread has not been added to the list yet
assert(exitingThreads.count(tid) == 0);
@@ -1708,7 +1711,7 @@
if (readyToExit) {
DPRINTF(O3CPU, "Exiting thread %d\n", thread_id);
haltContext(thread_id);
- tcBase(thread_id)->setStatus(::ThreadContext::Halted);
+ tcBase(thread_id)->setStatus(gem5::ThreadContext::Halted);
it = exitingThreads.erase(it);
} else {
it++;
@@ -1752,3 +1755,4 @@
}
} // namespace o3
+} // namespace gem5
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index e225c38..4e82df0 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -72,6 +72,9 @@
#include "params/O3CPU.hh"
#include "sim/process.hh"
+namespace gem5
+{
+
template <class>
class Checker;
class ThreadContext;
@@ -583,7 +586,7 @@
public:
/** Returns a pointer to a thread context. */
- ::ThreadContext *
+ gem5::ThreadContext *
tcBase(ThreadID tid)
{
return thread[tid]->getTC();
@@ -596,7 +599,7 @@
* instruction results at run time. This can be set to NULL if it
* is not being used.
*/
- ::Checker<DynInstPtr> *checker;
+ gem5::Checker<DynInstPtr> *checker;
/** Pointer to the system. */
System *system;
@@ -709,5 +712,6 @@
};
} // namespace o3
+} // namespace gem5
#endif // __CPU_O3_CPU_HH__
diff --git a/src/cpu/o3/decode.cc b/src/cpu/o3/decode.cc
index c568f5d..64aa9ce 100644
--- a/src/cpu/o3/decode.cc
+++ b/src/cpu/o3/decode.cc
@@ -56,6 +56,9 @@
// we open up the entire namespace std
using std::list;
+namespace gem5
+{
+
namespace o3
{
@@ -746,3 +749,4 @@
}
} // namespace o3
+} // namespace gem5
diff --git a/src/cpu/o3/decode.hh b/src/cpu/o3/decode.hh
index fbe9dfd..e8c2db2 100644
--- a/src/cpu/o3/decode.hh
+++ b/src/cpu/o3/decode.hh
@@ -49,6 +49,9 @@
#include "cpu/o3/limits.hh"
#include "cpu/timebuf.hh"
+namespace gem5
+{
+
struct O3CPUParams;
namespace o3
@@ -321,5 +324,6 @@
};
} // namespace o3
+} // namespace gem5
#endif // __CPU_O3_DECODE_HH__
diff --git a/src/cpu/o3/dep_graph.hh b/src/cpu/o3/dep_graph.hh
index ef59835..f5e74b7 100644
--- a/src/cpu/o3/dep_graph.hh
+++ b/src/cpu/o3/dep_graph.hh
@@ -43,6 +43,9 @@
#include "cpu/o3/comm.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -296,5 +299,6 @@
}
} // namespace o3
+} // namespace gem5
#endif // __CPU_O3_DEP_GRAPH_HH__
diff --git a/src/cpu/o3/dyn_inst.cc b/src/cpu/o3/dyn_inst.cc
index da89d95..bb7cf18 100644
--- a/src/cpu/o3/dyn_inst.cc
+++ b/src/cpu/o3/dyn_inst.cc
@@ -46,6 +46,9 @@
#include "debug/IQ.hh"
#include "debug/O3PipeView.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -331,3 +334,4 @@
}
} // namespace o3
+} // namespace gem5
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 31a0a11..79263dc 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -65,6 +65,9 @@
#include "cpu/translation.hh"
#include "debug/HtmCpu.hh"
+namespace gem5
+{
+
class Packet;
namespace o3
@@ -1018,7 +1021,7 @@
void setThreadState(ThreadState *state) { thread = state; }
/** Returns the thread context. */
- ::ThreadContext *tcBase() const override { return thread->getTC(); }
+ gem5::ThreadContext *tcBase() const override { return thread->getTC(); }
public:
/** Is this instruction's memory access strictly ordered? */
@@ -1064,7 +1067,7 @@
return cpu->mwait(threadNumber, pkt);
}
void
- mwaitAtomic(::ThreadContext *tc) override
+ mwaitAtomic(gem5::ThreadContext *tc) override
{
return cpu->mwaitAtomic(threadNumber, tc, cpu->mmu);
}
@@ -1328,5 +1331,6 @@
};
} // namespace o3
+} // namespace gem5
#endif // __CPU_O3_DYN_INST_HH__
diff --git a/src/cpu/o3/dyn_inst_ptr.hh b/src/cpu/o3/dyn_inst_ptr.hh
index ffc4f2d..38a38c3 100644
--- a/src/cpu/o3/dyn_inst_ptr.hh
+++ b/src/cpu/o3/dyn_inst_ptr.hh
@@ -44,6 +44,9 @@
#include "base/refcnt.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -53,5 +56,6 @@
using DynInstConstPtr = RefCountingPtr<const DynInst>;
} // namespace o3
+} // namespace gem5
#endif // __CPU_O3_DYN_INST_PTR_HH__
diff --git a/src/cpu/o3/fetch.cc b/src/cpu/o3/fetch.cc
index eb9e750..5637e5a 100644
--- a/src/cpu/o3/fetch.cc
+++ b/src/cpu/o3/fetch.cc
@@ -70,6 +70,9 @@
#include "sim/full_system.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -1621,3 +1624,4 @@
}
} // namespace o3
+} // namespace gem5
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 46c1219..b543709 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -57,6 +57,9 @@
#include "sim/eventq.hh"
#include "sim/probe/probe.hh"
+namespace gem5
+{
+
struct O3CPUParams;
namespace o3
@@ -109,8 +112,8 @@
void markDelayed() {}
void
- finish(const Fault &fault, const RequestPtr &req, ::ThreadContext *tc,
- BaseTLB::Mode mode)
+ finish(const Fault &fault, const RequestPtr &req,
+ gem5::ThreadContext *tc, BaseTLB::Mode mode)
{
assert(mode == BaseTLB::Execute);
fetch->finishTranslation(fault, req);
@@ -586,5 +589,6 @@
};
} // namespace o3
+} // namespace gem5
#endif //__CPU_O3_FETCH_HH__
diff --git a/src/cpu/o3/free_list.cc b/src/cpu/o3/free_list.cc
index bc57f16..ceb8508 100644
--- a/src/cpu/o3/free_list.cc
+++ b/src/cpu/o3/free_list.cc
@@ -32,6 +32,9 @@
#include "base/trace.hh"
#include "debug/FreeList.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -47,3 +50,4 @@
}
} // namespace o3
+} // namespace gem5
diff --git a/src/cpu/o3/free_list.hh b/src/cpu/o3/free_list.hh
index 869d7a2..b634690 100644
--- a/src/cpu/o3/free_list.hh
+++ b/src/cpu/o3/free_list.hh
@@ -51,6 +51,9 @@
#include "cpu/o3/regfile.hh"
#include "debug/FreeList.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -341,5 +344,6 @@
}
} // namespace o3
+} // namespace gem5
#endif // __CPU_O3_FREE_LIST_HH__
diff --git a/src/cpu/o3/fu_pool.cc b/src/cpu/o3/fu_pool.cc
index 2cacf7d..948d6de 100644
--- a/src/cpu/o3/fu_pool.cc
+++ b/src/cpu/o3/fu_pool.cc
@@ -44,6 +44,9 @@
#include "cpu/func_unit.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -248,3 +251,4 @@
}
} // namespace o3
+} // namespace gem5
diff --git a/src/cpu/o3/fu_pool.hh b/src/cpu/o3/fu_pool.hh
index b22f5e0..3c88a69 100644
--- a/src/cpu/o3/fu_pool.hh
+++ b/src/cpu/o3/fu_pool.hh
@@ -51,6 +51,9 @@
#include "params/FUPool.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class FUDesc;
class FuncUnit;
@@ -180,5 +183,6 @@
};
} // namespace o3
+} // namespace gem5
#endif // __CPU_O3_FU_POOL_HH__
diff --git a/src/cpu/o3/iew.cc b/src/cpu/o3/iew.cc
index a3985ab..f21fc74 100644
--- a/src/cpu/o3/iew.cc
+++ b/src/cpu/o3/iew.cc
@@ -59,6 +59,9 @@
#include "debug/O3PipeView.hh"
#include "params/O3CPU.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -1624,3 +1627,4 @@
}
} // namespace o3
+} // namespace gem5
diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh
index b1667df..ea5350d 100644
--- a/src/cpu/o3/iew.hh
+++ b/src/cpu/o3/iew.hh
@@ -55,6 +55,9 @@
#include "debug/IEW.hh"
#include "sim/probe/probe.hh"
+namespace gem5
+{
+
struct O3CPUParams;
namespace o3
@@ -489,5 +492,6 @@
};
} // namespace o3
+} // namespace gem5
#endif // __CPU_O3_IEW_HH__
diff --git a/src/cpu/o3/inst_queue.cc b/src/cpu/o3/inst_queue.cc
index cc38104..775fbcd 100644
--- a/src/cpu/o3/inst_queue.cc
+++ b/src/cpu/o3/inst_queue.cc
@@ -57,6 +57,9 @@
// we open up the entire namespace std
using std::list;
+namespace gem5
+{
+
namespace o3
{
@@ -1577,3 +1580,4 @@
}
} // namespace o3
+} // namespace gem5
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index 6be78d0..b69344a 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -61,6 +61,9 @@
#include "enums/SMTQueuePolicy.hh"
#include "sim/eventq.hh"
+namespace gem5
+{
+
struct O3CPUParams;
class MemInterface;
@@ -556,5 +559,6 @@
};
} // namespace o3
+} // namespace gem5
#endif //__CPU_O3_INST_QUEUE_HH__
diff --git a/src/cpu/o3/limits.hh b/src/cpu/o3/limits.hh
index 25a16f4..027a76c 100644
--- a/src/cpu/o3/limits.hh
+++ b/src/cpu/o3/limits.hh
@@ -28,6 +28,9 @@
#ifndef __CPU_O3_LIMITS_HH__
#define __CPU_O3_LIMITS_HH__
+namespace gem5
+{
+
namespace o3
{
@@ -35,5 +38,6 @@
static constexpr int MaxThreads = 4;
} // namespace o3
+} // namespace gem5
#endif // __CPU_O3_LIMITS_HH__
diff --git a/src/cpu/o3/lsq.cc b/src/cpu/o3/lsq.cc
index a82fc9c..d1ae662 100644
--- a/src/cpu/o3/lsq.cc
+++ b/src/cpu/o3/lsq.cc
@@ -58,6 +58,9 @@
#include "debug/Writeback.hh"
#include "params/O3CPU.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -856,7 +859,7 @@
void
LSQ::SingleDataRequest::finish(const Fault &fault, const RequestPtr &req,
- ::ThreadContext* tc, BaseTLB::Mode mode)
+ gem5::ThreadContext* tc, BaseTLB::Mode mode)
{
_fault.push_back(fault);
numInTranslationFragments = 0;
@@ -888,7 +891,7 @@
void
LSQ::SplitDataRequest::finish(const Fault &fault, const RequestPtr &req,
- ::ThreadContext* tc, BaseTLB::Mode mode)
+ gem5::ThreadContext* tc, BaseTLB::Mode mode)
{
int i;
for (i = 0; i < _requests.size() && _requests[i] != req; i++);
@@ -1275,14 +1278,14 @@
Cycles
LSQ::SingleDataRequest::handleLocalAccess(
- ::ThreadContext *thread, PacketPtr pkt)
+ gem5::ThreadContext *thread, PacketPtr pkt)
{
return pkt->req->localAccessor(thread, pkt);
}
Cycles
LSQ::SplitDataRequest::handleLocalAccess(
- ::ThreadContext *thread, PacketPtr mainPkt)
+ gem5::ThreadContext *thread, PacketPtr mainPkt)
{
Cycles delay(0);
unsigned offset = 0;
@@ -1412,7 +1415,7 @@
void
LSQ::HtmCmdRequest::finish(const Fault &fault, const RequestPtr &req,
- ::ThreadContext* tc, BaseTLB::Mode mode)
+ gem5::ThreadContext* tc, BaseTLB::Mode mode)
{
panic("unexpected behaviour");
}
@@ -1434,3 +1437,4 @@
}
} // namespace o3
+} // namespace gem5
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 13665ac..03a2caa 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -59,6 +59,9 @@
#include "mem/port.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
struct O3CPUParams;
namespace o3
@@ -228,7 +231,7 @@
{
protected:
typedef uint32_t FlagsStorage;
- typedef ::Flags<FlagsStorage> FlagsType;
+ typedef Flags<FlagsStorage> FlagsType;
enum Flag : FlagsStorage
{
@@ -481,7 +484,7 @@
* Memory mapped IPR accesses
*/
virtual Cycles handleLocalAccess(
- ::ThreadContext *thread, PacketPtr pkt) = 0;
+ gem5::ThreadContext *thread, PacketPtr pkt) = 0;
/**
* Test if the request accesses a particular cache line.
@@ -664,12 +667,12 @@
virtual ~SingleDataRequest() {}
virtual void initiateTranslation();
virtual void finish(const Fault &fault, const RequestPtr &req,
- ::ThreadContext* tc, BaseTLB::Mode mode);
+ gem5::ThreadContext* tc, BaseTLB::Mode mode);
virtual bool recvTimingResp(PacketPtr pkt);
virtual void sendPacketToCache();
virtual void buildPackets();
virtual Cycles handleLocalAccess(
- ::ThreadContext *thread, PacketPtr pkt);
+ gem5::ThreadContext *thread, PacketPtr pkt);
virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask);
virtual std::string name() const { return "SingleDataRequest"; }
};
@@ -698,7 +701,7 @@
virtual ~HtmCmdRequest() {}
virtual void initiateTranslation();
virtual void finish(const Fault &fault, const RequestPtr &req,
- ::ThreadContext* tc, BaseTLB::Mode mode);
+ gem5::ThreadContext* tc, BaseTLB::Mode mode);
virtual std::string name() const { return "HtmCmdRequest"; }
};
@@ -764,14 +767,14 @@
}
}
virtual void finish(const Fault &fault, const RequestPtr &req,
- ::ThreadContext* tc, BaseTLB::Mode mode);
+ gem5::ThreadContext* tc, BaseTLB::Mode mode);
virtual bool recvTimingResp(PacketPtr pkt);
virtual void initiateTranslation();
virtual void sendPacketToCache();
virtual void buildPackets();
virtual Cycles handleLocalAccess(
- ::ThreadContext *thread, PacketPtr pkt);
+ gem5::ThreadContext *thread, PacketPtr pkt);
virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask);
virtual RequestPtr mainRequest();
@@ -1069,5 +1072,6 @@
};
} // namespace o3
+} // namespace gem5
#endif // __CPU_O3_LSQ_HH__
diff --git a/src/cpu/o3/lsq_unit.cc b/src/cpu/o3/lsq_unit.cc
index 3393686..4102bd3 100644
--- a/src/cpu/o3/lsq_unit.cc
+++ b/src/cpu/o3/lsq_unit.cc
@@ -56,6 +56,9 @@
#include "mem/packet.hh"
#include "mem/request.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -445,7 +448,7 @@
DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr());
for (int x = 0; x < cpu->numContexts(); x++) {
- ::ThreadContext *tc = cpu->getContext(x);
+ gem5::ThreadContext *tc = cpu->getContext(x);
bool no_squash = cpu->thread[x]->noSquashFromTC;
cpu->thread[x]->noSquashFromTC = true;
TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask);
@@ -905,7 +908,7 @@
if (req->request()->isLocalAccess()) {
assert(!inst->isStoreConditional());
assert(!inst->inHtmTransactionalState());
- ::ThreadContext *thread = cpu->tcBase(lsqID);
+ gem5::ThreadContext *thread = cpu->tcBase(lsqID);
PacketPtr main_pkt = new Packet(req->mainRequest(),
MemCmd::WriteReq);
main_pkt->dataStatic(inst->memData);
@@ -1353,7 +1356,7 @@
assert(!load_inst->inHtmTransactionalState());
load_inst->memData = new uint8_t[MaxDataBytes];
- ::ThreadContext *thread = cpu->tcBase(lsqID);
+ gem5::ThreadContext *thread = cpu->tcBase(lsqID);
PacketPtr main_pkt = new Packet(req->mainRequest(), MemCmd::ReadReq);
main_pkt->dataStatic(load_inst->memData);
@@ -1668,3 +1671,4 @@
}
} // namespace o3
+} // namespace gem5
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 790054f..88e9849 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -51,6 +51,7 @@
#include "arch/generic/debugfaults.hh"
#include "arch/generic/vec_reg.hh"
#include "arch/locked_mem.hh"
+#include "base/circular_queue.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/inst_seq.hh"
@@ -64,8 +65,10 @@
#include "mem/packet.hh"
#include "mem/port.hh"
+namespace gem5
+{
+
struct O3CPUParams;
-#include "base/circular_queue.hh"
namespace o3
{
@@ -605,5 +608,6 @@
};
} // namespace o3
+} // namespace gem5
#endif // __CPU_O3_LSQ_UNIT_HH__
diff --git a/src/cpu/o3/mem_dep_unit.cc b/src/cpu/o3/mem_dep_unit.cc
index d12ce21..42e8471 100644
--- a/src/cpu/o3/mem_dep_unit.cc
+++ b/src/cpu/o3/mem_dep_unit.cc
@@ -40,6 +40,9 @@
#include "debug/MemDepUnit.hh"
#include "params/O3CPU.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -637,3 +640,4 @@
}
} // namespace o3
+} // namespace gem5
diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh
index 1754b0a..c6b270c 100644
--- a/src/cpu/o3/mem_dep_unit.hh
+++ b/src/cpu/o3/mem_dep_unit.hh
@@ -54,6 +54,9 @@
#include "cpu/o3/store_set.hh"
#include "debug/MemDepUnit.hh"
+namespace gem5
+{
+
struct SNHash
{
size_t
@@ -277,5 +280,6 @@
};
} // namespace o3
+} // namespace gem5
#endif // __CPU_O3_MEM_DEP_UNIT_HH__
diff --git a/src/cpu/o3/probe/ElasticTrace.py b/src/cpu/o3/probe/ElasticTrace.py
index 8441fa0..5386292 100644
--- a/src/cpu/o3/probe/ElasticTrace.py
+++ b/src/cpu/o3/probe/ElasticTrace.py
@@ -37,7 +37,7 @@
class ElasticTrace(ProbeListenerObject):
type = 'ElasticTrace'
- cxx_class = 'o3::ElasticTrace'
+ cxx_class = 'gem5::o3::ElasticTrace'
cxx_header = 'cpu/o3/probe/elastic_trace.hh'
# Trace files for the following params are created in the output directory.
diff --git a/src/cpu/o3/probe/SimpleTrace.py b/src/cpu/o3/probe/SimpleTrace.py
index d0c3b9d..9d36bec 100644
--- a/src/cpu/o3/probe/SimpleTrace.py
+++ b/src/cpu/o3/probe/SimpleTrace.py
@@ -37,5 +37,5 @@
class SimpleTrace(ProbeListenerObject):
type = 'SimpleTrace'
- cxx_class = 'o3::SimpleTrace'
+ cxx_class = 'gem5::o3::SimpleTrace'
cxx_header = 'cpu/o3/probe/simple_trace.hh'
diff --git a/src/cpu/o3/probe/elastic_trace.cc b/src/cpu/o3/probe/elastic_trace.cc
index 56816b0..95baa59 100644
--- a/src/cpu/o3/probe/elastic_trace.cc
+++ b/src/cpu/o3/probe/elastic_trace.cc
@@ -45,6 +45,9 @@
#include "debug/ElasticTrace.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -928,3 +931,4 @@
}
} // namespace o3
+} // namespace gem5
diff --git a/src/cpu/o3/probe/elastic_trace.hh b/src/cpu/o3/probe/elastic_trace.hh
index 4dddcea..53a6cbe 100644
--- a/src/cpu/o3/probe/elastic_trace.hh
+++ b/src/cpu/o3/probe/elastic_trace.hh
@@ -61,6 +61,9 @@
#include "sim/eventq.hh"
#include "sim/probe/probe.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -560,5 +563,6 @@
};
} // namespace o3
+} // namespace gem5
#endif//__CPU_O3_PROBE_ELASTIC_TRACE_HH__
diff --git a/src/cpu/o3/probe/simple_trace.cc b/src/cpu/o3/probe/simple_trace.cc
index 2431aba..c44e7ab 100644
--- a/src/cpu/o3/probe/simple_trace.cc
+++ b/src/cpu/o3/probe/simple_trace.cc
@@ -41,6 +41,9 @@
#include "cpu/o3/dyn_inst.hh"
#include "debug/SimpleTrace.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -72,3 +75,4 @@
}
} // namespace o3
+} // namespace gem5
diff --git a/src/cpu/o3/probe/simple_trace.hh b/src/cpu/o3/probe/simple_trace.hh
index 7fc5565..c3f1727 100644
--- a/src/cpu/o3/probe/simple_trace.hh
+++ b/src/cpu/o3/probe/simple_trace.hh
@@ -48,6 +48,9 @@
#include "params/SimpleTrace.hh"
#include "sim/probe/probe.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -76,5 +79,6 @@
};
} // namespace o3
+} // namespace gem5
#endif//__CPU_O3_PROBE_SIMPLE_TRACE_HH__
diff --git a/src/cpu/o3/regfile.cc b/src/cpu/o3/regfile.cc
index 06a1355..fed4125 100644
--- a/src/cpu/o3/regfile.cc
+++ b/src/cpu/o3/regfile.cc
@@ -45,6 +45,9 @@
#include "arch/generic/types.hh"
#include "cpu/o3/free_list.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -235,3 +238,4 @@
}
} // namespace o3
+} // namespace gem5
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index a2fbe67..c7cf807 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -52,6 +52,9 @@
#include "debug/IEW.hh"
#include "enums/VecRegRenameMode.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -365,5 +368,6 @@
};
} // namespace o3
+} // namespace gem5
#endif //__CPU_O3_REGFILE_HH__
diff --git a/src/cpu/o3/rename.cc b/src/cpu/o3/rename.cc
index f246631..ff052d3 100644
--- a/src/cpu/o3/rename.cc
+++ b/src/cpu/o3/rename.cc
@@ -52,6 +52,9 @@
#include "debug/Rename.hh"
#include "params/O3CPU.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -1009,7 +1012,7 @@
void
Rename::renameSrcRegs(const DynInstPtr &inst, ThreadID tid)
{
- ::ThreadContext *tc = inst->tcBase();
+ gem5::ThreadContext *tc = inst->tcBase();
UnifiedRenameMap *map = renameMap[tid];
unsigned num_src_regs = inst->numSrcRegs();
@@ -1075,7 +1078,7 @@
void
Rename::renameDestRegs(const DynInstPtr &inst, ThreadID tid)
{
- ::ThreadContext *tc = inst->tcBase();
+ gem5::ThreadContext *tc = inst->tcBase();
UnifiedRenameMap *map = renameMap[tid];
unsigned num_dest_regs = inst->numDestRegs();
@@ -1424,3 +1427,4 @@
}
} // namespace o3
+} // namespace gem5
diff --git a/src/cpu/o3/rename.hh b/src/cpu/o3/rename.hh
index 614e605..0204109 100644
--- a/src/cpu/o3/rename.hh
+++ b/src/cpu/o3/rename.hh
@@ -55,6 +55,9 @@
#include "cpu/timebuf.hh"
#include "sim/probe/probe.hh"
+namespace gem5
+{
+
struct O3CPUParams;
namespace o3
@@ -533,5 +536,6 @@
};
} // namespace o3
+} // namespace gem5
#endif // __CPU_O3_RENAME_HH__
diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc
index 071b69c..5589ff8 100644
--- a/src/cpu/o3/rename_map.cc
+++ b/src/cpu/o3/rename_map.cc
@@ -47,6 +47,9 @@
#include "cpu/reg_class.hh"
#include "debug/Rename.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -217,3 +220,4 @@
}
} // namespace o3
+} // namespace gem5
diff --git a/src/cpu/o3/rename_map.hh b/src/cpu/o3/rename_map.hh
index 503f4ab..b8c87e7 100644
--- a/src/cpu/o3/rename_map.hh
+++ b/src/cpu/o3/rename_map.hh
@@ -52,6 +52,9 @@
#include "cpu/reg_class.hh"
#include "enums/VecRegRenameMode.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -401,5 +404,6 @@
};
} // namespace o3
+} // namespace gem5
#endif //__CPU_O3_RENAME_MAP_HH__
diff --git a/src/cpu/o3/rob.cc b/src/cpu/o3/rob.cc
index b58231f..9e42651 100644
--- a/src/cpu/o3/rob.cc
+++ b/src/cpu/o3/rob.cc
@@ -49,6 +49,9 @@
#include "debug/ROB.hh"
#include "params/O3CPU.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -539,3 +542,4 @@
}
} // namespace o3
+} // namespace gem5
diff --git a/src/cpu/o3/rob.hh b/src/cpu/o3/rob.hh
index d81f4b5..3889ef5 100644
--- a/src/cpu/o3/rob.hh
+++ b/src/cpu/o3/rob.hh
@@ -54,6 +54,9 @@
#include "cpu/reg_class.hh"
#include "enums/SMTQueuePolicy.hh"
+namespace gem5
+{
+
struct O3CPUParams;
namespace o3
@@ -340,5 +343,6 @@
};
} // namespace o3
+} // namespace gem5
#endif //__CPU_O3_ROB_HH__
diff --git a/src/cpu/o3/scoreboard.cc b/src/cpu/o3/scoreboard.cc
index f1ca66a..5e9fc8b 100644
--- a/src/cpu/o3/scoreboard.cc
+++ b/src/cpu/o3/scoreboard.cc
@@ -29,6 +29,9 @@
#include "cpu/o3/scoreboard.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -39,3 +42,4 @@
{}
} // namespace o3
+} // namespace gem5
diff --git a/src/cpu/o3/scoreboard.hh b/src/cpu/o3/scoreboard.hh
index c8ca087..7a6b656 100644
--- a/src/cpu/o3/scoreboard.hh
+++ b/src/cpu/o3/scoreboard.hh
@@ -38,6 +38,9 @@
#include "cpu/reg_class.hh"
#include "debug/Scoreboard.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -137,5 +140,6 @@
};
} // namespace o3
+} // namespace gem5
#endif
diff --git a/src/cpu/o3/store_set.cc b/src/cpu/o3/store_set.cc
index a4de79c..cb3b732 100644
--- a/src/cpu/o3/store_set.cc
+++ b/src/cpu/o3/store_set.cc
@@ -33,6 +33,9 @@
#include "base/trace.hh"
#include "debug/StoreSet.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -369,3 +372,4 @@
}
} // namespace o3
+} // namespace gem5
diff --git a/src/cpu/o3/store_set.hh b/src/cpu/o3/store_set.hh
index f818c82..67c8d43 100644
--- a/src/cpu/o3/store_set.hh
+++ b/src/cpu/o3/store_set.hh
@@ -37,6 +37,9 @@
#include "base/types.hh"
#include "cpu/inst_seq.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -161,5 +164,6 @@
};
} // namespace o3
+} // namespace gem5
#endif // __CPU_O3_STORE_SET_HH__
diff --git a/src/cpu/o3/thread_context.cc b/src/cpu/o3/thread_context.cc
index a10de5a..225e03d 100644
--- a/src/cpu/o3/thread_context.cc
+++ b/src/cpu/o3/thread_context.cc
@@ -45,6 +45,9 @@
#include "config/the_isa.hh"
#include "debug/O3CPU.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -55,9 +58,9 @@
}
void
-ThreadContext::takeOverFrom(::ThreadContext *old_context)
+ThreadContext::takeOverFrom(gem5::ThreadContext *old_context)
{
- ::takeOverFrom(*this, *old_context);
+ gem5::takeOverFrom(*this, *old_context);
getIsaPtr()->takeOverFrom(this, old_context);
@@ -75,11 +78,11 @@
DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
threadId());
- if (thread->status() == ::ThreadContext::Active)
+ if (thread->status() == gem5::ThreadContext::Active)
return;
thread->lastActivate = curTick();
- thread->setStatus(::ThreadContext::Active);
+ thread->setStatus(gem5::ThreadContext::Active);
// status() == Suspended
cpu->activateContext(thread->threadId());
@@ -91,7 +94,7 @@
DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
threadId());
- if (thread->status() == ::ThreadContext::Suspended)
+ if (thread->status() == gem5::ThreadContext::Suspended)
return;
if (cpu->isDraining()) {
@@ -102,7 +105,7 @@
thread->lastActivate = curTick();
thread->lastSuspend = curTick();
- thread->setStatus(::ThreadContext::Suspended);
+ thread->setStatus(gem5::ThreadContext::Suspended);
cpu->suspendContext(thread->threadId());
}
@@ -111,15 +114,15 @@
{
DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId());
- if (thread->status() == ::ThreadContext::Halting ||
- thread->status() == ::ThreadContext::Halted)
+ if (thread->status() == gem5::ThreadContext::Halting ||
+ thread->status() == gem5::ThreadContext::Halted)
return;
// the thread is not going to halt/terminate immediately in this cycle.
// The thread will be removed after an exit trap is processed
// (e.g., after trapLatency cycles). Until then, the thread's status
// will be Halting.
- thread->setStatus(::ThreadContext::Halting);
+ thread->setStatus(gem5::ThreadContext::Halting);
// add this thread to the exiting list to mark that it is trying to exit.
cpu->addThreadToExitingList(thread->threadId());
@@ -138,7 +141,7 @@
}
void
-ThreadContext::copyArchRegs(::ThreadContext *tc)
+ThreadContext::copyArchRegs(gem5::ThreadContext *tc)
{
// Set vector renaming mode before copying registers
cpu->vecRenameMode(tc->getIsaPtr()->vecRegRenameMode(tc));
@@ -314,3 +317,4 @@
}
} // namespace o3
+} // namespace gem5
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index e0fd11f..a1fabb6 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -46,6 +46,9 @@
#include "cpu/o3/cpu.hh"
#include "cpu/thread_context.hh"
+namespace gem5
+{
+
namespace o3
{
@@ -62,7 +65,7 @@
* must be taken when using this interface (such as squashing all
* in-flight instructions when doing a write to this interface).
*/
-class ThreadContext : public ::ThreadContext
+class ThreadContext : public gem5::ThreadContext
{
public:
/** Pointer to the CPU. */
@@ -143,7 +146,7 @@
PortProxy &getVirtProxy() override;
void
- initMemProxies(::ThreadContext *tc) override
+ initMemProxies(gem5::ThreadContext *tc) override
{
thread->initMemProxies(tc);
}
@@ -168,7 +171,7 @@
void halt() override;
/** Takes over execution of a thread from another CPU. */
- void takeOverFrom(::ThreadContext *old_context) override;
+ void takeOverFrom(gem5::ThreadContext *old_context) override;
/** Reads the last tick that this thread was activated on. */
Tick readLastActivate() override;
@@ -176,7 +179,7 @@
Tick readLastSuspend() override;
/** Copies the architectural registers from another TC into this TC. */
- void copyArchRegs(::ThreadContext *tc) override;
+ void copyArchRegs(gem5::ThreadContext *tc) override;
/** Resets all architectural registers to 0. */
void clearArchRegs() override;
@@ -400,5 +403,6 @@
};
} // namespace o3
+} // namespace gem5
#endif
diff --git a/src/cpu/o3/thread_state.cc b/src/cpu/o3/thread_state.cc
index bdbb313..c5072e2 100644
--- a/src/cpu/o3/thread_state.cc
+++ b/src/cpu/o3/thread_state.cc
@@ -42,21 +42,24 @@
#include "cpu/o3/cpu.hh"
+namespace gem5
+{
+
namespace o3
{
ThreadState::ThreadState(CPU *_cpu, int _thread_num, Process *_process) :
- ::ThreadState(_cpu, _thread_num, _process),
+ gem5::ThreadState(_cpu, _thread_num, _process),
comInstEventQueue("instruction-based event queue")
{}
void
ThreadState::serialize(CheckpointOut &cp) const
{
- ::ThreadState::serialize(cp);
+ gem5::ThreadState::serialize(cp);
// Use the ThreadContext serialization helper to serialize the
// TC.
- ::serialize(*tc, cp);
+ gem5::serialize(*tc, cp);
}
void
@@ -66,11 +69,12 @@
// flight that we need to squash since we just instantiated a
// clean system.
noSquashFromTC = true;
- ::ThreadState::unserialize(cp);
+ gem5::ThreadState::unserialize(cp);
// Use the ThreadContext serialization helper to unserialize
// the TC.
- ::unserialize(*tc, cp);
+ gem5::unserialize(*tc, cp);
noSquashFromTC = false;
}
} // namespace o3
+} // namespace gem5
diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh
index a5ff450..bb15eed 100644
--- a/src/cpu/o3/thread_state.hh
+++ b/src/cpu/o3/thread_state.hh
@@ -46,6 +46,9 @@
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
+namespace gem5
+{
+
class Process;
namespace o3
@@ -60,7 +63,7 @@
* pointer, etc. It also handles anything related to a specific
* thread's process, such as syscalls and checking valid addresses.
*/
-class ThreadState : public ::ThreadState
+class ThreadState : public gem5::ThreadState
{
public:
PCEventQueue pcEventQueue;
@@ -94,12 +97,13 @@
void unserialize(CheckpointIn &cp) override;
/** Pointer to the ThreadContext of this thread. */
- ::ThreadContext *tc = nullptr;
+ gem5::ThreadContext *tc = nullptr;
/** Returns a pointer to the TC of this thread. */
- ::ThreadContext *getTC() { return tc; }
+ gem5::ThreadContext *getTC() { return tc; }
};
} // namespace o3
+} // namespace gem5
#endif // __CPU_O3_THREAD_STATE_HH__
diff --git a/src/cpu/op_class.hh b/src/cpu/op_class.hh
index 78c8da2..94730f3 100644
--- a/src/cpu/op_class.hh
+++ b/src/cpu/op_class.hh
@@ -43,6 +43,9 @@
#include "enums/OpClass.hh"
+namespace gem5
+{
+
/*
* Do a bunch of wonky stuff to maintain backward compatability so I
* don't have to change code in a zillion places.
@@ -104,4 +107,6 @@
static const OpClass InstPrefetchOp = enums::InstPrefetch;
static const OpClass Num_OpClasses = enums::Num_OpClass;
+} // namespace gem5
+
#endif // __CPU__OP_CLASS_HH__
diff --git a/src/cpu/pc_event.cc b/src/cpu/pc_event.cc
index dd52c71..2e66ecc 100644
--- a/src/cpu/pc_event.cc
+++ b/src/cpu/pc_event.cc
@@ -38,6 +38,9 @@
#include "sim/core.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
PCEventQueue::PCEventQueue()
{}
@@ -138,3 +141,5 @@
StringWrap name("panic_event");
panic(descr());
}
+
+} // namespace gem5
diff --git a/src/cpu/pc_event.hh b/src/cpu/pc_event.hh
index df63c04..98570ab 100644
--- a/src/cpu/pc_event.hh
+++ b/src/cpu/pc_event.hh
@@ -34,6 +34,9 @@
#include "base/logging.hh"
#include "base/types.hh"
+namespace gem5
+{
+
class ThreadContext;
class PCEventQueue;
class System;
@@ -160,4 +163,6 @@
virtual void process(ThreadContext *tc);
};
+} // namespace gem5
+
#endif // __PC_EVENT_HH__
diff --git a/src/cpu/pred/2bit_local.cc b/src/cpu/pred/2bit_local.cc
index 2e3aef9..61ce776 100644
--- a/src/cpu/pred/2bit_local.cc
+++ b/src/cpu/pred/2bit_local.cc
@@ -33,6 +33,9 @@
#include "base/trace.hh"
#include "debug/Fetch.hh"
+namespace gem5
+{
+
LocalBP::LocalBP(const LocalBPParams ¶ms)
: BPredUnit(params),
localPredictorSize(params.localPredictorSize),
@@ -133,3 +136,5 @@
LocalBP::uncondBranch(ThreadID tid, Addr pc, void *&bp_history)
{
}
+
+} // namespace gem5
diff --git a/src/cpu/pred/2bit_local.hh b/src/cpu/pred/2bit_local.hh
index 3dddd8c..8d2a09b 100644
--- a/src/cpu/pred/2bit_local.hh
+++ b/src/cpu/pred/2bit_local.hh
@@ -48,6 +48,9 @@
#include "cpu/pred/bpred_unit.hh"
#include "params/LocalBP.hh"
+namespace gem5
+{
+
/**
* Implements a local predictor that uses the PC to index into a table of
* counters. Note that any time a pointer to the bp_history is given, it
@@ -122,4 +125,6 @@
const unsigned indexMask;
};
+} // namespace gem5
+
#endif // __CPU_PRED_2BIT_LOCAL_PRED_HH__
diff --git a/src/cpu/pred/BranchPredictor.py b/src/cpu/pred/BranchPredictor.py
index 117d40d..aa8e5cf 100644
--- a/src/cpu/pred/BranchPredictor.py
+++ b/src/cpu/pred/BranchPredictor.py
@@ -31,7 +31,7 @@
class IndirectPredictor(SimObject):
type = 'IndirectPredictor'
- cxx_class = 'IndirectPredictor'
+ cxx_class = 'gem5::IndirectPredictor'
cxx_header = "cpu/pred/indirect.hh"
abstract = True
@@ -39,7 +39,7 @@
class SimpleIndirectPredictor(IndirectPredictor):
type = 'SimpleIndirectPredictor'
- cxx_class = 'SimpleIndirectPredictor'
+ cxx_class = 'gem5::SimpleIndirectPredictor'
cxx_header = "cpu/pred/simple_indirect.hh"
indirectHashGHR = Param.Bool(True, "Hash branch predictor GHR")
@@ -54,7 +54,7 @@
class BranchPredictor(SimObject):
type = 'BranchPredictor'
- cxx_class = 'BPredUnit'
+ cxx_class = 'gem5::BPredUnit'
cxx_header = "cpu/pred/bpred_unit.hh"
abstract = True
@@ -69,7 +69,7 @@
class LocalBP(BranchPredictor):
type = 'LocalBP'
- cxx_class = 'LocalBP'
+ cxx_class = 'gem5::LocalBP'
cxx_header = "cpu/pred/2bit_local.hh"
localPredictorSize = Param.Unsigned(2048, "Size of local predictor")
@@ -78,7 +78,7 @@
class TournamentBP(BranchPredictor):
type = 'TournamentBP'
- cxx_class = 'TournamentBP'
+ cxx_class = 'gem5::TournamentBP'
cxx_header = "cpu/pred/tournament.hh"
localPredictorSize = Param.Unsigned(2048, "Size of local predictor")
@@ -92,7 +92,7 @@
class BiModeBP(BranchPredictor):
type = 'BiModeBP'
- cxx_class = 'BiModeBP'
+ cxx_class = 'gem5::BiModeBP'
cxx_header = "cpu/pred/bi_mode.hh"
globalPredictorSize = Param.Unsigned(8192, "Size of global predictor")
@@ -102,7 +102,7 @@
class TAGEBase(SimObject):
type = 'TAGEBase'
- cxx_class = 'TAGEBase'
+ cxx_class = 'gem5::TAGEBase'
cxx_header = "cpu/pred/tage_base.hh"
numThreads = Param.Unsigned(Parent.numThreads, "Number of threads")
@@ -147,7 +147,7 @@
# The default sizes below are for the 8C-TAGE configuration (63.5 Kbits)
class TAGE(BranchPredictor):
type = 'TAGE'
- cxx_class = 'TAGE'
+ cxx_class = 'gem5::TAGE'
cxx_header = "cpu/pred/tage.hh"
tage = Param.TAGEBase(TAGEBase(), "Tage object")
@@ -161,7 +161,7 @@
class LoopPredictor(SimObject):
type = 'LoopPredictor'
- cxx_class = 'LoopPredictor'
+ cxx_class = 'gem5::LoopPredictor'
cxx_header = 'cpu/pred/loop_predictor.hh'
logSizeLoopPred = Param.Unsigned(8, "Log size of the loop predictor")
@@ -201,7 +201,7 @@
class TAGE_SC_L_TAGE(TAGEBase):
type = 'TAGE_SC_L_TAGE'
- cxx_class = 'TAGE_SC_L_TAGE'
+ cxx_class = 'gem5::TAGE_SC_L_TAGE'
cxx_header = "cpu/pred/tage_sc_l.hh"
abstract = True
tagTableTagWidths = [0]
@@ -238,7 +238,7 @@
class TAGE_SC_L_TAGE_64KB(TAGE_SC_L_TAGE):
type = 'TAGE_SC_L_TAGE_64KB'
- cxx_class = 'TAGE_SC_L_TAGE_64KB'
+ cxx_class = 'gem5::TAGE_SC_L_TAGE_64KB'
cxx_header = "cpu/pred/tage_sc_l_64KB.hh"
nHistoryTables = 36
@@ -268,7 +268,7 @@
class TAGE_SC_L_TAGE_8KB(TAGE_SC_L_TAGE):
type = 'TAGE_SC_L_TAGE_8KB'
- cxx_class = 'TAGE_SC_L_TAGE_8KB'
+ cxx_class = 'gem5::TAGE_SC_L_TAGE_8KB'
cxx_header = "cpu/pred/tage_sc_l_8KB.hh"
nHistoryTables = 30
@@ -297,7 +297,7 @@
# The differnt TAGE sizes are updated according to the paper values (256 Kbits)
class LTAGE(TAGE):
type = 'LTAGE'
- cxx_class = 'LTAGE'
+ cxx_class = 'gem5::LTAGE'
cxx_header = "cpu/pred/ltage.hh"
tage = LTAGE_TAGE()
@@ -306,7 +306,7 @@
class TAGE_SC_L_LoopPredictor(LoopPredictor):
type = 'TAGE_SC_L_LoopPredictor'
- cxx_class = 'TAGE_SC_L_LoopPredictor'
+ cxx_class = 'gem5::TAGE_SC_L_LoopPredictor'
cxx_header = "cpu/pred/tage_sc_l.hh"
loopTableAgeBits = 4
loopTableConfidenceBits = 4
@@ -322,7 +322,7 @@
class StatisticalCorrector(SimObject):
type = 'StatisticalCorrector'
- cxx_class = 'StatisticalCorrector'
+ cxx_class = 'gem5::StatisticalCorrector'
cxx_header = "cpu/pred/statistical_corrector.hh"
abstract = True
@@ -385,7 +385,7 @@
# of speculation: All the structures/histories are updated at commit time
class TAGE_SC_L(LTAGE):
type = 'TAGE_SC_L'
- cxx_class = 'TAGE_SC_L'
+ cxx_class = 'gem5::TAGE_SC_L'
cxx_header = "cpu/pred/tage_sc_l.hh"
abstract = True
@@ -400,7 +400,7 @@
class TAGE_SC_L_64KB_StatisticalCorrector(StatisticalCorrector):
type = 'TAGE_SC_L_64KB_StatisticalCorrector'
- cxx_class = 'TAGE_SC_L_64KB_StatisticalCorrector'
+ cxx_class = 'gem5::TAGE_SC_L_64KB_StatisticalCorrector'
cxx_header = "cpu/pred/tage_sc_l_64KB.hh"
pnb = Param.Unsigned(3, "Num variation global branch GEHL lengths")
@@ -446,8 +446,9 @@
class TAGE_SC_L_8KB_StatisticalCorrector(StatisticalCorrector):
type = 'TAGE_SC_L_8KB_StatisticalCorrector'
- cxx_class = 'TAGE_SC_L_8KB_StatisticalCorrector'
+ cxx_class = 'gem5::TAGE_SC_L_8KB_StatisticalCorrector'
cxx_header = "cpu/pred/tage_sc_l_8KB.hh"
+
gnb = Param.Unsigned(2, "Num global branch GEHL lengths")
gm = VectorParam.Int([6, 3], "Global branch GEHL lengths")
logGnb = Param.Unsigned(7, "Log number of global branch GEHL entries")
@@ -473,7 +474,7 @@
# http://www.jilp.org/cbp2016/paper/AndreSeznecLimited.pdf
class TAGE_SC_L_64KB(TAGE_SC_L):
type = 'TAGE_SC_L_64KB'
- cxx_class = 'TAGE_SC_L_64KB'
+ cxx_class = 'gem5::TAGE_SC_L_64KB'
cxx_header = "cpu/pred/tage_sc_l_64KB.hh"
tage = TAGE_SC_L_TAGE_64KB()
@@ -484,7 +485,7 @@
# http://www.jilp.org/cbp2016/paper/AndreSeznecLimited.pdf
class TAGE_SC_L_8KB(TAGE_SC_L):
type = 'TAGE_SC_L_8KB'
- cxx_class = 'TAGE_SC_L_8KB'
+ cxx_class = 'gem5::TAGE_SC_L_8KB'
cxx_header = "cpu/pred/tage_sc_l_8KB.hh"
tage = TAGE_SC_L_TAGE_8KB()
@@ -493,7 +494,7 @@
class MultiperspectivePerceptron(BranchPredictor):
type = 'MultiperspectivePerceptron'
- cxx_class = 'MultiperspectivePerceptron'
+ cxx_class = 'gem5::MultiperspectivePerceptron'
cxx_header = 'cpu/pred/multiperspective_perceptron.hh'
abstract = True
@@ -556,8 +557,9 @@
class MultiperspectivePerceptron8KB(MultiperspectivePerceptron):
type = 'MultiperspectivePerceptron8KB'
- cxx_class = 'MultiperspectivePerceptron8KB'
+ cxx_class = 'gem5::MultiperspectivePerceptron8KB'
cxx_header = 'cpu/pred/multiperspective_perceptron_8KB.hh'
+
budgetbits = 8192 * 8 + 2048
num_local_histories = 48
num_filter_entries = 0
@@ -567,8 +569,9 @@
class MultiperspectivePerceptron64KB(MultiperspectivePerceptron):
type = 'MultiperspectivePerceptron64KB'
- cxx_class = 'MultiperspectivePerceptron64KB'
+ cxx_class = 'gem5::MultiperspectivePerceptron64KB'
cxx_header = 'cpu/pred/multiperspective_perceptron_64KB.hh'
+
budgetbits = 65536 * 8 + 2048
num_local_histories = 510
num_filter_entries = 18025
@@ -578,8 +581,9 @@
class MPP_TAGE(TAGEBase):
type = 'MPP_TAGE'
- cxx_class = 'MPP_TAGE'
+ cxx_class = 'gem5::MPP_TAGE'
cxx_header = 'cpu/pred/multiperspective_perceptron_tage.hh'
+
nHistoryTables = 15
pathHistBits = 27
instShiftAmt = 0
@@ -599,8 +603,9 @@
class MPP_LoopPredictor(LoopPredictor):
type = 'MPP_LoopPredictor'
- cxx_class = 'MPP_LoopPredictor'
+ cxx_class = 'gem5::MPP_LoopPredictor'
cxx_header = 'cpu/pred/multiperspective_perceptron_tage.hh'
+
useDirectionBit = True
useHashing = True
useSpeculation = False
@@ -616,7 +621,7 @@
class MPP_StatisticalCorrector(StatisticalCorrector):
type = 'MPP_StatisticalCorrector'
- cxx_class = 'MPP_StatisticalCorrector'
+ cxx_class = 'gem5::MPP_StatisticalCorrector'
cxx_header = 'cpu/pred/multiperspective_perceptron_tage.hh'
abstract = True
@@ -652,9 +657,10 @@
class MultiperspectivePerceptronTAGE(MultiperspectivePerceptron):
type = 'MultiperspectivePerceptronTAGE'
- cxx_class = 'MultiperspectivePerceptronTAGE'
+ cxx_class = 'gem5::MultiperspectivePerceptronTAGE'
cxx_header = 'cpu/pred/multiperspective_perceptron_tage.hh'
abstract = True
+
instShiftAmt = 4
imli_mask1 = 0x70
@@ -673,7 +679,7 @@
class MPP_StatisticalCorrector_64KB(MPP_StatisticalCorrector):
type = 'MPP_StatisticalCorrector_64KB'
- cxx_class = 'MPP_StatisticalCorrector_64KB'
+ cxx_class = 'gem5::MPP_StatisticalCorrector_64KB'
cxx_header = 'cpu/pred/multiperspective_perceptron_tage_64KB.hh'
logBias = 8
@@ -697,7 +703,7 @@
class MultiperspectivePerceptronTAGE64KB(MultiperspectivePerceptronTAGE):
type = 'MultiperspectivePerceptronTAGE64KB'
- cxx_class = 'MultiperspectivePerceptronTAGE64KB'
+ cxx_class = 'gem5::MultiperspectivePerceptronTAGE64KB'
cxx_header = 'cpu/pred/multiperspective_perceptron_tage_64KB.hh'
budgetbits = 65536 * 8 + 2048
@@ -708,8 +714,9 @@
class MPP_TAGE_8KB(MPP_TAGE):
type = 'MPP_TAGE_8KB'
- cxx_class = 'MPP_TAGE_8KB'
+ cxx_class = 'gem5::MPP_TAGE_8KB'
cxx_header = 'cpu/pred/multiperspective_perceptron_tage_8KB.hh'
+
nHistoryTables = 10
tagTableTagWidths = [0, 7, 7, 7, 8, 9, 10, 10, 11, 13, 13]
logTagTableSizes = [12, 8, 8, 9, 9, 8, 8, 8, 7, 6, 7]
@@ -717,14 +724,15 @@
class MPP_LoopPredictor_8KB(MPP_LoopPredictor):
type = 'MPP_LoopPredictor_8KB'
- cxx_class = 'MPP_LoopPredictor_8KB'
+ cxx_class = 'gem5::MPP_LoopPredictor_8KB'
cxx_header = 'cpu/pred/multiperspective_perceptron_tage_8KB.hh'
+
loopTableIterBits = 10
logSizeLoopPred = 4
class MPP_StatisticalCorrector_8KB(MPP_StatisticalCorrector):
type = 'MPP_StatisticalCorrector_8KB'
- cxx_class = 'MPP_StatisticalCorrector_8KB'
+ cxx_class = 'gem5::MPP_StatisticalCorrector_8KB'
cxx_header = 'cpu/pred/multiperspective_perceptron_tage_8KB.hh'
logBias = 7
@@ -741,7 +749,7 @@
class MultiperspectivePerceptronTAGE8KB(MultiperspectivePerceptronTAGE):
type = 'MultiperspectivePerceptronTAGE8KB'
- cxx_class = 'MultiperspectivePerceptronTAGE8KB'
+ cxx_class = 'gem5::MultiperspectivePerceptronTAGE8KB'
cxx_header = 'cpu/pred/multiperspective_perceptron_tage_8KB.hh'
budgetbits = 8192 * 8 + 2048
diff --git a/src/cpu/pred/bi_mode.cc b/src/cpu/pred/bi_mode.cc
index 22e3e38..230d3a3 100644
--- a/src/cpu/pred/bi_mode.cc
+++ b/src/cpu/pred/bi_mode.cc
@@ -35,6 +35,9 @@
#include "base/bitfield.hh"
#include "base/intmath.hh"
+namespace gem5
+{
+
BiModeBP::BiModeBP(const BiModeBPParams ¶ms)
: BPredUnit(params),
globalHistoryReg(params.numThreads, 0),
@@ -225,3 +228,5 @@
(globalHistoryReg[tid] << 1);
globalHistoryReg[tid] &= historyRegisterMask;
}
+
+} // namespace gem5
diff --git a/src/cpu/pred/bi_mode.hh b/src/cpu/pred/bi_mode.hh
index 5774e83..1135770 100644
--- a/src/cpu/pred/bi_mode.hh
+++ b/src/cpu/pred/bi_mode.hh
@@ -37,6 +37,9 @@
#include "cpu/pred/bpred_unit.hh"
#include "params/BiModeBP.hh"
+namespace gem5
+{
+
/**
* Implements a bi-mode branch predictor. The bi-mode predictor is a two-level
* branch predictor that has three seprate history arrays: a taken array, a
@@ -109,4 +112,6 @@
unsigned notTakenThreshold;
};
+} // namespace gem5
+
#endif // __CPU_PRED_BI_MODE_PRED_HH__
diff --git a/src/cpu/pred/bpred_unit.cc b/src/cpu/pred/bpred_unit.cc
index d0f3812..a1ffeed 100644
--- a/src/cpu/pred/bpred_unit.cc
+++ b/src/cpu/pred/bpred_unit.cc
@@ -50,6 +50,9 @@
#include "config/the_isa.hh"
#include "debug/Branch.hh"
+namespace gem5
+{
+
BPredUnit::BPredUnit(const Params ¶ms)
: SimObject(params),
numThreads(params.numThreads),
@@ -518,3 +521,4 @@
}
}
+} // namespace gem5
diff --git a/src/cpu/pred/bpred_unit.hh b/src/cpu/pred/bpred_unit.hh
index fb9592f..11f9452 100644
--- a/src/cpu/pred/bpred_unit.hh
+++ b/src/cpu/pred/bpred_unit.hh
@@ -55,6 +55,9 @@
#include "sim/probe/pmu.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
/**
* Basically a wrapper class to hold both the branch predictor
* and the BTB.
@@ -341,4 +344,6 @@
/** @} */
};
+} // namespace gem5
+
#endif // __CPU_PRED_BPRED_UNIT_HH__
diff --git a/src/cpu/pred/btb.cc b/src/cpu/pred/btb.cc
index b6e9e83..755c69f 100644
--- a/src/cpu/pred/btb.cc
+++ b/src/cpu/pred/btb.cc
@@ -32,6 +32,9 @@
#include "base/trace.hh"
#include "debug/Fetch.hh"
+namespace gem5
+{
+
DefaultBTB::DefaultBTB(unsigned _numEntries,
unsigned _tagBits,
unsigned _instShiftAmt,
@@ -136,3 +139,5 @@
btb[btb_idx].target = target;
btb[btb_idx].tag = getTag(instPC);
}
+
+} // namespace gem5
diff --git a/src/cpu/pred/btb.hh b/src/cpu/pred/btb.hh
index 06adf87..8b99b6e 100644
--- a/src/cpu/pred/btb.hh
+++ b/src/cpu/pred/btb.hh
@@ -34,6 +34,9 @@
#include "base/types.hh"
#include "config/the_isa.hh"
+namespace gem5
+{
+
class DefaultBTB
{
private:
@@ -128,4 +131,6 @@
unsigned log2NumThreads;
};
+} // namespace gem5
+
#endif // __CPU_PRED_BTB_HH__
diff --git a/src/cpu/pred/indirect.hh b/src/cpu/pred/indirect.hh
index 9f64e3f..365d0e0 100644
--- a/src/cpu/pred/indirect.hh
+++ b/src/cpu/pred/indirect.hh
@@ -35,6 +35,9 @@
#include "params/IndirectPredictor.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class IndirectPredictor : public SimObject
{
public:
@@ -63,4 +66,6 @@
bool actually_taken) = 0;
};
+} // namespace gem5
+
#endif // __CPU_PRED_INDIRECT_BASE_HH__
diff --git a/src/cpu/pred/loop_predictor.cc b/src/cpu/pred/loop_predictor.cc
index 043d9d7..4333d9d8 100644
--- a/src/cpu/pred/loop_predictor.cc
+++ b/src/cpu/pred/loop_predictor.cc
@@ -38,6 +38,9 @@
#include "debug/LTage.hh"
#include "params/LoopPredictor.hh"
+namespace gem5
+{
+
LoopPredictor::LoopPredictor(const LoopPredictorParams &p)
: SimObject(p), logSizeLoopPred(p.logSizeLoopPred),
loopTableAgeBits(p.loopTableAgeBits),
@@ -365,3 +368,5 @@
loopTableConfidenceBits + loopTableTagBits +
loopTableAgeBits + useDirectionBit);
}
+
+} // namespace gem5
diff --git a/src/cpu/pred/loop_predictor.hh b/src/cpu/pred/loop_predictor.hh
index 4664ab3..e8967f9 100644
--- a/src/cpu/pred/loop_predictor.hh
+++ b/src/cpu/pred/loop_predictor.hh
@@ -38,6 +38,9 @@
#include "base/types.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
struct LoopPredictorParams;
class LoopPredictor : public SimObject
@@ -257,4 +260,7 @@
size_t getSizeInBits() const;
};
+
+} // namespace gem5
+
#endif//__CPU_PRED_LOOP_PREDICTOR_HH__
diff --git a/src/cpu/pred/ltage.cc b/src/cpu/pred/ltage.cc
index 8ea44fa..56375cf 100644
--- a/src/cpu/pred/ltage.cc
+++ b/src/cpu/pred/ltage.cc
@@ -44,6 +44,9 @@
#include "debug/Fetch.hh"
#include "debug/LTage.hh"
+namespace gem5
+{
+
LTAGE::LTAGE(const LTAGEParams ¶ms)
: TAGE(params), loopPredictor(params.loop_predictor)
{
@@ -141,3 +144,4 @@
TAGE::squash(tid, bp_history);
}
+} // namespace gem5
diff --git a/src/cpu/pred/ltage.hh b/src/cpu/pred/ltage.hh
index 95139b7..fbd6671 100644
--- a/src/cpu/pred/ltage.hh
+++ b/src/cpu/pred/ltage.hh
@@ -57,6 +57,9 @@
#include "cpu/pred/tage.hh"
#include "params/LTAGE.hh"
+namespace gem5
+{
+
class LTAGE : public TAGE
{
public:
@@ -109,4 +112,6 @@
ThreadID tid, Addr branch_pc, bool cond_branch, void* &b) override;
};
+} // namespace gem5
+
#endif // __CPU_PRED_LTAGE_HH__
diff --git a/src/cpu/pred/multiperspective_perceptron.cc b/src/cpu/pred/multiperspective_perceptron.cc
index 3e68e1a..fdb8077 100644
--- a/src/cpu/pred/multiperspective_perceptron.cc
+++ b/src/cpu/pred/multiperspective_perceptron.cc
@@ -41,6 +41,9 @@
#include "base/random.hh"
#include "debug/Branch.hh"
+namespace gem5
+{
+
int
MultiperspectivePerceptron::xlat[] =
{1,3,4,5,7,8,9,11,12,14,15,17,19,21,23,25,27,29,32,34,37,41,45,49,53,58,63,
@@ -822,3 +825,5 @@
MPPBranchInfo *bi = static_cast<MPPBranchInfo*>(bp_history);
delete bi;
}
+
+} // namespace gem5
diff --git a/src/cpu/pred/multiperspective_perceptron.hh b/src/cpu/pred/multiperspective_perceptron.hh
index d610d9d..6a67a7c 100644
--- a/src/cpu/pred/multiperspective_perceptron.hh
+++ b/src/cpu/pred/multiperspective_perceptron.hh
@@ -45,6 +45,9 @@
#include "cpu/pred/bpred_unit.hh"
#include "params/MultiperspectivePerceptron.hh"
+namespace gem5
+{
+
class MultiperspectivePerceptron : public BPredUnit
{
protected:
@@ -1051,4 +1054,7 @@
Addr corrTarget) override;
void btbUpdate(ThreadID tid, Addr branch_addr, void* &bp_history) override;
};
+
+} // namespace gem5
+
#endif//__CPU_PRED_MULTIPERSPECTIVE_PERCEPTRON_HH__
diff --git a/src/cpu/pred/multiperspective_perceptron_64KB.cc b/src/cpu/pred/multiperspective_perceptron_64KB.cc
index 035d8bd..e853c0e 100644
--- a/src/cpu/pred/multiperspective_perceptron_64KB.cc
+++ b/src/cpu/pred/multiperspective_perceptron_64KB.cc
@@ -39,6 +39,9 @@
#include "cpu/pred/multiperspective_perceptron_64KB.hh"
+namespace gem5
+{
+
MultiperspectivePerceptron64KB::MultiperspectivePerceptron64KB(
const MultiperspectivePerceptron64KBParams &p)
: MultiperspectivePerceptron(p)
@@ -85,3 +88,5 @@
addSpec(new SGHISTPATH(1, 2, 5, 1.25, 768, 6, *this));
addSpec(new SGHISTPATH(1, 5, 2, 1.3125, 972, 6, *this));
}
+
+} // namespace gem5
diff --git a/src/cpu/pred/multiperspective_perceptron_64KB.hh b/src/cpu/pred/multiperspective_perceptron_64KB.hh
index 4d24e86..10851fa 100644
--- a/src/cpu/pred/multiperspective_perceptron_64KB.hh
+++ b/src/cpu/pred/multiperspective_perceptron_64KB.hh
@@ -43,6 +43,9 @@
#include "cpu/pred/multiperspective_perceptron.hh"
#include "params/MultiperspectivePerceptron64KB.hh"
+namespace gem5
+{
+
class MultiperspectivePerceptron64KB : public MultiperspectivePerceptron
{
void createSpecs() override;
@@ -51,4 +54,6 @@
const MultiperspectivePerceptron64KBParams &p);
};
+} // namespace gem5
+
#endif // __CPU_PRED_MULTIPERSPECTIVE_PERCEPTRON_64KB_HH__
diff --git a/src/cpu/pred/multiperspective_perceptron_8KB.cc b/src/cpu/pred/multiperspective_perceptron_8KB.cc
index a4abe52..b341ada 100644
--- a/src/cpu/pred/multiperspective_perceptron_8KB.cc
+++ b/src/cpu/pred/multiperspective_perceptron_8KB.cc
@@ -39,6 +39,9 @@
#include "cpu/pred/multiperspective_perceptron_8KB.hh"
+namespace gem5
+{
+
MultiperspectivePerceptron8KB::MultiperspectivePerceptron8KB(
const MultiperspectivePerceptron8KBParams &p)
: MultiperspectivePerceptron(p)
@@ -64,3 +67,5 @@
addSpec(new SGHISTPATH(0, 4, 3, 1.65625, 0, 6, *this));
addSpec(new SGHISTPATH(1, 2, 5, 2.53125, 0, 5, *this));
}
+
+} // namespace gem5
diff --git a/src/cpu/pred/multiperspective_perceptron_8KB.hh b/src/cpu/pred/multiperspective_perceptron_8KB.hh
index d02baf9..58d1d02 100644
--- a/src/cpu/pred/multiperspective_perceptron_8KB.hh
+++ b/src/cpu/pred/multiperspective_perceptron_8KB.hh
@@ -43,6 +43,9 @@
#include "cpu/pred/multiperspective_perceptron.hh"
#include "params/MultiperspectivePerceptron8KB.hh"
+namespace gem5
+{
+
class MultiperspectivePerceptron8KB : public MultiperspectivePerceptron
{
void createSpecs() override;
@@ -51,4 +54,6 @@
const MultiperspectivePerceptron8KBParams &p);
};
+} // namespace gem5
+
#endif // __CPU_PRED_MULTIPERSPECTIVE_PERCEPTRON_8KB_HH__
diff --git a/src/cpu/pred/multiperspective_perceptron_tage.cc b/src/cpu/pred/multiperspective_perceptron_tage.cc
index 108295f..f0da006 100644
--- a/src/cpu/pred/multiperspective_perceptron_tage.cc
+++ b/src/cpu/pred/multiperspective_perceptron_tage.cc
@@ -40,6 +40,9 @@
#include "base/random.hh"
+namespace gem5
+{
+
void
MPP_TAGE::calculateParameters()
{
@@ -680,3 +683,5 @@
MPPTAGEBranchInfo *bi = static_cast<MPPTAGEBranchInfo*>(bp_history);
delete bi;
}
+
+} // namespace gem5
diff --git a/src/cpu/pred/multiperspective_perceptron_tage.hh b/src/cpu/pred/multiperspective_perceptron_tage.hh
index 8aafe72..b79c06b 100644
--- a/src/cpu/pred/multiperspective_perceptron_tage.hh
+++ b/src/cpu/pred/multiperspective_perceptron_tage.hh
@@ -48,6 +48,9 @@
#include "params/MPP_TAGE.hh"
#include "params/MultiperspectivePerceptronTAGE.hh"
+namespace gem5
+{
+
class MPP_TAGE : public TAGEBase
{
std::vector<unsigned int> tunedHistoryLengths;
@@ -238,4 +241,7 @@
void squash(ThreadID tid, void *bp_history) override;
};
+
+} // namespace gem5
+
#endif//__CPU_PRED_MULTIPERSPECTIVE_PERCEPTRON_TAGE_HH__
diff --git a/src/cpu/pred/multiperspective_perceptron_tage_64KB.cc b/src/cpu/pred/multiperspective_perceptron_tage_64KB.cc
index 68ecd9e..af1d5c5 100644
--- a/src/cpu/pred/multiperspective_perceptron_tage_64KB.cc
+++ b/src/cpu/pred/multiperspective_perceptron_tage_64KB.cc
@@ -39,6 +39,9 @@
#include "cpu/pred/multiperspective_perceptron_tage_64KB.hh"
+namespace gem5
+{
+
MPP_StatisticalCorrector_64KB::MPP_StatisticalCorrector_64KB(
const MPP_StatisticalCorrector_64KBParams &p)
: MPP_StatisticalCorrector(p),
@@ -215,3 +218,5 @@
addSpec(new RECENCY(9, 3, -1, 2.51, 0, 6, *this));
addSpec(new ACYCLIC(12, -1, -1, 2.0, 0, 6, *this));
}
+
+} // namespace gem5
diff --git a/src/cpu/pred/multiperspective_perceptron_tage_64KB.hh b/src/cpu/pred/multiperspective_perceptron_tage_64KB.hh
index 4336bac..41b7ae7 100644
--- a/src/cpu/pred/multiperspective_perceptron_tage_64KB.hh
+++ b/src/cpu/pred/multiperspective_perceptron_tage_64KB.hh
@@ -43,6 +43,9 @@
#include "params/MPP_StatisticalCorrector_64KB.hh"
#include "params/MultiperspectivePerceptronTAGE64KB.hh"
+namespace gem5
+{
+
class MPP_StatisticalCorrector_64KB : public MPP_StatisticalCorrector
{
const unsigned numEntriesSecondLocalHistories;
@@ -86,4 +89,6 @@
const MultiperspectivePerceptronTAGE64KBParams &p);
};
+} // namespace gem5
+
#endif // __CPU_PRED_MULTIPERSPECTIVE_PERCEPTRON_TAGE_64KB_HH__
diff --git a/src/cpu/pred/multiperspective_perceptron_tage_8KB.cc b/src/cpu/pred/multiperspective_perceptron_tage_8KB.cc
index f02a8bf..8d8ce3b 100644
--- a/src/cpu/pred/multiperspective_perceptron_tage_8KB.cc
+++ b/src/cpu/pred/multiperspective_perceptron_tage_8KB.cc
@@ -39,6 +39,9 @@
#include "cpu/pred/multiperspective_perceptron_tage_8KB.hh"
+namespace gem5
+{
+
MPP_StatisticalCorrector_8KB::MPP_StatisticalCorrector_8KB(
const MPP_StatisticalCorrector_8KBParams &p)
: MPP_StatisticalCorrector(p)
@@ -170,3 +173,5 @@
addSpec(new IMLI(1, 2.23, 0, 6, *this));
addSpec(new IMLI(4, 1.98, 0, 6, *this));
}
+
+} // namespace gem5
diff --git a/src/cpu/pred/multiperspective_perceptron_tage_8KB.hh b/src/cpu/pred/multiperspective_perceptron_tage_8KB.hh
index ad1037c..3adbcd4 100644
--- a/src/cpu/pred/multiperspective_perceptron_tage_8KB.hh
+++ b/src/cpu/pred/multiperspective_perceptron_tage_8KB.hh
@@ -46,6 +46,9 @@
#include "params/MPP_TAGE_8KB.hh"
#include "params/MultiperspectivePerceptronTAGE8KB.hh"
+namespace gem5
+{
+
class MPP_TAGE_8KB : public MPP_TAGE
{
public:
@@ -85,4 +88,6 @@
const MultiperspectivePerceptronTAGE8KBParams &p);
};
+} // namespace gem5
+
#endif // __CPU_PRED_MULTIPERSPECTIVE_PERCEPTRON_TAGE_8KB_HH__
diff --git a/src/cpu/pred/ras.cc b/src/cpu/pred/ras.cc
index 33eec0e..49969b7 100644
--- a/src/cpu/pred/ras.cc
+++ b/src/cpu/pred/ras.cc
@@ -28,6 +28,9 @@
#include "cpu/pred/ras.hh"
+namespace gem5
+{
+
void
ReturnAddrStack::init(unsigned _numEntries)
{
@@ -79,3 +82,5 @@
++usedEntries;
}
}
+
+} // namespace gem5
diff --git a/src/cpu/pred/ras.hh b/src/cpu/pred/ras.hh
index c05a835..a41ab88 100644
--- a/src/cpu/pred/ras.hh
+++ b/src/cpu/pred/ras.hh
@@ -35,6 +35,9 @@
#include "base/types.hh"
#include "config/the_isa.hh"
+namespace gem5
+{
+
/** Return address stack class, implements a simple RAS. */
class ReturnAddrStack
{
@@ -97,4 +100,6 @@
unsigned tos;
};
+} // namespace gem5
+
#endif // __CPU_PRED_RAS_HH__
diff --git a/src/cpu/pred/simple_indirect.cc b/src/cpu/pred/simple_indirect.cc
index 6000f90..7e9998f 100644
--- a/src/cpu/pred/simple_indirect.cc
+++ b/src/cpu/pred/simple_indirect.cc
@@ -31,6 +31,9 @@
#include "base/intmath.hh"
#include "debug/Indirect.hh"
+namespace gem5
+{
+
SimpleIndirectPredictor::SimpleIndirectPredictor(
const SimpleIndirectPredictorParams ¶ms)
: IndirectPredictor(params),
@@ -233,3 +236,5 @@
{
return (br_addr >> instShift) & ((0x1<<tagBits)-1);
}
+
+} // namespace gem5
diff --git a/src/cpu/pred/simple_indirect.hh b/src/cpu/pred/simple_indirect.hh
index 0c42fd9..a66b484 100644
--- a/src/cpu/pred/simple_indirect.hh
+++ b/src/cpu/pred/simple_indirect.hh
@@ -36,6 +36,9 @@
#include "cpu/pred/indirect.hh"
#include "params/SimpleIndirectPredictor.hh"
+namespace gem5
+{
+
class SimpleIndirectPredictor : public IndirectPredictor
{
public:
@@ -99,4 +102,6 @@
std::vector<ThreadInfo> threadInfo;
};
+} // namespace gem5
+
#endif // __CPU_PRED_INDIRECT_HH__
diff --git a/src/cpu/pred/statistical_corrector.cc b/src/cpu/pred/statistical_corrector.cc
index 8bd05af..c50686d 100644
--- a/src/cpu/pred/statistical_corrector.cc
+++ b/src/cpu/pred/statistical_corrector.cc
@@ -39,11 +39,14 @@
* Statistical corrector base class
*/
- #include "cpu/pred/statistical_corrector.hh"
+#include "cpu/pred/statistical_corrector.hh"
- #include "params/StatisticalCorrector.hh"
+#include "params/StatisticalCorrector.hh"
- StatisticalCorrector::StatisticalCorrector(
+namespace gem5
+{
+
+StatisticalCorrector::StatisticalCorrector(
const StatisticalCorrectorParams &p)
: SimObject(p),
logBias(p.logBias),
@@ -408,3 +411,5 @@
"prediction is wrong")
{
}
+
+} // namespace gem5
diff --git a/src/cpu/pred/statistical_corrector.hh b/src/cpu/pred/statistical_corrector.hh
index 91cc909..508fa67 100644
--- a/src/cpu/pred/statistical_corrector.hh
+++ b/src/cpu/pred/statistical_corrector.hh
@@ -47,6 +47,9 @@
#include "cpu/static_inst.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
struct StatisticalCorrectorParams;
class StatisticalCorrector : public SimObject
@@ -273,4 +276,7 @@
virtual size_t getSizeInBits() const;
};
+
+} // namespace gem5
+
#endif//__CPU_PRED_STATISTICAL_CORRECTOR_HH__
diff --git a/src/cpu/pred/tage.cc b/src/cpu/pred/tage.cc
index 353da75..0569050 100644
--- a/src/cpu/pred/tage.cc
+++ b/src/cpu/pred/tage.cc
@@ -44,6 +44,9 @@
#include "debug/Fetch.hh"
#include "debug/Tage.hh"
+namespace gem5
+{
+
TAGE::TAGE(const TAGEParams ¶ms) : BPredUnit(params), tage(params.tage)
{
}
@@ -125,3 +128,5 @@
TageBranchInfo *bi = static_cast<TageBranchInfo*>(bp_history);
tage->updateHistories(tid, br_pc, true, bi->tageBranchInfo, true);
}
+
+} // namespace gem5
diff --git a/src/cpu/pred/tage.hh b/src/cpu/pred/tage.hh
index ec4fce9..301c585 100644
--- a/src/cpu/pred/tage.hh
+++ b/src/cpu/pred/tage.hh
@@ -55,6 +55,9 @@
#include "cpu/pred/tage_base.hh"
#include "params/TAGE.hh"
+namespace gem5
+{
+
class TAGE: public BPredUnit
{
protected:
@@ -90,4 +93,6 @@
virtual void squash(ThreadID tid, void *bp_history) override;
};
+} // namespace gem5
+
#endif // __CPU_PRED_TAGE_HH__
diff --git a/src/cpu/pred/tage_base.cc b/src/cpu/pred/tage_base.cc
index c6e46c9..72e454c 100644
--- a/src/cpu/pred/tage_base.cc
+++ b/src/cpu/pred/tage_base.cc
@@ -42,6 +42,9 @@
#include "debug/Fetch.hh"
#include "debug/Tage.hh"
+namespace gem5
+{
+
TAGEBase::TAGEBase(const TAGEBaseParams &p)
: SimObject(p),
logRatioBiModalHystEntries(p.logRatioBiModalHystEntries),
@@ -798,3 +801,5 @@
bits += logUResetPeriod;
return bits;
}
+
+} // namespace gem5
diff --git a/src/cpu/pred/tage_base.hh b/src/cpu/pred/tage_base.hh
index d6ecf78..7063e6b 100644
--- a/src/cpu/pred/tage_base.hh
+++ b/src/cpu/pred/tage_base.hh
@@ -56,6 +56,9 @@
#include "params/TAGEBase.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class TAGEBase : public SimObject
{
public:
@@ -505,4 +508,6 @@
} stats;
};
+} // namespace gem5
+
#endif // __CPU_PRED_TAGE_BASE_HH__
diff --git a/src/cpu/pred/tage_sc_l.cc b/src/cpu/pred/tage_sc_l.cc
index b46f13b..c1d05fc 100644
--- a/src/cpu/pred/tage_sc_l.cc
+++ b/src/cpu/pred/tage_sc_l.cc
@@ -45,6 +45,9 @@
#include "base/random.hh"
#include "debug/TageSCL.hh"
+namespace gem5
+{
+
bool
TAGE_SC_L_LoopPredictor::calcConf(int index) const
{
@@ -458,3 +461,5 @@
delete bi;
}
+
+} // namespace gem5
diff --git a/src/cpu/pred/tage_sc_l.hh b/src/cpu/pred/tage_sc_l.hh
index 6691928..c9fe0e9 100644
--- a/src/cpu/pred/tage_sc_l.hh
+++ b/src/cpu/pred/tage_sc_l.hh
@@ -49,6 +49,9 @@
#include "params/TAGE_SC_L_LoopPredictor.hh"
#include "params/TAGE_SC_L_TAGE.hh"
+namespace gem5
+{
+
class TAGE_SC_L_TAGE : public TAGEBase
{
const unsigned firstLongTagTable;
@@ -185,4 +188,6 @@
};
+} // namespace gem5
+
#endif // __CPU_PRED_TAGE_SC_L_HH__
diff --git a/src/cpu/pred/tage_sc_l_64KB.cc b/src/cpu/pred/tage_sc_l_64KB.cc
index 6d3039b..aecc935 100644
--- a/src/cpu/pred/tage_sc_l_64KB.cc
+++ b/src/cpu/pred/tage_sc_l_64KB.cc
@@ -41,6 +41,9 @@
#include "cpu/pred/tage_sc_l_64KB.hh"
+namespace gem5
+{
+
TAGE_SC_L_64KB_StatisticalCorrector::TAGE_SC_L_64KB_StatisticalCorrector(
const TAGE_SC_L_64KB_StatisticalCorrectorParams &p)
: StatisticalCorrector(p),
@@ -307,3 +310,5 @@
: TAGE_SC_L(params)
{
}
+
+} // namespace gem5
diff --git a/src/cpu/pred/tage_sc_l_64KB.hh b/src/cpu/pred/tage_sc_l_64KB.hh
index 00bc896..7dff998 100644
--- a/src/cpu/pred/tage_sc_l_64KB.hh
+++ b/src/cpu/pred/tage_sc_l_64KB.hh
@@ -50,6 +50,9 @@
#include "params/TAGE_SC_L_64KB_StatisticalCorrector.hh"
#include "params/TAGE_SC_L_TAGE_64KB.hh"
+namespace gem5
+{
+
class TAGE_SC_L_TAGE_64KB : public TAGE_SC_L_TAGE
{
public:
@@ -132,4 +135,6 @@
TAGE_SC_L_64KB(const TAGE_SC_L_64KBParams ¶ms);
};
+} // namespace gem5
+
#endif // __CPU_PRED_TAGE_SC_L_64KB_HH__
diff --git a/src/cpu/pred/tage_sc_l_8KB.cc b/src/cpu/pred/tage_sc_l_8KB.cc
index 982f1cf..9218820 100644
--- a/src/cpu/pred/tage_sc_l_8KB.cc
+++ b/src/cpu/pred/tage_sc_l_8KB.cc
@@ -44,6 +44,9 @@
#include "base/random.hh"
#include "debug/TageSCL.hh"
+namespace gem5
+{
+
TAGE_SC_L_8KB_StatisticalCorrector::TAGE_SC_L_8KB_StatisticalCorrector(
const TAGE_SC_L_8KB_StatisticalCorrectorParams &p)
: StatisticalCorrector(p),
@@ -310,3 +313,5 @@
gtable[bi->hitBank][bi->hitBankIndex].u++;
}
}
+
+} // namespace gem5
diff --git a/src/cpu/pred/tage_sc_l_8KB.hh b/src/cpu/pred/tage_sc_l_8KB.hh
index fe249de..54157e0 100644
--- a/src/cpu/pred/tage_sc_l_8KB.hh
+++ b/src/cpu/pred/tage_sc_l_8KB.hh
@@ -47,6 +47,9 @@
#include "params/TAGE_SC_L_8KB_StatisticalCorrector.hh"
#include "params/TAGE_SC_L_TAGE_8KB.hh"
+namespace gem5
+{
+
class TAGE_SC_L_TAGE_8KB : public TAGE_SC_L_TAGE
{
public:
@@ -112,4 +115,6 @@
TAGE_SC_L_8KB(const TAGE_SC_L_8KBParams ¶ms);
};
+} // namespace gem5
+
#endif // __CPU_PRED_TAGE_SC_L_8KB_HH__
diff --git a/src/cpu/pred/tournament.cc b/src/cpu/pred/tournament.cc
index aebce098..53d8172 100644
--- a/src/cpu/pred/tournament.cc
+++ b/src/cpu/pred/tournament.cc
@@ -43,6 +43,9 @@
#include "base/bitfield.hh"
#include "base/intmath.hh"
+namespace gem5
+{
+
TournamentBP::TournamentBP(const TournamentBPParams ¶ms)
: BPredUnit(params),
localPredictorSize(params.localPredictorSize),
@@ -347,3 +350,5 @@
int
TournamentBP::BPHistory::newCount = 0;
#endif
+
+} // namespace gem5
diff --git a/src/cpu/pred/tournament.hh b/src/cpu/pred/tournament.hh
index 2426246..2adeba3 100644
--- a/src/cpu/pred/tournament.hh
+++ b/src/cpu/pred/tournament.hh
@@ -48,6 +48,9 @@
#include "cpu/pred/bpred_unit.hh"
#include "params/TournamentBP.hh"
+namespace gem5
+{
+
/**
* Implements a tournament branch predictor, hopefully identical to the one
* used in the 21264. It has a local predictor, which uses a local history
@@ -239,4 +242,6 @@
unsigned choiceThreshold;
};
+} // namespace gem5
+
#endif // __CPU_PRED_TOURNAMENT_PRED_HH__
diff --git a/src/cpu/profile.cc b/src/cpu/profile.cc
index 222e946..25d739c 100644
--- a/src/cpu/profile.cc
+++ b/src/cpu/profile.cc
@@ -37,6 +37,9 @@
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+namespace gem5
+{
+
void
BaseStackTrace::dump()
{
@@ -155,3 +158,5 @@
pc_count[pc]++;
}
}
+
+} // namespace gem5
diff --git a/src/cpu/profile.hh b/src/cpu/profile.hh
index 922ac80..efdfbfb 100644
--- a/src/cpu/profile.hh
+++ b/src/cpu/profile.hh
@@ -37,6 +37,9 @@
#include "cpu/static_inst.hh"
#include "debug/Stack.hh"
+namespace gem5
+{
+
class ThreadContext;
class FunctionProfile;
@@ -155,4 +158,6 @@
return consume(trace->getstack());
}
+} // namespace gem5
+
#endif // __CPU_PROFILE_HH__
diff --git a/src/cpu/reg_class.cc b/src/cpu/reg_class.cc
index 07b6993..c806560 100644
--- a/src/cpu/reg_class.cc
+++ b/src/cpu/reg_class.cc
@@ -40,6 +40,9 @@
#include "cpu/reg_class.hh"
+namespace gem5
+{
+
const char *RegId::regClassStrings[] = {
"IntRegClass",
"FloatRegClass",
@@ -50,3 +53,4 @@
"MiscRegClass"
};
+} // namespace gem5
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index 36c4206..eaa2c0e 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -48,6 +48,9 @@
#include "base/types.hh"
#include "config/the_isa.hh"
+namespace gem5
+{
+
/** Enumerate the classes of registers. */
enum RegClass
{
@@ -304,19 +307,22 @@
using PhysRegIdPtr = PhysRegId*;
+} // namespace gem5
+
namespace std
{
template<>
-struct hash<RegId>
+struct hash<gem5::RegId>
{
size_t
- operator()(const RegId& reg_id) const
+ operator()(const gem5::RegId& reg_id) const
{
// Extract unique integral values for the effective fields of a RegId.
const size_t flat_index = static_cast<size_t>(reg_id.flatIndex());
const size_t class_num = static_cast<size_t>(reg_id.regClass);
- const size_t shifted_class_num = class_num << (sizeof(RegIndex) << 3);
+ const size_t shifted_class_num =
+ class_num << (sizeof(gem5::RegIndex) << 3);
// Concatenate the class_num to the end of the flat_index, in order to
// maximize information retained.
@@ -325,12 +331,12 @@
// If RegIndex is larger than size_t, then class_num will not be
// considered by this hash function, so we may wish to perform a
// different operation to include that information in the hash.
- static_assert(sizeof(RegIndex) < sizeof(size_t),
+ static_assert(sizeof(gem5::RegIndex) < sizeof(size_t),
"sizeof(RegIndex) should be less than sizeof(size_t)");
return concatenated_hash;
}
};
-}
+} // namespace std
#endif // __CPU__REG_CLASS_HH__
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index 9491cd1..8dc0a5b 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -47,6 +47,7 @@
type = 'AtomicSimpleCPU'
cxx_header = "cpu/simple/atomic.hh"
+ cxx_class = 'gem5::AtomicSimpleCPU'
@classmethod
def memory_mode(cls):
diff --git a/src/cpu/simple/BaseSimpleCPU.py b/src/cpu/simple/BaseSimpleCPU.py
index 3da462c..64444e4 100644
--- a/src/cpu/simple/BaseSimpleCPU.py
+++ b/src/cpu/simple/BaseSimpleCPU.py
@@ -35,6 +35,7 @@
type = 'BaseSimpleCPU'
abstract = True
cxx_header = "cpu/simple/base.hh"
+ cxx_class = 'gem5::BaseSimpleCPU'
def addCheckerCpu(self):
if buildEnv['TARGET_ISA'] in ['arm']:
diff --git a/src/cpu/simple/NonCachingSimpleCPU.py b/src/cpu/simple/NonCachingSimpleCPU.py
index 98cb728..e01905a 100644
--- a/src/cpu/simple/NonCachingSimpleCPU.py
+++ b/src/cpu/simple/NonCachingSimpleCPU.py
@@ -47,6 +47,7 @@
type = 'NonCachingSimpleCPU'
cxx_header = "cpu/simple/noncaching.hh"
+ cxx_class = 'gem5::NonCachingSimpleCPU'
numThreads = 1
diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
index 3d7458d..f670cc4 100644
--- a/src/cpu/simple/TimingSimpleCPU.py
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -31,6 +31,7 @@
class TimingSimpleCPU(BaseSimpleCPU):
type = 'TimingSimpleCPU'
cxx_header = "cpu/simple/timing.hh"
+ cxx_class = 'gem5::TimingSimpleCPU'
@classmethod
def memory_mode(cls):
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index c507f70..a9a5af3 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -57,6 +57,9 @@
#include "sim/full_system.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
void
AtomicSimpleCPU::init()
{
@@ -766,3 +769,5 @@
{
dcachePort.printAddr(a);
}
+
+} // namespace gem5
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index febba9e..74d4868 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -47,6 +47,9 @@
#include "params/AtomicSimpleCPU.hh"
#include "sim/probe/probe.hh"
+namespace gem5
+{
+
class AtomicSimpleCPU : public BaseSimpleCPU
{
public:
@@ -251,4 +254,6 @@
void printAddr(Addr a);
};
+} // namespace gem5
+
#endif // __CPU_SIMPLE_ATOMIC_HH__
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 820cde8..0a4595c 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -77,6 +77,9 @@
#include "sim/stats.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
BaseSimpleCPU::BaseSimpleCPU(const BaseSimpleCPUParams &p)
: BaseCPU(p),
curThread(0),
@@ -499,3 +502,5 @@
}
}
}
+
+} // namespace gem5
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index c63db8b..8117138 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -56,6 +56,9 @@
#include "sim/full_system.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
// forward declarations
class Checkpoint;
class Process;
@@ -196,4 +199,6 @@
virtual void htmSendAbortSignal(HtmFailureFaultCause cause) = 0;
};
+} // namespace gem5
+
#endif // __CPU_SIMPLE_BASE_HH__
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 578cc55..23e6e47 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -52,6 +52,9 @@
#include "cpu/translation.hh"
#include "mem/request.hh"
+namespace gem5
+{
+
class BaseSimpleCPU;
class SimpleExecContext : public ExecContext
@@ -626,4 +629,6 @@
}
};
+} // namespace gem5
+
#endif // __CPU_EXEC_CONTEXT_HH__
diff --git a/src/cpu/simple/noncaching.cc b/src/cpu/simple/noncaching.cc
index ce8bf99..0423b2e 100644
--- a/src/cpu/simple/noncaching.cc
+++ b/src/cpu/simple/noncaching.cc
@@ -39,6 +39,9 @@
#include <cassert>
+namespace gem5
+{
+
NonCachingSimpleCPU::NonCachingSimpleCPU(const NonCachingSimpleCPUParams &p)
: AtomicSimpleCPU(p)
{
@@ -95,3 +98,5 @@
memcpy(decoder.moreBytesPtr(), bd->ptr() + offset, ifetch_req->getSize());
return 0;
}
+
+} // namespace gem5
diff --git a/src/cpu/simple/noncaching.hh b/src/cpu/simple/noncaching.hh
index 4cb9638..289f482 100644
--- a/src/cpu/simple/noncaching.hh
+++ b/src/cpu/simple/noncaching.hh
@@ -43,6 +43,9 @@
#include "mem/backdoor.hh"
#include "params/NonCachingSimpleCPU.hh"
+namespace gem5
+{
+
/**
* The NonCachingSimpleCPU is an AtomicSimpleCPU using the
* 'atomic_noncaching' memory mode instead of just 'atomic'.
@@ -61,4 +64,6 @@
Tick fetchInstMem() override;
};
+} // namespace gem5
+
#endif // __CPU_SIMPLE_NONCACHING_HH__
diff --git a/src/cpu/simple/probes/SimPoint.py b/src/cpu/simple/probes/SimPoint.py
index ec2c2f8..9dd3077 100644
--- a/src/cpu/simple/probes/SimPoint.py
+++ b/src/cpu/simple/probes/SimPoint.py
@@ -41,6 +41,7 @@
type = 'SimPoint'
cxx_header = "cpu/simple/probes/simpoint.hh"
+ cxx_class = 'gem5::SimPoint'
interval = Param.UInt64(100000000, "Interval Size (insts)")
profile_file = Param.String("simpoint.bb.gz", "BBV (output) file")
diff --git a/src/cpu/simple/probes/simpoint.cc b/src/cpu/simple/probes/simpoint.cc
index d835b2b..d5fc4f3 100644
--- a/src/cpu/simple/probes/simpoint.cc
+++ b/src/cpu/simple/probes/simpoint.cc
@@ -39,6 +39,9 @@
#include "base/output.hh"
+namespace gem5
+{
+
SimPoint::SimPoint(const SimPointParams &p)
: ProbeListenerObject(p),
intervalSize(p.interval),
@@ -138,3 +141,5 @@
}
}
}
+
+} // namespace gem5
diff --git a/src/cpu/simple/probes/simpoint.hh b/src/cpu/simple/probes/simpoint.hh
index 379353a..4df51f5 100644
--- a/src/cpu/simple/probes/simpoint.hh
+++ b/src/cpu/simple/probes/simpoint.hh
@@ -45,6 +45,9 @@
#include "params/SimPoint.hh"
#include "sim/probe/probe.hh"
+namespace gem5
+{
+
/**
* Probe for SimPoints BBV generation
*/
@@ -57,17 +60,24 @@
*/
typedef std::pair<Addr, Addr> BasicBlockRange;
+} // namespace gem5
+
/** Overload hash function for BasicBlockRange type */
-namespace std {
+namespace std
+{
template <>
-struct hash<BasicBlockRange>
+struct hash<gem5::BasicBlockRange>
{
public:
- size_t operator()(const BasicBlockRange &bb) const {
- return hash<Addr>()(bb.first + bb.second);
+ size_t operator()(const gem5::BasicBlockRange &bb) const
+ {
+ return hash<gem5::Addr>()(bb.first + bb.second);
}
};
-}
+} // namespace std
+
+namespace gem5
+{
class SimPoint : public ProbeListenerObject
{
@@ -116,4 +126,6 @@
uint64_t currentBBVInstCount;
};
+} // namespace gem5
+
#endif // __CPU_SIMPLE_PROBES_SIMPOINT_HH__
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 2814aed..a1165d6 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -58,6 +58,9 @@
#include "sim/full_system.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
void
TimingSimpleCPU::init()
{
@@ -1287,3 +1290,5 @@
sendData(req, data, nullptr, true);
}
+
+} // namespace gem5
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 352b41f..830f7a3 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -46,6 +46,9 @@
#include "cpu/translation.hh"
#include "params/TimingSimpleCPU.hh"
+namespace gem5
+{
+
class TimingSimpleCPU : public BaseSimpleCPU
{
public:
@@ -370,4 +373,6 @@
bool tryCompleteDrain();
};
+} // namespace gem5
+
#endif // __CPU_SIMPLE_TIMING_HH__
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index b3e6e48..67756b4 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -61,6 +61,9 @@
#include "sim/sim_exit.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
// constructor
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
Process *_process, BaseMMU *_mmu,
@@ -90,7 +93,7 @@
void
SimpleThread::takeOverFrom(ThreadContext *oldContext)
{
- ::takeOverFrom(*this, *oldContext);
+ gem5::takeOverFrom(*this, *oldContext);
decoder.takeOverFrom(oldContext->getDecoderPtr());
isa->takeOverFrom(this, oldContext);
@@ -113,7 +116,7 @@
SimpleThread::serialize(CheckpointOut &cp) const
{
ThreadState::serialize(cp);
- ::serialize(*this, cp);
+ gem5::serialize(*this, cp);
}
@@ -121,7 +124,7 @@
SimpleThread::unserialize(CheckpointIn &cp)
{
ThreadState::unserialize(cp);
- ::unserialize(*this, cp);
+ gem5::unserialize(*this, cp);
}
void
@@ -189,3 +192,5 @@
{
_htmCheckpoint = std::move(new_cpt);
}
+
+} // namespace gem5
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index f64f2c1..d95b2ba 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -71,6 +71,9 @@
#include "sim/serialize.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
class BaseCPU;
class CheckerCPU;
@@ -568,5 +571,6 @@
void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override;
};
+} // namespace gem5
#endif // __CPU_SIMPLE_THREAD_HH__
diff --git a/src/cpu/smt.hh b/src/cpu/smt.hh
index 50c2ce6..2e5391b 100644
--- a/src/cpu/smt.hh
+++ b/src/cpu/smt.hh
@@ -41,6 +41,9 @@
#define SMT_MAX_THREADS 4
#endif
+namespace gem5
+{
+
/**
* The maximum number of active threads across all cpus. Used to
* initialize per-thread statistics in the cache.
@@ -58,4 +61,6 @@
*/
void change_thread_state(ThreadID tid, int activate, int priority);
+} // namespace gem5
+
#endif // __SMT_HH__
diff --git a/src/cpu/static_inst.cc b/src/cpu/static_inst.cc
index 4af450b..903e3d7 100644
--- a/src/cpu/static_inst.cc
+++ b/src/cpu/static_inst.cc
@@ -30,6 +30,9 @@
#include <iostream>
+namespace gem5
+{
+
bool
StaticInst::hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
TheISA::PCState &tgt) const
@@ -95,3 +98,5 @@
}
}
}
+
+} // namespace gem5
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 2af6a0b..f63baf2 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -57,6 +57,9 @@
#include "enums/StaticInstFlags.hh"
#include "sim/byteswap.hh"
+namespace gem5
+{
+
// forward declarations
class Packet;
@@ -400,4 +403,6 @@
virtual size_t asBytes(void *buf, size_t max_size) { return 0; }
};
+} // namespace gem5
+
#endif // __CPU_STATIC_INST_HH__
diff --git a/src/cpu/static_inst_fwd.hh b/src/cpu/static_inst_fwd.hh
index 31cbe3c..9fa5c3e 100644
--- a/src/cpu/static_inst_fwd.hh
+++ b/src/cpu/static_inst_fwd.hh
@@ -31,7 +31,12 @@
#include "base/refcnt.hh"
+namespace gem5
+{
+
class StaticInst;
typedef RefCountingPtr<StaticInst> StaticInstPtr;
+} // namespace gem5
+
#endif // __CPU_STATIC_INST_FWD_HH__
diff --git a/src/cpu/testers/directedtest/DirectedGenerator.cc b/src/cpu/testers/directedtest/DirectedGenerator.cc
index 2aab068..498f25f 100644
--- a/src/cpu/testers/directedtest/DirectedGenerator.cc
+++ b/src/cpu/testers/directedtest/DirectedGenerator.cc
@@ -31,6 +31,9 @@
#include "sim/system.hh"
+namespace gem5
+{
+
DirectedGenerator::DirectedGenerator(const Params &p)
: SimObject(p),
requestorId(p.system->getRequestorId(this))
@@ -45,3 +48,5 @@
assert(m_directed_tester == NULL);
m_directed_tester = directed_tester;
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/directedtest/DirectedGenerator.hh b/src/cpu/testers/directedtest/DirectedGenerator.hh
index 503f866..1a28ef7 100644
--- a/src/cpu/testers/directedtest/DirectedGenerator.hh
+++ b/src/cpu/testers/directedtest/DirectedGenerator.hh
@@ -34,6 +34,9 @@
#include "params/DirectedGenerator.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class DirectedGenerator : public SimObject
{
public:
@@ -53,5 +56,6 @@
RubyDirectedTester* m_directed_tester;
};
-#endif //__CPU_DIRECTEDTEST_DIRECTEDGENERATOR_HH__
+} // namespace gem5
+#endif //__CPU_DIRECTEDTEST_DIRECTEDGENERATOR_HH__
diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.cc b/src/cpu/testers/directedtest/InvalidateGenerator.cc
index e55a731..ad87d44 100644
--- a/src/cpu/testers/directedtest/InvalidateGenerator.cc
+++ b/src/cpu/testers/directedtest/InvalidateGenerator.cc
@@ -34,6 +34,9 @@
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
#include "debug/DirectedTest.hh"
+namespace gem5
+{
+
InvalidateGenerator::InvalidateGenerator(const Params &p)
: DirectedGenerator(p)
{
@@ -133,3 +136,5 @@
}
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.hh b/src/cpu/testers/directedtest/InvalidateGenerator.hh
index aadbad2..5860c03 100644
--- a/src/cpu/testers/directedtest/InvalidateGenerator.hh
+++ b/src/cpu/testers/directedtest/InvalidateGenerator.hh
@@ -40,6 +40,9 @@
#include "mem/ruby/protocol/InvalidateGeneratorStatus.hh"
#include "params/InvalidateGenerator.hh"
+namespace gem5
+{
+
class InvalidateGenerator : public DirectedGenerator
{
public:
@@ -59,5 +62,6 @@
uint32_t m_addr_increment_size;
};
-#endif //__CPU_DIRECTEDTEST_INVALIDATEGENERATOR_HH__
+} // namespace gem5
+#endif //__CPU_DIRECTEDTEST_INVALIDATEGENERATOR_HH__
diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.cc b/src/cpu/testers/directedtest/RubyDirectedTester.cc
index 455a986..75124e9 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.cc
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.cc
@@ -46,6 +46,9 @@
#include "debug/DirectedTest.hh"
#include "sim/sim_exit.hh"
+namespace gem5
+{
+
RubyDirectedTester::RubyDirectedTester(const Params &p)
: ClockedObject(p),
directedStartEvent([this]{ wakeup(); }, "Directed tick",
@@ -136,3 +139,5 @@
exitSimLoop("Ruby DirectedTester completed");
}
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.hh b/src/cpu/testers/directedtest/RubyDirectedTester.hh
index a0e20c0..80e1831 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.hh
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh
@@ -42,6 +42,9 @@
#include "params/RubyDirectedTester.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
class DirectedGenerator;
class RubyDirectedTester : public ClockedObject
@@ -103,4 +106,6 @@
DirectedGenerator* generator;
};
+} // namespace gem5
+
#endif // __CPU_DIRECTEDTEST_RUBYDIRECTEDTESTER_HH__
diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.py b/src/cpu/testers/directedtest/RubyDirectedTester.py
index 0bbcb34..ec7797e 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.py
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.py
@@ -34,12 +34,16 @@
type = 'DirectedGenerator'
abstract = True
cxx_header = "cpu/testers/directedtest/DirectedGenerator.hh"
+ cxx_class = 'gem5::DirectedGenerator'
+
num_cpus = Param.Int("num of cpus")
system = Param.System(Parent.any, "System we belong to")
class SeriesRequestGenerator(DirectedGenerator):
type = 'SeriesRequestGenerator'
cxx_header = "cpu/testers/directedtest/SeriesRequestGenerator.hh"
+ cxx_class = 'gem5::SeriesRequestGenerator'
+
addr_increment_size = Param.Int(64, "address increment size")
num_series = Param.UInt32(1,
"number of different address streams to generate")
@@ -48,11 +52,15 @@
class InvalidateGenerator(DirectedGenerator):
type = 'InvalidateGenerator'
cxx_header = "cpu/testers/directedtest/InvalidateGenerator.hh"
+ cxx_class = 'gem5::InvalidateGenerator'
+
addr_increment_size = Param.Int(64, "address increment size")
class RubyDirectedTester(ClockedObject):
type = 'RubyDirectedTester'
cxx_header = "cpu/testers/directedtest/RubyDirectedTester.hh"
+ cxx_class = 'gem5::RubyDirectedTester'
+
cpuPort = VectorRequestPort("the cpu ports")
requests_to_complete = Param.Int("checks to complete")
generator = Param.DirectedGenerator("the request generator")
diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
index 5704ea0..f43cf85 100644
--- a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
+++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
@@ -35,6 +35,9 @@
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
#include "debug/DirectedTest.hh"
+namespace gem5
+{
+
SeriesRequestGenerator::SeriesRequestGenerator(const Params &p)
: DirectedGenerator(p),
m_addr_increment_size(p.addr_increment_size),
@@ -108,3 +111,5 @@
m_active_node = 0;
}
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.hh b/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
index 27c19db..14ad9ae 100644
--- a/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
+++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
@@ -40,6 +40,9 @@
#include "mem/ruby/protocol/SeriesRequestGeneratorStatus.hh"
#include "params/SeriesRequestGenerator.hh"
+namespace gem5
+{
+
class SeriesRequestGenerator : public DirectedGenerator
{
public:
@@ -59,5 +62,6 @@
uint32_t m_percent_writes;
};
-#endif //__CPU_DIRECTEDTEST_SERIESREQUESTGENERATOR_HH__
+} // namespace gem5
+#endif //__CPU_DIRECTEDTEST_SERIESREQUESTGENERATOR_HH__
diff --git a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
index 7b534f9..fc3d620 100644
--- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
+++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
@@ -45,6 +45,9 @@
#include "sim/stats.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
int TESTER_NETWORK=0;
bool
@@ -346,3 +349,5 @@
{
cachePort.printAddr(a);
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
index b132a48..1667da1 100644
--- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
+++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
@@ -40,6 +40,9 @@
#include "sim/sim_object.hh"
#include "sim/stats.hh"
+namespace gem5
+{
+
enum TrafficType {BIT_COMPLEMENT_ = 0,
BIT_REVERSE_ = 1,
BIT_ROTATION_ = 2,
@@ -143,4 +146,6 @@
friend class MemCompleteEvent;
};
+} // namespace gem5
+
#endif // __CPU_GARNET_SYNTHETIC_TRAFFIC_HH__
diff --git a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
index 8ad00b6..f23a141 100644
--- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
+++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
@@ -32,6 +32,8 @@
type = 'GarnetSyntheticTraffic'
cxx_header = \
"cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh"
+ cxx_class = 'gem5::GarnetSyntheticTraffic'
+
block_offset = Param.Int(6, "block offset in bits")
num_dest = Param.Int(1, "Number of Destinations")
memory_size = Param.Int(65536, "memory size")
diff --git a/src/cpu/testers/gpu_ruby_test/CpuThread.py b/src/cpu/testers/gpu_ruby_test/CpuThread.py
index 8cb3269..be64692 100644
--- a/src/cpu/testers/gpu_ruby_test/CpuThread.py
+++ b/src/cpu/testers/gpu_ruby_test/CpuThread.py
@@ -37,3 +37,4 @@
class CpuThread(TesterThread):
type = 'CpuThread'
cxx_header = "cpu/testers/gpu_ruby_test/cpu_thread.hh"
+ cxx_class = 'gem5::CpuThread'
diff --git a/src/cpu/testers/gpu_ruby_test/DmaThread.py b/src/cpu/testers/gpu_ruby_test/DmaThread.py
index 570c6ae..5f9165f 100644
--- a/src/cpu/testers/gpu_ruby_test/DmaThread.py
+++ b/src/cpu/testers/gpu_ruby_test/DmaThread.py
@@ -37,3 +37,4 @@
class DmaThread(TesterThread):
type = 'DmaThread'
cxx_header = "cpu/testers/gpu_ruby_test/dma_thread.hh"
+ cxx_class = 'gem5::DmaThread'
diff --git a/src/cpu/testers/gpu_ruby_test/GpuWavefront.py b/src/cpu/testers/gpu_ruby_test/GpuWavefront.py
index d8d7dae..b1dc45b 100644
--- a/src/cpu/testers/gpu_ruby_test/GpuWavefront.py
+++ b/src/cpu/testers/gpu_ruby_test/GpuWavefront.py
@@ -37,4 +37,6 @@
class GpuWavefront(TesterThread):
type = 'GpuWavefront'
cxx_header = "cpu/testers/gpu_ruby_test/gpu_wavefront.hh"
+ cxx_class = 'gem5::GpuWavefront'
+
cu_id = Param.Int("Compute Unit ID")
diff --git a/src/cpu/testers/gpu_ruby_test/ProtocolTester.py b/src/cpu/testers/gpu_ruby_test/ProtocolTester.py
index a1b55c8..cf24aec 100644
--- a/src/cpu/testers/gpu_ruby_test/ProtocolTester.py
+++ b/src/cpu/testers/gpu_ruby_test/ProtocolTester.py
@@ -36,6 +36,7 @@
class ProtocolTester(ClockedObject):
type = 'ProtocolTester'
cxx_header = "cpu/testers/gpu_ruby_test/protocol_tester.hh"
+ cxx_class = 'gem5::ProtocolTester'
cpu_ports = VectorRequestPort("Ports for CPUs")
dma_ports = VectorRequestPort("Ports for DMAs")
diff --git a/src/cpu/testers/gpu_ruby_test/TesterDma.py b/src/cpu/testers/gpu_ruby_test/TesterDma.py
index 2f669c0..0b864ff 100644
--- a/src/cpu/testers/gpu_ruby_test/TesterDma.py
+++ b/src/cpu/testers/gpu_ruby_test/TesterDma.py
@@ -34,3 +34,4 @@
class TesterDma(DmaDevice):
type = 'TesterDma'
cxx_header = "cpu/testers/gpu_ruby_test/tester_dma.hh"
+ cxx_class = 'gem5::TesterDma'
diff --git a/src/cpu/testers/gpu_ruby_test/TesterThread.py b/src/cpu/testers/gpu_ruby_test/TesterThread.py
index e3e6c01..eaa5cc4 100644
--- a/src/cpu/testers/gpu_ruby_test/TesterThread.py
+++ b/src/cpu/testers/gpu_ruby_test/TesterThread.py
@@ -37,6 +37,8 @@
type = 'TesterThread'
abstract = True
cxx_header = "cpu/testers/gpu_ruby_test/tester_thread.hh"
+ cxx_class = 'gem5::TesterThread'
+
thread_id = Param.Int("Unique TesterThread ID")
num_lanes = Param.Int("Number of lanes this thread has")
deadlock_threshold = Param.Cycles(1000000000, "Deadlock threshold")
diff --git a/src/cpu/testers/gpu_ruby_test/address_manager.cc b/src/cpu/testers/gpu_ruby_test/address_manager.cc
index fb3eb75..959f8a2 100644
--- a/src/cpu/testers/gpu_ruby_test/address_manager.cc
+++ b/src/cpu/testers/gpu_ruby_test/address_manager.cc
@@ -40,6 +40,9 @@
#include "base/random.hh"
#include "base/trace.hh"
+namespace gem5
+{
+
const int AddressManager::INVALID_VALUE = -1;
const int AddressManager::INVALID_LOCATION = -1;
@@ -429,3 +432,5 @@
assert(loc >= 0 && loc < numAtomicLocs);
return atomicStructs[loc]->isExpectedValue(ret_val);
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/gpu_ruby_test/address_manager.hh b/src/cpu/testers/gpu_ruby_test/address_manager.hh
index 2ea586f..1527db4 100644
--- a/src/cpu/testers/gpu_ruby_test/address_manager.hh
+++ b/src/cpu/testers/gpu_ruby_test/address_manager.hh
@@ -42,6 +42,9 @@
#include "base/types.hh"
#include "sim/eventq.hh"
+namespace gem5
+{
+
/*
* --- AddressManager has 3 main tasks ---
* (1) generate DRF request sequences
@@ -271,4 +274,6 @@
LogTable logTable;
};
+} // namespace gem5
+
#endif /* CPU_TESTERS_PROTOCOL_TESTER_ADDRESS_MANAGER_HH_ */
diff --git a/src/cpu/testers/gpu_ruby_test/cpu_thread.cc b/src/cpu/testers/gpu_ruby_test/cpu_thread.cc
index d0ac10e..2dce83a 100644
--- a/src/cpu/testers/gpu_ruby_test/cpu_thread.cc
+++ b/src/cpu/testers/gpu_ruby_test/cpu_thread.cc
@@ -35,6 +35,9 @@
#include "debug/ProtocolTest.hh"
+namespace gem5
+{
+
CpuThread::CpuThread(const Params &p)
: TesterThread(p)
{
@@ -115,3 +118,5 @@
{
fatal("CpuThread::hitCallback - not yet implemented");
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/gpu_ruby_test/cpu_thread.hh b/src/cpu/testers/gpu_ruby_test/cpu_thread.hh
index 1e37c6f..32c2020 100644
--- a/src/cpu/testers/gpu_ruby_test/cpu_thread.hh
+++ b/src/cpu/testers/gpu_ruby_test/cpu_thread.hh
@@ -38,6 +38,9 @@
#include "params/CpuThread.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
class CpuThread : public TesterThread
{
public:
@@ -58,4 +61,6 @@
void issueReleaseOp();
};
+} // namespace gem5
+
#endif /* CPU_TESTERS_PROTOCOL_TESTER_CPU_THREAD_HH_ */
diff --git a/src/cpu/testers/gpu_ruby_test/dma_thread.cc b/src/cpu/testers/gpu_ruby_test/dma_thread.cc
index e5f79c9..c888288 100644
--- a/src/cpu/testers/gpu_ruby_test/dma_thread.cc
+++ b/src/cpu/testers/gpu_ruby_test/dma_thread.cc
@@ -35,6 +35,9 @@
#include "debug/ProtocolTest.hh"
+namespace gem5
+{
+
DmaThread::DmaThread(const Params& _params)
: TesterThread(_params)
{
@@ -287,3 +290,5 @@
scheduleWakeup();
}
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/gpu_ruby_test/dma_thread.hh b/src/cpu/testers/gpu_ruby_test/dma_thread.hh
index 1b6fd2b..a80322b 100644
--- a/src/cpu/testers/gpu_ruby_test/dma_thread.hh
+++ b/src/cpu/testers/gpu_ruby_test/dma_thread.hh
@@ -37,6 +37,9 @@
#include "cpu/testers/gpu_ruby_test/tester_thread.hh"
#include "params/DmaThread.hh"
+namespace gem5
+{
+
class DmaThread : public TesterThread
{
public:
@@ -57,4 +60,6 @@
void issueReleaseOp();
};
+} // namespace gem5
+
#endif /* CPU_TESTERS_PROTOCOL_TESTER_DMATHREAD_HH_ */
diff --git a/src/cpu/testers/gpu_ruby_test/episode.cc b/src/cpu/testers/gpu_ruby_test/episode.cc
index 2094317..fb6c849 100644
--- a/src/cpu/testers/gpu_ruby_test/episode.cc
+++ b/src/cpu/testers/gpu_ruby_test/episode.cc
@@ -39,6 +39,9 @@
#include "cpu/testers/gpu_ruby_test/protocol_tester.hh"
#include "cpu/testers/gpu_ruby_test/tester_thread.hh"
+namespace gem5
+{
+
Episode::Episode(ProtocolTester* _tester, TesterThread* _thread, int num_loads,
int num_stores)
: tester(_tester),
@@ -319,3 +322,5 @@
else
panic("Invalid action type\n");
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/gpu_ruby_test/episode.hh b/src/cpu/testers/gpu_ruby_test/episode.hh
index cec85be..091329d 100644
--- a/src/cpu/testers/gpu_ruby_test/episode.hh
+++ b/src/cpu/testers/gpu_ruby_test/episode.hh
@@ -38,6 +38,9 @@
#include "cpu/testers/gpu_ruby_test/address_manager.hh"
+namespace gem5
+{
+
class ProtocolTester;
class TesterThread;
@@ -125,4 +128,6 @@
void initActions();
};
+} // namespace gem5
+
#endif /* CPU_TESTERS_PROTOCOL_TESTER_EPISODE_HH_ */
diff --git a/src/cpu/testers/gpu_ruby_test/gpu_wavefront.cc b/src/cpu/testers/gpu_ruby_test/gpu_wavefront.cc
index a90b204..0a24461 100644
--- a/src/cpu/testers/gpu_ruby_test/gpu_wavefront.cc
+++ b/src/cpu/testers/gpu_ruby_test/gpu_wavefront.cc
@@ -35,6 +35,9 @@
#include "debug/ProtocolTest.hh"
+namespace gem5
+{
+
GpuWavefront::GpuWavefront(const Params &p)
: TesterThread(p), cuId(p.cu_id)
{
@@ -369,3 +372,5 @@
{
// No extra request flag is set
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/gpu_ruby_test/gpu_wavefront.hh b/src/cpu/testers/gpu_ruby_test/gpu_wavefront.hh
index dfc4898..065eb69 100644
--- a/src/cpu/testers/gpu_ruby_test/gpu_wavefront.hh
+++ b/src/cpu/testers/gpu_ruby_test/gpu_wavefront.hh
@@ -38,6 +38,9 @@
#include "params/GpuWavefront.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
class GpuWavefront : public TesterThread
{
public:
@@ -65,4 +68,6 @@
int cuId; // compute unit associated with this wavefront
};
+} // namespace gem5
+
#endif /* CPU_TESTERS_PROTOCOL_TESTER_GPU_WAVEFRONT_HH_ */
diff --git a/src/cpu/testers/gpu_ruby_test/protocol_tester.cc b/src/cpu/testers/gpu_ruby_test/protocol_tester.cc
index 95e6035..5cedd1f 100644
--- a/src/cpu/testers/gpu_ruby_test/protocol_tester.cc
+++ b/src/cpu/testers/gpu_ruby_test/protocol_tester.cc
@@ -47,6 +47,9 @@
#include "sim/sim_exit.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
ProtocolTester::ProtocolTester(const Params &p)
: ClockedObject(p),
_requestorId(p.system->getRequestorId(this)),
@@ -357,3 +360,5 @@
return true;
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/gpu_ruby_test/protocol_tester.hh b/src/cpu/testers/gpu_ruby_test/protocol_tester.hh
index 57e9d18..1d9b99f 100644
--- a/src/cpu/testers/gpu_ruby_test/protocol_tester.hh
+++ b/src/cpu/testers/gpu_ruby_test/protocol_tester.hh
@@ -61,6 +61,9 @@
#include "mem/token_port.hh"
#include "params/ProtocolTester.hh"
+namespace gem5
+{
+
class TesterThread;
class CpuThread;
class GpuWavefront;
@@ -198,4 +201,6 @@
OutputStream* logFile;
};
+} // namespace gem5
+
#endif /* CPU_TESTERS_PROTOCOL_TESTER_PROTOCOL_TESTER_HH_ */
diff --git a/src/cpu/testers/gpu_ruby_test/tester_dma.hh b/src/cpu/testers/gpu_ruby_test/tester_dma.hh
index 772745b..d4743ad 100644
--- a/src/cpu/testers/gpu_ruby_test/tester_dma.hh
+++ b/src/cpu/testers/gpu_ruby_test/tester_dma.hh
@@ -43,6 +43,9 @@
#include "dev/dma_device.hh"
#include "params/TesterDma.hh"
+namespace gem5
+{
+
class TesterDma : public DmaDevice
{
public:
@@ -65,4 +68,6 @@
Tick write(PacketPtr) override { return 10; }
};
+} // namespace gem5
+
#endif /* __CPU_TESTERS_GPU_RUBY_TEST_TESTER_DMA_HH__ */
diff --git a/src/cpu/testers/gpu_ruby_test/tester_thread.cc b/src/cpu/testers/gpu_ruby_test/tester_thread.cc
index 0164b5e..854e352 100644
--- a/src/cpu/testers/gpu_ruby_test/tester_thread.cc
+++ b/src/cpu/testers/gpu_ruby_test/tester_thread.cc
@@ -37,6 +37,9 @@
#include "debug/ProtocolTest.hh"
+namespace gem5
+{
+
TesterThread::TesterThread(const Params &p)
: ClockedObject(p),
threadEvent(this, "TesterThread tick"),
@@ -444,3 +447,5 @@
ss << "\t\tNumber of outstanding acquires & releases: "
<< pendingFenceCount << std::endl;
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/gpu_ruby_test/tester_thread.hh b/src/cpu/testers/gpu_ruby_test/tester_thread.hh
index bee4fda..714a193 100644
--- a/src/cpu/testers/gpu_ruby_test/tester_thread.hh
+++ b/src/cpu/testers/gpu_ruby_test/tester_thread.hh
@@ -45,6 +45,9 @@
#include "mem/token_port.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
class TesterThread : public ClockedObject
{
public:
@@ -204,4 +207,6 @@
std::stringstream& ss) const;
};
+} // namespace gem5
+
#endif /* CPU_TESTERS_PROTOCOL_TESTER_TESTER_THREAD_HH_ */
diff --git a/src/cpu/testers/memtest/MemTest.py b/src/cpu/testers/memtest/MemTest.py
index a91c946..7be4a76 100644
--- a/src/cpu/testers/memtest/MemTest.py
+++ b/src/cpu/testers/memtest/MemTest.py
@@ -44,6 +44,7 @@
class MemTest(ClockedObject):
type = 'MemTest'
cxx_header = "cpu/testers/memtest/memtest.hh"
+ cxx_class = 'gem5::MemTest'
# Interval of packet injection, the size of the memory range
# touched, and an optional stop condition
diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc
index c6dbeeb..c8937ec 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -49,6 +49,9 @@
#include "sim/stats.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
static unsigned int TESTER_ALLOCATOR = 0;
bool
@@ -322,3 +325,5 @@
reschedule(noRequestEvent, clockEdge(progressCheck), true);
}
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/memtest/memtest.hh b/src/cpu/testers/memtest/memtest.hh
index 5c417bf..2e7824e 100644
--- a/src/cpu/testers/memtest/memtest.hh
+++ b/src/cpu/testers/memtest/memtest.hh
@@ -51,6 +51,9 @@
#include "sim/eventq.hh"
#include "sim/stats.hh"
+namespace gem5
+{
+
/**
* The MemTest class tests a cache coherent memory system by
* generating false sharing and verifying the read data against a
@@ -187,4 +190,6 @@
};
+} // namespace gem5
+
#endif // __CPU_MEMTEST_MEMTEST_HH__
diff --git a/src/cpu/testers/rubytest/Check.cc b/src/cpu/testers/rubytest/Check.cc
index cf60097..ce2d1a1 100644
--- a/src/cpu/testers/rubytest/Check.cc
+++ b/src/cpu/testers/rubytest/Check.cc
@@ -34,6 +34,9 @@
#include "debug/RubyTest.hh"
#include "mem/ruby/common/SubBlock.hh"
+namespace gem5
+{
+
typedef RubyTester::SenderState SenderState;
Check::Check(Addr address, Addr pc, int _num_writers, int _num_readers,
@@ -393,3 +396,5 @@
m_address, (int)m_value, TesterStatus_to_string(m_status).c_str(),
m_initiatingNode, m_store_count);
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/rubytest/Check.hh b/src/cpu/testers/rubytest/Check.hh
index 1a33174..11f9e49 100644
--- a/src/cpu/testers/rubytest/Check.hh
+++ b/src/cpu/testers/rubytest/Check.hh
@@ -37,6 +37,9 @@
#include "mem/ruby/protocol/RubyAccessMode.hh"
#include "mem/ruby/protocol/TesterStatus.hh"
+namespace gem5
+{
+
class SubBlock;
const int CHECK_SIZE_BITS = 2;
@@ -86,4 +89,6 @@
return out;
}
+} // namespace gem5
+
#endif // __CPU_RUBYTEST_CHECK_HH__
diff --git a/src/cpu/testers/rubytest/CheckTable.cc b/src/cpu/testers/rubytest/CheckTable.cc
index 843a7cf..39aed52 100644
--- a/src/cpu/testers/rubytest/CheckTable.cc
+++ b/src/cpu/testers/rubytest/CheckTable.cc
@@ -35,6 +35,9 @@
#include "cpu/testers/rubytest/Check.hh"
#include "debug/RubyTest.hh"
+namespace gem5
+{
+
CheckTable::CheckTable(int _num_writers, int _num_readers, RubyTester* _tester)
: m_num_writers(_num_writers), m_num_readers(_num_readers),
m_tester_ptr(_tester)
@@ -133,3 +136,5 @@
CheckTable::print(std::ostream& out) const
{
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/rubytest/CheckTable.hh b/src/cpu/testers/rubytest/CheckTable.hh
index 23ca855..d832343 100644
--- a/src/cpu/testers/rubytest/CheckTable.hh
+++ b/src/cpu/testers/rubytest/CheckTable.hh
@@ -36,6 +36,9 @@
#include "mem/ruby/common/Address.hh"
+namespace gem5
+{
+
class Check;
class RubyTester;
@@ -78,4 +81,6 @@
return out;
}
+} // namespace gem5
+
#endif // __CPU_RUBYTEST_CHECKTABLE_HH__
diff --git a/src/cpu/testers/rubytest/RubyTester.cc b/src/cpu/testers/rubytest/RubyTester.cc
index 9209b17..dcf9117 100644
--- a/src/cpu/testers/rubytest/RubyTester.cc
+++ b/src/cpu/testers/rubytest/RubyTester.cc
@@ -49,6 +49,9 @@
#include "sim/sim_exit.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
RubyTester::RubyTester(const Params &p)
: ClockedObject(p),
checkStartEvent([this]{ wakeup(); }, "RubyTester tick",
@@ -278,3 +281,5 @@
{
out << "[RubyTester]" << std::endl;
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/rubytest/RubyTester.hh b/src/cpu/testers/rubytest/RubyTester.hh
index 50c3343..1cb8514 100644
--- a/src/cpu/testers/rubytest/RubyTester.hh
+++ b/src/cpu/testers/rubytest/RubyTester.hh
@@ -54,6 +54,9 @@
#include "params/RubyTester.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
class RubyTester : public ClockedObject
{
public:
@@ -157,4 +160,6 @@
return out;
}
+} // namespace gem5
+
#endif // __CPU_RUBYTEST_RUBYTESTER_HH__
diff --git a/src/cpu/testers/rubytest/RubyTester.py b/src/cpu/testers/rubytest/RubyTester.py
index 9bcbcd1..408dc04 100644
--- a/src/cpu/testers/rubytest/RubyTester.py
+++ b/src/cpu/testers/rubytest/RubyTester.py
@@ -33,6 +33,8 @@
class RubyTester(ClockedObject):
type = 'RubyTester'
cxx_header = "cpu/testers/rubytest/RubyTester.hh"
+ cxx_class = 'gem5::RubyTester'
+
num_cpus = Param.Int("number of cpus / RubyPorts")
cpuInstDataPort = VectorRequestPort("cpu combo ports to inst & "
"data caches")
diff --git a/src/cpu/testers/traffic_gen/BaseTrafficGen.py b/src/cpu/testers/traffic_gen/BaseTrafficGen.py
index 3055348..4bccaa1 100644
--- a/src/cpu/testers/traffic_gen/BaseTrafficGen.py
+++ b/src/cpu/testers/traffic_gen/BaseTrafficGen.py
@@ -55,6 +55,7 @@
type = 'BaseTrafficGen'
abstract = True
cxx_header = "cpu/testers/traffic_gen/traffic_gen.hh"
+ cxx_class = 'gem5::BaseTrafficGen'
# Port used for sending requests and receiving responses
port = RequestPort("This port sends requests and receives responses")
diff --git a/src/cpu/testers/traffic_gen/PyTrafficGen.py b/src/cpu/testers/traffic_gen/PyTrafficGen.py
index baf4ef5..a3097a5 100644
--- a/src/cpu/testers/traffic_gen/PyTrafficGen.py
+++ b/src/cpu/testers/traffic_gen/PyTrafficGen.py
@@ -41,6 +41,7 @@
class PyTrafficGen(BaseTrafficGen):
type = 'PyTrafficGen'
cxx_header = "cpu/testers/traffic_gen/pygen.hh"
+ cxx_class = 'gem5::PyTrafficGen'
@cxxMethod
def start(self, meta_generator):
diff --git a/src/cpu/testers/traffic_gen/TrafficGen.py b/src/cpu/testers/traffic_gen/TrafficGen.py
index 504824f..5a4a0ea 100644
--- a/src/cpu/testers/traffic_gen/TrafficGen.py
+++ b/src/cpu/testers/traffic_gen/TrafficGen.py
@@ -47,6 +47,7 @@
class TrafficGen(BaseTrafficGen):
type = 'TrafficGen'
cxx_header = "cpu/testers/traffic_gen/traffic_gen.hh"
+ cxx_class = 'gem5::TrafficGen'
# Config file to parse for the state descriptions
config_file = Param.String("Configuration file describing the behaviour")
diff --git a/src/cpu/testers/traffic_gen/base.cc b/src/cpu/testers/traffic_gen/base.cc
index 54a7cbd..03cf2a9 100644
--- a/src/cpu/testers/traffic_gen/base.cc
+++ b/src/cpu/testers/traffic_gen/base.cc
@@ -64,6 +64,8 @@
#include "cpu/testers/traffic_gen/trace_gen.hh"
#endif
+namespace gem5
+{
BaseTrafficGen::BaseTrafficGen(const BaseTrafficGenParams &p)
: ClockedObject(p),
@@ -585,3 +587,5 @@
return true;
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/traffic_gen/base.hh b/src/cpu/testers/traffic_gen/base.hh
index 850326e..5a9af61 100644
--- a/src/cpu/testers/traffic_gen/base.hh
+++ b/src/cpu/testers/traffic_gen/base.hh
@@ -47,6 +47,9 @@
#include "mem/qport.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
class BaseGen;
class StreamGen;
class System;
@@ -343,4 +346,6 @@
std::unique_ptr<StreamGen> streamGenerator;
};
+} // namespace gem5
+
#endif //__CPU_TRAFFIC_GEN_BASE_HH__
diff --git a/src/cpu/testers/traffic_gen/base_gen.cc b/src/cpu/testers/traffic_gen/base_gen.cc
index c389114..14e4c5f 100644
--- a/src/cpu/testers/traffic_gen/base_gen.cc
+++ b/src/cpu/testers/traffic_gen/base_gen.cc
@@ -42,6 +42,9 @@
#include "base/logging.hh"
#include "cpu/testers/traffic_gen/base.hh"
+namespace gem5
+{
+
BaseGen::BaseGen(SimObject &obj, RequestorID requestor_id, Tick _duration)
: _name(obj.name()), requestorId(requestor_id),
duration(_duration)
@@ -95,3 +98,5 @@
if (min_period > max_period)
fatal("%s cannot have min_period > max_period", name());
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/traffic_gen/base_gen.hh b/src/cpu/testers/traffic_gen/base_gen.hh
index 664678e..6c8c5ea 100644
--- a/src/cpu/testers/traffic_gen/base_gen.hh
+++ b/src/cpu/testers/traffic_gen/base_gen.hh
@@ -50,6 +50,9 @@
#include "mem/packet.hh"
#include "mem/request.hh"
+namespace gem5
+{
+
class BaseTrafficGen;
class SimObject;
@@ -169,4 +172,6 @@
const Addr dataLimit;
};
+} // namespace gem5
+
#endif
diff --git a/src/cpu/testers/traffic_gen/dram_gen.cc b/src/cpu/testers/traffic_gen/dram_gen.cc
index be29b5d..73f56fc 100644
--- a/src/cpu/testers/traffic_gen/dram_gen.cc
+++ b/src/cpu/testers/traffic_gen/dram_gen.cc
@@ -44,6 +44,9 @@
#include "debug/TrafficGen.hh"
#include "enums/AddrMap.hh"
+namespace gem5
+{
+
DramGen::DramGen(SimObject &obj,
RequestorID requestor_id, Tick _duration,
Addr start_addr, Addr end_addr,
@@ -187,3 +190,5 @@
}
}
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/traffic_gen/dram_gen.hh b/src/cpu/testers/traffic_gen/dram_gen.hh
index 6b39802..e5d17af 100644
--- a/src/cpu/testers/traffic_gen/dram_gen.hh
+++ b/src/cpu/testers/traffic_gen/dram_gen.hh
@@ -50,6 +50,9 @@
#include "mem/packet.hh"
#include "random_gen.hh"
+namespace gem5
+{
+
/**
* DRAM specific generator is for issuing request with variable page
* hit length and bank utilization. Currently assumes a single
@@ -146,4 +149,6 @@
};
+} // namespace gem5
+
#endif
diff --git a/src/cpu/testers/traffic_gen/dram_rot_gen.cc b/src/cpu/testers/traffic_gen/dram_rot_gen.cc
index accbaf0..e9fb85c 100644
--- a/src/cpu/testers/traffic_gen/dram_rot_gen.cc
+++ b/src/cpu/testers/traffic_gen/dram_rot_gen.cc
@@ -44,6 +44,9 @@
#include "debug/TrafficGen.hh"
#include "enums/AddrMap.hh"
+namespace gem5
+{
+
PacketPtr
DramRotGen::getNextPacket()
{
@@ -132,3 +135,5 @@
// return the generated packet
return pkt;
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/traffic_gen/dram_rot_gen.hh b/src/cpu/testers/traffic_gen/dram_rot_gen.hh
index 7365a97..ebc84af 100644
--- a/src/cpu/testers/traffic_gen/dram_rot_gen.hh
+++ b/src/cpu/testers/traffic_gen/dram_rot_gen.hh
@@ -50,6 +50,9 @@
#include "enums/AddrMap.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
class DramRotGen : public DramGen
{
@@ -123,4 +126,6 @@
unsigned int nextSeqCount;
};
+} // namespace gem5
+
#endif
diff --git a/src/cpu/testers/traffic_gen/exit_gen.cc b/src/cpu/testers/traffic_gen/exit_gen.cc
index 17faf59..16e399c 100644
--- a/src/cpu/testers/traffic_gen/exit_gen.cc
+++ b/src/cpu/testers/traffic_gen/exit_gen.cc
@@ -41,6 +41,9 @@
#include "exit_gen.hh"
#include "sim/sim_exit.hh"
+namespace gem5
+{
+
void
ExitGen::enter()
{
@@ -62,3 +65,5 @@
{
return MaxTick;
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/traffic_gen/exit_gen.hh b/src/cpu/testers/traffic_gen/exit_gen.hh
index 65939a6..23ebbe1 100644
--- a/src/cpu/testers/traffic_gen/exit_gen.hh
+++ b/src/cpu/testers/traffic_gen/exit_gen.hh
@@ -45,6 +45,9 @@
#include "base_gen.hh"
+namespace gem5
+{
+
/**
* The exit generator exits from the simulation
* once entered.
@@ -66,4 +69,6 @@
};
+} // namespace gem5
+
#endif
diff --git a/src/cpu/testers/traffic_gen/hybrid_gen.cc b/src/cpu/testers/traffic_gen/hybrid_gen.cc
index 5dc92e8..3be569b 100644
--- a/src/cpu/testers/traffic_gen/hybrid_gen.cc
+++ b/src/cpu/testers/traffic_gen/hybrid_gen.cc
@@ -44,6 +44,9 @@
#include "debug/TrafficGen.hh"
#include "enums/AddrMap.hh"
+namespace gem5
+{
+
HybridGen::HybridGen(SimObject &obj,
RequestorID requestor_id, Tick _duration,
Addr start_addr_dram, Addr end_addr_dram,
@@ -308,3 +311,5 @@
return curTick() + wait;
}
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/traffic_gen/hybrid_gen.hh b/src/cpu/testers/traffic_gen/hybrid_gen.hh
index f0d158e..3a9cd5e 100644
--- a/src/cpu/testers/traffic_gen/hybrid_gen.hh
+++ b/src/cpu/testers/traffic_gen/hybrid_gen.hh
@@ -50,6 +50,9 @@
#include "enums/AddrMap.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
/**
* Hybrid NVM + DRAM specific generator is for issuing request with variable
* buffer hit length and bank utilization. Currently assumes a single
@@ -272,4 +275,6 @@
};
+} // namespace gem5
+
#endif
diff --git a/src/cpu/testers/traffic_gen/idle_gen.cc b/src/cpu/testers/traffic_gen/idle_gen.cc
index 38ffcc4..1bebc8a 100644
--- a/src/cpu/testers/traffic_gen/idle_gen.cc
+++ b/src/cpu/testers/traffic_gen/idle_gen.cc
@@ -43,6 +43,9 @@
#include "base/trace.hh"
#include "debug/TrafficGen.hh"
+namespace gem5
+{
+
void
IdleGen::enter() { }
@@ -58,3 +61,4 @@
return MaxTick;
}
+} // namespace gem5
diff --git a/src/cpu/testers/traffic_gen/idle_gen.hh b/src/cpu/testers/traffic_gen/idle_gen.hh
index 40e98b8..c8465ad 100644
--- a/src/cpu/testers/traffic_gen/idle_gen.hh
+++ b/src/cpu/testers/traffic_gen/idle_gen.hh
@@ -48,6 +48,9 @@
#include "base_gen.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
/**
* The idle generator does nothing.
*/
@@ -67,4 +70,6 @@
Tick nextPacketTick(bool elastic, Tick delay) const ;
};
+} // namespace gem5
+
#endif
diff --git a/src/cpu/testers/traffic_gen/linear_gen.cc b/src/cpu/testers/traffic_gen/linear_gen.cc
index 516ea48..7b90ba2 100644
--- a/src/cpu/testers/traffic_gen/linear_gen.cc
+++ b/src/cpu/testers/traffic_gen/linear_gen.cc
@@ -43,6 +43,9 @@
#include "base/trace.hh"
#include "debug/TrafficGen.hh"
+namespace gem5
+{
+
void
LinearGen::enter()
{
@@ -111,3 +114,5 @@
return curTick() + wait;
}
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/traffic_gen/linear_gen.hh b/src/cpu/testers/traffic_gen/linear_gen.hh
index fbd3d8f..4e3aa5e 100644
--- a/src/cpu/testers/traffic_gen/linear_gen.hh
+++ b/src/cpu/testers/traffic_gen/linear_gen.hh
@@ -49,6 +49,9 @@
#include "base_gen.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
/**
* The linear generator generates sequential requests from a
* start to an end address, with a fixed block size. A
@@ -109,4 +112,6 @@
Addr dataManipulated;
};
+} // namespace gem5
+
#endif
diff --git a/src/cpu/testers/traffic_gen/nvm_gen.cc b/src/cpu/testers/traffic_gen/nvm_gen.cc
index ffd262d..2b43c87 100644
--- a/src/cpu/testers/traffic_gen/nvm_gen.cc
+++ b/src/cpu/testers/traffic_gen/nvm_gen.cc
@@ -44,6 +44,9 @@
#include "debug/TrafficGen.hh"
#include "enums/AddrMap.hh"
+namespace gem5
+{
+
NvmGen::NvmGen(SimObject &obj,
RequestorID requestor_id, Tick _duration,
Addr start_addr, Addr end_addr,
@@ -183,3 +186,5 @@
}
}
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/traffic_gen/nvm_gen.hh b/src/cpu/testers/traffic_gen/nvm_gen.hh
index d72353d..00b7cce 100644
--- a/src/cpu/testers/traffic_gen/nvm_gen.hh
+++ b/src/cpu/testers/traffic_gen/nvm_gen.hh
@@ -50,6 +50,9 @@
#include "mem/packet.hh"
#include "random_gen.hh"
+namespace gem5
+{
+
/**
* NVM specific generator is for issuing request with variable buffer
* hit length and bank utilization. Currently assumes a single
@@ -146,4 +149,6 @@
};
+} // namespace gem5
+
#endif
diff --git a/src/cpu/testers/traffic_gen/pygen.cc b/src/cpu/testers/traffic_gen/pygen.cc
index 9532dbb..2837fa2 100644
--- a/src/cpu/testers/traffic_gen/pygen.cc
+++ b/src/cpu/testers/traffic_gen/pygen.cc
@@ -44,6 +44,9 @@
namespace py = pybind11;
+namespace gem5
+{
+
PyTrafficGen::PyTrafficGen(const PyTrafficGenParams &p)
: BaseTrafficGen(p)
{
@@ -90,3 +93,4 @@
static EmbeddedPyBind _py_tracers("trace", pybind_init_tracers);
+} // namespace gem5
diff --git a/src/cpu/testers/traffic_gen/pygen.hh b/src/cpu/testers/traffic_gen/pygen.hh
index c0e02df..4d82858 100644
--- a/src/cpu/testers/traffic_gen/pygen.hh
+++ b/src/cpu/testers/traffic_gen/pygen.hh
@@ -44,6 +44,9 @@
#include "cpu/testers/traffic_gen/base.hh"
#include "cpu/testers/traffic_gen/base_gen.hh"
+namespace gem5
+{
+
struct PyTrafficGenParams;
class GEM5_LOCAL PyTrafficGen : public BaseTrafficGen
@@ -62,4 +65,6 @@
pybind11::iterator metaGenerator;
};
+} // namespace gem5
+
#endif //__CPU_TRAFFIC_GEN_PYGEN_HH__
diff --git a/src/cpu/testers/traffic_gen/random_gen.cc b/src/cpu/testers/traffic_gen/random_gen.cc
index 590628d..8a692dc 100644
--- a/src/cpu/testers/traffic_gen/random_gen.cc
+++ b/src/cpu/testers/traffic_gen/random_gen.cc
@@ -43,6 +43,9 @@
#include "base/trace.hh"
#include "debug/TrafficGen.hh"
+namespace gem5
+{
+
void
RandomGen::enter()
{
@@ -105,3 +108,5 @@
return curTick() + wait;
}
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/traffic_gen/random_gen.hh b/src/cpu/testers/traffic_gen/random_gen.hh
index 3bf1a86..0d60265 100644
--- a/src/cpu/testers/traffic_gen/random_gen.hh
+++ b/src/cpu/testers/traffic_gen/random_gen.hh
@@ -49,6 +49,9 @@
#include "base_gen.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
/**
* The random generator is similar to the linear one, but does
* not generate sequential addresses. Instead it randomly
@@ -103,4 +106,6 @@
Addr dataManipulated;
};
+} // namespace gem5
+
#endif
diff --git a/src/cpu/testers/traffic_gen/stream_gen.cc b/src/cpu/testers/traffic_gen/stream_gen.cc
index d36b0f6..4eb6ffe 100644
--- a/src/cpu/testers/traffic_gen/stream_gen.cc
+++ b/src/cpu/testers/traffic_gen/stream_gen.cc
@@ -39,6 +39,9 @@
#include "base/random.hh"
+namespace gem5
+{
+
StreamGen*
StreamGen::create(const BaseTrafficGenParams &p)
{
@@ -59,3 +62,5 @@
// Pick a random entry in the vector of IDs
return svec[random_mt.random<size_t>(0, svec.size()-1)];
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/traffic_gen/stream_gen.hh b/src/cpu/testers/traffic_gen/stream_gen.hh
index 01aab9b..92509c8 100644
--- a/src/cpu/testers/traffic_gen/stream_gen.hh
+++ b/src/cpu/testers/traffic_gen/stream_gen.hh
@@ -46,6 +46,9 @@
#include "params/BaseTrafficGen.hh"
+namespace gem5
+{
+
class StreamGen
{
protected:
@@ -136,4 +139,6 @@
uint32_t randomPick(const std::vector<uint32_t> &svec);
};
+} // namespace gem5
+
#endif // __CPU_TRAFFIC_GEN_STREAM_GEN_HH__
diff --git a/src/cpu/testers/traffic_gen/strided_gen.cc b/src/cpu/testers/traffic_gen/strided_gen.cc
index 0b77872..7823b93 100644
--- a/src/cpu/testers/traffic_gen/strided_gen.cc
+++ b/src/cpu/testers/traffic_gen/strided_gen.cc
@@ -43,6 +43,9 @@
#include "base/trace.hh"
#include "debug/TrafficGen.hh"
+namespace gem5
+{
+
void
StridedGen::enter()
{
@@ -111,3 +114,5 @@
return curTick() + wait;
}
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/traffic_gen/strided_gen.hh b/src/cpu/testers/traffic_gen/strided_gen.hh
index d0a1391..4e3ad80 100644
--- a/src/cpu/testers/traffic_gen/strided_gen.hh
+++ b/src/cpu/testers/traffic_gen/strided_gen.hh
@@ -49,6 +49,9 @@
#include "base_gen.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
/**
* The strided generator generates sequential requests from a
* start to an end address, with a fixed block size. A
@@ -127,4 +130,6 @@
int genID;
};
+} // namespace gem5
+
#endif
diff --git a/src/cpu/testers/traffic_gen/trace_gen.cc b/src/cpu/testers/traffic_gen/trace_gen.cc
index 951765c..813a4b5 100644
--- a/src/cpu/testers/traffic_gen/trace_gen.cc
+++ b/src/cpu/testers/traffic_gen/trace_gen.cc
@@ -44,6 +44,9 @@
#include "debug/TrafficGen.hh"
#include "proto/packet.pb.h"
+namespace gem5
+{
+
TraceGen::InputStream::InputStream(const std::string& filename)
: trace(filename)
{
@@ -174,3 +177,5 @@
// file
trace.reset();
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/traffic_gen/trace_gen.hh b/src/cpu/testers/traffic_gen/trace_gen.hh
index c60c8a0..947b58d 100644
--- a/src/cpu/testers/traffic_gen/trace_gen.hh
+++ b/src/cpu/testers/traffic_gen/trace_gen.hh
@@ -50,6 +50,9 @@
#include "mem/packet.hh"
#include "proto/protoio.hh"
+namespace gem5
+{
+
/**
* The trace replay generator reads a trace file and plays
* back the transactions. The trace is offset with respect to
@@ -206,4 +209,6 @@
bool traceComplete;
};
+} // namespace gem5
+
#endif
diff --git a/src/cpu/testers/traffic_gen/traffic_gen.cc b/src/cpu/testers/traffic_gen/traffic_gen.cc
index ffae679..6eab460 100644
--- a/src/cpu/testers/traffic_gen/traffic_gen.cc
+++ b/src/cpu/testers/traffic_gen/traffic_gen.cc
@@ -50,6 +50,9 @@
#include "sim/stats.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
TrafficGen::TrafficGen(const TrafficGenParams &p)
: BaseTrafficGen(p),
configFile(p.config_file),
@@ -368,3 +371,5 @@
DPRINTF(TrafficGen, "Transition to state %d\n", currState);
return states[currState];
}
+
+} // namespace gem5
diff --git a/src/cpu/testers/traffic_gen/traffic_gen.hh b/src/cpu/testers/traffic_gen/traffic_gen.hh
index de1b486..8e69596 100644
--- a/src/cpu/testers/traffic_gen/traffic_gen.hh
+++ b/src/cpu/testers/traffic_gen/traffic_gen.hh
@@ -42,6 +42,9 @@
#include "cpu/testers/traffic_gen/base.hh"
+namespace gem5
+{
+
struct TrafficGenParams;
/**
@@ -133,4 +136,6 @@
};
+} // namespace gem5
+
#endif //__CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index 00afe7c..4852111 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -52,6 +52,9 @@
#include "params/BaseCPU.hh"
#include "sim/full_system.hh"
+namespace gem5
+{
+
void
ThreadContext::compare(ThreadContext *one, ThreadContext *two)
{
@@ -262,3 +265,5 @@
otc.setStatus(ThreadContext::Halted);
}
+
+} // namespace gem5
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 5203869..d7002a9 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -54,6 +54,9 @@
#include "cpu/pc_event.hh"
#include "cpu/reg_class.hh"
+namespace gem5
+{
+
// @todo: Figure out a more architecture independent way to obtain the ITB and
// DTB pointers.
namespace TheISA
@@ -349,4 +352,6 @@
*/
void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
+} // namespace gem5
+
#endif
diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index 620ce1e..853c47b 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -38,6 +38,9 @@
#include "sim/serialize.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
: numInst(0), numOp(0), threadStats(cpu, _tid),
numLoad(0), startNumLoad(0),
@@ -100,3 +103,5 @@
{
}
+
+} // namespace gem5
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index e805b01..8d0835f 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -33,6 +33,9 @@
#include "cpu/thread_context.hh"
#include "sim/process.hh"
+namespace gem5
+{
+
class Checkpoint;
/**
@@ -149,4 +152,6 @@
unsigned storeCondFailures;
};
+} // namespace gem5
+
#endif // __CPU_THREAD_STATE_HH__
diff --git a/src/cpu/timebuf.hh b/src/cpu/timebuf.hh
index 95faa56..f35f568 100644
--- a/src/cpu/timebuf.hh
+++ b/src/cpu/timebuf.hh
@@ -33,6 +33,9 @@
#include <cstring>
#include <vector>
+namespace gem5
+{
+
template <class T>
class TimeBuffer
{
@@ -244,5 +247,6 @@
}
};
-#endif // __BASE_TIMEBUF_HH__
+} // namespace gem5
+#endif // __BASE_TIMEBUF_HH__
diff --git a/src/cpu/timing_expr.cc b/src/cpu/timing_expr.cc
index 2e361cf..6cca06a 100644
--- a/src/cpu/timing_expr.cc
+++ b/src/cpu/timing_expr.cc
@@ -39,6 +39,9 @@
#include "base/intmath.hh"
+namespace gem5
+{
+
TimingExprEvalContext::TimingExprEvalContext(const StaticInstPtr &inst_,
ThreadContext *thread_,
TimingExprLet *let_) :
@@ -197,3 +200,5 @@
else
return falseExpr->eval(context);
}
+
+} // namespace gem5
diff --git a/src/cpu/timing_expr.hh b/src/cpu/timing_expr.hh
index f216315..170364e 100644
--- a/src/cpu/timing_expr.hh
+++ b/src/cpu/timing_expr.hh
@@ -61,6 +61,9 @@
#include "params/TimingExprUn.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
/** These classes are just the C++ counterparts for those in Expr.py and
* are, therefore, documented there */
@@ -211,4 +214,6 @@
uint64_t eval(TimingExprEvalContext &context);
};
+} // namespace gem5
+
#endif
diff --git a/src/cpu/trace/TraceCPU.py b/src/cpu/trace/TraceCPU.py
index 37f1cf6..7134968 100644
--- a/src/cpu/trace/TraceCPU.py
+++ b/src/cpu/trace/TraceCPU.py
@@ -42,6 +42,7 @@
"""
type = 'TraceCPU'
cxx_header = "cpu/trace/trace_cpu.hh"
+ cxx_class = 'gem5::TraceCPU'
@classmethod
def memory_mode(cls):
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index 32f021c..d62e856 100644
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -40,6 +40,9 @@
#include "base/compiler.hh"
#include "sim/sim_exit.hh"
+namespace gem5
+{
+
// Declare and initialize the static counter for number of trace CPUs.
int TraceCPU::numTraceCPUs = 0;
@@ -1413,3 +1416,5 @@
// We have reached the end of the file
return false;
}
+
+} // namespace gem5
diff --git a/src/cpu/trace/trace_cpu.hh b/src/cpu/trace/trace_cpu.hh
index 4301a66..9d3ae52 100644
--- a/src/cpu/trace/trace_cpu.hh
+++ b/src/cpu/trace/trace_cpu.hh
@@ -54,6 +54,9 @@
#include "proto/protoio.hh"
#include "sim/sim_events.hh"
+namespace gem5
+{
+
/**
* The trace cpu replays traces generated using the elastic trace probe
* attached to the O3 CPU model. The elastic trace is an execution trace with
@@ -1123,4 +1126,7 @@
Port &getDataPort() { return dcachePort; }
};
+
+} // namespace gem5
+
#endif // __CPU_TRACE_TRACE_CPU_HH__
diff --git a/src/cpu/translation.hh b/src/cpu/translation.hh
index 097951a..5e3c8fc 100644
--- a/src/cpu/translation.hh
+++ b/src/cpu/translation.hh
@@ -45,6 +45,9 @@
#include "arch/generic/tlb.hh"
#include "sim/faults.hh"
+namespace gem5
+{
+
/**
* This class captures the state of an address translation. A translation
* can be split in two if the ISA supports it and the memory access crosses
@@ -268,4 +271,6 @@
}
};
+} // namespace gem5
+
#endif // __CPU_TRANSLATION_HH__
diff --git a/src/cpu/utils.hh b/src/cpu/utils.hh
index fe49937..2ca2508 100644
--- a/src/cpu/utils.hh
+++ b/src/cpu/utils.hh
@@ -40,6 +40,9 @@
#include "base/types.hh"
+namespace gem5
+{
+
/**
* Calculates the offset of a given address wrt aligned fixed-size blocks.
* @param addr Input address.
@@ -91,4 +94,6 @@
return (it_tmp != it_end);
}
+} // namespace gem5
+
#endif // __CPU_UTILS_HH__
diff --git a/src/dev/BadDevice.py b/src/dev/BadDevice.py
index d7aa907..75509b7 100644
--- a/src/dev/BadDevice.py
+++ b/src/dev/BadDevice.py
@@ -30,4 +30,6 @@
class BadDevice(BasicPioDevice):
type = 'BadDevice'
cxx_header = "dev/baddev.hh"
+ cxx_class = 'gem5::BadDevice'
+
devicename = Param.String("Name of device to error on")
diff --git a/src/dev/Device.py b/src/dev/Device.py
index 46e992c..ef3b7e1 100644
--- a/src/dev/Device.py
+++ b/src/dev/Device.py
@@ -45,7 +45,9 @@
class PioDevice(ClockedObject):
type = 'PioDevice'
cxx_header = "dev/io_device.hh"
+ cxx_class = 'gem5::PioDevice'
abstract = True
+
pio = ResponsePort("Programmed I/O port")
system = Param.System(Parent.any, "System this device is part of")
@@ -71,14 +73,18 @@
class BasicPioDevice(PioDevice):
type = 'BasicPioDevice'
cxx_header = "dev/io_device.hh"
+ cxx_class = 'gem5::BasicPioDevice'
abstract = True
+
pio_addr = Param.Addr("Device Address")
pio_latency = Param.Latency('100ns', "Programmed IO latency")
class DmaDevice(PioDevice):
type = 'DmaDevice'
cxx_header = "dev/dma_device.hh"
+ cxx_class = 'gem5::DmaDevice'
abstract = True
+
dma = RequestPort("DMA port")
_iommu = None
@@ -105,6 +111,8 @@
class IsaFake(BasicPioDevice):
type = 'IsaFake'
cxx_header = "dev/isa_fake.hh"
+ cxx_class = 'gem5::IsaFake'
+
pio_size = Param.Addr(0x8, "Size of address range")
ret_data8 = Param.UInt8(0xFF, "Default data to return")
ret_data16 = Param.UInt16(0xFFFF, "Default data to return")
diff --git a/src/dev/Platform.py b/src/dev/Platform.py
index fdc661e..4f28db3 100644
--- a/src/dev/Platform.py
+++ b/src/dev/Platform.py
@@ -32,6 +32,8 @@
type = 'Platform'
abstract = True
cxx_header = "dev/platform.hh"
+ cxx_class = 'gem5::Platform'
+
system = Param.System(Parent.any, "system")
# for platforms using device trees to set properties of CPU nodes
diff --git a/src/dev/amdgpu/AMDGPU.py b/src/dev/amdgpu/AMDGPU.py
index 092a380..f72f512 100644
--- a/src/dev/amdgpu/AMDGPU.py
+++ b/src/dev/amdgpu/AMDGPU.py
@@ -43,6 +43,7 @@
class AMDGPUDevice(PciDevice):
type = 'AMDGPUDevice'
cxx_header = "dev/amdgpu/amdgpu_device.hh"
+ cxx_class = 'gem5::AMDGPUDevice'
# IDs for AMD Vega 10
VendorID = 0x1002
diff --git a/src/dev/amdgpu/amdgpu_device.cc b/src/dev/amdgpu/amdgpu_device.cc
index 23d22bb..92cd278 100644
--- a/src/dev/amdgpu/amdgpu_device.cc
+++ b/src/dev/amdgpu/amdgpu_device.cc
@@ -42,6 +42,9 @@
#include "sim/byteswap.hh"
#include "sim/sim_exit.hh"
+namespace gem5
+{
+
AMDGPUDevice::AMDGPUDevice(const AMDGPUDeviceParams &p)
: PciDevice(p), checkpoint_before_mmios(p.checkpoint_before_mmios),
init_interrupt_count(0)
@@ -274,3 +277,5 @@
// Unserialize the PciDevice base class
PciDevice::unserialize(cp);
}
+
+} // namespace gem5
diff --git a/src/dev/amdgpu/amdgpu_device.hh b/src/dev/amdgpu/amdgpu_device.hh
index 87ada0b..6915d3d 100644
--- a/src/dev/amdgpu/amdgpu_device.hh
+++ b/src/dev/amdgpu/amdgpu_device.hh
@@ -42,6 +42,9 @@
#include "dev/pci/device.hh"
#include "params/AMDGPUDevice.hh"
+namespace gem5
+{
+
/* Names of BARs used by the device. */
constexpr int FRAMEBUFFER_BAR = 0;
constexpr int DOORBELL_BAR = 2;
@@ -128,4 +131,6 @@
void unserialize(CheckpointIn &cp) override;
};
+} // namespace gem5
+
#endif // __DEV_AMDGPU_AMDGPU_DEVICE_HH__
diff --git a/src/dev/amdgpu/mmio_reader.cc b/src/dev/amdgpu/mmio_reader.cc
index 07e0233..ddb860f 100644
--- a/src/dev/amdgpu/mmio_reader.cc
+++ b/src/dev/amdgpu/mmio_reader.cc
@@ -39,6 +39,8 @@
#include "debug/AMDGPUDevice.hh"
#include "mem/packet_access.hh"
+namespace gem5
+{
void
AMDMMIOReader::readMMIOTrace(std::string trace_file)
@@ -113,3 +115,5 @@
trace_cur_index++;
}
}
+
+} // namespace gem5
diff --git a/src/dev/amdgpu/mmio_reader.hh b/src/dev/amdgpu/mmio_reader.hh
index 544e3c0..6c88f0b 100644
--- a/src/dev/amdgpu/mmio_reader.hh
+++ b/src/dev/amdgpu/mmio_reader.hh
@@ -44,6 +44,9 @@
#include "base/logging.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
/**
* Helper class to read Linux kernel MMIO trace from amdgpu modprobes. This
* class is used rather than implementing MMIOs in code as it is easier to
@@ -246,4 +249,6 @@
void writeFromTrace(PacketPtr pkt, int barnum, Addr offset);
};
-#endif /* __DEV_AMDGPU_MMIO_READER_HH__ */
+} // namespace gem5
+
+#endif // __DEV_AMDGPU_MMIO_READER_HH__
diff --git a/src/dev/arm/AbstractNVM.py b/src/dev/arm/AbstractNVM.py
index 147af01..7cfcc3e 100644
--- a/src/dev/arm/AbstractNVM.py
+++ b/src/dev/arm/AbstractNVM.py
@@ -41,3 +41,4 @@
type = 'AbstractNVM'
abstract = True
cxx_header = "dev/arm/abstract_nvm.hh"
+ cxx_class = 'gem5::AbstractNVM'
diff --git a/src/dev/arm/Display.py b/src/dev/arm/Display.py
index 2606966..035d971 100644
--- a/src/dev/arm/Display.py
+++ b/src/dev/arm/Display.py
@@ -40,6 +40,7 @@
class Display(SimObject):
type = 'Display'
cxx_header = "dev/arm/display.hh"
+ cxx_class = 'gem5::Display'
clock_frequency = Param.Unsigned("clock-frequency property")
hactive = Param.Unsigned("hactive property")
vactive = Param.Unsigned("vactive property")
diff --git a/src/dev/arm/Doorbell.py b/src/dev/arm/Doorbell.py
index 9a8e690..9120452 100644
--- a/src/dev/arm/Doorbell.py
+++ b/src/dev/arm/Doorbell.py
@@ -40,5 +40,6 @@
type = 'Doorbell'
abstract = True
cxx_header = "dev/arm/doorbell.hh"
+ cxx_class = 'gem5::Doorbell'
set_address = Param.Addr("Doorbell set address")
clear_address = Param.Addr("Doorbell clear address")
diff --git a/src/dev/arm/EnergyCtrl.py b/src/dev/arm/EnergyCtrl.py
index 9e30771..2dcef4f 100644
--- a/src/dev/arm/EnergyCtrl.py
+++ b/src/dev/arm/EnergyCtrl.py
@@ -42,6 +42,7 @@
class EnergyCtrl(BasicPioDevice):
type = 'EnergyCtrl'
cxx_header = "dev/arm/energy_ctrl.hh"
+ cxx_class = 'gem5::EnergyCtrl'
dvfs_handler = Param.DVFSHandler(Parent.dvfs_handler, "DVFS handler")
def generateDeviceTree(self, state):
diff --git a/src/dev/arm/FlashDevice.py b/src/dev/arm/FlashDevice.py
index 6455bbf..cf06bda 100644
--- a/src/dev/arm/FlashDevice.py
+++ b/src/dev/arm/FlashDevice.py
@@ -47,6 +47,7 @@
class FlashDevice(AbstractNVM):
type = 'FlashDevice'
cxx_header = "dev/arm/flash_device.hh"
+ cxx_class = 'gem5::FlashDevice'
# default blocksize is 128 KiB.This seems to be the most common size in
# mobile devices (not the image blocksize)
blk_size = Param.MemorySize("128KiB", "Size of one disk block")
diff --git a/src/dev/arm/GenericTimer.py b/src/dev/arm/GenericTimer.py
index db93532..da686c1 100644
--- a/src/dev/arm/GenericTimer.py
+++ b/src/dev/arm/GenericTimer.py
@@ -52,6 +52,7 @@
type = 'SystemCounter'
cxx_header = "dev/arm/generic_timer.hh"
+ cxx_class = 'gem5::SystemCounter'
# Maximum of 1004 frequency entries, including end marker
freqs = VectorParam.UInt32([0x01800000], "Frequencies available for the "
@@ -77,6 +78,7 @@
type = 'GenericTimer'
cxx_header = "dev/arm/generic_timer.hh"
+ cxx_class = 'gem5::GenericTimer'
_freq_in_dtb = False
@@ -129,6 +131,7 @@
type = 'GenericTimerFrame'
cxx_header = "dev/arm/generic_timer.hh"
+ cxx_class = 'gem5::GenericTimerFrame'
_frame_num = 0
@@ -173,6 +176,7 @@
type = 'GenericTimerMem'
cxx_header = "dev/arm/generic_timer.hh"
+ cxx_class = 'gem5::GenericTimerMem'
_freq_in_dtb = False
diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py
index 8531aaa..953ccb4 100644
--- a/src/dev/arm/Gic.py
+++ b/src/dev/arm/Gic.py
@@ -46,6 +46,7 @@
type = 'BaseGic'
abstract = True
cxx_header = "dev/arm/base_gic.hh"
+ cxx_class = 'gem5::BaseGic'
# Used for DTB autogeneration
_state = FdtState(addr_cells=0, interrupt_cells=3)
@@ -96,7 +97,7 @@
class ArmInterruptPin(SimObject):
type = 'ArmInterruptPin'
cxx_header = "dev/arm/base_gic.hh"
- cxx_class = "ArmInterruptPinGen"
+ cxx_class = "gem5::ArmInterruptPinGen"
abstract = True
platform = Param.Platform(Parent.any, "Platform with interrupt controller")
@@ -107,7 +108,7 @@
class ArmSPI(ArmInterruptPin):
type = 'ArmSPI'
cxx_header = "dev/arm/base_gic.hh"
- cxx_class = "ArmSPIGen"
+ cxx_class = "gem5::ArmSPIGen"
_LINUX_ID = 0
@@ -124,7 +125,7 @@
class ArmPPI(ArmInterruptPin):
type = 'ArmPPI'
cxx_header = "dev/arm/base_gic.hh"
- cxx_class = "ArmPPIGen"
+ cxx_class = "gem5::ArmPPIGen"
_LINUX_ID = 1
@@ -141,13 +142,14 @@
class ArmSigInterruptPin(ArmInterruptPin):
type = 'ArmSigInterruptPin'
cxx_header = "dev/arm/base_gic.hh"
- cxx_class = "ArmSigInterruptPinGen"
+ cxx_class = "gem5::ArmSigInterruptPinGen"
irq = IntSourcePin('Interrupt pin')
class GicV2(BaseGic):
type = 'GicV2'
cxx_header = "dev/arm/gic_v2.hh"
+ cxx_class = 'gem5::GicV2'
dist_addr = Param.Addr("Address for distributor")
cpu_addr = Param.Addr("Address for cpu")
@@ -174,6 +176,7 @@
class Gicv2mFrame(SimObject):
type = 'Gicv2mFrame'
cxx_header = "dev/arm/gic_v2m.hh"
+ cxx_class = 'gem5::Gicv2mFrame'
spi_base = Param.UInt32(0x0, "Frame SPI base number");
spi_len = Param.UInt32(0x0, "Frame SPI total number");
addr = Param.Addr("Address for frame PIO")
@@ -181,6 +184,7 @@
class Gicv2m(PioDevice):
type = 'Gicv2m'
cxx_header = "dev/arm/gic_v2m.hh"
+ cxx_class = 'gem5::Gicv2m'
pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
gic = Param.BaseGic(Parent.any, "Gic on which to trigger interrupts")
@@ -189,6 +193,7 @@
class VGic(PioDevice):
type = 'VGic'
cxx_header = "dev/arm/vgic.hh"
+ cxx_class = 'gem5::VGic'
gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
platform = Param.Platform(Parent.any, "Platform this device is part of.")
vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
@@ -232,6 +237,7 @@
class Gicv3Its(BasicPioDevice):
type = 'Gicv3Its'
cxx_header = "dev/arm/gic_v3_its.hh"
+ cxx_class = 'gem5::Gicv3Its'
dma = RequestPort("DMA port")
pio_size = Param.Unsigned(0x20000, "Gicv3Its pio size")
@@ -253,6 +259,7 @@
class Gicv3(BaseGic):
type = 'Gicv3'
cxx_header = "dev/arm/gic_v3.hh"
+ cxx_class = 'gem5::Gicv3'
# Used for DTB autogeneration
_state = FdtState(addr_cells=2, size_cells=2, interrupt_cells=3)
diff --git a/src/dev/arm/NoMali.py b/src/dev/arm/NoMali.py
index 4141ac0..6a933d6 100644
--- a/src/dev/arm/NoMali.py
+++ b/src/dev/arm/NoMali.py
@@ -47,6 +47,7 @@
class NoMaliGpu(PioDevice):
type = 'NoMaliGpu'
cxx_header = "dev/arm/gpu_nomali.hh"
+ cxx_class = 'gem5::NoMaliGpu'
pio_addr = Param.Addr("Device base address")
@@ -69,6 +70,7 @@
type = 'CustomNoMaliGpu'
cxx_header = "dev/arm/gpu_nomali.hh"
+ cxx_class = 'gem5::CustomNoMaliGpu'
gpu_id = Param.UInt32("")
l2_features = Param.UInt32("")
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 1bc050f..919ff63 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -84,12 +84,14 @@
type = 'AmbaPioDevice'
abstract = True
cxx_header = "dev/arm/amba_device.hh"
+ cxx_class = 'gem5::AmbaPioDevice'
amba_id = Param.UInt32("ID of AMBA device for kernel detection")
class AmbaIntDevice(AmbaPioDevice):
type = 'AmbaIntDevice'
abstract = True
cxx_header = "dev/arm/amba_device.hh"
+ cxx_class = 'gem5::AmbaIntDevice'
interrupt = Param.ArmInterruptPin("Interrupt that connects to GIC")
int_delay = Param.Latency("100ns",
"Time between action and interrupt generation by device")
@@ -98,6 +100,7 @@
type = 'AmbaDmaDevice'
abstract = True
cxx_header = "dev/arm/amba_device.hh"
+ cxx_class = 'gem5::AmbaDmaDevice'
pio_addr = Param.Addr("Address for AMBA responder interface")
pio_latency = Param.Latency("10ns", "Time between action and write/read"
"result by AMBA DMA Device")
@@ -107,6 +110,7 @@
class A9SCU(BasicPioDevice):
type = 'A9SCU'
cxx_header = "dev/arm/a9scu.hh"
+ cxx_class = 'gem5::A9SCU'
class ArmPciIntRouting(Enum): vals = [
'ARM_PCI_INT_STATIC',
@@ -117,6 +121,7 @@
class GenericArmPciHost(GenericPciHost):
type = 'GenericArmPciHost'
cxx_header = "dev/arm/pci_host.hh"
+ cxx_class = 'gem5::GenericArmPciHost'
int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy")
int_base = Param.Unsigned("PCI interrupt base")
@@ -208,6 +213,7 @@
class RealViewCtrl(BasicPioDevice):
type = 'RealViewCtrl'
cxx_header = "dev/arm/rv_ctrl.hh"
+ cxx_class = 'gem5::RealViewCtrl'
proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
@@ -227,6 +233,7 @@
class RealViewOsc(ClockDomain):
type = 'RealViewOsc'
cxx_header = "dev/arm/rv_ctrl.hh"
+ cxx_class = 'gem5::RealViewOsc'
parent = Param.RealViewCtrl(Parent.any, "RealView controller")
@@ -275,6 +282,7 @@
class RealViewTemperatureSensor(SimObject):
type = 'RealViewTemperatureSensor'
cxx_header = "dev/arm/rv_ctrl.hh"
+ cxx_class = 'gem5::RealViewTemperatureSensor'
parent = Param.RealViewCtrl(Parent.any, "RealView controller")
@@ -362,7 +370,9 @@
class AmbaFake(AmbaPioDevice):
type = 'AmbaFake'
cxx_header = "dev/arm/amba_fake.hh"
- ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
+ cxx_class = 'gem5::AmbaFake'
+ ignore_access = Param.Bool(False,
+ "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
amba_id = 0;
# Simple fixed-rate clock source. Intended to be instantiated in Platform
@@ -388,9 +398,12 @@
class Pl011(Uart):
type = 'Pl011'
cxx_header = "dev/arm/pl011.hh"
+ cxx_class = 'gem5::Pl011'
interrupt = Param.ArmInterruptPin("Interrupt that connects to GIC")
- end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
- int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
+ end_on_eot = Param.Bool(False,
+ "End the simulation when a EOT is received on the UART")
+ int_delay = Param.Latency("100ns",
+ "Time between action and interrupt generation by UART")
def generateDeviceTree(self, state):
node = self.generateBasicPioDeviceNode(state, 'uart', self.pio_addr,
@@ -409,6 +422,7 @@
class Sp804(AmbaPioDevice):
type = 'Sp804'
cxx_header = "dev/arm/timer_sp804.hh"
+ cxx_class = 'gem5::Sp804'
int0 = Param.ArmSPI("Interrupt that connects to GIC")
clock0 = Param.Clock('1MHz', "Clock speed of the input")
int1 = Param.ArmSPI("Interrupt that connects to GIC")
@@ -425,6 +439,7 @@
type = 'Sp805'
cxx_header = 'dev/arm/watchdog_sp805.hh'
+ cxx_class = 'gem5::Sp805'
amba_id = 0x00141805
@@ -446,6 +461,7 @@
class GenericWatchdog(PioDevice):
type = 'GenericWatchdog'
cxx_header = 'dev/arm/watchdog_generic.hh'
+ cxx_class = 'gem5::GenericWatchdog'
refresh_start = Param.Addr("Start address for the refresh frame")
control_start = Param.Addr("Start address for the control frame")
@@ -461,13 +477,16 @@
class CpuLocalTimer(BasicPioDevice):
type = 'CpuLocalTimer'
cxx_header = "dev/arm/timer_cpulocal.hh"
+ cxx_class = 'gem5::CpuLocalTimer'
int_timer = Param.ArmPPI("Interrrupt used per-cpu to GIC")
int_watchdog = Param.ArmPPI("Interrupt for per-cpu watchdog to GIC")
class PL031(AmbaIntDevice):
type = 'PL031'
cxx_header = "dev/arm/rtc_pl031.hh"
- time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)")
+ cxx_class = 'gem5::PL031'
+ time = Param.Time('01/01/2009',
+ "System time to use ('Now' for actual time)")
amba_id = 0x00041031
def generateDeviceTree(self, state):
@@ -484,6 +503,7 @@
class Pl050(AmbaIntDevice):
type = 'Pl050'
cxx_header = "dev/arm/kmi.hh"
+ cxx_class = 'gem5::Pl050'
amba_id = 0x00141050
ps2 = Param.PS2Device("PS/2 device")
@@ -501,14 +521,18 @@
class Pl111(AmbaDmaDevice):
type = 'Pl111'
cxx_header = "dev/arm/pl111.hh"
+ cxx_class = 'gem5::Pl111'
pixel_clock = Param.Clock('24MHz', "Pixel clock")
- vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
+ vnc = Param.VncInput(Parent.any,
+ "Vnc server for remote frame buffer display")
amba_id = 0x00141111
- enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp")
+ enable_capture = Param.Bool(True,
+ "capture frame to system.framebuffer.bmp")
class HDLcd(AmbaDmaDevice):
type = 'HDLcd'
cxx_header = "dev/arm/hdlcd.hh"
+ cxx_class = 'gem5::HDLcd'
vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer "
"display")
amba_id = 0x00141000
@@ -630,6 +654,7 @@
type = 'FVPBasePwrCtrl'
cxx_header = 'dev/arm/fvp_base_pwr_ctrl.hh'
+ cxx_class = 'gem5::FVPBasePwrCtrl'
class GenericMHU(MHU):
lowp_scp2ap = Scp2ApDoorbell(
@@ -651,6 +676,7 @@
class RealView(Platform):
type = 'RealView'
cxx_header = "dev/arm/realview.hh"
+ cxx_class = 'gem5::RealView'
_mem_regions = [ AddrRange(0, size='256MiB') ]
_num_pci_dev = 0
diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py
index 85c10ad..f14d985 100644
--- a/src/dev/arm/SMMUv3.py
+++ b/src/dev/arm/SMMUv3.py
@@ -42,6 +42,7 @@
class SMMUv3DeviceInterface(ClockedObject):
type = 'SMMUv3DeviceInterface'
cxx_header = 'dev/arm/smmu_v3_deviceifc.hh'
+ cxx_class = 'gem5::SMMUv3DeviceInterface'
device_port = ResponsePort('Device port')
slave = DeprecatedParam(device_port,
@@ -81,6 +82,7 @@
class SMMUv3(ClockedObject):
type = 'SMMUv3'
cxx_header = 'dev/arm/smmu_v3.hh'
+ cxx_class = 'gem5::SMMUv3'
request = RequestPort('Request port')
walker = RequestPort(
diff --git a/src/dev/arm/UFSHostDevice.py b/src/dev/arm/UFSHostDevice.py
index 879503a..bae7124 100644
--- a/src/dev/arm/UFSHostDevice.py
+++ b/src/dev/arm/UFSHostDevice.py
@@ -42,6 +42,7 @@
class UFSHostDevice(DmaDevice):
type = 'UFSHostDevice'
cxx_header = "dev/arm/ufs_device.hh"
+ cxx_class = 'gem5::UFSHostDevice'
pio_addr = Param.Addr("Address for SCSI configuration responder interface")
pio_latency = Param.Latency("10ns", "Time between action and write/read \
result by AMBA DMA Device")
diff --git a/src/dev/arm/VirtIOMMIO.py b/src/dev/arm/VirtIOMMIO.py
index 60aee16..2661db2 100644
--- a/src/dev/arm/VirtIOMMIO.py
+++ b/src/dev/arm/VirtIOMMIO.py
@@ -46,6 +46,7 @@
class MmioVirtIO(BasicPioDevice):
type = 'MmioVirtIO'
cxx_header = 'dev/arm/vio_mmio.hh'
+ cxx_class = 'gem5::MmioVirtIO'
pio_size = Param.Addr(4096, "IO range")
interrupt = Param.ArmInterruptPin("Interrupt to use for this device")
diff --git a/src/dev/arm/a9scu.cc b/src/dev/arm/a9scu.cc
index 2bc713e..e9e2230 100644
--- a/src/dev/arm/a9scu.cc
+++ b/src/dev/arm/a9scu.cc
@@ -43,6 +43,9 @@
#include "mem/packet_access.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
A9SCU::A9SCU(const Params &p)
: BasicPioDevice(p, 0x60)
{
@@ -103,3 +106,5 @@
pkt->makeAtomicResponse();
return pioDelay;
}
+
+} // namespace gem5
diff --git a/src/dev/arm/a9scu.hh b/src/dev/arm/a9scu.hh
index c91b7d2..4f0ecef 100644
--- a/src/dev/arm/a9scu.hh
+++ b/src/dev/arm/a9scu.hh
@@ -45,6 +45,9 @@
* This defines the snoop control unit register on an A9
*/
+namespace gem5
+{
+
class A9SCU : public BasicPioDevice
{
protected:
@@ -78,6 +81,7 @@
virtual Tick write(PacketPtr pkt);
};
+} // namespace gem5
#endif // __DEV_ARM_A9SCU_HH__
diff --git a/src/dev/arm/abstract_nvm.hh b/src/dev/arm/abstract_nvm.hh
index 659fbd4..21bff35 100644
--- a/src/dev/arm/abstract_nvm.hh
+++ b/src/dev/arm/abstract_nvm.hh
@@ -42,6 +42,9 @@
#include "params/AbstractNVM.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
/**
* This is an interface between the disk interface (which will handle the disk
* data transactions) and the timing model. The timing model only takes care
@@ -104,4 +107,6 @@
const std::function<void()> &event) = 0;
};
+} // namespace gem5
+
#endif //__DEV_ARM_ABSTRACT_NVM_HH__
diff --git a/src/dev/arm/amba.hh b/src/dev/arm/amba.hh
index cfc3f56..6a2c4c2 100644
--- a/src/dev/arm/amba.hh
+++ b/src/dev/arm/amba.hh
@@ -40,6 +40,9 @@
#include "mem/packet.hh"
+namespace gem5
+{
+
namespace AMBA
{
@@ -52,5 +55,6 @@
}
} // namespace AMBA
+} // namespace gem5
#endif // __DEV_ARM_AMBA_HH__
diff --git a/src/dev/arm/amba_device.cc b/src/dev/arm/amba_device.cc
index edf54b8..502851a 100644
--- a/src/dev/arm/amba_device.cc
+++ b/src/dev/arm/amba_device.cc
@@ -46,6 +46,9 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+namespace gem5
+{
+
const uint64_t AmbaVendor = 0xb105f00d00000000ULL;
AmbaPioDevice::AmbaPioDevice(const Params &p, Addr pio_size)
@@ -84,3 +87,5 @@
pkt->setUintX((amba_id >> byte) & 0xFF, ByteOrder::little);
return true;
}
+
+} // namespace gem5
diff --git a/src/dev/arm/amba_device.hh b/src/dev/arm/amba_device.hh
index c1c46cf..e1924db 100644
--- a/src/dev/arm/amba_device.hh
+++ b/src/dev/arm/amba_device.hh
@@ -56,6 +56,8 @@
#include "params/AmbaDmaDevice.hh"
#include "params/AmbaIntDevice.hh"
+namespace gem5
+{
class AmbaDevice
{
@@ -108,5 +110,6 @@
AmbaDmaDevice(const Params &p, Addr pio_size = 0);
};
+} // namespace gem5
#endif //__DEV_ARM_AMBA_DEVICE_HH__
diff --git a/src/dev/arm/amba_fake.cc b/src/dev/arm/amba_fake.cc
index 0048c8a..06bd203 100644
--- a/src/dev/arm/amba_fake.cc
+++ b/src/dev/arm/amba_fake.cc
@@ -45,6 +45,9 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+namespace gem5
+{
+
AmbaFake::AmbaFake(const Params &p)
: AmbaPioDevice(p, 0x1000)
{
@@ -81,3 +84,5 @@
pkt->makeAtomicResponse();
return pioDelay;
}
+
+} // namespace gem5
diff --git a/src/dev/arm/amba_fake.hh b/src/dev/arm/amba_fake.hh
index 3944ec6..4598cf8 100644
--- a/src/dev/arm/amba_fake.hh
+++ b/src/dev/arm/amba_fake.hh
@@ -52,6 +52,9 @@
#include "dev/arm/amba_device.hh"
#include "params/AmbaFake.hh"
+namespace gem5
+{
+
class AmbaFake : public AmbaPioDevice
{
public:
@@ -63,4 +66,6 @@
};
+} // namespace gem5
+
#endif //__DEV_ARM_AMBA_FAKE_H__
diff --git a/src/dev/arm/base_gic.cc b/src/dev/arm/base_gic.cc
index 27bf266..4685ce4 100644
--- a/src/dev/arm/base_gic.cc
+++ b/src/dev/arm/base_gic.cc
@@ -45,6 +45,9 @@
#include "params/ArmSPI.hh"
#include "params/BaseGic.hh"
+namespace gem5
+{
+
BaseGic::BaseGic(const Params &p)
: PioDevice(p),
platform(p.platform)
@@ -243,3 +246,5 @@
if (pin)
pin->lower();
}
+
+} // namespace gem5
diff --git a/src/dev/arm/base_gic.hh b/src/dev/arm/base_gic.hh
index d6d856e..72fe9f4 100644
--- a/src/dev/arm/base_gic.hh
+++ b/src/dev/arm/base_gic.hh
@@ -52,6 +52,9 @@
#include "enums/ArmInterruptType.hh"
+namespace gem5
+{
+
class Platform;
class RealView;
class ThreadContext;
@@ -288,4 +291,6 @@
void clear() override;
};
-#endif
+} // namespace gem5
+
+#endif // __DEV_ARM_BASE_GIC_H__
diff --git a/src/dev/arm/css/MHU.py b/src/dev/arm/css/MHU.py
index f5bb7e5..1791739 100644
--- a/src/dev/arm/css/MHU.py
+++ b/src/dev/arm/css/MHU.py
@@ -43,21 +43,25 @@
type = 'MhuDoorbell'
abstract = True
cxx_header = "dev/arm/css/mhu.hh"
+ cxx_class = 'gem5::MhuDoorbell'
class Scp2ApDoorbell(MhuDoorbell):
type = 'Scp2ApDoorbell'
cxx_header = "dev/arm/css/mhu.hh"
+ cxx_class = 'gem5::Scp2ApDoorbell'
interrupt = Param.ArmInterruptPin("Interrupt Pin")
class Ap2ScpDoorbell(MhuDoorbell):
type = 'Ap2ScpDoorbell'
cxx_header = "dev/arm/css/mhu.hh"
+ cxx_class = 'gem5::Ap2ScpDoorbell'
# Message Handling Unit
class MHU(BasicPioDevice):
type = 'MHU'
cxx_header = "dev/arm/css/mhu.hh"
+ cxx_class = 'gem5::MHU'
pio_size = Param.Unsigned(0x1000, "MHU pio size")
lowp_scp2ap = Param.Scp2ApDoorbell(
diff --git a/src/dev/arm/css/Scmi.py b/src/dev/arm/css/Scmi.py
index b5759cf..0e14cf5 100644
--- a/src/dev/arm/css/Scmi.py
+++ b/src/dev/arm/css/Scmi.py
@@ -46,7 +46,7 @@
"""
type = 'ScmiChannel'
cxx_header = "dev/arm/css/scmi_platform.hh"
- cxx_class = "scmi::VirtualChannel"
+ cxx_class = "gem5::scmi::VirtualChannel"
shmem_range = Param.AddrRange(
"Virtual channel's shared memory address range")
phys_id = Param.Unsigned(4,
@@ -78,7 +78,7 @@
"""
type = 'ScmiAgentChannel'
cxx_header = "dev/arm/css/scmi_platform.hh"
- cxx_class = "scmi::AgentChannel"
+ cxx_class = "gem5::scmi::AgentChannel"
class ScmiPlatformChannel(ScmiChannel):
@@ -87,7 +87,7 @@
"""
type = 'ScmiPlatformChannel'
cxx_header = "dev/arm/css/scmi_platform.hh"
- cxx_class = "scmi::PlatformChannel"
+ cxx_class = "gem5::scmi::PlatformChannel"
class ScmiCommunication(SimObject):
"""
@@ -98,7 +98,7 @@
"""
type = 'ScmiCommunication'
cxx_header = "dev/arm/css/scmi_platform.hh"
- cxx_class = "scmi::Communication"
+ cxx_class = "gem5::scmi::Communication"
agent_channel = Param.ScmiAgentChannel(
"Agent to Platform channel")
@@ -108,7 +108,7 @@
class ScmiPlatform(Scp):
type = 'ScmiPlatform'
cxx_header = "dev/arm/css/scmi_platform.hh"
- cxx_class = "scmi::Platform"
+ cxx_class = "gem5::scmi::Platform"
comms = VectorParam.ScmiCommunication([],
"SCMI Communications")
diff --git a/src/dev/arm/css/Scp.py b/src/dev/arm/css/Scp.py
index 3e42e27..c834811 100644
--- a/src/dev/arm/css/Scp.py
+++ b/src/dev/arm/css/Scp.py
@@ -40,3 +40,4 @@
type = 'Scp'
abstract = True
cxx_header = "dev/arm/css/scp.hh"
+ cxx_class = 'gem5::Scp'
diff --git a/src/dev/arm/css/mhu.cc b/src/dev/arm/css/mhu.cc
index 2bf42ea..b1be3f5 100644
--- a/src/dev/arm/css/mhu.cc
+++ b/src/dev/arm/css/mhu.cc
@@ -45,6 +45,9 @@
#include "params/MHU.hh"
#include "params/Scp2ApDoorbell.hh"
+namespace gem5
+{
+
Scp2ApDoorbell::Scp2ApDoorbell(const Scp2ApDoorbellParams &p)
: MhuDoorbell(p), interrupt(p.interrupt->get())
{}
@@ -239,3 +242,5 @@
{
scp->clearInterrupt(this);
}
+
+} // namespace gem5
diff --git a/src/dev/arm/css/mhu.hh b/src/dev/arm/css/mhu.hh
index 4e13605..508cfa0 100644
--- a/src/dev/arm/css/mhu.hh
+++ b/src/dev/arm/css/mhu.hh
@@ -41,6 +41,9 @@
#include "dev/arm/doorbell.hh"
#include "dev/io_device.hh"
+namespace gem5
+{
+
struct Ap2ScpDoorbellParams;
class ArmInterruptPin;
class MHU;
@@ -166,4 +169,6 @@
uint32_t scfg;
};
+} // namespace gem5
+
#endif // __DEV_ARM_CSS_MHU_H__
diff --git a/src/dev/arm/css/scmi_platform.cc b/src/dev/arm/css/scmi_platform.cc
index d9a42da..123fb6c 100644
--- a/src/dev/arm/css/scmi_platform.cc
+++ b/src/dev/arm/css/scmi_platform.cc
@@ -43,6 +43,9 @@
#include "dev/arm/doorbell.hh"
#include "mem/packet_access.hh"
+namespace gem5
+{
+
using namespace scmi;
AgentChannel::AgentChannel(const ScmiChannelParams &p)
@@ -303,3 +306,5 @@
return nullptr;
}
+
+} // namespace gem5
diff --git a/src/dev/arm/css/scmi_platform.hh b/src/dev/arm/css/scmi_platform.hh
index e56f024..ad53b83 100644
--- a/src/dev/arm/css/scmi_platform.hh
+++ b/src/dev/arm/css/scmi_platform.hh
@@ -43,6 +43,9 @@
#include "dev/dma_device.hh"
#include "params/ScmiPlatform.hh"
+namespace gem5
+{
+
class Doorbell;
GEM5_DEPRECATED_NAMESPACE(SCMI, scmi);
@@ -327,5 +330,6 @@
};
} // namespace scmi
+} // namespace gem5
#endif // __DEV_ARM_CSS_SCMI_PLATFORM_H__
diff --git a/src/dev/arm/css/scmi_protocols.cc b/src/dev/arm/css/scmi_protocols.cc
index 61b3174..432a761 100644
--- a/src/dev/arm/css/scmi_protocols.cc
+++ b/src/dev/arm/css/scmi_protocols.cc
@@ -40,6 +40,9 @@
#include "debug/SCMI.hh"
#include "dev/arm/css/scmi_platform.hh"
+namespace gem5
+{
+
using namespace scmi;
const std::string
@@ -280,3 +283,5 @@
payload.status = NOT_FOUND;
msg.length = sizeof(uint32_t) * 2;
}
+
+} // namespace gem5
diff --git a/src/dev/arm/css/scmi_protocols.hh b/src/dev/arm/css/scmi_protocols.hh
index 28d8d6c..03d6ea4 100644
--- a/src/dev/arm/css/scmi_protocols.hh
+++ b/src/dev/arm/css/scmi_protocols.hh
@@ -43,6 +43,9 @@
#include "base/compiler.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(SCMI, scmi);
namespace scmi
{
@@ -151,6 +154,7 @@
};
-}; // namespace scmi
+} // namespace scmi
+} // namespace gem5
#endif
diff --git a/src/dev/arm/css/scp.hh b/src/dev/arm/css/scp.hh
index de8011c..d4f4478 100644
--- a/src/dev/arm/css/scp.hh
+++ b/src/dev/arm/css/scp.hh
@@ -40,6 +40,9 @@
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
class Doorbell;
class Scp : public ClockedObject
@@ -55,4 +58,6 @@
virtual void clearInterrupt(const Doorbell *doorbell) = 0;
};
+} // namespace gem5
+
#endif // __DEV_ARM_CSS_SCP_H__
diff --git a/src/dev/arm/display.cc b/src/dev/arm/display.cc
index e4b7449..ab031b1 100644
--- a/src/dev/arm/display.cc
+++ b/src/dev/arm/display.cc
@@ -39,6 +39,11 @@
#include "params/Display.hh"
+namespace gem5
+{
+
Display::Display(const DisplayParams &p)
: SimObject(p)
{}
+
+} // namespace gem5
diff --git a/src/dev/arm/display.hh b/src/dev/arm/display.hh
index 91819ff..9e601f5 100644
--- a/src/dev/arm/display.hh
+++ b/src/dev/arm/display.hh
@@ -40,6 +40,9 @@
#include "sim/sim_object.hh"
+namespace gem5
+{
+
struct DisplayParams;
class Display : public SimObject
@@ -48,4 +51,6 @@
Display(const DisplayParams &p);
};
+} // namespace gem5
+
#endif // __DEV_ARM_DISPLAY_H__
diff --git a/src/dev/arm/doorbell.hh b/src/dev/arm/doorbell.hh
index 0f786cf..03ea4cf 100644
--- a/src/dev/arm/doorbell.hh
+++ b/src/dev/arm/doorbell.hh
@@ -41,6 +41,9 @@
#include "params/Doorbell.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
/**
* Generic doorbell interface.
* A Doorbell implementation will override the set and
@@ -63,4 +66,6 @@
const Addr _clearAddress;
};
+} // namespace gem5
+
#endif // __DEV_ARM_DOORBELL_H__
diff --git a/src/dev/arm/energy_ctrl.cc b/src/dev/arm/energy_ctrl.cc
index b03a394..fa1ebee 100644
--- a/src/dev/arm/energy_ctrl.cc
+++ b/src/dev/arm/energy_ctrl.cc
@@ -45,6 +45,9 @@
#include "sim/dvfs_handler.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
EnergyCtrl::EnergyCtrl(const Params &p)
: BasicPioDevice(p, PIO_NUM_FIELDS * 4), // each field is 32 bit
dvfsHandler(p.dvfs_handler),
@@ -255,3 +258,5 @@
{
BasicPioDevice::init();
}
+
+} // namespace gem5
diff --git a/src/dev/arm/energy_ctrl.hh b/src/dev/arm/energy_ctrl.hh
index 8a15b6c..681f2c1 100644
--- a/src/dev/arm/energy_ctrl.hh
+++ b/src/dev/arm/energy_ctrl.hh
@@ -56,6 +56,9 @@
#include "dev/io_device.hh"
#include "params/EnergyCtrl.hh"
+namespace gem5
+{
+
class DVFSHandler;
class EnergyCtrl : public BasicPioDevice
@@ -181,4 +184,7 @@
EventFunctionWrapper updateAckEvent;
};
+
+} // namespace gem5
+
#endif //__DEV_ARM_ENERGY_CTRL_HH__
diff --git a/src/dev/arm/flash_device.cc b/src/dev/arm/flash_device.cc
index 5585d96..fafcde3 100644
--- a/src/dev/arm/flash_device.cc
+++ b/src/dev/arm/flash_device.cc
@@ -55,6 +55,9 @@
#include "base/trace.hh"
#include "debug/Drain.hh"
+namespace gem5
+{
+
/**
* Flash Device constructor and destructor
*/
@@ -576,3 +579,5 @@
signalDrainDone();
}
}
+
+} // namespace gem5
diff --git a/src/dev/arm/flash_device.hh b/src/dev/arm/flash_device.hh
index 3e2d676..e6baf38 100644
--- a/src/dev/arm/flash_device.hh
+++ b/src/dev/arm/flash_device.hh
@@ -46,6 +46,9 @@
#include "params/FlashDevice.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
/**
* Flash Device model
* The Flash Device model is a timing model for a NAND flash device.
@@ -198,4 +201,7 @@
/** Completion event */
EventFunctionWrapper planeEvent;
};
+
+} // namespace gem5
+
#endif //__DEV_ARM_FLASH_DEVICE_HH__
diff --git a/src/dev/arm/fvp_base_pwr_ctrl.cc b/src/dev/arm/fvp_base_pwr_ctrl.cc
index 781e475..d56b77c 100644
--- a/src/dev/arm/fvp_base_pwr_ctrl.cc
+++ b/src/dev/arm/fvp_base_pwr_ctrl.cc
@@ -47,6 +47,9 @@
#include "params/FVPBasePwrCtrl.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
FVPBasePwrCtrl::FVPBasePwrCtrl(const FVPBasePwrCtrlParams ¶ms)
: BasicPioDevice(params, 0x1000),
regs(),
@@ -310,3 +313,5 @@
ArmISA::Reset().invoke(tc);
tc->activate();
}
+
+} // namespace gem5
diff --git a/src/dev/arm/fvp_base_pwr_ctrl.hh b/src/dev/arm/fvp_base_pwr_ctrl.hh
index e6fd5c8..ee0c239 100644
--- a/src/dev/arm/fvp_base_pwr_ctrl.hh
+++ b/src/dev/arm/fvp_base_pwr_ctrl.hh
@@ -43,6 +43,9 @@
#include "base/bitunion.hh"
#include "dev/io_device.hh"
+namespace gem5
+{
+
class ArmSystem;
struct FVPBasePwrCtrlParams;
class ThreadContext;
@@ -182,4 +185,6 @@
ArmSystem &system;
};
+} // namespace gem5
+
#endif // __DEV_ARM_FVP_BASE_PWR_CTRL_HH__
diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index d5028c4..c2e5635 100644
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -52,6 +52,9 @@
#include "params/GenericTimerMem.hh"
#include "params/SystemCounter.hh"
+namespace gem5
+{
+
using namespace ArmISA;
SystemCounter::SystemCounter(const SystemCounterParams &p)
@@ -1580,3 +1583,5 @@
"(0x%x:%i), assuming WI\n", addr, size);
}
}
+
+} // namespace gem5
diff --git a/src/dev/arm/generic_timer.hh b/src/dev/arm/generic_timer.hh
index 6424549..d654c3e 100644
--- a/src/dev/arm/generic_timer.hh
+++ b/src/dev/arm/generic_timer.hh
@@ -63,6 +63,9 @@
/// G6.2 - The AArch32 view of the Generic Timer
/// I2 - System Level Implementation of the Generic Timer
+namespace gem5
+{
+
class Checkpoint;
struct SystemCounterParams;
struct GenericTimerParams;
@@ -585,4 +588,6 @@
ArmSystem &system;
};
+} // namespace gem5
+
#endif // __DEV_ARM_GENERIC_TIMER_HH__
diff --git a/src/dev/arm/generic_timer_miscregs_types.hh b/src/dev/arm/generic_timer_miscregs_types.hh
index 0c23b2a..ea42090 100644
--- a/src/dev/arm/generic_timer_miscregs_types.hh
+++ b/src/dev/arm/generic_timer_miscregs_types.hh
@@ -40,6 +40,9 @@
#include "base/bitunion.hh"
+namespace gem5
+{
+
namespace ArmISA
{
BitUnion64(CNTKCTL)
@@ -93,4 +96,6 @@
// ENDIF Armv8.1-VHE && HCR_EL2.E2H == 1
}
+} // namespace gem5
+
#endif // __DEV_ARM_GENERIC_TIMER_MISCREGS_TYPES_HH__
diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc
index a6ed295..3b72441 100644
--- a/src/dev/arm/gic_v2.cc
+++ b/src/dev/arm/gic_v2.cc
@@ -50,6 +50,9 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+namespace gem5
+{
+
const AddrRange GicV2::GICD_IGROUPR (0x080, 0x100);
const AddrRange GicV2::GICD_ISENABLER (0x100, 0x180);
const AddrRange GicV2::GICD_ICENABLER (0x180, 0x200);
@@ -1095,3 +1098,5 @@
UNSERIALIZE_ARRAY(intConfig, 2);
UNSERIALIZE_ARRAY(intPriority, SGI_MAX + PPI_MAX);
}
+
+} // namespace gem5
diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index e91d300..9e68745 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -56,6 +56,9 @@
#include "dev/platform.hh"
#include "params/GicV2.hh"
+namespace gem5
+{
+
class GicV2 : public BaseGic, public BaseGicRegisters
{
protected:
@@ -547,4 +550,6 @@
void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override;
};
+} // namespace gem5
+
#endif //__DEV_ARM_GIC_H__
diff --git a/src/dev/arm/gic_v2m.cc b/src/dev/arm/gic_v2m.cc
index 0864dbe..d625387 100644
--- a/src/dev/arm/gic_v2m.cc
+++ b/src/dev/arm/gic_v2m.cc
@@ -64,6 +64,9 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+namespace gem5
+{
+
Gicv2m::Gicv2m(const Params &p)
: PioDevice(p), pioDelay(p.pio_delay), frames(p.frames), gic(p.gic)
{
@@ -154,3 +157,5 @@
}
return -1;
}
+
+} // namespace gem5
diff --git a/src/dev/arm/gic_v2m.hh b/src/dev/arm/gic_v2m.hh
index afdd89f..6b9e8e8 100644
--- a/src/dev/arm/gic_v2m.hh
+++ b/src/dev/arm/gic_v2m.hh
@@ -51,6 +51,9 @@
#include "params/Gicv2m.hh"
#include "params/Gicv2mFrame.hh"
+namespace gem5
+{
+
/**
* Ultimately this class should be embedded in the Gicv2m class, but
* this confuses Python as 'Gicv2m::Frame' gets interpreted as 'Frame'
@@ -115,4 +118,6 @@
int frameFromAddr(Addr a) const;
};
+} // namespace gem5
+
#endif //__DEV_ARM_GIC_V2M_H__
diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc
index bed264e..223e86a 100644
--- a/src/dev/arm/gic_v3.cc
+++ b/src/dev/arm/gic_v3.cc
@@ -51,6 +51,9 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+namespace gem5
+{
+
Gicv3::Gicv3(const Params &p)
: BaseGic(p)
{
@@ -298,3 +301,5 @@
cpuInterfaces[cpu_interface_id]->unserializeSection(cp,
csprintf("cpuInterface.%i", cpu_interface_id));
}
+
+} // namespace gem5
diff --git a/src/dev/arm/gic_v3.hh b/src/dev/arm/gic_v3.hh
index 5e05034..ab8543c 100644
--- a/src/dev/arm/gic_v3.hh
+++ b/src/dev/arm/gic_v3.hh
@@ -45,6 +45,9 @@
#include "dev/arm/base_gic.hh"
#include "params/Gicv3.hh"
+namespace gem5
+{
+
class Gicv3CPUInterface;
class Gicv3Distributor;
class Gicv3Redistributor;
@@ -161,4 +164,6 @@
void postInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
};
+} // namespace gem5
+
#endif //__DEV_ARM_GICV3_H__
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc
index 8c6f481..f4cdfc1 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -47,6 +47,9 @@
#include "dev/arm/gic_v3_distributor.hh"
#include "dev/arm/gic_v3_redistributor.hh"
+namespace gem5
+{
+
using namespace ArmISA;
const uint8_t Gicv3CPUInterface::GIC_MIN_BPR;
@@ -2336,7 +2339,7 @@
CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR);
- return ::inSecureState(scr, cpsr);
+ return gem5::inSecureState(scr, cpsr);
}
int
@@ -2623,3 +2626,5 @@
UNSERIALIZE_SCALAR(hppi.prio);
UNSERIALIZE_ENUM(hppi.group);
}
+
+} // namespace gem5
diff --git a/src/dev/arm/gic_v3_cpu_interface.hh b/src/dev/arm/gic_v3_cpu_interface.hh
index 721be79..09db7b5 100644
--- a/src/dev/arm/gic_v3_cpu_interface.hh
+++ b/src/dev/arm/gic_v3_cpu_interface.hh
@@ -44,6 +44,9 @@
#include "arch/arm/isa_device.hh"
#include "dev/arm/gic_v3.hh"
+namespace gem5
+{
+
class Gicv3Distributor;
class Gicv3Redistributor;
@@ -357,4 +360,6 @@
void setThreadContext(ThreadContext *tc) override;
};
+} // namespace gem5
+
#endif //__DEV_ARM_GICV3_CPU_INTERFACE_H__
diff --git a/src/dev/arm/gic_v3_distributor.cc b/src/dev/arm/gic_v3_distributor.cc
index be826fd..a4124ae 100644
--- a/src/dev/arm/gic_v3_distributor.cc
+++ b/src/dev/arm/gic_v3_distributor.cc
@@ -49,6 +49,9 @@
#include "dev/arm/gic_v3_cpu_interface.hh"
#include "dev/arm/gic_v3_redistributor.hh"
+namespace gem5
+{
+
const AddrRange Gicv3Distributor::GICD_IGROUPR (0x0080, 0x0100);
const AddrRange Gicv3Distributor::GICD_ISENABLER (0x0100, 0x0180);
const AddrRange Gicv3Distributor::GICD_ICENABLER (0x0180, 0x0200);
@@ -1213,3 +1216,5 @@
UNSERIALIZE_CONTAINER(irqNsacr);
UNSERIALIZE_CONTAINER(irqAffinityRouting);
}
+
+} // namespace gem5
diff --git a/src/dev/arm/gic_v3_distributor.hh b/src/dev/arm/gic_v3_distributor.hh
index e97829d..22c5ad7 100644
--- a/src/dev/arm/gic_v3_distributor.hh
+++ b/src/dev/arm/gic_v3_distributor.hh
@@ -45,6 +45,9 @@
#include "dev/arm/gic_v3.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
class Gicv3Distributor : public Serializable
{
private:
@@ -271,4 +274,6 @@
bool is_secure_access);
};
+} // namespace gem5
+
#endif //__DEV_ARM_GICV3_DISTRIBUTOR_H__
diff --git a/src/dev/arm/gic_v3_its.cc b/src/dev/arm/gic_v3_its.cc
index c30c33a..24329a2 100644
--- a/src/dev/arm/gic_v3_its.cc
+++ b/src/dev/arm/gic_v3_its.cc
@@ -53,6 +53,9 @@
#define COMMAND(x, method) { x, DispatchEntry(#x, method) }
+namespace gem5
+{
+
const AddrRange Gicv3Its::GITS_BASER(0x0100, 0x0140);
const uint32_t Gicv3Its::CTLR_QUIESCENT = 0x80000000;
@@ -1291,3 +1294,5 @@
rd2->updateDistributor();
}
+
+} // namespace gem5
diff --git a/src/dev/arm/gic_v3_its.hh b/src/dev/arm/gic_v3_its.hh
index 7221e26..2729394 100644
--- a/src/dev/arm/gic_v3_its.hh
+++ b/src/dev/arm/gic_v3_its.hh
@@ -50,6 +50,9 @@
#include "dev/dma_device.hh"
#include "params/Gicv3Its.hh"
+namespace gem5
+{
+
class Gicv3;
class Gicv3Redistributor;
class ItsProcess;
@@ -79,9 +82,10 @@
*/
class Gicv3Its : public BasicPioDevice
{
- friend class ::ItsProcess;
- friend class ::ItsTranslation;
- friend class ::ItsCommand;
+ friend class gem5::ItsProcess;
+ friend class gem5::ItsTranslation;
+ friend class gem5::ItsCommand;
+
public:
class DataPort : public RequestPort
{
@@ -542,4 +546,6 @@
}
};
+} // namespace gem5
+
#endif
diff --git a/src/dev/arm/gic_v3_redistributor.cc b/src/dev/arm/gic_v3_redistributor.cc
index df3a11d..8d4c29b 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -46,6 +46,9 @@
#include "dev/arm/gic_v3_cpu_interface.hh"
#include "dev/arm/gic_v3_distributor.hh"
+namespace gem5
+{
+
using namespace ArmISA;
const AddrRange Gicv3Redistributor::GICR_IPRIORITYR(SGI_base + 0x0400,
@@ -1093,3 +1096,5 @@
UNSERIALIZE_SCALAR(lpiIDBits);
UNSERIALIZE_SCALAR(lpiPendingTablePtr);
}
+
+} // namespace gem5
diff --git a/src/dev/arm/gic_v3_redistributor.hh b/src/dev/arm/gic_v3_redistributor.hh
index f833cd4..4d4bc99 100644
--- a/src/dev/arm/gic_v3_redistributor.hh
+++ b/src/dev/arm/gic_v3_redistributor.hh
@@ -45,6 +45,9 @@
#include "dev/arm/gic_v3.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
class Gicv3CPUInterface;
class Gicv3Distributor;
class Gicv3Its;
@@ -259,4 +262,6 @@
void write(Addr addr, uint64_t data, size_t size, bool is_secure_access);
};
+} // namespace gem5
+
#endif //__DEV_ARM_GICV3_REDISTRIBUTOR_H__
diff --git a/src/dev/arm/gpu_nomali.cc b/src/dev/arm/gpu_nomali.cc
index 809ef59..d793e67 100644
--- a/src/dev/arm/gpu_nomali.cc
+++ b/src/dev/arm/gpu_nomali.cc
@@ -46,6 +46,9 @@
#include "params/CustomNoMaliGpu.hh"
#include "params/NoMaliGpu.hh"
+namespace gem5
+{
+
static const std::map<enums::NoMaliGpuType, nomali_gpu_type_t> gpuTypeMap{
{ enums::T60x, NOMALI_GPU_T60X },
{ enums::T62x, NOMALI_GPU_T62X },
@@ -374,3 +377,5 @@
for (const auto ® : idRegs)
writeRegRaw(reg.first, reg.second);
}
+
+} // namespace gem5
diff --git a/src/dev/arm/gpu_nomali.hh b/src/dev/arm/gpu_nomali.hh
index e30f3ed..d143371 100644
--- a/src/dev/arm/gpu_nomali.hh
+++ b/src/dev/arm/gpu_nomali.hh
@@ -43,6 +43,9 @@
#include "dev/io_device.hh"
#include "libnomali/nomali.h"
+namespace gem5
+{
+
struct NoMaliGpuParams;
struct CustomNoMaliGpuParams;
class RealView;
@@ -199,4 +202,6 @@
std::map<nomali_addr_t, uint32_t> idRegs;
};
+} // namespace gem5
+
#endif // __DEV_ARM_NOMALI_GPU_HH__
diff --git a/src/dev/arm/hdlcd.cc b/src/dev/arm/hdlcd.cc
index 0a68412..7a80f10 100644
--- a/src/dev/arm/hdlcd.cc
+++ b/src/dev/arm/hdlcd.cc
@@ -53,6 +53,8 @@
using std::vector;
+namespace gem5
+{
// initialize hdlcd registers
HDLcd::HDLcd(const HDLcdParams &p)
@@ -688,3 +690,5 @@
inform("PixelPump vertical fron porch: %u", t.vFrontPorch);
inform("PixelPump vertical fron porch: %u", t.vSync);
}
+
+} // namespace gem5
diff --git a/src/dev/arm/hdlcd.hh b/src/dev/arm/hdlcd.hh
index e9a9120..6056fb5 100644
--- a/src/dev/arm/hdlcd.hh
+++ b/src/dev/arm/hdlcd.hh
@@ -84,6 +84,9 @@
#include "dev/pixelpump.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
class VncInput;
struct HDLcdParams;
class HDLcdPixelPump;
@@ -418,4 +421,6 @@
} stats;
};
+} // namespace gem5
+
#endif
diff --git a/src/dev/arm/kmi.cc b/src/dev/arm/kmi.cc
index 4f0541e..4eaefe4 100644
--- a/src/dev/arm/kmi.cc
+++ b/src/dev/arm/kmi.cc
@@ -48,6 +48,9 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+namespace gem5
+{
+
Pl050::Pl050(const Pl050Params &p)
: AmbaIntDevice(p, 0x1000), control(0), status(0x43), clkdiv(0),
rawInterrupts(0),
@@ -219,3 +222,5 @@
UNSERIALIZE_SCALAR(clkdiv);
paramIn(cp, "raw_ints", rawInterrupts);
}
+
+} // namespace gem5
diff --git a/src/dev/arm/kmi.hh b/src/dev/arm/kmi.hh
index 5a9894b..3763974 100644
--- a/src/dev/arm/kmi.hh
+++ b/src/dev/arm/kmi.hh
@@ -52,6 +52,9 @@
#include "dev/arm/amba_device.hh"
#include "params/Pl050.hh"
+namespace gem5
+{
+
namespace ps2 {
class Device;
} // namespace ps2
@@ -137,4 +140,6 @@
void unserialize(CheckpointIn &cp) override;
};
+} // namespace gem5
+
#endif // __DEV_ARM_PL050_HH__
diff --git a/src/dev/arm/pci_host.cc b/src/dev/arm/pci_host.cc
index c50a302..3ef012a 100644
--- a/src/dev/arm/pci_host.cc
+++ b/src/dev/arm/pci_host.cc
@@ -39,6 +39,9 @@
#include "params/GenericArmPciHost.hh"
+namespace gem5
+{
+
GenericArmPciHost::GenericArmPciHost(const GenericArmPciHostParams &p)
: GenericPciHost(p),
intPolicy(p.int_policy), intBase(p.int_base),
@@ -68,3 +71,5 @@
fatal("Unsupported PCI interrupt routing policy.");
}
}
+
+} // namespace gem5
diff --git a/src/dev/arm/pci_host.hh b/src/dev/arm/pci_host.hh
index c6cb2b5..aceaa82 100644
--- a/src/dev/arm/pci_host.hh
+++ b/src/dev/arm/pci_host.hh
@@ -41,6 +41,9 @@
#include "dev/pci/host.hh"
#include "enums/ArmPciIntRouting.hh"
+namespace gem5
+{
+
class BaseGic;
struct GenericArmPciHostParams;
@@ -61,4 +64,6 @@
const uint32_t intCount;
};
+} // namespace gem5
+
#endif // __DEV_ARM_PCI_HOST_HH__
diff --git a/src/dev/arm/pl011.cc b/src/dev/arm/pl011.cc
index cfe241d..bbc6cdd 100755
--- a/src/dev/arm/pl011.cc
+++ b/src/dev/arm/pl011.cc
@@ -50,6 +50,9 @@
#include "params/Pl011.hh"
#include "sim/sim_exit.hh"
+namespace gem5
+{
+
Pl011::Pl011(const Pl011Params &p)
: Uart(p, 0x1000),
intEvent([this]{ generateInterrupt(); }, name()),
@@ -296,3 +299,5 @@
paramIn(cp, "imsc_serial", imsc);
paramIn(cp, "rawInt_serial", rawInt);
}
+
+} // namespace gem5
diff --git a/src/dev/arm/pl011.hh b/src/dev/arm/pl011.hh
index 5095c39..bc0470f 100755
--- a/src/dev/arm/pl011.hh
+++ b/src/dev/arm/pl011.hh
@@ -49,6 +49,9 @@
#include "dev/arm/amba_device.hh"
#include "dev/serial/uart.hh"
+namespace gem5
+{
+
class BaseGic;
struct Pl011Params;
@@ -180,4 +183,6 @@
const Tick intDelay;
};
+} // namespace gem5
+
#endif //__DEV_ARM_PL011_H__
diff --git a/src/dev/arm/pl111.cc b/src/dev/arm/pl111.cc
index be3ff5e..c814496 100644
--- a/src/dev/arm/pl111.cc
+++ b/src/dev/arm/pl111.cc
@@ -52,6 +52,9 @@
// we open up the entire namespace std
using std::vector;
+namespace gem5
+{
+
// initialize clcd registers
Pl111::Pl111(const Params &p)
: AmbaDmaDevice(p, 0x10000), lcdTiming0(0), lcdTiming1(0), lcdTiming2(0),
@@ -740,3 +743,5 @@
ranges.push_back(RangeSize(pioAddr, pioSize));
return ranges;
}
+
+} // namespace gem5
diff --git a/src/dev/arm/pl111.hh b/src/dev/arm/pl111.hh
index 43a6dc0..5736761 100644
--- a/src/dev/arm/pl111.hh
+++ b/src/dev/arm/pl111.hh
@@ -53,6 +53,9 @@
#include "params/Pl111.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
class VncInput;
class Pl111: public AmbaDmaDevice
@@ -375,4 +378,6 @@
AddrRangeList getAddrRanges() const override;
};
+} // namespace gem5
+
#endif
diff --git a/src/dev/arm/realview.cc b/src/dev/arm/realview.cc
index 55ba9b3..b9425e4f 100644
--- a/src/dev/arm/realview.cc
+++ b/src/dev/arm/realview.cc
@@ -47,6 +47,9 @@
#include "base/logging.hh"
#include "dev/arm/base_gic.hh"
+namespace gem5
+{
+
RealView::RealView(const Params &p)
: Platform(p), gic(nullptr)
{}
@@ -76,3 +79,5 @@
{
gic->clearInt(line);
}
+
+} // namespace gem5
diff --git a/src/dev/arm/realview.hh b/src/dev/arm/realview.hh
index 065b753..392d5c2 100644
--- a/src/dev/arm/realview.hh
+++ b/src/dev/arm/realview.hh
@@ -50,6 +50,9 @@
#include "dev/platform.hh"
#include "params/RealView.hh"
+namespace gem5
+{
+
class BaseGic;
class IdeController;
@@ -74,4 +77,6 @@
void clearPciInt(int line) override;
};
+} // namespace gem5
+
#endif // __DEV_ARM_RealView_HH__
diff --git a/src/dev/arm/rtc_pl031.cc b/src/dev/arm/rtc_pl031.cc
index 6f4aa88..9abfbc5 100644
--- a/src/dev/arm/rtc_pl031.cc
+++ b/src/dev/arm/rtc_pl031.cc
@@ -46,6 +46,9 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+namespace gem5
+{
+
PL031::PL031(const Params &p)
: AmbaIntDevice(p, 0x1000), lastWrittenTick(0), loadVal(0), matchVal(0),
rawInt(false), maskInt(false), pendingInt(false),
@@ -223,3 +226,5 @@
schedule(matchEvent, event_time);
}
}
+
+} // namespace gem5
diff --git a/src/dev/arm/rtc_pl031.hh b/src/dev/arm/rtc_pl031.hh
index 68377c3..cad6bdd 100644
--- a/src/dev/arm/rtc_pl031.hh
+++ b/src/dev/arm/rtc_pl031.hh
@@ -45,6 +45,9 @@
* This implements the ARM Primecell 031 RTC
*/
+namespace gem5
+{
+
class PL031 : public AmbaIntDevice
{
protected:
@@ -124,5 +127,6 @@
void unserialize(CheckpointIn &cp) override;
};
+} // namespace gem5
#endif // __DEV_ARM_RTC_PL031_HH__
diff --git a/src/dev/arm/rv_ctrl.cc b/src/dev/arm/rv_ctrl.cc
index 054a796..4285b48 100644
--- a/src/dev/arm/rv_ctrl.cc
+++ b/src/dev/arm/rv_ctrl.cc
@@ -45,6 +45,9 @@
#include "sim/system.hh"
#include "sim/voltage_domain.hh"
+namespace gem5
+{
+
RealViewCtrl::RealViewCtrl(const Params &p)
: BasicPioDevice(p, 0xD4), flags(0), scData(0)
{
@@ -313,3 +316,5 @@
// Report a dummy 25 degrees temperature
return 25000000;
}
+
+} // namespace gem5
diff --git a/src/dev/arm/rv_ctrl.hh b/src/dev/arm/rv_ctrl.hh
index 70f870b..ae780a6 100644
--- a/src/dev/arm/rv_ctrl.hh
+++ b/src/dev/arm/rv_ctrl.hh
@@ -48,6 +48,9 @@
* This implements the simple real view registers on a PBXA9
*/
+namespace gem5
+{
+
class RealViewCtrl : public BasicPioDevice
{
public:
@@ -243,5 +246,6 @@
System * system;
};
+} // namespace gem5
#endif // __DEV_ARM_RV_HH__
diff --git a/src/dev/arm/smmu_v3.cc b/src/dev/arm/smmu_v3.cc
index f50f376..ac71023 100644
--- a/src/dev/arm/smmu_v3.cc
+++ b/src/dev/arm/smmu_v3.cc
@@ -52,6 +52,9 @@
#include "mem/packet_access.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
SMMUv3::SMMUv3(const SMMUv3Params ¶ms) :
ClockedObject(params),
system(*params.system),
@@ -818,3 +821,5 @@
return ClockedObject::getPort(name, id);
}
}
+
+} // namespace gem5
diff --git a/src/dev/arm/smmu_v3.hh b/src/dev/arm/smmu_v3.hh
index ea5a717..8169da7 100644
--- a/src/dev/arm/smmu_v3.hh
+++ b/src/dev/arm/smmu_v3.hh
@@ -76,6 +76,10 @@
* - Checkpointing is not supported
* - Stall/resume for faulting transactions is not supported
*/
+
+namespace gem5
+{
+
class SMMUTranslationProcess;
class SMMUv3 : public ClockedObject
@@ -195,4 +199,6 @@
PortID id = InvalidPortID) override;
};
+} // namespace gem5
+
#endif /* __DEV_ARM_SMMU_V3_HH__ */
diff --git a/src/dev/arm/smmu_v3_caches.cc b/src/dev/arm/smmu_v3_caches.cc
index fcb0125..1280499 100644
--- a/src/dev/arm/smmu_v3_caches.cc
+++ b/src/dev/arm/smmu_v3_caches.cc
@@ -58,6 +58,9 @@
* TODO: move more code into this base class to reduce duplication.
*/
+namespace gem5
+{
+
SMMUv3BaseCache::SMMUv3BaseCache(const std::string &policy_name, uint32_t seed,
statistics::Group *parent, const std::string &name)
: replacementPolicy(decodePolicyName(policy_name)),
@@ -1330,3 +1333,5 @@
for (auto avg_hitrate : averageHitRateByStageLevel)
delete avg_hitrate;
}
+
+} // namespace gem5
diff --git a/src/dev/arm/smmu_v3_caches.hh b/src/dev/arm/smmu_v3_caches.hh
index 007664d..5a84263 100644
--- a/src/dev/arm/smmu_v3_caches.hh
+++ b/src/dev/arm/smmu_v3_caches.hh
@@ -51,6 +51,9 @@
#define WALK_CACHE_LEVELS 4
+namespace gem5
+{
+
enum
{
SMMU_CACHE_REPL_ROUND_ROBIN,
@@ -358,4 +361,6 @@
unsigned stage, unsigned level);
};
+} // namespace gem5
+
#endif /* __DEV_ARM_SMMU_V3_CACHES_HH__ */
diff --git a/src/dev/arm/smmu_v3_cmdexec.cc b/src/dev/arm/smmu_v3_cmdexec.cc
index 70d1410..7fcbad0 100644
--- a/src/dev/arm/smmu_v3_cmdexec.cc
+++ b/src/dev/arm/smmu_v3_cmdexec.cc
@@ -40,6 +40,9 @@
#include "base/bitfield.hh"
#include "dev/arm/smmu_v3.hh"
+namespace gem5
+{
+
void
SMMUCommandExecProcess::main(Yield &yield)
{
@@ -86,3 +89,5 @@
doSleep(yield);
}
}
+
+} // namespace gem5
diff --git a/src/dev/arm/smmu_v3_cmdexec.hh b/src/dev/arm/smmu_v3_cmdexec.hh
index c8c92ca..650e576 100644
--- a/src/dev/arm/smmu_v3_cmdexec.hh
+++ b/src/dev/arm/smmu_v3_cmdexec.hh
@@ -41,6 +41,9 @@
#include "dev/arm/smmu_v3_defs.hh"
#include "dev/arm/smmu_v3_proc.hh"
+namespace gem5
+{
+
class SMMUv3;
class SMMUCommandExecProcess : public SMMUProcess
@@ -65,4 +68,6 @@
bool isBusy() const { return busy; }
};
+} // namespace gem5
+
#endif /* __DEV_ARM_SMMU_V3_CMDEXEC_HH__ */
diff --git a/src/dev/arm/smmu_v3_defs.hh b/src/dev/arm/smmu_v3_defs.hh
index e0219e4..8b7dfe0 100644
--- a/src/dev/arm/smmu_v3_defs.hh
+++ b/src/dev/arm/smmu_v3_defs.hh
@@ -42,6 +42,9 @@
#include "base/bitunion.hh"
+namespace gem5
+{
+
enum
{
SMMU_SECURE_SZ = 0x184, // Secure regs are within page0
@@ -407,4 +410,6 @@
SMMU_MAX_TRANS_ID = 64
};
+} // namespace gem5
+
#endif /* __DEV_ARM_SMMU_V3_DEFS_HH__ */
diff --git a/src/dev/arm/smmu_v3_deviceifc.cc b/src/dev/arm/smmu_v3_deviceifc.cc
index 6683e76..166b85d 100644
--- a/src/dev/arm/smmu_v3_deviceifc.cc
+++ b/src/dev/arm/smmu_v3_deviceifc.cc
@@ -42,6 +42,9 @@
#include "dev/arm/smmu_v3.hh"
#include "dev/arm/smmu_v3_transl.hh"
+namespace gem5
+{
+
SMMUv3DeviceInterface::SMMUv3DeviceInterface(
const SMMUv3DeviceInterfaceParams &p) :
ClockedObject(p),
@@ -261,3 +264,5 @@
}
return DrainState::Drained;
}
+
+} // namespace gem5
diff --git a/src/dev/arm/smmu_v3_deviceifc.hh b/src/dev/arm/smmu_v3_deviceifc.hh
index 9961fb9..c4ffa37 100644
--- a/src/dev/arm/smmu_v3_deviceifc.hh
+++ b/src/dev/arm/smmu_v3_deviceifc.hh
@@ -48,6 +48,9 @@
#include "params/SMMUv3DeviceInterface.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
class SMMUTranslationProcess;
class SMMUv3;
class SMMUDevicePort;
@@ -133,4 +136,6 @@
void sendRange();
};
+} // namespace gem5
+
#endif /* __DEV_ARM_SMMU_V3_DEVICEIFC_HH__ */
diff --git a/src/dev/arm/smmu_v3_events.cc b/src/dev/arm/smmu_v3_events.cc
index 774f2da..ffef2c9 100644
--- a/src/dev/arm/smmu_v3_events.cc
+++ b/src/dev/arm/smmu_v3_events.cc
@@ -39,6 +39,9 @@
#include "dev/arm/smmu_v3_deviceifc.hh"
+namespace gem5
+{
+
void
SMMUDeviceRetryEvent::process()
{
@@ -50,3 +53,5 @@
{
return smmuIfc.name() + ".device_retry_event";
}
+
+} // namespace gem5
diff --git a/src/dev/arm/smmu_v3_events.hh b/src/dev/arm/smmu_v3_events.hh
index cfc980e..7011a96 100644
--- a/src/dev/arm/smmu_v3_events.hh
+++ b/src/dev/arm/smmu_v3_events.hh
@@ -41,6 +41,9 @@
#include <base/types.hh>
#include <sim/eventq.hh>
+namespace gem5
+{
+
class SMMUv3DeviceInterface;
class SMMUDeviceRetryEvent : public Event
@@ -61,4 +64,6 @@
{ return "DeviceRetryEvent"; }
};
+} // namespace gem5
+
#endif /* __DEV_ARM_SMMU_V3_EVENTS_HH__ */
diff --git a/src/dev/arm/smmu_v3_ports.cc b/src/dev/arm/smmu_v3_ports.cc
index 5d5e787..95915b2 100644
--- a/src/dev/arm/smmu_v3_ports.cc
+++ b/src/dev/arm/smmu_v3_ports.cc
@@ -41,6 +41,9 @@
#include "dev/arm/smmu_v3.hh"
#include "dev/arm/smmu_v3_deviceifc.hh"
+namespace gem5
+{
+
SMMURequestPort::SMMURequestPort(const std::string &_name, SMMUv3 &_smmu) :
RequestPort(_name, &_smmu),
smmu(_smmu)
@@ -174,3 +177,5 @@
{
return ifc.atsRecvTimingReq(pkt);
}
+
+} // namespace gem5
diff --git a/src/dev/arm/smmu_v3_ports.hh b/src/dev/arm/smmu_v3_ports.hh
index 9d567fa8..88d3a2f 100644
--- a/src/dev/arm/smmu_v3_ports.hh
+++ b/src/dev/arm/smmu_v3_ports.hh
@@ -41,6 +41,9 @@
#include "mem/qport.hh"
#include "mem/tport.hh"
+namespace gem5
+{
+
class SMMUv3;
class SMMUv3DeviceInterface;
@@ -138,4 +141,6 @@
virtual ~SMMUATSDevicePort() {}
};
+} // namespace gem5
+
#endif /* __DEV_ARM_SMMU_V3_PORTS_HH__ */
diff --git a/src/dev/arm/smmu_v3_proc.cc b/src/dev/arm/smmu_v3_proc.cc
index 866939b..2cf2cf9 100644
--- a/src/dev/arm/smmu_v3_proc.cc
+++ b/src/dev/arm/smmu_v3_proc.cc
@@ -43,6 +43,9 @@
#include "dev/arm/smmu_v3.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
SMMUProcess::SMMUProcess(const std::string &name, SMMUv3 &_smmu) :
coroutine(NULL),
myName(name),
@@ -209,3 +212,5 @@
assert(*coroutine);
return (*coroutine)(pkt).get();
}
+
+} // namespace gem5
diff --git a/src/dev/arm/smmu_v3_proc.hh b/src/dev/arm/smmu_v3_proc.hh
index eaf5659..775c9e1 100644
--- a/src/dev/arm/smmu_v3_proc.hh
+++ b/src/dev/arm/smmu_v3_proc.hh
@@ -46,6 +46,9 @@
#include "base/types.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
class SMMUv3DeviceInterface;
/*
@@ -132,4 +135,6 @@
const std::string name() const { return myName; };
};
+} // namespace gem5
+
#endif /* __DEV_ARM_SMMU_V3_PROC_HH__ */
diff --git a/src/dev/arm/smmu_v3_ptops.cc b/src/dev/arm/smmu_v3_ptops.cc
index c9b7801..058cca4 100644
--- a/src/dev/arm/smmu_v3_ptops.cc
+++ b/src/dev/arm/smmu_v3_ptops.cc
@@ -40,6 +40,9 @@
#include "base/bitfield.hh"
#include "base/logging.hh"
+namespace gem5
+{
+
bool
V7LPageTableOps::isValid(pte_t pte, unsigned level) const
{
@@ -421,3 +424,5 @@
{
return 3;
}
+
+} // namespace gem5
diff --git a/src/dev/arm/smmu_v3_ptops.hh b/src/dev/arm/smmu_v3_ptops.hh
index 48c6d45..2e025f8 100644
--- a/src/dev/arm/smmu_v3_ptops.hh
+++ b/src/dev/arm/smmu_v3_ptops.hh
@@ -42,6 +42,9 @@
#include "base/types.hh"
+namespace gem5
+{
+
struct PageTableOps
{
typedef int64_t pte_t;
@@ -109,4 +112,6 @@
unsigned lastLevel() const override;
};
+} // namespace gem5
+
#endif /* __DEV_ARM_SMMU_V3_PTOPS_HH__ */
diff --git a/src/dev/arm/smmu_v3_transl.cc b/src/dev/arm/smmu_v3_transl.cc
index 9888838..4c88ee1 100644
--- a/src/dev/arm/smmu_v3_transl.cc
+++ b/src/dev/arm/smmu_v3_transl.cc
@@ -43,6 +43,9 @@
#include "dev/arm/smmu_v3.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
SMMUTranslRequest
SMMUTranslRequest::fromPacket(PacketPtr pkt, bool ats)
{
@@ -1477,3 +1480,5 @@
doRead(yield, base, ptr, pte_size);
}
+
+} // namespace gem5
diff --git a/src/dev/arm/smmu_v3_transl.hh b/src/dev/arm/smmu_v3_transl.hh
index fbe97b0..0cd4908 100644
--- a/src/dev/arm/smmu_v3_transl.hh
+++ b/src/dev/arm/smmu_v3_transl.hh
@@ -44,6 +44,9 @@
#include "dev/arm/smmu_v3_ptops.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
struct SMMUTranslRequest
{
Addr addr;
@@ -182,4 +185,6 @@
void resumeTransaction();
};
+} // namespace gem5
+
#endif /* __DEV_ARM_SMMU_V3_TRANSL_HH__ */
diff --git a/src/dev/arm/timer_cpulocal.cc b/src/dev/arm/timer_cpulocal.cc
index 3b120f6..1b5a459 100644
--- a/src/dev/arm/timer_cpulocal.cc
+++ b/src/dev/arm/timer_cpulocal.cc
@@ -49,6 +49,9 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+namespace gem5
+{
+
CpuLocalTimer::CpuLocalTimer(const Params &p)
: BasicPioDevice(p, 0x38)
{
@@ -441,3 +444,5 @@
for (int i = 0; i < sys->threads.size(); i++)
localTimer[i]->unserializeSection(cp, csprintf("timer%d", i));
}
+
+} // namespace gem5
diff --git a/src/dev/arm/timer_cpulocal.hh b/src/dev/arm/timer_cpulocal.hh
index 086ff90..9063f90 100644
--- a/src/dev/arm/timer_cpulocal.hh
+++ b/src/dev/arm/timer_cpulocal.hh
@@ -53,6 +53,9 @@
* Technical Reference Manual rev r2p2 (ARM DDI 0407F)
*/
+namespace gem5
+{
+
class BaseGic;
class ArmInterruptPin;
@@ -192,6 +195,6 @@
void unserialize(CheckpointIn &cp) override;
};
+} // namespace gem5
#endif // __DEV_ARM_SP804_HH__
-
diff --git a/src/dev/arm/timer_sp804.cc b/src/dev/arm/timer_sp804.cc
index f69da13..8cb30cd 100644
--- a/src/dev/arm/timer_sp804.cc
+++ b/src/dev/arm/timer_sp804.cc
@@ -48,6 +48,9 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+namespace gem5
+{
+
Sp804::Sp804(const Params &p)
: AmbaPioDevice(p, 0x1000),
timer0(name() + ".timer0", this, p.int0->get(), p.clock0),
@@ -283,3 +286,5 @@
timer0.unserializeSection(cp, "timer0");
timer1.unserializeSection(cp, "timer1");
}
+
+} // namespace gem5
diff --git a/src/dev/arm/timer_sp804.hh b/src/dev/arm/timer_sp804.hh
index c47c62b..8f80911 100644
--- a/src/dev/arm/timer_sp804.hh
+++ b/src/dev/arm/timer_sp804.hh
@@ -51,6 +51,9 @@
* This implements the dual Sp804 timer block
*/
+namespace gem5
+{
+
class BaseGic;
class Sp804 : public AmbaPioDevice
@@ -163,6 +166,6 @@
void unserialize(CheckpointIn &cp) override;
};
+} // namespace gem5
#endif // __DEV_ARM_SP804_HH__
-
diff --git a/src/dev/arm/ufs_device.cc b/src/dev/arm/ufs_device.cc
index 3ad9f93..3a0e11a 100644
--- a/src/dev/arm/ufs_device.cc
+++ b/src/dev/arm/ufs_device.cc
@@ -69,6 +69,9 @@
#include "dev/arm/ufs_device.hh"
+namespace gem5
+{
+
/**
* Constructor and destructor functions of UFSHCM device
*/
@@ -2325,3 +2328,5 @@
signalDrainDone();
}
}
+
+} // namespace gem5
diff --git a/src/dev/arm/ufs_device.hh b/src/dev/arm/ufs_device.hh
index 6da9dd9..ea58b85 100644
--- a/src/dev/arm/ufs_device.hh
+++ b/src/dev/arm/ufs_device.hh
@@ -160,6 +160,9 @@
#include "sim/serialize.hh"
#include "sim/stats.hh"
+namespace gem5
+{
+
/**
* Host controller layer: This is your Host controller
* This layer handles the UFS functionality.
@@ -1233,4 +1236,6 @@
};
};
+} // namespace gem5
+
#endif //__DEV_ARM_UFS_DEVICE_HH__
diff --git a/src/dev/arm/vgic.cc b/src/dev/arm/vgic.cc
index 764bc8a..7265d02 100644
--- a/src/dev/arm/vgic.cc
+++ b/src/dev/arm/vgic.cc
@@ -46,6 +46,9 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+namespace gem5
+{
+
VGic::VGic(const Params &p)
: PioDevice(p), gicvIIDR(p.gicv_iidr), platform(p.platform),
gic(p.gic), vcpuAddr(p.vcpu_addr), hvAddr(p.hv_addr),
@@ -555,3 +558,5 @@
paramIn(cp, "lr", LR[i]);
}
}
+
+} // namespace gem5
diff --git a/src/dev/arm/vgic.hh b/src/dev/arm/vgic.hh
index 63859f0..d426a53 100644
--- a/src/dev/arm/vgic.hh
+++ b/src/dev/arm/vgic.hh
@@ -59,6 +59,9 @@
#include "dev/platform.hh"
#include "params/VGic.hh"
+namespace gem5
+{
+
class VGic : public PioDevice
{
private:
@@ -257,4 +260,6 @@
}
};
+} // namespace gem5
+
#endif
diff --git a/src/dev/arm/vio_mmio.cc b/src/dev/arm/vio_mmio.cc
index b5eaae3..ad71a5c 100644
--- a/src/dev/arm/vio_mmio.cc
+++ b/src/dev/arm/vio_mmio.cc
@@ -42,6 +42,9 @@
#include "mem/packet_access.hh"
#include "params/MmioVirtIO.hh"
+namespace gem5
+{
+
MmioVirtIO::MmioVirtIO(const MmioVirtIOParams ¶ms)
: BasicPioDevice(params, params.pio_size),
hostFeaturesSelect(0), guestFeaturesSelect(0), pageSize(0),
@@ -273,3 +276,5 @@
interrupt->clear();
}
}
+
+} // namespace gem5
diff --git a/src/dev/arm/vio_mmio.hh b/src/dev/arm/vio_mmio.hh
index 298ea0a..a52e68d 100644
--- a/src/dev/arm/vio_mmio.hh
+++ b/src/dev/arm/vio_mmio.hh
@@ -41,6 +41,9 @@
#include "dev/io_device.hh"
#include "dev/virtio/base.hh"
+namespace gem5
+{
+
class ArmInterruptPin;
struct MmioVirtIOParams;
@@ -110,4 +113,6 @@
ArmInterruptPin *const interrupt;
};
+} // namespace gem5
+
#endif // __DEV_ARM_VIO_MMIO_HH__
diff --git a/src/dev/arm/watchdog_generic.cc b/src/dev/arm/watchdog_generic.cc
index 3361665..59e069c 100644
--- a/src/dev/arm/watchdog_generic.cc
+++ b/src/dev/arm/watchdog_generic.cc
@@ -40,6 +40,8 @@
#include "dev/arm/base_gic.hh"
#include "params/GenericWatchdog.hh"
+namespace gem5
+{
GenericWatchdog::GenericWatchdog(const GenericWatchdogParams &p)
: PioDevice(p),
@@ -261,3 +263,5 @@
reschedule(timeoutEvent, when, true);
}
}
+
+} // namespace gem5
diff --git a/src/dev/arm/watchdog_generic.hh b/src/dev/arm/watchdog_generic.hh
index 177df93..0baa912 100644
--- a/src/dev/arm/watchdog_generic.hh
+++ b/src/dev/arm/watchdog_generic.hh
@@ -41,6 +41,9 @@
#include "dev/arm/generic_timer.hh"
#include "dev/io_device.hh"
+namespace gem5
+{
+
class ArmInterruptPin;
struct GenericWatchdogParams;
@@ -153,4 +156,6 @@
ArmInterruptPin * const ws1;
};
+} // namespace gem5
+
#endif // __DEV_ARM_WATCHDOG_GENERIC_HH__
diff --git a/src/dev/arm/watchdog_sp805.cc b/src/dev/arm/watchdog_sp805.cc
index 69a6d3c..2fa7d91 100644
--- a/src/dev/arm/watchdog_sp805.cc
+++ b/src/dev/arm/watchdog_sp805.cc
@@ -42,6 +42,9 @@
#include "mem/packet_access.hh"
#include "params/Sp805.hh"
+namespace gem5
+{
+
Sp805::Sp805(const Sp805Params ¶ms)
: AmbaIntDevice(params, 0x1000),
timeoutInterval(0xffffffff),
@@ -259,3 +262,5 @@
reschedule(timeoutEvent, when, true);
}
}
+
+} // namespace gem5
diff --git a/src/dev/arm/watchdog_sp805.hh b/src/dev/arm/watchdog_sp805.hh
index 0adfe94..ff1fe65 100644
--- a/src/dev/arm/watchdog_sp805.hh
+++ b/src/dev/arm/watchdog_sp805.hh
@@ -40,6 +40,9 @@
#include "dev/arm/amba_device.hh"
+namespace gem5
+{
+
struct Sp805Params;
/**
@@ -128,4 +131,6 @@
static constexpr uint32_t WDOGLOCK_MAGIC = 0x1acce551;
};
+} // namespace gem5
+
#endif // __DEV_ARM_WATCHDOG_SP805_HH__
diff --git a/src/dev/baddev.cc b/src/dev/baddev.cc
index f291459..dab1074 100644
--- a/src/dev/baddev.cc
+++ b/src/dev/baddev.cc
@@ -38,6 +38,9 @@
#include "params/BadDevice.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
BadDevice::BadDevice(const Params &p)
: BasicPioDevice(p, 0x10), devname(p.devicename)
{
@@ -54,3 +57,5 @@
{
panic("Device %s not imlpmented\n", devname);
}
+
+} // namespace gem5
diff --git a/src/dev/baddev.hh b/src/dev/baddev.hh
index 835a34e..f1ce919 100644
--- a/src/dev/baddev.hh
+++ b/src/dev/baddev.hh
@@ -37,6 +37,9 @@
#include "dev/io_device.hh"
#include "params/BadDevice.hh"
+namespace gem5
+{
+
/**
* BadDevice
* This device just panics when accessed. It is supposed to warn
@@ -62,4 +65,6 @@
virtual Tick write(PacketPtr pkt);
};
+} // namespace gem5
+
#endif // __DEV_BADDEV_HH__
diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index 57cee49..ee871aa 100644
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -52,6 +52,9 @@
#include "sim/clocked_object.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
DmaPort::DmaPort(ClockedObject *dev, System *s,
uint32_t sid, uint32_t ssid)
: RequestPort(dev->name() + ".dma", dev),
@@ -597,3 +600,5 @@
_done = true;
parent->dmaDone();
}
+
+} // namespace gem5
diff --git a/src/dev/dma_device.hh b/src/dev/dma_device.hh
index 330be1a..2a3468c 100644
--- a/src/dev/dma_device.hh
+++ b/src/dev/dma_device.hh
@@ -53,6 +53,9 @@
#include "sim/drain.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
class ClockedObject;
class DmaPort : public RequestPort, public Drainable
@@ -565,4 +568,6 @@
std::deque<DmaDoneEventUPtr> freeRequests;
};
+} // namespace gem5
+
#endif // __DEV_DMA_DEVICE_HH__
diff --git a/src/dev/hsa/HSADevice.py b/src/dev/hsa/HSADevice.py
index 922b22a..f67d9a8 100644
--- a/src/dev/hsa/HSADevice.py
+++ b/src/dev/hsa/HSADevice.py
@@ -37,6 +37,8 @@
class HSAPacketProcessor(DmaDevice):
type = 'HSAPacketProcessor'
cxx_header = 'dev/hsa/hsa_packet_processor.hh'
+ cxx_class = 'gem5::HSAPacketProcessor'
+
pioAddr = Param.Addr("doorbell physical address")
numHWQueues = Param.Int("Number of HW queues")
# See:
diff --git a/src/dev/hsa/HSADriver.py b/src/dev/hsa/HSADriver.py
index ebcd6f6..4173dcf 100644
--- a/src/dev/hsa/HSADriver.py
+++ b/src/dev/hsa/HSADriver.py
@@ -38,4 +38,5 @@
type = 'HSADriver'
abstract = True
cxx_header = 'dev/hsa/hsa_driver.hh'
+ cxx_class = 'gem5::HSADriver'
device = Param.HSADevice('HSA device controlled by this driver')
diff --git a/src/dev/hsa/hsa.h b/src/dev/hsa/hsa.h
index ef01de6..09380d3 100644
--- a/src/dev/hsa/hsa.h
+++ b/src/dev/hsa/hsa.h
@@ -105,6 +105,9 @@
#define HSA_VERSION_1_0 1
#ifdef __cplusplus
+namespace gem5
+{
+
extern "C" {
#endif /* __cplusplus */
@@ -5692,6 +5695,7 @@
#ifdef __cplusplus
} // end extern "C" block
+} // namespace gem5
#endif
#endif // header guard
diff --git a/src/dev/hsa/hsa_packet.hh b/src/dev/hsa/hsa_packet.hh
index 036e061..31e7636 100644
--- a/src/dev/hsa/hsa_packet.hh
+++ b/src/dev/hsa/hsa_packet.hh
@@ -38,6 +38,9 @@
#include <cstdint>
+namespace gem5
+{
+
typedef struct hsa_packet_header_s
{
// TODO: replace with more portable impl based on offset, length
@@ -99,4 +102,6 @@
uint64_t completion_signal;
} _hsa_barrier_or_packet_t;
+} // namespace gem5
+
#endif // __DEV_HSA_HSA_PACKET_HH__
diff --git a/src/dev/hsa/hsa_packet_processor.cc b/src/dev/hsa/hsa_packet_processor.cc
index 8749aa7..ff1543b 100644
--- a/src/dev/hsa/hsa_packet_processor.cc
+++ b/src/dev/hsa/hsa_packet_processor.cc
@@ -66,6 +66,9 @@
#define IS_BARRIER(PKT) ((hsa_packet_header_t)(((PKT->header) >> \
HSA_PACKET_HEADER_BARRIER) & HSA_PACKET_HEADER_WIDTH_BARRIER))
+namespace gem5
+{
+
HSAPP_EVENT_DESCRIPTION_GENERATOR(UpdateReadDispIdDmaEvent)
HSAPP_EVENT_DESCRIPTION_GENERATOR(CmdQueueCmdDmaEvent)
HSAPP_EVENT_DESCRIPTION_GENERATOR(QueueProcessEvent)
@@ -769,3 +772,5 @@
dmaWriteVirt(signal_addr, sizeof(hsa_signal_value_t), nullptr, new_signal, 0);
}
+
+} // namespace gem5
diff --git a/src/dev/hsa/hsa_packet_processor.hh b/src/dev/hsa/hsa_packet_processor.hh
index fe71612..0d7ae04 100644
--- a/src/dev/hsa/hsa_packet_processor.hh
+++ b/src/dev/hsa/hsa_packet_processor.hh
@@ -52,6 +52,9 @@
// HSA runtime supports only 5 signals per barrier packet
#define NumSignalsPerBarrier 5
+namespace gem5
+{
+
// Ideally, each queue should store this status and
// the processPkt() should make decisions based on that
// status variable.
@@ -418,4 +421,6 @@
};
};
+} // namespace gem5
+
#endif // __DEV_HSA_HSA_PACKET_PROCESSOR__
diff --git a/src/dev/hsa/hsa_queue.hh b/src/dev/hsa/hsa_queue.hh
index 2c9c585..19a678c 100644
--- a/src/dev/hsa/hsa_queue.hh
+++ b/src/dev/hsa/hsa_queue.hh
@@ -36,6 +36,9 @@
#include <cstdint>
+namespace gem5
+{
+
typedef enum
{
_HSA_QUEUE_TYPE_MULTI = 0,
@@ -87,4 +90,6 @@
uint32_t reserved4[14];
} _amd_queue_t;
+} // namespace gem5
+
#endif // __DEV_HSA_HSA_QUEUE_HH__
diff --git a/src/dev/hsa/hsa_signal.hh b/src/dev/hsa/hsa_signal.hh
index 160a2a8..725aca3 100644
--- a/src/dev/hsa/hsa_signal.hh
+++ b/src/dev/hsa/hsa_signal.hh
@@ -35,6 +35,9 @@
#include <cstdint>
+namespace gem5
+{
+
// AMD Signal Kind Enumeration Values.
typedef int64_t amd_signal_kind64_t;
enum amd_signal_kind_t
@@ -68,4 +71,6 @@
uint32_t reserved3[2];
} amd_signal_t;
+} // namespace gem5
+
#endif // DEV_HSA_HSA_SIGNAL_H
diff --git a/src/dev/hsa/hw_scheduler.cc b/src/dev/hsa/hw_scheduler.cc
index be7b369..5e6fdb9 100644
--- a/src/dev/hsa/hw_scheduler.cc
+++ b/src/dev/hsa/hw_scheduler.cc
@@ -45,6 +45,9 @@
return #XEVENT; \
}
+namespace gem5
+{
+
HWSCHDLR_EVENT_DESCRIPTION_GENERATOR(SchedulerWakeupEvent)
void
@@ -369,3 +372,5 @@
}
schedWakeup();
}
+
+} // namespace gem5
diff --git a/src/dev/hsa/hw_scheduler.hh b/src/dev/hsa/hw_scheduler.hh
index c4fe66c..b50273d 100644
--- a/src/dev/hsa/hw_scheduler.hh
+++ b/src/dev/hsa/hw_scheduler.hh
@@ -45,6 +45,9 @@
// address is 8 bytes
#define MAX_ACTIVE_QUEUES (PAGE_SIZE/8)
+namespace gem5
+{
+
class HWScheduler
{
public:
@@ -106,4 +109,6 @@
SchedulerWakeupEvent schedWakeupEvent;
};
+} // namespace gem5
+
#endif // __DEV_HSA_HW_SCHEDULER_HH__
diff --git a/src/dev/hsa/kfd_event_defines.h b/src/dev/hsa/kfd_event_defines.h
index f52bb59..020c174 100644
--- a/src/dev/hsa/kfd_event_defines.h
+++ b/src/dev/hsa/kfd_event_defines.h
@@ -35,6 +35,9 @@
#include "dev/hsa/kfd_ioctl.h"
+namespace gem5
+{
+
#define KFD_GPU_ID_HASH_WIDTH 16
#define PAGE_SHIFT 12
@@ -50,4 +53,6 @@
#define KFD_MMAP_GPU_ID(gpu_id) \
((((uint64_t)gpu_id) << KFD_MMAP_GPU_ID_SHIFT) & KFD_MMAP_GPU_ID_MASK)
+} // namespace gem5
+
#endif
diff --git a/src/dev/hsa/kfd_ioctl.h b/src/dev/hsa/kfd_ioctl.h
index 7099851..e1286dc 100644
--- a/src/dev/hsa/kfd_ioctl.h
+++ b/src/dev/hsa/kfd_ioctl.h
@@ -23,10 +23,14 @@
#ifndef KFD_IOCTL_H_INCLUDED
#define KFD_IOCTL_H_INCLUDED
+#include <cstdint>
#include <drm/drm.h>
#include <linux/ioctl.h>
#include <linux/types.h>
+namespace gem5
+{
+
/*
* - 1.1 - initial version
* - 1.3 - Add SMI events support
@@ -613,4 +617,6 @@
#define AMDKFD_COMMAND_START 0x01
#define AMDKFD_COMMAND_END 0x20
+} // namespace gem5
+
#endif
diff --git a/src/dev/i2c/I2C.py b/src/dev/i2c/I2C.py
index c144629..aa9afea 100644
--- a/src/dev/i2c/I2C.py
+++ b/src/dev/i2c/I2C.py
@@ -40,10 +40,12 @@
class I2CDevice(SimObject):
type = 'I2CDevice'
cxx_header = "dev/i2c/device.hh"
+ cxx_class = 'gem5::I2CDevice'
abstract = True
i2c_addr = Param.UInt8("Address of device on i2c bus")
class I2CBus(BasicPioDevice):
type = 'I2CBus'
cxx_header = "dev/i2c/bus.hh"
+ cxx_class = 'gem5::I2CBus'
devices = VectorParam.I2CDevice([], "Devices")
diff --git a/src/dev/i2c/bus.cc b/src/dev/i2c/bus.cc
index 7e362ac..9d6fbce 100644
--- a/src/dev/i2c/bus.cc
+++ b/src/dev/i2c/bus.cc
@@ -48,6 +48,9 @@
using std::vector;
using std::map;
+namespace gem5
+{
+
/**
* 4KB - see e.g.
* http://infocenter.arm.com/help/topic/com.arm.doc.dui0440b/Bbajihec.html
@@ -235,3 +238,5 @@
UNSERIALIZE_SCALAR(i2cAddr);
UNSERIALIZE_SCALAR(message);
}
+
+} // namespace gem5
diff --git a/src/dev/i2c/bus.hh b/src/dev/i2c/bus.hh
index 2678c40..5bd7542 100644
--- a/src/dev/i2c/bus.hh
+++ b/src/dev/i2c/bus.hh
@@ -48,6 +48,9 @@
#include "dev/io_device.hh"
#include "params/I2CBus.hh"
+namespace gem5
+{
+
class I2CDevice;
class I2CBus : public BasicPioDevice
@@ -150,4 +153,6 @@
void unserialize(CheckpointIn &cp) override;
};
+} // namespace gem5
+
#endif // __DEV_I2C_BUS_HH__
diff --git a/src/dev/i2c/device.hh b/src/dev/i2c/device.hh
index 6d76e78..e558af5 100644
--- a/src/dev/i2c/device.hh
+++ b/src/dev/i2c/device.hh
@@ -47,6 +47,9 @@
#include "params/I2CDevice.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class I2CDevice : public SimObject
{
@@ -91,4 +94,6 @@
};
+} // namespace gem5
+
#endif // __DEV_I2C_DEVICE__
diff --git a/src/dev/intel_8254_timer.cc b/src/dev/intel_8254_timer.cc
index 44f266e..85818a3 100644
--- a/src/dev/intel_8254_timer.cc
+++ b/src/dev/intel_8254_timer.cc
@@ -31,6 +31,9 @@
#include "base/logging.hh"
#include "debug/Intel8254Timer.hh"
+namespace gem5
+{
+
Intel8254Timer::Intel8254Timer(EventManager *em, const std::string &name,
Counter *counter0, Counter *counter1, Counter *counter2) :
EventManager(em), _name(name)
@@ -322,3 +325,4 @@
return interval;
}
+} // namespace gem5
diff --git a/src/dev/intel_8254_timer.hh b/src/dev/intel_8254_timer.hh
index 0ac9882..9876d13 100644
--- a/src/dev/intel_8254_timer.hh
+++ b/src/dev/intel_8254_timer.hh
@@ -39,6 +39,9 @@
#include "sim/eventq.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
/** Programmable Interval Timer (Intel 8254) */
class Intel8254Timer : public EventManager
{
@@ -259,4 +262,6 @@
void startup();
};
+} // namespace gem5
+
#endif // __DEV_8254_HH__
diff --git a/src/dev/intpin.cc b/src/dev/intpin.cc
index 08aad5f..3268fdb 100644
--- a/src/dev/intpin.cc
+++ b/src/dev/intpin.cc
@@ -29,6 +29,9 @@
#include "base/logging.hh"
+namespace gem5
+{
+
void
IntSinkPinBase::bind(Port &peer)
{
@@ -65,3 +68,5 @@
sink = nullptr;
Port::unbind();
}
+
+} // namespace gem5
diff --git a/src/dev/intpin.hh b/src/dev/intpin.hh
index 180fd69..d5f81a5 100644
--- a/src/dev/intpin.hh
+++ b/src/dev/intpin.hh
@@ -30,6 +30,9 @@
#include "sim/port.hh"
+namespace gem5
+{
+
class IntSourcePinBase;
class IntSinkPinBase : public Port
@@ -115,4 +118,6 @@
{}
};
+} // namespace gem5
+
#endif //__DEV_INTPIN_HH__
diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc
index ae6a5e3..8895b41 100644
--- a/src/dev/io_device.cc
+++ b/src/dev/io_device.cc
@@ -44,6 +44,9 @@
#include "debug/AddrRanges.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
PioDevice::PioDevice(const Params &p)
: ClockedObject(p), sys(p.system), pioPort(this)
{}
@@ -83,3 +86,5 @@
ranges.push_back(RangeSize(pioAddr, pioSize));
return ranges;
}
+
+} // namespace gem5
diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh
index 834b505..6e3cfa7 100644
--- a/src/dev/io_device.hh
+++ b/src/dev/io_device.hh
@@ -46,6 +46,9 @@
#include "params/PioDevice.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
class PioDevice;
class System;
@@ -165,4 +168,6 @@
AddrRangeList getAddrRanges() const override;
};
+} // namespace gem5
+
#endif // __DEV_IO_DEVICE_HH__
diff --git a/src/dev/isa_fake.cc b/src/dev/isa_fake.cc
index 0132ddc..f4bfcf7 100644
--- a/src/dev/isa_fake.cc
+++ b/src/dev/isa_fake.cc
@@ -38,6 +38,9 @@
#include "mem/packet_access.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
IsaFake::IsaFake(const Params &p)
: BasicPioDevice(p, p.ret_bad_addr ? 0 : p.pio_size)
{
@@ -140,3 +143,5 @@
}
return pioDelay;
}
+
+} // namespace gem5
diff --git a/src/dev/isa_fake.hh b/src/dev/isa_fake.hh
index e0687c5..0cd0e6e 100644
--- a/src/dev/isa_fake.hh
+++ b/src/dev/isa_fake.hh
@@ -39,6 +39,9 @@
#include "mem/packet.hh"
#include "params/IsaFake.hh"
+namespace gem5
+{
+
/**
* IsaFake is a device that returns, BadAddr, 1 or 0 on all reads and
* rites. It is meant to be placed at an address range
@@ -78,4 +81,6 @@
virtual Tick write(PacketPtr pkt);
};
+} // namespace gem5
+
#endif // __ISA_FAKE_HH__
diff --git a/src/dev/mc146818.cc b/src/dev/mc146818.cc
index 0bc52fc..919efb0 100644
--- a/src/dev/mc146818.cc
+++ b/src/dev/mc146818.cc
@@ -39,6 +39,9 @@
#include "debug/MC146818.hh"
#include "dev/rtcreg.h"
+namespace gem5
+{
+
static uint8_t
bcdize(uint8_t val)
{
@@ -342,3 +345,5 @@
{
return "RTC clock tick";
}
+
+} // namespace gem5
diff --git a/src/dev/mc146818.hh b/src/dev/mc146818.hh
index b5e895f..4f2cb0a 100644
--- a/src/dev/mc146818.hh
+++ b/src/dev/mc146818.hh
@@ -34,6 +34,9 @@
#include "sim/core.hh"
#include "sim/eventq.hh"
+namespace gem5
+{
+
/** Real-Time Clock (MC146818) */
class MC146818 : public EventManager
{
@@ -181,4 +184,6 @@
void unserialize(const std::string &base, CheckpointIn &cp);
};
+} // namespace gem5
+
#endif // __DEV_MC146818_HH__
diff --git a/src/dev/mips/Malta.py b/src/dev/mips/Malta.py
index e6e5b98..f461256 100755
--- a/src/dev/mips/Malta.py
+++ b/src/dev/mips/Malta.py
@@ -35,11 +35,13 @@
class MaltaCChip(BasicPioDevice):
type = 'MaltaCChip'
cxx_header = "dev/mips/malta_cchip.hh"
+ cxx_class = 'gem5::MaltaCChip'
malta = Param.Malta(Parent.any, "Malta")
class MaltaIO(BasicPioDevice):
type = 'MaltaIO'
cxx_header = "dev/mips/malta_io.hh"
+ cxx_class = 'gem5::MaltaIO'
time = Param.Time('01/01/2009',
"System time to use (0 for actual time, default is 1/1/06)")
year_is_bcd = Param.Bool(False,
@@ -50,6 +52,7 @@
class Malta(Platform):
type = 'Malta'
cxx_header = "dev/mips/malta.hh"
+ cxx_class = 'gem5::Malta'
cchip = MaltaCChip(pio_addr=0x801a0000000)
io = MaltaIO(pio_addr=0x801fc000000)
uart = Uart8250(pio_addr=0xBFD003F8)
diff --git a/src/dev/mips/malta.cc b/src/dev/mips/malta.cc
index b327d1e..1d01491 100644
--- a/src/dev/mips/malta.cc
+++ b/src/dev/mips/malta.cc
@@ -37,6 +37,9 @@
#include "dev/mips/malta_io.hh"
#include "params/Malta.hh"
+namespace gem5
+{
+
Malta::Malta(const Params &p)
: Platform(p)
{
@@ -81,3 +84,5 @@
{
UNSERIALIZE_ARRAY(intr_sum_type, Malta::Max_CPUs);
}
+
+} // namespace gem5
diff --git a/src/dev/mips/malta.hh b/src/dev/mips/malta.hh
index 637e571..af44b50 100644
--- a/src/dev/mips/malta.hh
+++ b/src/dev/mips/malta.hh
@@ -38,6 +38,9 @@
#include "dev/platform.hh"
#include "params/Malta.hh"
+namespace gem5
+{
+
class MaltaCChip;
class MaltaIO;
@@ -94,4 +97,6 @@
void unserialize(CheckpointIn &cp) override;
};
+} // namespace gem5
+
#endif // __DEV_MALTA_HH__
diff --git a/src/dev/mips/malta_cchip.cc b/src/dev/mips/malta_cchip.cc
index e845ba0..dc29f0e 100644
--- a/src/dev/mips/malta_cchip.cc
+++ b/src/dev/mips/malta_cchip.cc
@@ -48,6 +48,9 @@
#include "params/MaltaCChip.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
MaltaCChip::MaltaCChip(const Params &p)
: BasicPioDevice(p, 0xfffffff), malta(p.malta)
{
@@ -139,3 +142,5 @@
MaltaCChip::unserialize(CheckpointIn &cp)
{
}
+
+} // namespace gem5
diff --git a/src/dev/mips/malta_cchip.hh b/src/dev/mips/malta_cchip.hh
index 82dcad2..5994d2f 100644
--- a/src/dev/mips/malta_cchip.hh
+++ b/src/dev/mips/malta_cchip.hh
@@ -37,6 +37,9 @@
#include "dev/io_device.hh"
#include "params/MaltaCChip.hh"
+namespace gem5
+{
+
/**
* Malta CChip CSR Emulation. This device includes all the interrupt
* handling code for the chipset.
@@ -128,4 +131,6 @@
void unserialize(CheckpointIn &cp) override;
};
+} // namespace gem5
+
#endif // __MALTA_CCHIP_HH__
diff --git a/src/dev/mips/malta_io.cc b/src/dev/mips/malta_io.cc
index a90fc94..9a3be16 100644
--- a/src/dev/mips/malta_io.cc
+++ b/src/dev/mips/malta_io.cc
@@ -51,6 +51,9 @@
#include "params/MaltaIO.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
MaltaIO::RTC::RTC(const std::string &name, const MaltaIOParams &p)
: MC146818(p.malta, name, p.time, p.year_is_bcd, p.frequency),
malta(p.malta)
@@ -141,3 +144,5 @@
rtc.startup();
pitimer.startup();
}
+
+} // namespace gem5
diff --git a/src/dev/mips/malta_io.hh b/src/dev/mips/malta_io.hh
index a838d18..45fc545 100644
--- a/src/dev/mips/malta_io.hh
+++ b/src/dev/mips/malta_io.hh
@@ -41,6 +41,9 @@
#include "params/MaltaIO.hh"
#include "sim/eventq.hh"
+namespace gem5
+{
+
/**
* Malta I/O device is a catch all for all the south bridge stuff we care
* to implement.
@@ -130,4 +133,6 @@
};
+} // namespace gem5
+
#endif // __DEV_MALTA_IO_HH__
diff --git a/src/dev/net/Ethernet.py b/src/dev/net/Ethernet.py
index dc29ce6..15a7fe3 100644
--- a/src/dev/net/Ethernet.py
+++ b/src/dev/net/Ethernet.py
@@ -56,6 +56,8 @@
class EtherLink(SimObject):
type = 'EtherLink'
cxx_header = "dev/net/etherlink.hh"
+ cxx_class = 'gem5::EtherLink'
+
int0 = EtherInt("interface 0")
int1 = EtherInt("interface 1")
delay = Param.Latency('0us', "packet transmit delay")
@@ -66,6 +68,8 @@
class DistEtherLink(SimObject):
type = 'DistEtherLink'
cxx_header = "dev/net/dist_etherlink.hh"
+ cxx_class = 'gem5::DistEtherLink'
+
int0 = EtherInt("interface 0")
delay = Param.Latency('0us', "packet transmit delay")
delay_var = Param.Latency('0ns', "packet transmit delay variability")
@@ -84,6 +88,8 @@
class EtherBus(SimObject):
type = 'EtherBus'
cxx_header = "dev/net/etherbus.hh"
+ cxx_class = 'gem5::EtherBus'
+
loopback = Param.Bool(True, "send packet back to the sending interface")
dump = Param.EtherDump(NULL, "dump object")
speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
@@ -91,6 +97,8 @@
class EtherSwitch(SimObject):
type = 'EtherSwitch'
cxx_header = "dev/net/etherswitch.hh"
+ cxx_class = 'gem5::EtherSwitch'
+
dump = Param.EtherDump(NULL, "dump object")
fabric_speed = Param.NetworkBandwidth('10Gbps', "switch fabric speed in "
"bits per second")
@@ -105,6 +113,8 @@
type = 'EtherTapBase'
abstract = True
cxx_header = "dev/net/ethertap.hh"
+ cxx_class = 'gem5::EtherTapBase'
+
bufsz = Param.Int(10000, "tap buffer size")
dump = Param.EtherDump(NULL, "dump object")
tap = EtherInt("Ethernet interface to connect to gem5's network")
@@ -113,6 +123,8 @@
class EtherTap(EtherTapBase):
type = 'EtherTap'
cxx_header = "dev/net/ethertap.hh"
+ cxx_class = 'gem5::EtherTap'
+
tun_clone_device = Param.String('/dev/net/tun',
"Path to the tun clone device node")
tap_device_name = Param.String('gem5-tap', "Tap device name")
@@ -120,11 +132,15 @@
class EtherTapStub(EtherTapBase):
type = 'EtherTapStub'
cxx_header = "dev/net/ethertap.hh"
+ cxx_class = 'gem5::EtherTapStub'
+
port = Param.UInt16(3500, "Port helper should send packets to")
class EtherDump(SimObject):
type = 'EtherDump'
cxx_header = "dev/net/etherdump.hh"
+ cxx_class = 'gem5::EtherDump'
+
file = Param.String("dump file")
maxlen = Param.Int(96, "max portion of packet data to dump")
@@ -132,12 +148,16 @@
type = 'EtherDevice'
abstract = True
cxx_header = "dev/net/etherdevice.hh"
+ cxx_class = 'gem5::EtherDevice'
+
interface = EtherInt("Ethernet Interface")
class IGbE(EtherDevice):
# Base class for two IGbE adapters listed above
type = 'IGbE'
cxx_header = "dev/net/i8254xGBe.hh"
+ cxx_class = 'gem5::IGbE'
+
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
rx_fifo_size = Param.MemorySize('384KiB', "Size of the rx FIFO")
@@ -185,6 +205,7 @@
type = 'EtherDevBase'
abstract = True
cxx_header = "dev/net/etherdevice.hh"
+ cxx_class = 'gem5::EtherDevBase'
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
@@ -208,6 +229,7 @@
class NSGigE(EtherDevBase):
type = 'NSGigE'
cxx_header = "dev/net/ns_gige.hh"
+ cxx_class = 'gem5::NSGigE'
dma_data_free = Param.Bool(False, "DMA of Data is free")
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
@@ -229,7 +251,7 @@
class Sinic(EtherDevBase):
type = 'Sinic'
- cxx_class = 'sinic::Device'
+ cxx_class = 'gem5::sinic::Device'
cxx_header = "dev/net/sinic.hh"
rx_max_copy = Param.MemorySize('1514B', "rx max copy")
diff --git a/src/dev/net/dist_etherlink.cc b/src/dev/net/dist_etherlink.cc
index 8cbf6ef..4bb8221 100644
--- a/src/dev/net/dist_etherlink.cc
+++ b/src/dev/net/dist_etherlink.cc
@@ -66,6 +66,9 @@
#include "sim/serialize.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
DistEtherLink::DistEtherLink(const Params &p)
: SimObject(p), linkDelay(p.delay)
{
@@ -251,4 +254,4 @@
rx->setDistInt(m);
}
-
+} // namespace gem5
diff --git a/src/dev/net/dist_etherlink.hh b/src/dev/net/dist_etherlink.hh
index a3f32d3..4551d82 100644
--- a/src/dev/net/dist_etherlink.hh
+++ b/src/dev/net/dist_etherlink.hh
@@ -57,6 +57,9 @@
#include "sim/serialize.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class DistIface;
class EthPacketData;
@@ -229,4 +232,6 @@
void unserialize(CheckpointIn &cp) override;
};
+} // namespace gem5
+
#endif // __DEV_DIST_ETHERLINK_HH__
diff --git a/src/dev/net/dist_iface.cc b/src/dev/net/dist_iface.cc
index 7f8a4a0..ac3f1fe 100644
--- a/src/dev/net/dist_iface.cc
+++ b/src/dev/net/dist_iface.cc
@@ -54,6 +54,9 @@
#include "sim/sim_object.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
DistIface::Sync *DistIface::sync = nullptr;
System *DistIface::sys = nullptr;
DistIface::SyncEvent *DistIface::syncEvent = nullptr;
@@ -937,3 +940,5 @@
}
return val;
}
+
+} // namespace gem5
diff --git a/src/dev/net/dist_iface.hh b/src/dev/net/dist_iface.hh
index 04843aa..7383019 100644
--- a/src/dev/net/dist_iface.hh
+++ b/src/dev/net/dist_iface.hh
@@ -89,6 +89,9 @@
#include "sim/global_event.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
class EventManager;
class System;
class ThreadContext;
@@ -640,4 +643,6 @@
static void toggleSync(ThreadContext *tc);
};
-#endif
+} // namespace gem5
+
+#endif // __DEV_DIST_IFACE_HH__
diff --git a/src/dev/net/dist_packet.hh b/src/dev/net/dist_packet.hh
index 39bfb0b..c1ab18c 100644
--- a/src/dev/net/dist_packet.hh
+++ b/src/dev/net/dist_packet.hh
@@ -55,6 +55,9 @@
#include "base/types.hh"
+namespace gem5
+{
+
class DistHeaderPkt
{
private:
@@ -111,4 +114,6 @@
};
};
-#endif
+} // namespace gem5
+
+#endif // __DEV_DIST_PACKET_HH__
diff --git a/src/dev/net/etherbus.cc b/src/dev/net/etherbus.cc
index bc9379e..1a56a56 100644
--- a/src/dev/net/etherbus.cc
+++ b/src/dev/net/etherbus.cc
@@ -46,6 +46,9 @@
#include "params/EtherBus.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
EtherBus::EtherBus(const Params &p)
: SimObject(p), ticksPerByte(p.speed), loopback(p.loopback),
event([this]{ txDone(); }, "ethernet bus completion"),
@@ -103,3 +106,5 @@
return true;
}
+
+} // namespace gem5
diff --git a/src/dev/net/etherbus.hh b/src/dev/net/etherbus.hh
index e280f2b..839ab4c 100644
--- a/src/dev/net/etherbus.hh
+++ b/src/dev/net/etherbus.hh
@@ -38,6 +38,9 @@
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class EtherDump;
class EtherInt;
class EtherBus : public SimObject
@@ -67,4 +70,6 @@
PortID idx=InvalidPortID) override;
};
+} // namespace gem5
+
#endif // __DEV_NET_ETHERBUS_HH__
diff --git a/src/dev/net/etherdevice.cc b/src/dev/net/etherdevice.cc
index 04d0ca2..51293e9 100644
--- a/src/dev/net/etherdevice.cc
+++ b/src/dev/net/etherdevice.cc
@@ -30,6 +30,9 @@
#include "sim/stats.hh"
+namespace gem5
+{
+
EtherDevice::EtherDeviceStats::EtherDeviceStats(statistics::Group *parent)
: statistics::Group(parent, "EtherDevice"),
ADD_STAT(postedInterrupts, statistics::units::Count::get(),
@@ -326,3 +329,5 @@
totalTxOk + totalTxIdle + totalTxDesc +
totalRxOrn) / postedInterrupts;
}
+
+} // namespace gem5
diff --git a/src/dev/net/etherdevice.hh b/src/dev/net/etherdevice.hh
index a5e1009..25101f6 100644
--- a/src/dev/net/etherdevice.hh
+++ b/src/dev/net/etherdevice.hh
@@ -40,6 +40,9 @@
#include "params/EtherDevice.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class EtherInt;
class EtherDevice : public PciDevice
@@ -146,5 +149,6 @@
{}
};
-#endif // __DEV_NET_ETHERDEVICE_HH__
+} // namespace gem5
+#endif // __DEV_NET_ETHERDEVICE_HH__
diff --git a/src/dev/net/etherdump.cc b/src/dev/net/etherdump.cc
index 4aa40e3..435d978 100644
--- a/src/dev/net/etherdump.cc
+++ b/src/dev/net/etherdump.cc
@@ -42,6 +42,9 @@
using std::string;
+namespace gem5
+{
+
EtherDump::EtherDump(const Params &p)
: SimObject(p), stream(simout.create(p.file, true)->stream()),
maxlen(p.maxlen)
@@ -102,3 +105,5 @@
stream->write(reinterpret_cast<char *>(packet->data), pkthdr.caplen);
stream->flush();
}
+
+} // namespace gem5
diff --git a/src/dev/net/etherdump.hh b/src/dev/net/etherdump.hh
index 594e56d..062dec7 100644
--- a/src/dev/net/etherdump.hh
+++ b/src/dev/net/etherdump.hh
@@ -39,6 +39,9 @@
#include "params/EtherDump.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
/*
* Simple object for creating a simple pcap style packet trace
*/
@@ -57,4 +60,6 @@
inline void dump(EthPacketPtr &pkt) { dumpPacket(pkt); }
};
+} // namespace gem5
+
#endif // __DEV_NET_ETHERDUMP_HH__
diff --git a/src/dev/net/etherint.cc b/src/dev/net/etherint.cc
index 7c16286..5ce57ba 100644
--- a/src/dev/net/etherint.cc
+++ b/src/dev/net/etherint.cc
@@ -31,6 +31,9 @@
#include "base/logging.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
void
EtherInt::bind(Port &peer)
{
@@ -59,3 +62,5 @@
peer = p;
}
+
+} // namespace gem5
diff --git a/src/dev/net/etherint.hh b/src/dev/net/etherint.hh
index 59b5b19..3827b82 100644
--- a/src/dev/net/etherint.hh
+++ b/src/dev/net/etherint.hh
@@ -39,6 +39,9 @@
#include "dev/net/etherpkt.hh"
#include "mem/port.hh"
+namespace gem5
+{
+
/*
* Class representing the actual interface between two ethernet
* components. These components are intended to attach to another
@@ -75,4 +78,6 @@
virtual bool isBusy() { return false; }
};
+} // namespace gem5
+
#endif // __DEV_NET_ETHERINT_HH__
diff --git a/src/dev/net/etherlink.cc b/src/dev/net/etherlink.cc
index 3c9bfea..67b0dd3 100644
--- a/src/dev/net/etherlink.cc
+++ b/src/dev/net/etherlink.cc
@@ -63,6 +63,9 @@
#include "sim/serialize.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
EtherLink::EtherLink(const Params &p)
: SimObject(p)
{
@@ -264,3 +267,5 @@
"in-flight packets may have been dropped.\n");
}
}
+
+} // namespace gem5
diff --git a/src/dev/net/etherlink.hh b/src/dev/net/etherlink.hh
index f275366..435096d 100644
--- a/src/dev/net/etherlink.hh
+++ b/src/dev/net/etherlink.hh
@@ -55,6 +55,9 @@
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class EtherDump;
class Checkpoint;
/*
@@ -152,4 +155,6 @@
};
+} // namespace gem5
+
#endif // __DEV_NET_ETHERLINK_HH__
diff --git a/src/dev/net/etherpkt.cc b/src/dev/net/etherpkt.cc
index d64815c..8d4a287 100644
--- a/src/dev/net/etherpkt.cc
+++ b/src/dev/net/etherpkt.cc
@@ -34,6 +34,9 @@
#include "base/logging.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
void
EthPacketData::serialize(const std::string &base, CheckpointOut &cp) const
{
@@ -68,3 +71,4 @@
simLength = length;
}
+} // namespace gem5
diff --git a/src/dev/net/etherpkt.hh b/src/dev/net/etherpkt.hh
index 3582779..6fef412 100644
--- a/src/dev/net/etherpkt.hh
+++ b/src/dev/net/etherpkt.hh
@@ -40,6 +40,9 @@
#include "base/types.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
/*
* Reference counted class containing ethernet packet data
*/
@@ -86,4 +89,6 @@
typedef std::shared_ptr<EthPacketData> EthPacketPtr;
+} // namespace gem5
+
#endif // __DEV_NET_ETHERPKT_HH__
diff --git a/src/dev/net/etherswitch.cc b/src/dev/net/etherswitch.cc
index cd22d46..934e5d0 100644
--- a/src/dev/net/etherswitch.cc
+++ b/src/dev/net/etherswitch.cc
@@ -37,6 +37,9 @@
#include "debug/EthernetAll.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
EtherSwitch::EtherSwitch(const Params &p)
: SimObject(p), ttl(p.time_to_live)
{
@@ -343,3 +346,5 @@
}
}
+
+} // namespace gem5
diff --git a/src/dev/net/etherswitch.hh b/src/dev/net/etherswitch.hh
index 6cba36a..8aa56c5 100644
--- a/src/dev/net/etherswitch.hh
+++ b/src/dev/net/etherswitch.hh
@@ -48,6 +48,9 @@
#include "sim/serialize.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class EtherSwitch : public SimObject
{
public:
@@ -190,4 +193,6 @@
void unserialize(CheckpointIn &cp) override;
};
+} // namespace gem5
+
#endif // __DEV_ETHERSWITCH_HH__
diff --git a/src/dev/net/ethertap.cc b/src/dev/net/ethertap.cc
index d5e2984..f0b77f9 100644
--- a/src/dev/net/ethertap.cc
+++ b/src/dev/net/ethertap.cc
@@ -67,6 +67,9 @@
#include "dev/net/etherint.hh"
#include "dev/net/etherpkt.hh"
+namespace gem5
+{
+
class TapEvent : public PollEvent
{
protected:
@@ -467,4 +470,6 @@
return true;
}
+} // namespace gem5
+
#endif
diff --git a/src/dev/net/ethertap.hh b/src/dev/net/ethertap.hh
index feac79d..e289753 100644
--- a/src/dev/net/ethertap.hh
+++ b/src/dev/net/ethertap.hh
@@ -50,6 +50,9 @@
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class TapEvent;
class EtherTapInt;
@@ -172,5 +175,6 @@
};
#endif
+} // namespace gem5
#endif // __DEV_NET_ETHERTAP_HH__
diff --git a/src/dev/net/i8254xGBe.cc b/src/dev/net/i8254xGBe.cc
index fd9005a..12057b1 100644
--- a/src/dev/net/i8254xGBe.cc
+++ b/src/dev/net/i8254xGBe.cc
@@ -52,6 +52,9 @@
#include "sim/stats.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace igbreg;
using namespace networking;
@@ -2460,3 +2463,5 @@
txDescCache.unserializeSection(cp, "TxDescCache");
rxDescCache.unserializeSection(cp, "RxDescCache");
}
+
+} // namespace gem5
diff --git a/src/dev/net/i8254xGBe.hh b/src/dev/net/i8254xGBe.hh
index dfefd73..e6aa35d 100644
--- a/src/dev/net/i8254xGBe.hh
+++ b/src/dev/net/i8254xGBe.hh
@@ -52,6 +52,9 @@
#include "sim/eventq.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
class IGbEInt;
class IGbE : public EtherDevice
@@ -514,4 +517,6 @@
virtual void sendDone() { dev->ethTxDone(); }
};
+} // namespace gem5
+
#endif //__DEV_NET_I8254XGBE_HH__
diff --git a/src/dev/net/i8254xGBe_defs.hh b/src/dev/net/i8254xGBe_defs.hh
index 795d043..e2508fa 100644
--- a/src/dev/net/i8254xGBe_defs.hh
+++ b/src/dev/net/i8254xGBe_defs.hh
@@ -32,6 +32,9 @@
#include "base/bitfield.hh"
#include "base/compiler.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(iGbReg, igbreg);
namespace igbreg
{
@@ -940,4 +943,6 @@
UNSERIALIZE_SCALAR(sw_fw_sync);
}
};
+
} // namespace igbreg
+} // namespace gem5
diff --git a/src/dev/net/ns_gige.cc b/src/dev/net/ns_gige.cc
index bb38acb..b89a6d3 100644
--- a/src/dev/net/ns_gige.cc
+++ b/src/dev/net/ns_gige.cc
@@ -54,6 +54,9 @@
using std::ostream;
using std::string;
+namespace gem5
+{
+
const char *NsRxStateStrings[] =
{
"rxIdle",
@@ -2365,3 +2368,5 @@
schedule(intrEvent, intrEventTick);
}
}
+
+} // namespace gem5
diff --git a/src/dev/net/ns_gige.hh b/src/dev/net/ns_gige.hh
index e42367c..13a2ec0 100644
--- a/src/dev/net/ns_gige.hh
+++ b/src/dev/net/ns_gige.hh
@@ -44,6 +44,9 @@
#include "params/NSGigE.hh"
#include "sim/eventq.hh"
+namespace gem5
+{
+
// Hash filtering constants
const uint16_t FHASH_ADDR = 0x100;
const uint16_t FHASH_SIZE = 0x100;
@@ -370,4 +373,6 @@
virtual void sendDone() { dev->transferDone(); }
};
+} // namespace gem5
+
#endif // __DEV_NET_NS_GIGE_HH__
diff --git a/src/dev/net/ns_gige_reg.h b/src/dev/net/ns_gige_reg.h
index 6d5750b..854f804 100644
--- a/src/dev/net/ns_gige_reg.h
+++ b/src/dev/net/ns_gige_reg.h
@@ -34,6 +34,9 @@
#ifndef __DEV_NS_GIGE_REG_H__
#define __DEV_NS_GIGE_REG_H__
+namespace gem5
+{
+
/* Device Register Address Map */
enum DeviceRegisterAddress
{
@@ -421,4 +424,6 @@
(lnksts ? CFGR_LNKSTS : CFGR_ZERO));
}
+} // namespace gem5
+
#endif /* __DEV_NS_GIGE_REG_H__ */
diff --git a/src/dev/net/pktfifo.cc b/src/dev/net/pktfifo.cc
index bf92933..b98900a 100644
--- a/src/dev/net/pktfifo.cc
+++ b/src/dev/net/pktfifo.cc
@@ -30,6 +30,9 @@
#include "base/logging.hh"
+namespace gem5
+{
+
bool
PacketFifo::copyout(void *dest, unsigned offset, unsigned len)
{
@@ -110,3 +113,5 @@
fifo.push_back(entry);
}
}
+
+} // namespace gem5
diff --git a/src/dev/net/pktfifo.hh b/src/dev/net/pktfifo.hh
index b57c642..6fa2952 100644
--- a/src/dev/net/pktfifo.hh
+++ b/src/dev/net/pktfifo.hh
@@ -37,6 +37,9 @@
#include "dev/net/etherpkt.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
class Checkpoint;
struct PacketFifoEntry
@@ -207,4 +210,6 @@
void unserialize(const std::string &base, CheckpointIn &cp);
};
+} // namespace gem5
+
#endif // __DEV_NET_PKTFIFO_HH__
diff --git a/src/dev/net/sinic.cc b/src/dev/net/sinic.cc
index 79a7e29..5b45b5e 100644
--- a/src/dev/net/sinic.cc
+++ b/src/dev/net/sinic.cc
@@ -43,6 +43,9 @@
#include "sim/eventq.hh"
#include "sim/stats.hh"
+namespace gem5
+{
+
using namespace networking;
GEM5_DEPRECATED_NAMESPACE(Sinic, sinic);
@@ -1494,3 +1497,4 @@
}
} // namespace sinic
+} // namespace gem5
diff --git a/src/dev/net/sinic.hh b/src/dev/net/sinic.hh
index 5e35d93..2b0f9fa 100644
--- a/src/dev/net/sinic.hh
+++ b/src/dev/net/sinic.hh
@@ -42,6 +42,9 @@
#include "params/Sinic.hh"
#include "sim/eventq.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Sinic, sinic);
namespace sinic
{
@@ -323,5 +326,6 @@
};
} // namespace sinic
+} // namespace gem5
#endif // __DEV_NET_SINIC_HH__
diff --git a/src/dev/net/sinicreg.hh b/src/dev/net/sinicreg.hh
index f479c68..120b9a1 100644
--- a/src/dev/net/sinicreg.hh
+++ b/src/dev/net/sinicreg.hh
@@ -56,6 +56,9 @@
static inline uint64_t set_##NAME(uint64_t reg, uint64_t val) \
{ return (reg & ~NAME) | ((val << OFFSET) & NAME); }
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Sinic, sinic);
namespace sinic
{
@@ -243,4 +246,6 @@
} // namespace sinic
+} // namespace gem5
+
#endif // __DEV_NET_SINICREG_HH__
diff --git a/src/dev/net/tcp_iface.cc b/src/dev/net/tcp_iface.cc
index c0bb02f..944b73c 100644
--- a/src/dev/net/tcp_iface.cc
+++ b/src/dev/net/tcp_iface.cc
@@ -72,6 +72,9 @@
#endif
#endif
+namespace gem5
+{
+
std::vector<std::pair<TCPIface::NodeInfo, int> > TCPIface::nodes;
std::vector<int> TCPIface::sockRegistry;
int TCPIface::fdStatic = -1;
@@ -340,3 +343,5 @@
// phase. That information is necessary for global connection ordering.
establishConnection();
}
+
+} // namespace gem5
diff --git a/src/dev/net/tcp_iface.hh b/src/dev/net/tcp_iface.hh
index 3e99a2d..32f2afc 100644
--- a/src/dev/net/tcp_iface.hh
+++ b/src/dev/net/tcp_iface.hh
@@ -54,6 +54,9 @@
#include "dev/net/dist_iface.hh"
+namespace gem5
+{
+
class EventManager;
class TCPIface : public DistIface
@@ -150,4 +153,6 @@
~TCPIface() override;
};
+} // namespace gem5
+
#endif // __DEV_NET_TCP_IFACE_HH__
diff --git a/src/dev/pci/CopyEngine.py b/src/dev/pci/CopyEngine.py
index 62d9bd7..a1888af 100644
--- a/src/dev/pci/CopyEngine.py
+++ b/src/dev/pci/CopyEngine.py
@@ -33,6 +33,7 @@
class CopyEngine(PciDevice):
type = 'CopyEngine'
cxx_header = "dev/pci/copy_engine.hh"
+ cxx_class = 'gem5::CopyEngine'
dma = VectorRequestPort("Copy engine DMA port")
VendorID = 0x8086
DeviceID = 0x1a38
diff --git a/src/dev/pci/PciDevice.py b/src/dev/pci/PciDevice.py
index 72473ce..cc794d1 100644
--- a/src/dev/pci/PciDevice.py
+++ b/src/dev/pci/PciDevice.py
@@ -44,25 +44,25 @@
class PciBar(SimObject):
type = 'PciBar'
- cxx_class = 'PciBar'
+ cxx_class = 'gem5::PciBar'
cxx_header = "dev/pci/device.hh"
abstract = True
class PciBarNone(PciBar):
type = 'PciBarNone'
- cxx_class = 'PciBarNone'
+ cxx_class = 'gem5::PciBarNone'
cxx_header = "dev/pci/device.hh"
class PciIoBar(PciBar):
type = 'PciIoBar'
- cxx_class = 'PciIoBar'
+ cxx_class = 'gem5::PciIoBar'
cxx_header = "dev/pci/device.hh"
size = Param.MemorySize32("IO region size")
class PciLegacyIoBar(PciIoBar):
type = 'PciLegacyIoBar'
- cxx_class = 'PciLegacyIoBar'
+ cxx_class = 'gem5::PciLegacyIoBar'
cxx_header = "dev/pci/device.hh"
addr = Param.UInt32("Legacy IO address")
@@ -73,19 +73,19 @@
# consumed.
class PciMemBar(PciBar):
type = 'PciMemBar'
- cxx_class = 'PciMemBar'
+ cxx_class = 'gem5::PciMemBar'
cxx_header = "dev/pci/device.hh"
size = Param.MemorySize("Memory region size")
class PciMemUpperBar(PciBar):
type = 'PciMemUpperBar'
- cxx_class = 'PciMemUpperBar'
+ cxx_class = 'gem5::PciMemUpperBar'
cxx_header = "dev/pci/device.hh"
class PciDevice(DmaDevice):
type = 'PciDevice'
- cxx_class = 'PciDevice'
+ cxx_class = 'gem5::PciDevice'
cxx_header = "dev/pci/device.hh"
abstract = True
diff --git a/src/dev/pci/PciHost.py b/src/dev/pci/PciHost.py
index 58ef6af..36a8856 100644
--- a/src/dev/pci/PciHost.py
+++ b/src/dev/pci/PciHost.py
@@ -41,13 +41,13 @@
class PciHost(PioDevice):
type = 'PciHost'
- cxx_class = 'PciHost'
+ cxx_class = 'gem5::PciHost'
cxx_header = "dev/pci/host.hh"
abstract = True
class GenericPciHost(PciHost):
type = 'GenericPciHost'
- cxx_class = 'GenericPciHost'
+ cxx_class = 'gem5::GenericPciHost'
cxx_header = "dev/pci/host.hh"
platform = Param.Platform(Parent.any, "Platform to use for interrupts")
diff --git a/src/dev/pci/copy_engine.cc b/src/dev/pci/copy_engine.cc
index 4189cc1..bc832c9 100644
--- a/src/dev/pci/copy_engine.cc
+++ b/src/dev/pci/copy_engine.cc
@@ -56,6 +56,9 @@
#include "sim/stats.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace copy_engine_reg;
CopyEngine::CopyEngine(const Params &p)
@@ -731,3 +734,5 @@
DPRINTF(DMACopyEngine, "Restarting state machine at state %d\n", nextState);
restartStateMachine();
}
+
+} // namespace gem5
diff --git a/src/dev/pci/copy_engine.hh b/src/dev/pci/copy_engine.hh
index c55baf6..f9441d3 100644
--- a/src/dev/pci/copy_engine.hh
+++ b/src/dev/pci/copy_engine.hh
@@ -55,6 +55,9 @@
#include "sim/drain.hh"
#include "sim/eventq.hh"
+namespace gem5
+{
+
class CopyEngine : public PciDevice
{
class CopyEngineChannel : public Drainable, public Serializable
@@ -176,5 +179,6 @@
void unserialize(CheckpointIn &cp) override;
};
-#endif //__DEV_PCI_COPY_ENGINE_HH__
+} // namespace gem5
+#endif //__DEV_PCI_COPY_ENGINE_HH__
diff --git a/src/dev/pci/copy_engine_defs.hh b/src/dev/pci/copy_engine_defs.hh
index 6fdcd6d..9e687e3 100644
--- a/src/dev/pci/copy_engine_defs.hh
+++ b/src/dev/pci/copy_engine_defs.hh
@@ -33,6 +33,9 @@
#include "base/compiler.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(CopyEngineReg, copy_engine_reg);
namespace copy_engine_reg
{
@@ -235,5 +238,4 @@
};
} // namespace copy_engine_reg
-
-
+} // namespace gem5
diff --git a/src/dev/pci/device.cc b/src/dev/pci/device.cc
index 9c5117b..e3d5bd8 100644
--- a/src/dev/pci/device.cc
+++ b/src/dev/pci/device.cc
@@ -59,6 +59,9 @@
#include "sim/byteswap.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
PciDevice::PciDevice(const PciDeviceParams &p)
: DmaDevice(p),
_busAddr(p.pci_bus, p.pci_dev, p.pci_func),
@@ -550,3 +553,5 @@
pxcap.pxdc2 = tmp32;
pioPort.sendRangeChange();
}
+
+} // namespace gem5
diff --git a/src/dev/pci/device.hh b/src/dev/pci/device.hh
index 7e82c44..dfa70b5 100644
--- a/src/dev/pci/device.hh
+++ b/src/dev/pci/device.hh
@@ -63,6 +63,9 @@
#define BAR_NUMBER(x) (((x) - PCI0_BASE_ADDR0) >> 0x2);
+namespace gem5
+{
+
class PciBar : public SimObject
{
protected:
@@ -392,4 +395,7 @@
const PciBusAddr &busAddr() const { return _busAddr; }
};
+
+} // namespace gem5
+
#endif // __DEV_PCI_DEVICE_HH__
diff --git a/src/dev/pci/host.cc b/src/dev/pci/host.cc
index 67acf70..e7dea6c 100644
--- a/src/dev/pci/host.cc
+++ b/src/dev/pci/host.cc
@@ -45,6 +45,9 @@
#include "params/GenericPciHost.hh"
#include "params/PciHost.hh"
+namespace gem5
+{
+
PciHost::PciHost(const PciHostParams &p)
: PioDevice(p)
{
@@ -217,3 +220,4 @@
return dev->interruptLine();
}
+} // namespace gem5
diff --git a/src/dev/pci/host.hh b/src/dev/pci/host.hh
index 8cf5f34..de36338 100644
--- a/src/dev/pci/host.hh
+++ b/src/dev/pci/host.hh
@@ -41,6 +41,9 @@
#include "dev/io_device.hh"
#include "dev/pci/types.hh"
+namespace gem5
+{
+
struct PciHostParams;
struct GenericPciHostParams;
@@ -90,7 +93,7 @@
*/
class DeviceInterface
{
- friend class ::PciHost;
+ friend class gem5::PciHost;
protected:
/**
@@ -325,4 +328,6 @@
const Addr pciDmaBase;
};
+} // namespace gem5
+
#endif // __DEV_PCI_HOST_HH__
diff --git a/src/dev/pci/types.hh b/src/dev/pci/types.hh
index e8fb525..630f0b1 100644
--- a/src/dev/pci/types.hh
+++ b/src/dev/pci/types.hh
@@ -38,6 +38,9 @@
#ifndef __DEV_PCI_TYPES_HH__
#define __DEV_PCI_TYPES_HH__
+namespace gem5
+{
+
struct PciBusAddr
{
public:
@@ -69,4 +72,6 @@
INTD
};
+} // namespace gem5
+
#endif // __DEV_PCI_TYPES_HH__
diff --git a/src/dev/pixelpump.cc b/src/dev/pixelpump.cc
index 0722f3e..8c8817b 100644
--- a/src/dev/pixelpump.cc
+++ b/src/dev/pixelpump.cc
@@ -39,6 +39,9 @@
#include "base/logging.hh"
+namespace gem5
+{
+
const DisplayTimings DisplayTimings::vga(
640, 480,
48, 96, 16,
@@ -355,3 +358,5 @@
suspended = false;
relativeTick = 0;
}
+
+} // namespace gem5
diff --git a/src/dev/pixelpump.hh b/src/dev/pixelpump.hh
index b2987bb..dc9bdc6 100644
--- a/src/dev/pixelpump.hh
+++ b/src/dev/pixelpump.hh
@@ -43,6 +43,9 @@
#include "base/framebuffer.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
struct BasePixelPumpParams;
struct DisplayTimings : public Serializable
@@ -362,4 +365,6 @@
bool _underrun;
};
+} // namespace gem5
+
#endif // __DEV_PIXELPUMP_HH__
diff --git a/src/dev/platform.cc b/src/dev/platform.cc
index 4d06a09..0174730 100644
--- a/src/dev/platform.cc
+++ b/src/dev/platform.cc
@@ -30,6 +30,9 @@
#include "base/logging.hh"
+namespace gem5
+{
+
Platform::Platform(const Params &p) : SimObject(p), system(p.system) {}
void
@@ -43,3 +46,5 @@
{
panic("No PCI interrupt support in platform.");
}
+
+} // namespace gem5
diff --git a/src/dev/platform.hh b/src/dev/platform.hh
index 572842a..e1ba64c 100644
--- a/src/dev/platform.hh
+++ b/src/dev/platform.hh
@@ -40,6 +40,9 @@
#include "params/Platform.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class Terminal;
class Uart;
class System;
@@ -75,4 +78,6 @@
virtual void clearPciInt(int line);
};
+} // namespace gem5
+
#endif // __DEV_PLATFORM_HH__
diff --git a/src/dev/ps2/PS2.py b/src/dev/ps2/PS2.py
index 3c31b6b..b017025 100644
--- a/src/dev/ps2/PS2.py
+++ b/src/dev/ps2/PS2.py
@@ -40,24 +40,24 @@
class PS2Device(SimObject):
type = 'PS2Device'
cxx_header = "dev/ps2/device.hh"
- cxx_class = "ps2::Device"
+ cxx_class = "gem5::ps2::Device"
abstract = True
class PS2Keyboard(PS2Device):
type = 'PS2Keyboard'
cxx_header = "dev/ps2/keyboard.hh"
- cxx_class = "ps2::PS2Keyboard"
+ cxx_class = "gem5::ps2::PS2Keyboard"
vnc = Param.VncInput(Parent.any, "VNC server providing keyboard input")
class PS2Mouse(PS2Device):
type = 'PS2Mouse'
cxx_header = "dev/ps2/mouse.hh"
- cxx_class = "ps2::PS2Mouse"
+ cxx_class = "gem5::ps2::PS2Mouse"
class PS2TouchKit(PS2Device):
type = 'PS2TouchKit'
cxx_header = "dev/ps2/touchkit.hh"
- cxx_class = "ps2::TouchKit"
+ cxx_class = "gem5::ps2::TouchKit"
vnc = Param.VncInput(Parent.any, "VNC server providing mouse input")
diff --git a/src/dev/ps2/device.cc b/src/dev/ps2/device.cc
index 71139e4..7ddc3c7 100644
--- a/src/dev/ps2/device.cc
+++ b/src/dev/ps2/device.cc
@@ -49,6 +49,9 @@
#include "params/PS2Device.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
namespace ps2
{
@@ -128,3 +131,4 @@
}
} // namespace ps2
+} // namespace gem5
diff --git a/src/dev/ps2/device.hh b/src/dev/ps2/device.hh
index 397529d..410a787 100644
--- a/src/dev/ps2/device.hh
+++ b/src/dev/ps2/device.hh
@@ -49,6 +49,9 @@
#include "base/compiler.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
struct PS2DeviceParams;
namespace ps2
@@ -149,7 +152,8 @@
};
} // namespace ps2
+} // namespace gem5
-GEM5_DEPRECATED_CLASS(PS2Device, ps2::Device);
+GEM5_DEPRECATED_CLASS(PS2Device, gem5::ps2::Device);
#endif // __DEV_PS2_HOUSE_HH__
diff --git a/src/dev/ps2/keyboard.cc b/src/dev/ps2/keyboard.cc
index 99fe636..fb63d48 100644
--- a/src/dev/ps2/keyboard.cc
+++ b/src/dev/ps2/keyboard.cc
@@ -49,6 +49,9 @@
#include "dev/ps2/types.hh"
#include "params/PS2Keyboard.hh"
+namespace gem5
+{
+
namespace ps2
{
@@ -179,3 +182,4 @@
}
} // namespace ps2
+} // namespace gem5
diff --git a/src/dev/ps2/keyboard.hh b/src/dev/ps2/keyboard.hh
index 603bcdb..ea63d97 100644
--- a/src/dev/ps2/keyboard.hh
+++ b/src/dev/ps2/keyboard.hh
@@ -44,6 +44,9 @@
#include "base/vnc/vncinput.hh"
#include "dev/ps2/device.hh"
+namespace gem5
+{
+
struct PS2KeyboardParams;
namespace ps2
@@ -72,5 +75,6 @@
};
} // namespace ps2
+} // namespace gem5
#endif // __DEV_PS2_KEYBOARD_hH__
diff --git a/src/dev/ps2/mouse.cc b/src/dev/ps2/mouse.cc
index c3f85b0..f87e1a0 100644
--- a/src/dev/ps2/mouse.cc
+++ b/src/dev/ps2/mouse.cc
@@ -47,6 +47,9 @@
#include "params/PS2Mouse.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
namespace ps2
{
@@ -172,3 +175,4 @@
}
} // namespace ps2
+} // namespace gem5
diff --git a/src/dev/ps2/mouse.hh b/src/dev/ps2/mouse.hh
index 19bc5ac..3304d95 100644
--- a/src/dev/ps2/mouse.hh
+++ b/src/dev/ps2/mouse.hh
@@ -44,6 +44,9 @@
#include "base/bitunion.hh"
#include "dev/ps2/device.hh"
+namespace gem5
+{
+
struct PS2MouseParams;
namespace ps2
@@ -75,6 +78,7 @@
};
} // namespace ps2
+} // namespace gem5
#endif // __DEV_PS2_MOUSE_hH__
diff --git a/src/dev/ps2/touchkit.cc b/src/dev/ps2/touchkit.cc
index fa1af6f..dbd4f88 100644
--- a/src/dev/ps2/touchkit.cc
+++ b/src/dev/ps2/touchkit.cc
@@ -49,6 +49,9 @@
#include "dev/ps2/types.hh"
#include "params/PS2TouchKit.hh"
+namespace gem5
+{
+
namespace ps2
{
@@ -212,3 +215,4 @@
}
} // namespace ps2
+} // namespace gem5
diff --git a/src/dev/ps2/touchkit.hh b/src/dev/ps2/touchkit.hh
index ec7526d..78831a3 100644
--- a/src/dev/ps2/touchkit.hh
+++ b/src/dev/ps2/touchkit.hh
@@ -42,6 +42,9 @@
#include "base/vnc/vncinput.hh"
#include "dev/ps2/device.hh"
+namespace gem5
+{
+
struct PS2TouchKitParams;
namespace ps2
@@ -94,7 +97,8 @@
};
} // namespace ps2
+} // namespace gem5
-GEM5_DEPRECATED_CLASS(PS2TouchKit, ps2::TouchKit);
+GEM5_DEPRECATED_CLASS(PS2TouchKit, gem5::ps2::TouchKit);
#endif // __DEV_PS2_TOUCHKIT_HH__
diff --git a/src/dev/ps2/types.cc b/src/dev/ps2/types.cc
index ad6c844..99e740e 100644
--- a/src/dev/ps2/types.cc
+++ b/src/dev/ps2/types.cc
@@ -42,6 +42,9 @@
#include "base/logging.hh"
#include "x11keysym/keysym.h"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Ps2, ps2);
namespace ps2
{
@@ -206,5 +209,5 @@
return;
}
-} /* namespace ps2 */
-
+} // namespace ps2
+} // namespace gem5
diff --git a/src/dev/ps2/types.hh b/src/dev/ps2/types.hh
index 04e632e..4ad7b05 100644
--- a/src/dev/ps2/types.hh
+++ b/src/dev/ps2/types.hh
@@ -50,6 +50,9 @@
* emulate ps2 devices
*/
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Ps2, ps2);
namespace ps2
{
@@ -133,5 +136,7 @@
void keySymToPs2(uint32_t key, bool down, bool &cur_shift,
std::list<uint8_t> &keys);
-} /* namespace ps2 */
+} // namespace ps2
+} // namespace gem5
+
#endif // __DEV_PS2_HH__
diff --git a/src/dev/reg_bank.hh b/src/dev/reg_bank.hh
index 5dee49e..44df906 100644
--- a/src/dev/reg_bank.hh
+++ b/src/dev/reg_bank.hh
@@ -286,6 +286,9 @@
* the RegisterBank.
*/
+namespace gem5
+{
+
// Common bases to make it easier to identify both endiannesses at once.
class RegisterBankBase
{
@@ -961,4 +964,6 @@
}
};
+} // namespace gem5
+
#endif // __DEV_REG_BANK_HH__
diff --git a/src/dev/reg_bank.test.cc b/src/dev/reg_bank.test.cc
index 088f1f3..534f862 100644
--- a/src/dev/reg_bank.test.cc
+++ b/src/dev/reg_bank.test.cc
@@ -57,6 +57,8 @@
#include "dev/reg_bank.hh"
+using namespace gem5;
+
// Compare the elements of an array against expected values.
using testing::ElementsAre;
// This version is needed with enough elements, empirically more than 10.
diff --git a/src/dev/riscv/Clint.py b/src/dev/riscv/Clint.py
index a9cf440..75c89aa 100644
--- a/src/dev/riscv/Clint.py
+++ b/src/dev/riscv/Clint.py
@@ -49,6 +49,7 @@
"""
type = 'Clint'
cxx_header = 'dev/riscv/clint.hh'
+ cxx_class = 'gem5::Clint'
int_pin = IntSinkPin('Pin to receive RTC signal')
pio_size = Param.Addr(0xC000, "PIO Size")
@@ -68,4 +69,4 @@
node.append(FdtPropertyWords("interrupts-extended", int_extended))
node.appendCompatible(["riscv,clint0"])
- yield node
\ No newline at end of file
+ yield node
diff --git a/src/dev/riscv/HiFive.py b/src/dev/riscv/HiFive.py
index 07b6806..8af2ddd 100755
--- a/src/dev/riscv/HiFive.py
+++ b/src/dev/riscv/HiFive.py
@@ -97,6 +97,7 @@
"""
type = 'HiFive'
cxx_header = "dev/riscv/hifive.hh"
+ cxx_class = 'gem5::HiFive'
# CLINT
clint = Param.Clint(Clint(pio_addr=0x2000000), "CLINT")
@@ -205,4 +206,4 @@
self.cpu_count += 1
int_node.append(FdtPropertyWords("phandle", [phandle]))
- cpu.append(int_node)
\ No newline at end of file
+ cpu.append(int_node)
diff --git a/src/dev/riscv/Plic.py b/src/dev/riscv/Plic.py
index 42b3f44..24ed5a5 100644
--- a/src/dev/riscv/Plic.py
+++ b/src/dev/riscv/Plic.py
@@ -48,6 +48,7 @@
"""
type = 'Plic'
cxx_header = 'dev/riscv/plic.hh'
+ cxx_class = 'gem5::Plic'
pio_size = Param.Addr(0x4000000, "PIO Size")
n_src = Param.Int("Number of interrupt sources")
@@ -76,4 +77,4 @@
node.append(FdtProperty("interrupt-controller"))
node.appendCompatible(["riscv,plic0"])
- yield node
\ No newline at end of file
+ yield node
diff --git a/src/dev/riscv/PlicDevice.py b/src/dev/riscv/PlicDevice.py
index f0b30c0..a124ee7 100644
--- a/src/dev/riscv/PlicDevice.py
+++ b/src/dev/riscv/PlicDevice.py
@@ -41,7 +41,9 @@
class PlicIntDevice(BasicPioDevice):
type = 'PlicIntDevice'
cxx_header = 'dev/riscv/plic_device.hh'
+ cxx_class = 'gem5::PlicIntDevice'
abstract = True
+
platform = Param.Platform(Parent.any, "Platform")
pio_size = Param.Addr("PIO Size")
interrupt_id = Param.Int("PLIC Interrupt ID")
diff --git a/src/dev/riscv/RTC.py b/src/dev/riscv/RTC.py
index 2de7d32..52bdd4c 100644
--- a/src/dev/riscv/RTC.py
+++ b/src/dev/riscv/RTC.py
@@ -40,7 +40,7 @@
class RiscvRTC(SimObject):
type = 'RiscvRTC'
- cxx_class='RiscvRTC'
+ cxx_class='gem5::RiscvRTC'
cxx_header = "dev/riscv/rtc.hh"
time = Param.Time('01/01/2012',
"System time to use")
@@ -48,4 +48,4 @@
# The default 1MHz setting is taken from SiFive's U54MC
# core complex. Set to other frequencies if necessary.
frequency = Param.Frequency("1MHz", "RTC Frequency")
- bcd = Param.Bool(False, "Binary Coded Decimal Mode for MC146818")
\ No newline at end of file
+ bcd = Param.Bool(False, "Binary Coded Decimal Mode for MC146818")
diff --git a/src/dev/riscv/VirtIOMMIO.py b/src/dev/riscv/VirtIOMMIO.py
index 06208df..6068a53 100644
--- a/src/dev/riscv/VirtIOMMIO.py
+++ b/src/dev/riscv/VirtIOMMIO.py
@@ -45,10 +45,11 @@
class MmioVirtIO(PlicIntDevice):
type = 'MmioVirtIO'
cxx_header = 'dev/riscv/vio_mmio.hh'
+ cxx_class = 'gem5::MmioVirtIO'
vio = Param.VirtIODeviceBase(VirtIODummyDevice(), "VirtIO device")
def generateDeviceTree(self, state):
node = self.generatePlicDeviceNode(state, "virtio_mmio")
node.appendCompatible(["virtio,mmio"])
- yield node
\ No newline at end of file
+ yield node
diff --git a/src/dev/riscv/clint.cc b/src/dev/riscv/clint.cc
index 21a4d93..0356af0 100644
--- a/src/dev/riscv/clint.cc
+++ b/src/dev/riscv/clint.cc
@@ -44,6 +44,9 @@
#include "params/Clint.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace RiscvISA;
Clint::Clint(const Params ¶ms) :
@@ -228,3 +231,5 @@
}
paramIn(cp, "mtime", registers.mtime);
}
+
+} // namespace gem5
diff --git a/src/dev/riscv/clint.hh b/src/dev/riscv/clint.hh
index 3d4234a..fad0995 100644
--- a/src/dev/riscv/clint.hh
+++ b/src/dev/riscv/clint.hh
@@ -48,6 +48,9 @@
#include "params/Clint.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace RiscvISA;
/**
@@ -143,5 +146,6 @@
};
+} // namespace gem5
#endif // __DEV_RISCV_CLINT_HH__
diff --git a/src/dev/riscv/hifive.cc b/src/dev/riscv/hifive.cc
index bd2e6f4..74ae346 100644
--- a/src/dev/riscv/hifive.cc
+++ b/src/dev/riscv/hifive.cc
@@ -42,6 +42,9 @@
#include "params/HiFive.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace RiscvISA;
HiFive::HiFive(const Params ¶ms) :
@@ -84,3 +87,5 @@
HiFive::unserialize(CheckpointIn &cp)
{
}
+
+} // namespace gem5
diff --git a/src/dev/riscv/hifive.hh b/src/dev/riscv/hifive.hh
index 87e9d7b..78d4504 100644
--- a/src/dev/riscv/hifive.hh
+++ b/src/dev/riscv/hifive.hh
@@ -43,6 +43,9 @@
#include "dev/riscv/plic.hh"
#include "params/HiFive.hh"
+namespace gem5
+{
+
using namespace RiscvISA;
class HiFive : public Platform
@@ -69,4 +72,6 @@
void unserialize(CheckpointIn &cp) override;
};
+} // namespace gem5
+
#endif // __DEV_RISCV_HIFIVE_HH__
diff --git a/src/dev/riscv/plic.cc b/src/dev/riscv/plic.cc
index 56a7838..4dea475 100644
--- a/src/dev/riscv/plic.cc
+++ b/src/dev/riscv/plic.cc
@@ -47,6 +47,9 @@
#include "params/Plic.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace RiscvISA;
Plic::Plic(const Params ¶ms) :
@@ -553,3 +556,5 @@
UNSERIALIZE_CONTAINER(lastID);
updateInt();
}
+
+} // namespace gem5
diff --git a/src/dev/riscv/plic.hh b/src/dev/riscv/plic.hh
index 2515f1b..d077e73 100644
--- a/src/dev/riscv/plic.hh
+++ b/src/dev/riscv/plic.hh
@@ -49,6 +49,9 @@
#include "params/Plic.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace RiscvISA;
/**
* NOTE:
@@ -279,5 +282,6 @@
void updateInt();
};
+} // namespace gem5
#endif // __DEV_RISCV_PLIC_HH__
diff --git a/src/dev/riscv/plic_device.cc b/src/dev/riscv/plic_device.cc
index dec5f63..34828cb 100644
--- a/src/dev/riscv/plic_device.cc
+++ b/src/dev/riscv/plic_device.cc
@@ -37,6 +37,9 @@
#include "dev/riscv/plic_device.hh"
+namespace gem5
+{
+
using namespace RiscvISA;
PlicIntDevice::PlicIntDevice(const Params ¶ms) :
@@ -45,4 +48,6 @@
platform(params.platform),
_interruptID(params.interrupt_id)
{
-}
\ No newline at end of file
+}
+
+} // namespace gem5
diff --git a/src/dev/riscv/plic_device.hh b/src/dev/riscv/plic_device.hh
index 75fbde4..a969b909 100644
--- a/src/dev/riscv/plic_device.hh
+++ b/src/dev/riscv/plic_device.hh
@@ -43,6 +43,9 @@
#include "params/PlicIntDevice.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace RiscvISA;
class PlicIntDevice : public BasicPioDevice
@@ -71,5 +74,6 @@
};
+} // namespace gem5
#endif // __DEV_RISCV_PLIC_DEVICE_HH__
diff --git a/src/dev/riscv/rtc.cc b/src/dev/riscv/rtc.cc
index 0f6e844..580c256 100644
--- a/src/dev/riscv/rtc.cc
+++ b/src/dev/riscv/rtc.cc
@@ -40,6 +40,9 @@
#include "dev/mc146818.hh"
#include "params/RiscvRTC.hh"
+namespace gem5
+{
+
RiscvRTC::RiscvRTC(const Params ¶ms) :
SimObject(params),
rtc(this, params.name, params.time, params.bcd,
@@ -94,3 +97,5 @@
// Serialize the timer
rtc.unserialize("rtc", cp);
}
+
+} // namespace gem5
diff --git a/src/dev/riscv/rtc.hh b/src/dev/riscv/rtc.hh
index 42a2d29..1d017ab 100644
--- a/src/dev/riscv/rtc.hh
+++ b/src/dev/riscv/rtc.hh
@@ -43,6 +43,9 @@
#include "params/RiscvRTC.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
/**
* NOTE:
* This is a generic wrapper around the MC146818 RTC
@@ -79,4 +82,6 @@
void unserialize(CheckpointIn &cp) override;
};
+} // namespace gem5
+
#endif //__DEV_RISCV_RTC_HH__
diff --git a/src/dev/riscv/vio_mmio.cc b/src/dev/riscv/vio_mmio.cc
index 686f94b..9f24ede 100644
--- a/src/dev/riscv/vio_mmio.cc
+++ b/src/dev/riscv/vio_mmio.cc
@@ -43,6 +43,9 @@
#include "mem/packet_access.hh"
#include "params/MmioVirtIO.hh"
+namespace gem5
+{
+
MmioVirtIO::MmioVirtIO(const MmioVirtIOParams ¶ms)
: PlicIntDevice(params),
hostFeaturesSelect(0), guestFeaturesSelect(0), pageSize(0),
@@ -271,3 +274,4 @@
}
}
+} // namespace gem5
diff --git a/src/dev/riscv/vio_mmio.hh b/src/dev/riscv/vio_mmio.hh
index 5cb89d5..50df354 100644
--- a/src/dev/riscv/vio_mmio.hh
+++ b/src/dev/riscv/vio_mmio.hh
@@ -43,6 +43,9 @@
#include "dev/riscv/plic_device.hh"
#include "dev/virtio/base.hh"
+namespace gem5
+{
+
struct MmioVirtIOParams;
class MmioVirtIO : public PlicIntDevice
@@ -110,4 +113,6 @@
VirtIODeviceBase &vio;
};
+} // namespace gem5
+
#endif // __DEV_ARM_VIO_MMIO_HH__
diff --git a/src/dev/serial/Serial.py b/src/dev/serial/Serial.py
index eb6b868..53af8ae 100644
--- a/src/dev/serial/Serial.py
+++ b/src/dev/serial/Serial.py
@@ -40,7 +40,9 @@
type = 'SerialDevice'
abstract = True
cxx_header = "dev/serial/serial.hh"
+ cxx_class = 'gem5::SerialDevice'
class SerialNullDevice(SerialDevice):
type = 'SerialNullDevice'
cxx_header = "dev/serial/serial.hh"
+ cxx_class = 'gem5::SerialNullDevice'
diff --git a/src/dev/serial/Terminal.py b/src/dev/serial/Terminal.py
index 49d5737..7604521 100644
--- a/src/dev/serial/Terminal.py
+++ b/src/dev/serial/Terminal.py
@@ -48,6 +48,7 @@
class Terminal(SerialDevice):
type = 'Terminal'
cxx_header = "dev/serial/terminal.hh"
+ cxx_class = 'gem5::Terminal'
port = Param.TcpPort(3456, "listen port")
number = Param.Int(0, "terminal number")
outfile = Param.TerminalDump("file",
diff --git a/src/dev/serial/Uart.py b/src/dev/serial/Uart.py
index 76ac066..aecdfe3 100644
--- a/src/dev/serial/Uart.py
+++ b/src/dev/serial/Uart.py
@@ -48,12 +48,14 @@
type = 'Uart'
abstract = True
cxx_header = "dev/serial/uart.hh"
+ cxx_class = 'gem5::Uart'
platform = Param.Platform(Parent.any, "Platform this device is part of.")
device = Param.SerialDevice(Parent.any, "The terminal")
class SimpleUart(Uart):
type = 'SimpleUart'
cxx_header = "dev/serial/simple.hh"
+ cxx_class = 'gem5::SimpleUart'
byte_order = Param.ByteOrder("little", "Device byte order")
pio_size = Param.Addr(0x4, "Size of address range")
end_on_eot = Param.Bool(False, "End the simulation when a EOT is "\
@@ -62,6 +64,7 @@
class Uart8250(Uart):
type = 'Uart8250'
cxx_header = "dev/serial/uart8250.hh"
+ cxx_class = 'gem5::Uart8250'
pio_size = Param.Addr(0x8, "Size of address range")
def generateDeviceTree(self, state):
diff --git a/src/dev/serial/serial.cc b/src/dev/serial/serial.cc
index 6910638..1d2203f 100644
--- a/src/dev/serial/serial.cc
+++ b/src/dev/serial/serial.cc
@@ -41,6 +41,9 @@
#include "params/SerialDevice.hh"
#include "params/SerialNullDevice.hh"
+namespace gem5
+{
+
SerialDevice::SerialDevice(const SerialDeviceParams &p) : SimObject(p)
{
}
@@ -82,3 +85,5 @@
{
panic("SerialNullDevice does not have pending data.\n");
}
+
+} // namespace gem5
diff --git a/src/dev/serial/serial.hh b/src/dev/serial/serial.hh
index 5ba4f70..06d8c5f 100644
--- a/src/dev/serial/serial.hh
+++ b/src/dev/serial/serial.hh
@@ -42,6 +42,9 @@
#include "sim/sim_object.hh"
+namespace gem5
+{
+
struct SerialDeviceParams;
struct SerialNullDeviceParams;
@@ -154,4 +157,6 @@
uint8_t readData() override;
};
+} // namespace gem5
+
#endif // __DEV_SERIAL_HH__
diff --git a/src/dev/serial/simple.cc b/src/dev/serial/simple.cc
index 811991b..cf1d963 100644
--- a/src/dev/serial/simple.cc
+++ b/src/dev/serial/simple.cc
@@ -42,6 +42,9 @@
#include "params/SimpleUart.hh"
#include "sim/sim_exit.hh"
+namespace gem5
+{
+
SimpleUart::SimpleUart(const SimpleUartParams &p)
: Uart(p, p.pio_size), byteOrder(p.byte_order), endOnEOT(p.end_on_eot)
{
@@ -78,3 +81,5 @@
pkt->makeAtomicResponse();
return pioDelay;
}
+
+} // namespace gem5
diff --git a/src/dev/serial/simple.hh b/src/dev/serial/simple.hh
index 3d841f0..c80dc4c 100644
--- a/src/dev/serial/simple.hh
+++ b/src/dev/serial/simple.hh
@@ -41,6 +41,9 @@
#include "dev/serial/uart.hh"
+namespace gem5
+{
+
struct SimpleUartParams;
class SimpleUart : public Uart
@@ -64,4 +67,6 @@
const bool endOnEOT;
};
+} // namespace gem5
+
#endif // __DEV_SERIAL_SIMPLE_HH__
diff --git a/src/dev/serial/terminal.cc b/src/dev/serial/terminal.cc
index 67cc643..feb0e09 100644
--- a/src/dev/serial/terminal.cc
+++ b/src/dev/serial/terminal.cc
@@ -73,6 +73,9 @@
#include "dev/platform.hh"
#include "dev/serial/uart.hh"
+namespace gem5
+{
+
/*
* Poll event for the listen socket
*/
@@ -356,3 +359,5 @@
isprint(c) ? c : ' ', (int)c);
}
+
+} // namespace gem5
diff --git a/src/dev/serial/terminal.hh b/src/dev/serial/terminal.hh
index ba93998..83ea64b 100644
--- a/src/dev/serial/terminal.hh
+++ b/src/dev/serial/terminal.hh
@@ -55,6 +55,9 @@
#include "params/Terminal.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class OutputStream;
class TerminalListener;
@@ -147,4 +150,6 @@
uint64_t console_in();
};
+} // namespace gem5
+
#endif // __DEV_TERMINAL_HH__
diff --git a/src/dev/serial/uart.cc b/src/dev/serial/uart.cc
index 60edf71..d69346f 100644
--- a/src/dev/serial/uart.cc
+++ b/src/dev/serial/uart.cc
@@ -32,6 +32,9 @@
#include "dev/serial/uart.hh"
+namespace gem5
+{
+
Uart::Uart(const Params &p, Addr pio_size) :
BasicPioDevice(p, pio_size), platform(p.platform), device(p.device)
{
@@ -40,3 +43,5 @@
// setup serial device callbacks
device->regInterfaceCallback([this]() { dataAvailable(); });
}
+
+} // namespace gem5
diff --git a/src/dev/serial/uart.hh b/src/dev/serial/uart.hh
index 770e7a0..3ede3ba 100644
--- a/src/dev/serial/uart.hh
+++ b/src/dev/serial/uart.hh
@@ -38,6 +38,9 @@
#include "dev/serial/serial.hh"
#include "params/Uart.hh"
+namespace gem5
+{
+
class Platform;
const int RX_INT = 0x1;
@@ -66,4 +69,6 @@
bool intStatus() { return status ? true : false; }
};
+} // namespace gem5
+
#endif // __UART_HH__
diff --git a/src/dev/serial/uart8250.cc b/src/dev/serial/uart8250.cc
index bced0e2..a2f13be 100644
--- a/src/dev/serial/uart8250.cc
+++ b/src/dev/serial/uart8250.cc
@@ -43,6 +43,9 @@
#include "mem/packet_access.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
void
Uart8250::processIntrEvent(int intrBit)
{
@@ -293,3 +296,5 @@
if (txintrwhen != 0)
schedule(txIntrEvent, txintrwhen);
}
+
+} // namespace gem5
diff --git a/src/dev/serial/uart8250.hh b/src/dev/serial/uart8250.hh
index a4eb2c7..c55d889 100644
--- a/src/dev/serial/uart8250.hh
+++ b/src/dev/serial/uart8250.hh
@@ -40,6 +40,9 @@
#include "dev/serial/uart.hh"
#include "params/Uart8250.hh"
+namespace gem5
+{
+
const uint8_t UART_MCR_LOOP = 0x10;
class Terminal;
@@ -233,4 +236,6 @@
void unserialize(CheckpointIn &cp) override;
};
+} // namespace gem5
+
#endif // __TSUNAMI_UART_HH__
diff --git a/src/dev/sparc/T1000.py b/src/dev/sparc/T1000.py
index 299d6b2..f2d87e7 100644
--- a/src/dev/sparc/T1000.py
+++ b/src/dev/sparc/T1000.py
@@ -36,18 +36,21 @@
class MmDisk(BasicPioDevice):
type = 'MmDisk'
cxx_header = "dev/sparc/mm_disk.hh"
+ cxx_class = 'gem5::MmDisk'
image = Param.DiskImage("Disk Image")
pio_addr = 0x1F40000000
class DumbTOD(BasicPioDevice):
type = 'DumbTOD'
cxx_header = "dev/sparc/dtod.hh"
+ cxx_class = 'gem5::DumbTOD'
time = Param.Time('01/01/2009', "System time to use ('Now' for real time)")
pio_addr = 0xfff0c1fff8
class Iob(PioDevice):
type = 'Iob'
cxx_header = "dev/sparc/iob.hh"
+ cxx_class = 'gem5::Iob'
platform = Param.Platform(Parent.any, "Platform this device is part of.")
pio_latency = Param.Latency('1ns', "Programed IO latency")
@@ -55,6 +58,7 @@
class T1000(Platform):
type = 'T1000'
cxx_header = "dev/sparc/t1000.hh"
+ cxx_class = 'gem5::T1000'
fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000)
#warn_access="Accessing Clock Unit -- Unimplemented!")
diff --git a/src/dev/sparc/dtod.cc b/src/dev/sparc/dtod.cc
index b36b7f5..145d332 100644
--- a/src/dev/sparc/dtod.cc
+++ b/src/dev/sparc/dtod.cc
@@ -44,6 +44,9 @@
#include "mem/port.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
DumbTOD::DumbTOD(const Params &p)
: BasicPioDevice(p, 0x08)
{
@@ -84,3 +87,5 @@
{
UNSERIALIZE_SCALAR(todTime);
}
+
+} // namespace gem5
diff --git a/src/dev/sparc/dtod.hh b/src/dev/sparc/dtod.hh
index deb39f1..2eb2373 100644
--- a/src/dev/sparc/dtod.hh
+++ b/src/dev/sparc/dtod.hh
@@ -39,6 +39,9 @@
#include "dev/io_device.hh"
#include "params/DumbTOD.hh"
+namespace gem5
+{
+
/**
* DumbTOD simply returns some idea of time when read. Until we finish with
* legion it starts with the start time and increments itself by 1000 each time.
@@ -59,4 +62,6 @@
void unserialize(CheckpointIn &cp) override;
};
+} // namespace gem5
+
#endif // __DEV_BADDEV_HH__
diff --git a/src/dev/sparc/iob.cc b/src/dev/sparc/iob.cc
index fbc3b58..83bd714 100644
--- a/src/dev/sparc/iob.cc
+++ b/src/dev/sparc/iob.cc
@@ -50,6 +50,9 @@
#include "sim/faults.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
Iob::Iob(const Params &p) : PioDevice(p)
{
iobManAddr = 0x9800000000ULL;
@@ -382,3 +385,5 @@
paramIn(cp, "source", jIntBusy[x].source);
};
}
+
+} // namespace gem5
diff --git a/src/dev/sparc/iob.hh b/src/dev/sparc/iob.hh
index 4c981ed..85d24a1 100644
--- a/src/dev/sparc/iob.hh
+++ b/src/dev/sparc/iob.hh
@@ -37,6 +37,9 @@
#include "dev/io_device.hh"
#include "params/Iob.hh"
+namespace gem5
+{
+
const int MaxNiagaraProcs = 32;
// IOB Managment Addresses
const Addr IntManAddr = 0x0000;
@@ -139,5 +142,6 @@
void unserialize(CheckpointIn &cp) override;
};
-#endif //__DEV_SPARC_IOB_HH__
+} // namespace gem5
+#endif //__DEV_SPARC_IOB_HH__
diff --git a/src/dev/sparc/mm_disk.cc b/src/dev/sparc/mm_disk.cc
index f1da2b9..ae6fca0 100644
--- a/src/dev/sparc/mm_disk.cc
+++ b/src/dev/sparc/mm_disk.cc
@@ -43,6 +43,9 @@
#include "sim/byteswap.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
MmDisk::MmDisk(const Params &p)
: BasicPioDevice(p, p.image->size() * SectorSize),
image(p.image), curSector((off_t)-1), dirty(false)
@@ -182,3 +185,5 @@
}
ClockedObject::serialize(cp);
}
+
+} // namespace gem5
diff --git a/src/dev/sparc/mm_disk.hh b/src/dev/sparc/mm_disk.hh
index 645f346..c6c1120 100644
--- a/src/dev/sparc/mm_disk.hh
+++ b/src/dev/sparc/mm_disk.hh
@@ -38,6 +38,9 @@
#include "dev/storage/disk_image.hh"
#include "params/MmDisk.hh"
+namespace gem5
+{
+
class MmDisk : public BasicPioDevice
{
private:
@@ -56,5 +59,6 @@
void serialize(CheckpointOut &cp) const override;
};
-#endif //__DEV_SPARC_MM_DISK_HH__
+} // namespace gem5
+#endif //__DEV_SPARC_MM_DISK_HH__
diff --git a/src/dev/sparc/t1000.cc b/src/dev/sparc/t1000.cc
index 783dd3f..e879a6e 100644
--- a/src/dev/sparc/t1000.cc
+++ b/src/dev/sparc/t1000.cc
@@ -34,6 +34,9 @@
#include "base/logging.hh"
+namespace gem5
+{
+
T1000::T1000(const Params &p) : Platform(p) {}
void
@@ -61,3 +64,5 @@
{
panic("Need implementation\n");
}
+
+} // namespace gem5
diff --git a/src/dev/sparc/t1000.hh b/src/dev/sparc/t1000.hh
index 94a7cac..d98cc26 100644
--- a/src/dev/sparc/t1000.hh
+++ b/src/dev/sparc/t1000.hh
@@ -38,6 +38,9 @@
#include "dev/platform.hh"
#include "params/T1000.hh"
+namespace gem5
+{
+
class T1000 : public Platform
{
public:
@@ -71,4 +74,6 @@
virtual void clearPciInt(int line);
};
+} // namespace gem5
+
#endif // __DEV_T1000_HH__
diff --git a/src/dev/storage/DiskImage.py b/src/dev/storage/DiskImage.py
index 5815899..d0942b8 100644
--- a/src/dev/storage/DiskImage.py
+++ b/src/dev/storage/DiskImage.py
@@ -30,16 +30,19 @@
type = 'DiskImage'
abstract = True
cxx_header = "dev/storage/disk_image.hh"
+ cxx_class = 'gem5::DiskImage'
image_file = Param.String("disk image file")
read_only = Param.Bool(False, "read only image")
class RawDiskImage(DiskImage):
type = 'RawDiskImage'
cxx_header = "dev/storage/disk_image.hh"
+ cxx_class = 'gem5::RawDiskImage'
class CowDiskImage(DiskImage):
type = 'CowDiskImage'
cxx_header = "dev/storage/disk_image.hh"
+ cxx_class = 'gem5::CowDiskImage'
child = Param.DiskImage(RawDiskImage(read_only=True),
"child image")
table_size = Param.Int(65536, "initial table size")
diff --git a/src/dev/storage/Ide.py b/src/dev/storage/Ide.py
index 01bd759..0b1890e 100644
--- a/src/dev/storage/Ide.py
+++ b/src/dev/storage/Ide.py
@@ -33,6 +33,7 @@
class IdeDisk(SimObject):
type = 'IdeDisk'
cxx_header = "dev/storage/ide_disk.hh"
+ cxx_class = 'gem5::IdeDisk'
delay = Param.Latency('1us', "Fixed disk delay in microseconds")
driveID = Param.IdeID('device0', "Drive ID")
image = Param.DiskImage("Disk image")
@@ -40,6 +41,7 @@
class IdeController(PciDevice):
type = 'IdeController'
cxx_header = "dev/storage/ide_ctrl.hh"
+ cxx_class = 'gem5::IdeController'
disks = VectorParam.IdeDisk("IDE disks attached to this controller")
VendorID = 0x8086
diff --git a/src/dev/storage/SimpleDisk.py b/src/dev/storage/SimpleDisk.py
index e120ed1..b59d5af 100644
--- a/src/dev/storage/SimpleDisk.py
+++ b/src/dev/storage/SimpleDisk.py
@@ -31,5 +31,6 @@
class SimpleDisk(SimObject):
type = 'SimpleDisk'
cxx_header = "dev/storage/simple_disk.hh"
+ cxx_class = 'gem5::SimpleDisk'
disk = Param.DiskImage("Disk Image")
system = Param.System(Parent.any, "System Pointer")
diff --git a/src/dev/storage/disk_image.cc b/src/dev/storage/disk_image.cc
index 2bb702b..9f0afa6 100644
--- a/src/dev/storage/disk_image.cc
+++ b/src/dev/storage/disk_image.cc
@@ -50,6 +50,9 @@
#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
+namespace gem5
+{
+
////////////////////////////////////////////////////////////////////////
//
// Raw Disk image
@@ -434,3 +437,5 @@
cowFilename = cp.getCptDir() + "/" + cowFilename;
open(cowFilename);
}
+
+} // namespace gem5
diff --git a/src/dev/storage/disk_image.hh b/src/dev/storage/disk_image.hh
index e9d311c..74d6f40 100644
--- a/src/dev/storage/disk_image.hh
+++ b/src/dev/storage/disk_image.hh
@@ -43,6 +43,9 @@
#define SectorSize (512)
+namespace gem5
+{
+
/**
* Basic interface for accessing a disk image.
*/
@@ -157,4 +160,7 @@
template<class T>
void SafeWriteSwap(std::ofstream &stream, const T &data);
+} // namespace gem5
+
+
#endif // __DEV_STORAGE_DISK_IMAGE_HH__
diff --git a/src/dev/storage/ide_ctrl.cc b/src/dev/storage/ide_ctrl.cc
index 66d9e78..7d4ecac 100644
--- a/src/dev/storage/ide_ctrl.cc
+++ b/src/dev/storage/ide_ctrl.cc
@@ -54,6 +54,9 @@
// we open up the entire namespace std
using std::string;
+namespace gem5
+{
+
// Bus master IDE registers
enum BMIRegOffset
{
@@ -446,3 +449,5 @@
paramIn(cp, base + ".selectBit", selectBit);
select(selectBit);
}
+
+} // namespace gem5
diff --git a/src/dev/storage/ide_ctrl.hh b/src/dev/storage/ide_ctrl.hh
index b1ce0e8..cf6a58b 100644
--- a/src/dev/storage/ide_ctrl.hh
+++ b/src/dev/storage/ide_ctrl.hh
@@ -40,6 +40,9 @@
#include "dev/reg_bank.hh"
#include "params/IdeController.hh"
+namespace gem5
+{
+
class IdeDisk;
/**
@@ -184,4 +187,7 @@
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
+
+} // namespace gem5
+
#endif // __DEV_STORAGE_IDE_CTRL_HH_
diff --git a/src/dev/storage/ide_disk.cc b/src/dev/storage/ide_disk.cc
index 5cedbe5..fbbcfa4 100644
--- a/src/dev/storage/ide_disk.cc
+++ b/src/dev/storage/ide_disk.cc
@@ -59,6 +59,9 @@
#include "sim/core.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
IdeDisk::IdeDisk(const Params &p)
: SimObject(p), ctrl(NULL), image(p.image), diskDelay(p.delay),
ideDiskStats(this),
@@ -1184,3 +1187,5 @@
UNSERIALIZE_ENUM(dmaState);
UNSERIALIZE_ARRAY(dataBuffer, MAX_DMA_SIZE);
}
+
+} // namespace gem5
diff --git a/src/dev/storage/ide_disk.hh b/src/dev/storage/ide_disk.hh
index ee94d66..bfe9f9b 100644
--- a/src/dev/storage/ide_disk.hh
+++ b/src/dev/storage/ide_disk.hh
@@ -54,6 +54,9 @@
#include "params/IdeDisk.hh"
#include "sim/eventq.hh"
+namespace gem5
+{
+
class ChunkGenerator;
#define DMA_BACKOFF_PERIOD 200
@@ -374,5 +377,6 @@
void unserialize(CheckpointIn &cp) override;
};
+} // namespace gem5
#endif // __DEV_STORAGE_IDE_DISK_HH__
diff --git a/src/dev/storage/simple_disk.cc b/src/dev/storage/simple_disk.cc
index e52526b..4a543b6 100644
--- a/src/dev/storage/simple_disk.cc
+++ b/src/dev/storage/simple_disk.cc
@@ -48,6 +48,9 @@
#include "mem/port_proxy.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
SimpleDisk::SimpleDisk(const Params &p)
: SimObject(p), system(p.system), image(p.disk)
{}
@@ -80,3 +83,5 @@
{
panic("unimplemented!\n");
}
+
+} // namespace gem5
diff --git a/src/dev/storage/simple_disk.hh b/src/dev/storage/simple_disk.hh
index e0442c6..149f945 100644
--- a/src/dev/storage/simple_disk.hh
+++ b/src/dev/storage/simple_disk.hh
@@ -36,6 +36,9 @@
#include "params/SimpleDisk.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class DiskImage;
class System;
@@ -60,4 +63,6 @@
void write(Addr addr, baddr_t block, int count);
};
+} // namespace gem5
+
#endif // __DEV_STORAGE_SIMPLE_DISK_HH__
diff --git a/src/dev/virtio/VirtIO.py b/src/dev/virtio/VirtIO.py
index 56c9248..b0ddb0e 100644
--- a/src/dev/virtio/VirtIO.py
+++ b/src/dev/virtio/VirtIO.py
@@ -45,6 +45,7 @@
class VirtIODeviceBase(SimObject):
type = 'VirtIODeviceBase'
cxx_header = 'dev/virtio/base.hh'
+ cxx_class = 'gem5::VirtIODeviceBase'
abstract = True
subsystem = Param.UInt8(0x00, "VirtIO subsystem ID")
@@ -55,10 +56,12 @@
class VirtIODummyDevice(VirtIODeviceBase):
type = 'VirtIODummyDevice'
cxx_header = 'dev/virtio/base.hh'
+ cxx_class = 'gem5::VirtIODummyDevice'
class PciVirtIO(PciDevice):
type = 'PciVirtIO'
cxx_header = 'dev/virtio/pci.hh'
+ cxx_class = 'gem5::PciVirtIO'
vio = Param.VirtIODeviceBase(VirtIODummyDevice(), "VirtIO device")
diff --git a/src/dev/virtio/VirtIO9P.py b/src/dev/virtio/VirtIO9P.py
index a6f4803..84e1a7b 100644
--- a/src/dev/virtio/VirtIO9P.py
+++ b/src/dev/virtio/VirtIO9P.py
@@ -43,6 +43,7 @@
type = 'VirtIO9PBase'
abstract = True
cxx_header = 'dev/virtio/fs9p.hh'
+ cxx_class = 'gem5::VirtIO9PBase'
queueSize = Param.Unsigned(32, "Output queue size (pages)")
tag = Param.String("gem5", "Mount tag")
@@ -52,10 +53,12 @@
type = 'VirtIO9PProxy'
abstract = True
cxx_header = 'dev/virtio/fs9p.hh'
+ cxx_class = 'gem5::VirtIO9PProxy'
class VirtIO9PDiod(VirtIO9PProxy):
type = 'VirtIO9PDiod'
cxx_header = 'dev/virtio/fs9p.hh'
+ cxx_class = 'gem5::VirtIO9PDiod'
diod = Param.String("diod", "Path to diod, optionally in PATH")
root = Param.String("Path to export through diod")
@@ -64,6 +67,7 @@
class VirtIO9PSocket(VirtIO9PProxy):
type = 'VirtIO9PSocket'
cxx_header = 'dev/virtio/fs9p.hh'
+ cxx_class = 'gem5::VirtIO9PSocket'
server = Param.String("127.0.0.1", "9P server address or host name")
port = Param.String("564", "9P server port")
diff --git a/src/dev/virtio/VirtIOBlock.py b/src/dev/virtio/VirtIOBlock.py
index eab8e18..25afd24 100644
--- a/src/dev/virtio/VirtIOBlock.py
+++ b/src/dev/virtio/VirtIOBlock.py
@@ -42,6 +42,7 @@
class VirtIOBlock(VirtIODeviceBase):
type = 'VirtIOBlock'
cxx_header = 'dev/virtio/block.hh'
+ cxx_class = 'gem5::VirtIOBlock'
queueSize = Param.Unsigned(128, "Output queue size (pages)")
diff --git a/src/dev/virtio/VirtIOConsole.py b/src/dev/virtio/VirtIOConsole.py
index 92f4108..41c419a 100644
--- a/src/dev/virtio/VirtIOConsole.py
+++ b/src/dev/virtio/VirtIOConsole.py
@@ -43,6 +43,7 @@
class VirtIOConsole(VirtIODeviceBase):
type = 'VirtIOConsole'
cxx_header = 'dev/virtio/console.hh'
+ cxx_class = 'gem5::VirtIOConsole'
qRecvSize = Param.Unsigned(16, "Receive queue size (descriptors)")
qTransSize = Param.Unsigned(16, "Transmit queue size (descriptors)")
diff --git a/src/dev/virtio/base.cc b/src/dev/virtio/base.cc
index 17fe9c8..7fe08095 100644
--- a/src/dev/virtio/base.cc
+++ b/src/dev/virtio/base.cc
@@ -43,6 +43,9 @@
#include "params/VirtIODummyDevice.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
VirtDescriptor::VirtDescriptor(PortProxy &_memProxy, ByteOrder bo,
VirtQueue &_queue, Index descIndex)
: memProxy(&_memProxy), queue(&_queue), byteOrder(bo), _index(descIndex),
@@ -495,3 +498,5 @@
: VirtIODeviceBase(params, ID_INVALID, 0, 0)
{
}
+
+} // namespace gem5
diff --git a/src/dev/virtio/base.hh b/src/dev/virtio/base.hh
index 6eeb4a4..0e173e2 100644
--- a/src/dev/virtio/base.hh
+++ b/src/dev/virtio/base.hh
@@ -50,6 +50,9 @@
#include "sim/serialize.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
struct VirtIODeviceBaseParams;
struct VirtIODummyDeviceParams;
@@ -910,4 +913,6 @@
static const DeviceId ID_INVALID = 0x00;
};
+} // namespace gem5
+
#endif // __DEV_VIRTIO_BASE_HH__
diff --git a/src/dev/virtio/block.cc b/src/dev/virtio/block.cc
index 2a08a8b..8f8e7f5 100644
--- a/src/dev/virtio/block.cc
+++ b/src/dev/virtio/block.cc
@@ -41,6 +41,9 @@
#include "params/VirtIOBlock.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
VirtIOBlock::VirtIOBlock(const Params ¶ms)
: VirtIODeviceBase(params, ID_BLOCK, sizeof(Config), 0),
qRequests(params.system->physProxy, byteOrder,
@@ -164,3 +167,5 @@
produceDescriptor(desc, sizeof(BlkRequest) + data_size + sizeof(Status));
parent.kick();
}
+
+} // namespace gem5
diff --git a/src/dev/virtio/block.hh b/src/dev/virtio/block.hh
index ba28400..271c4e3 100644
--- a/src/dev/virtio/block.hh
+++ b/src/dev/virtio/block.hh
@@ -42,6 +42,9 @@
#include "dev/storage/disk_image.hh"
#include "dev/virtio/base.hh"
+namespace gem5
+{
+
struct VirtIOBlockParams;
/**
@@ -184,4 +187,6 @@
DiskImage ℑ
};
+} // namespace gem5
+
#endif // __DEV_VIRTIO_BLOCK_HH__
diff --git a/src/dev/virtio/console.cc b/src/dev/virtio/console.cc
index 8f5d3f7..454216e 100644
--- a/src/dev/virtio/console.cc
+++ b/src/dev/virtio/console.cc
@@ -41,6 +41,9 @@
#include "params/VirtIOConsole.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
VirtIOConsole::VirtIOConsole(const Params ¶ms)
: VirtIODeviceBase(params, ID_CONSOLE, sizeof(Config), F_SIZE),
qRecv(params.system->physProxy, byteOrder, params.qRecvSize, *this),
@@ -112,3 +115,5 @@
produceDescriptor(desc, 0);
parent.kick();
}
+
+} // namespace gem5
diff --git a/src/dev/virtio/console.hh b/src/dev/virtio/console.hh
index b7d2656..7740376 100644
--- a/src/dev/virtio/console.hh
+++ b/src/dev/virtio/console.hh
@@ -42,6 +42,9 @@
#include "dev/serial/serial.hh"
#include "dev/virtio/base.hh"
+namespace gem5
+{
+
struct VirtIOConsoleParams;
/**
@@ -152,4 +155,6 @@
SerialDevice &device;
};
+} // namespace gem5
+
#endif // __DEV_VIRTIO_CONSOLE_HH__
diff --git a/src/dev/virtio/fs9p.cc b/src/dev/virtio/fs9p.cc
index 4b7ae07..737ea98 100644
--- a/src/dev/virtio/fs9p.cc
+++ b/src/dev/virtio/fs9p.cc
@@ -60,6 +60,9 @@
#include "params/VirtIO9PSocket.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
struct P9MsgInfo
{
P9MsgInfo(P9MsgType _type, std::string _name)
@@ -554,3 +557,5 @@
{
parent.serverDataReady();
}
+
+} // namespace gem5
diff --git a/src/dev/virtio/fs9p.hh b/src/dev/virtio/fs9p.hh
index 2106052..423fa9c 100644
--- a/src/dev/virtio/fs9p.hh
+++ b/src/dev/virtio/fs9p.hh
@@ -46,6 +46,9 @@
#include "base/pollevent.hh"
#include "dev/virtio/base.hh"
+namespace gem5
+{
+
struct VirtIO9PBaseParams;
typedef uint8_t P9MsgType;
@@ -384,4 +387,6 @@
std::unique_ptr<SocketDataEvent> dataEvent;
};
+} // namespace gem5
+
#endif // __DEV_VIRTIO_FS9P_HH__
diff --git a/src/dev/virtio/pci.cc b/src/dev/virtio/pci.cc
index f0d60b0..8b2ae5b 100644
--- a/src/dev/virtio/pci.cc
+++ b/src/dev/virtio/pci.cc
@@ -43,6 +43,9 @@
#include "mem/packet_access.hh"
#include "params/PciVirtIO.hh"
+namespace gem5
+{
+
PciVirtIO::PciVirtIO(const Params ¶ms)
: PciDevice(params), queueNotify(0), interruptDeliveryPending(false),
vio(*params.vio)
@@ -223,3 +226,5 @@
interruptDeliveryPending = true;
intrPost();
}
+
+} // namespace gem5
diff --git a/src/dev/virtio/pci.hh b/src/dev/virtio/pci.hh
index 598f07e..9a25ba1 100644
--- a/src/dev/virtio/pci.hh
+++ b/src/dev/virtio/pci.hh
@@ -42,6 +42,9 @@
#include "dev/virtio/base.hh"
#include "dev/pci/device.hh"
+namespace gem5
+{
+
struct PciVirtIOParams;
class PciVirtIO : public PciDevice
@@ -82,4 +85,6 @@
VirtIODeviceBase &vio;
};
+} // namespace gem5
+
#endif // __DEV_VIRTIO_PCI_HH__
diff --git a/src/dev/x86/Cmos.py b/src/dev/x86/Cmos.py
index e9e2d5a..14f9e45 100644
--- a/src/dev/x86/Cmos.py
+++ b/src/dev/x86/Cmos.py
@@ -31,8 +31,9 @@
class Cmos(BasicPioDevice):
type = 'Cmos'
- cxx_class='X86ISA::Cmos'
+ cxx_class='gem5::X86ISA::Cmos'
cxx_header = "dev/x86/cmos.hh"
+
time = Param.Time('01/01/2012',
"System time to use ('Now' for actual time)")
int_pin = IntSourcePin('Pin to signal RTC alarm interrupts to')
diff --git a/src/dev/x86/I8042.py b/src/dev/x86/I8042.py
index 7f77f2b..d2d9a17 100644
--- a/src/dev/x86/I8042.py
+++ b/src/dev/x86/I8042.py
@@ -32,8 +32,9 @@
class I8042(BasicPioDevice):
type = 'I8042'
- cxx_class = 'X86ISA::I8042'
+ cxx_class = 'gem5::X86ISA::I8042'
cxx_header = "dev/x86/i8042.hh"
+
# This isn't actually used for anything here.
pio_addr = 0x0
data_port = Param.Addr('Data port address')
diff --git a/src/dev/x86/I82094AA.py b/src/dev/x86/I82094AA.py
index ce1f394..212bca3 100644
--- a/src/dev/x86/I82094AA.py
+++ b/src/dev/x86/I82094AA.py
@@ -31,8 +31,9 @@
class I82094AA(BasicPioDevice):
type = 'I82094AA'
- cxx_class = 'X86ISA::I82094AA'
+ cxx_class = 'gem5::X86ISA::I82094AA'
cxx_header = "dev/x86/i82094aa.hh"
+
apic_id = Param.Int(1, 'APIC id for this IO APIC')
int_requestor = RequestPort("Port for sending interrupt messages")
int_latency = Param.Latency('1ns', \
diff --git a/src/dev/x86/I8237.py b/src/dev/x86/I8237.py
index 08632c9..3278367 100644
--- a/src/dev/x86/I8237.py
+++ b/src/dev/x86/I8237.py
@@ -30,5 +30,5 @@
class I8237(BasicPioDevice):
type = 'I8237'
- cxx_class = 'X86ISA::I8237'
+ cxx_class = 'gem5::X86ISA::I8237'
cxx_header = "dev/x86/i8237.hh"
diff --git a/src/dev/x86/I8254.py b/src/dev/x86/I8254.py
index ae4bded..d98c2c0 100644
--- a/src/dev/x86/I8254.py
+++ b/src/dev/x86/I8254.py
@@ -31,6 +31,7 @@
class I8254(BasicPioDevice):
type = 'I8254'
- cxx_class = 'X86ISA::I8254'
+ cxx_class = 'gem5::X86ISA::I8254'
cxx_header = "dev/x86/i8254.hh"
+
int_pin = IntSourcePin('Pin to signal timer interrupts to')
diff --git a/src/dev/x86/I8259.py b/src/dev/x86/I8259.py
index 56af363..d73bc85 100644
--- a/src/dev/x86/I8259.py
+++ b/src/dev/x86/I8259.py
@@ -37,8 +37,9 @@
class I8259(BasicPioDevice):
type = 'I8259'
- cxx_class='X86ISA::I8259'
+ cxx_class='gem5::X86ISA::I8259'
cxx_header = "dev/x86/i8259.hh"
+
output = IntSourcePin('The pin this I8259 drives')
inputs = VectorIntSinkPin('The pins that drive this I8259')
mode = Param.X86I8259CascadeMode('How this I8259 is cascaded')
diff --git a/src/dev/x86/Pc.py b/src/dev/x86/Pc.py
index 767c697..42c35c1 100644
--- a/src/dev/x86/Pc.py
+++ b/src/dev/x86/Pc.py
@@ -48,6 +48,7 @@
class Pc(Platform):
type = 'Pc'
cxx_header = "dev/x86/pc.hh"
+ cxx_class = 'gem5::Pc'
system = Param.System(Parent.any, "system")
south_bridge = Param.SouthBridge(SouthBridge(), "Southbridge")
diff --git a/src/dev/x86/PcSpeaker.py b/src/dev/x86/PcSpeaker.py
index 8184691..41c31d4 100644
--- a/src/dev/x86/PcSpeaker.py
+++ b/src/dev/x86/PcSpeaker.py
@@ -30,6 +30,6 @@
class PcSpeaker(BasicPioDevice):
type = 'PcSpeaker'
- cxx_class = 'X86ISA::Speaker'
+ cxx_class = 'gem5::X86ISA::Speaker'
cxx_header = "dev/x86/speaker.hh"
i8254 = Param.I8254('Timer that drives the speaker')
diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py
index d10a0cf..9e0a88f 100644
--- a/src/dev/x86/SouthBridge.py
+++ b/src/dev/x86/SouthBridge.py
@@ -44,6 +44,7 @@
class SouthBridge(SimObject):
type = 'SouthBridge'
cxx_header = "dev/x86/south_bridge.hh"
+ cxx_class = 'gem5::SouthBridge'
pic1 = Param.I8259(I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master'),
"Master PIC")
diff --git a/src/dev/x86/cmos.cc b/src/dev/x86/cmos.cc
index 3c38c25..19fab68 100644
--- a/src/dev/x86/cmos.cc
+++ b/src/dev/x86/cmos.cc
@@ -33,6 +33,9 @@
#include "dev/x86/intdev.hh"
#include "mem/packet_access.hh"
+namespace gem5
+{
+
void
X86ISA::Cmos::X86RTC::handleEvent()
{
@@ -138,3 +141,5 @@
// Serialize the timer
rtc.unserialize("rtc", cp);
}
+
+} // namespace gem5
diff --git a/src/dev/x86/cmos.hh b/src/dev/x86/cmos.hh
index 51abee3..72937af 100644
--- a/src/dev/x86/cmos.hh
+++ b/src/dev/x86/cmos.hh
@@ -34,6 +34,9 @@
#include "dev/mc146818.hh"
#include "params/Cmos.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -100,5 +103,6 @@
};
} // namespace X86ISA
+} // namespace gem5
#endif //__DEV_X86_CMOS_HH__
diff --git a/src/dev/x86/i8042.cc b/src/dev/x86/i8042.cc
index c6c1dd4..723affe 100644
--- a/src/dev/x86/i8042.cc
+++ b/src/dev/x86/i8042.cc
@@ -39,6 +39,9 @@
* https://wiki.osdev.org/%228042%22_PS/2_Controller
*/
+namespace gem5
+{
+
// The 8042 has a whopping 32 bytes of internal RAM.
const uint8_t RamSize = 32;
const uint8_t NumOutputBits = 14;
@@ -305,3 +308,5 @@
UNSERIALIZE_SCALAR(dataReg);
UNSERIALIZE_SCALAR(lastCommand);
}
+
+} // namespace gem5
diff --git a/src/dev/x86/i8042.hh b/src/dev/x86/i8042.hh
index e468f02..4ab86ac 100644
--- a/src/dev/x86/i8042.hh
+++ b/src/dev/x86/i8042.hh
@@ -37,6 +37,9 @@
#include "dev/ps2/device.hh"
#include "params/I8042.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -143,5 +146,6 @@
};
} // namespace X86ISA
+} // namespace gem5
#endif //__DEV_X86_I8042_HH__
diff --git a/src/dev/x86/i82094aa.cc b/src/dev/x86/i82094aa.cc
index 5ae4315..f5e51b0 100644
--- a/src/dev/x86/i82094aa.cc
+++ b/src/dev/x86/i82094aa.cc
@@ -39,6 +39,9 @@
#include "mem/packet_access.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
X86ISA::I82094AA::I82094AA(const Params &p)
: BasicPioDevice(p, 20), extIntPic(p.external_int_pic),
lowestPriorityOffset(0),
@@ -291,3 +294,5 @@
redirTable[i] = (RedirTableEntry)redirTableArray[i];
}
}
+
+} // namespace gem5
diff --git a/src/dev/x86/i82094aa.hh b/src/dev/x86/i82094aa.hh
index 1b8a25f..6427dbf 100644
--- a/src/dev/x86/i82094aa.hh
+++ b/src/dev/x86/i82094aa.hh
@@ -37,6 +37,9 @@
#include "dev/io_device.hh"
#include "params/I82094AA.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -111,5 +114,6 @@
};
} // namespace X86ISA
+} // namespace gem5
#endif //__DEV_X86_SOUTH_BRIDGE_I8254_HH__
diff --git a/src/dev/x86/i8237.cc b/src/dev/x86/i8237.cc
index a7f641f..437a376 100644
--- a/src/dev/x86/i8237.cc
+++ b/src/dev/x86/i8237.cc
@@ -32,6 +32,9 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -162,3 +165,4 @@
}
} // namespace X86ISA
+} // namespace gem5
diff --git a/src/dev/x86/i8237.hh b/src/dev/x86/i8237.hh
index fbc30f7..9fb9b89 100644
--- a/src/dev/x86/i8237.hh
+++ b/src/dev/x86/i8237.hh
@@ -35,6 +35,9 @@
#include "dev/reg_bank.hh"
#include "params/I8237.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -104,5 +107,6 @@
};
} // namespace X86ISA
+} // namespace gem5
#endif //__DEV_X86_I8237_HH__
diff --git a/src/dev/x86/i8254.cc b/src/dev/x86/i8254.cc
index 74428f1..d947900 100644
--- a/src/dev/x86/i8254.cc
+++ b/src/dev/x86/i8254.cc
@@ -33,6 +33,9 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+namespace gem5
+{
+
void
X86ISA::I8254::counterInterrupt(unsigned int num)
{
@@ -95,3 +98,5 @@
{
pit.startup();
}
+
+} // namespace gem5
diff --git a/src/dev/x86/i8254.hh b/src/dev/x86/i8254.hh
index 79e701f..671d05c 100644
--- a/src/dev/x86/i8254.hh
+++ b/src/dev/x86/i8254.hh
@@ -34,6 +34,9 @@
#include "dev/io_device.hh"
#include "params/I8254.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -121,5 +124,6 @@
};
} // namespace X86ISA
+} // namespace gem5
#endif //__DEV_X86_SOUTH_BRIDGE_I8254_HH__
diff --git a/src/dev/x86/i8259.cc b/src/dev/x86/i8259.cc
index 70d5cc2..5cae5b8 100644
--- a/src/dev/x86/i8259.cc
+++ b/src/dev/x86/i8259.cc
@@ -35,6 +35,9 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+namespace gem5
+{
+
X86ISA::I8259::I8259(const Params &p)
: BasicPioDevice(p, 2),
latency(p.pio_latency),
@@ -364,3 +367,5 @@
UNSERIALIZE_SCALAR(initControlWord);
UNSERIALIZE_SCALAR(autoEOI);
}
+
+} // namespace gem5
diff --git a/src/dev/x86/i8259.hh b/src/dev/x86/i8259.hh
index c876eb1..dcc5987 100644
--- a/src/dev/x86/i8259.hh
+++ b/src/dev/x86/i8259.hh
@@ -34,6 +34,9 @@
#include "enums/X86I8259CascadeMode.hh"
#include "params/I8259.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -121,5 +124,6 @@
};
} // namespace X86ISA
+} // namespace gem5
#endif //__DEV_X86_I8259_HH__
diff --git a/src/dev/x86/intdev.hh b/src/dev/x86/intdev.hh
index f757fdb..0c30ef5 100644
--- a/src/dev/x86/intdev.hh
+++ b/src/dev/x86/intdev.hh
@@ -49,6 +49,9 @@
#include "mem/tport.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -148,5 +151,6 @@
};
} // namespace X86ISA
+} // namespace gem5
#endif //__DEV_X86_INTDEV_HH__
diff --git a/src/dev/x86/pc.cc b/src/dev/x86/pc.cc
index c3e813d..0473aa5 100644
--- a/src/dev/x86/pc.cc
+++ b/src/dev/x86/pc.cc
@@ -40,6 +40,9 @@
#include "dev/x86/south_bridge.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
Pc::Pc(const Params &p) : Platform(p), southBridge(p.south_bridge)
{}
@@ -126,3 +129,5 @@
{
warn_once("Tried to clear PCI interrupt %d\n", line);
}
+
+} // namespace gem5
diff --git a/src/dev/x86/pc.hh b/src/dev/x86/pc.hh
index 8503069..8ae494d 100644
--- a/src/dev/x86/pc.hh
+++ b/src/dev/x86/pc.hh
@@ -38,6 +38,9 @@
#include "dev/platform.hh"
#include "params/Pc.hh"
+namespace gem5
+{
+
class SouthBridge;
class Pc : public Platform
@@ -63,4 +66,6 @@
void clearPciInt(int line) override;
};
+} // namespace gem5
+
#endif // __DEV_PC_HH__
diff --git a/src/dev/x86/south_bridge.cc b/src/dev/x86/south_bridge.cc
index 8875d54..9d8bbcd 100644
--- a/src/dev/x86/south_bridge.cc
+++ b/src/dev/x86/south_bridge.cc
@@ -30,9 +30,14 @@
#include <cassert>
+namespace gem5
+{
+
using namespace X86ISA;
SouthBridge::SouthBridge(const Params &p) : SimObject(p),
pit(p.pit), pic1(p.pic1), pic2(p.pic2), cmos(p.cmos), speaker(p.speaker),
ioApic(p.io_apic)
{}
+
+} // namespace gem5
diff --git a/src/dev/x86/south_bridge.hh b/src/dev/x86/south_bridge.hh
index 2f63052..6e294e5 100644
--- a/src/dev/x86/south_bridge.hh
+++ b/src/dev/x86/south_bridge.hh
@@ -32,6 +32,9 @@
#include "params/SouthBridge.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -58,4 +61,6 @@
SouthBridge(const Params &p);
};
+} // namespace gem5
+
#endif //__DEV_X86_SOUTH_BRIDGE_HH__
diff --git a/src/dev/x86/speaker.cc b/src/dev/x86/speaker.cc
index e6c85ce..b4bbe61 100644
--- a/src/dev/x86/speaker.cc
+++ b/src/dev/x86/speaker.cc
@@ -35,6 +35,9 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+namespace gem5
+{
+
Tick
X86ISA::Speaker::read(PacketPtr pkt)
{
@@ -83,3 +86,5 @@
{
UNSERIALIZE_SCALAR(controlVal);
}
+
+} // namespace gem5
diff --git a/src/dev/x86/speaker.hh b/src/dev/x86/speaker.hh
index 7189359..6651f53 100644
--- a/src/dev/x86/speaker.hh
+++ b/src/dev/x86/speaker.hh
@@ -33,6 +33,9 @@
#include "dev/io_device.hh"
#include "params/PcSpeaker.hh"
+namespace gem5
+{
+
namespace X86ISA
{
@@ -70,5 +73,6 @@
};
} // namespace X86ISA
+} // namespace gem5
#endif //__DEV_X86_SPEAKER_HH__
diff --git a/src/gpu-compute/GPU.py b/src/gpu-compute/GPU.py
index ace83a5..6b0bb2e 100644
--- a/src/gpu-compute/GPU.py
+++ b/src/gpu-compute/GPU.py
@@ -57,6 +57,7 @@
class PoolManager(SimObject):
type = 'PoolManager'
abstract = True
+ cxx_class = 'gem5::PoolManager'
cxx_header = "gpu-compute/pool_manager.hh"
min_alloc = Param.Int(4, 'min number of VGPRs allocated per WF')
@@ -66,18 +67,18 @@
# be executing on a CU at any given time.
class SimplePoolManager(PoolManager):
type = 'SimplePoolManager'
- cxx_class = 'SimplePoolManager'
+ cxx_class = 'gem5::SimplePoolManager'
cxx_header = "gpu-compute/simple_pool_manager.hh"
## This is for allowing multiple workgroups on one CU
class DynPoolManager(PoolManager):
type = 'DynPoolManager'
- cxx_class = 'DynPoolManager'
+ cxx_class = 'gem5::DynPoolManager'
cxx_header = "gpu-compute/dyn_pool_manager.hh"
class RegisterFile(SimObject):
type = 'RegisterFile'
- cxx_class = 'RegisterFile'
+ cxx_class = 'gem5::RegisterFile'
cxx_header = 'gpu-compute/register_file.hh'
simd_id = Param.Int(-1, 'SIMD ID associated with this Register File')
@@ -86,17 +87,17 @@
class ScalarRegisterFile(RegisterFile):
type = 'ScalarRegisterFile'
- cxx_class = 'ScalarRegisterFile'
+ cxx_class = 'gem5::ScalarRegisterFile'
cxx_header = 'gpu-compute/scalar_register_file.hh'
class VectorRegisterFile(RegisterFile):
type = 'VectorRegisterFile'
- cxx_class = 'VectorRegisterFile'
+ cxx_class = 'gem5::VectorRegisterFile'
cxx_header = 'gpu-compute/vector_register_file.hh'
class RegisterManager(SimObject):
type = 'RegisterManager'
- cxx_class = 'RegisterManager'
+ cxx_class = 'gem5::RegisterManager'
cxx_header = 'gpu-compute/register_manager.hh'
policy = Param.String("static", "Register Manager Policy")
@@ -105,7 +106,7 @@
class Wavefront(SimObject):
type = 'Wavefront'
- cxx_class = 'Wavefront'
+ cxx_class = 'gem5::Wavefront'
cxx_header = 'gpu-compute/wavefront.hh'
simdId = Param.Int('SIMD id (0-ComputeUnit.num_SIMDs)')
@@ -118,7 +119,7 @@
# AMD Graphics Core Next (GCN) Architecture whitepaper.
class ComputeUnit(ClockedObject):
type = 'ComputeUnit'
- cxx_class = 'ComputeUnit'
+ cxx_class = 'gem5::ComputeUnit'
cxx_header = 'gpu-compute/compute_unit.hh'
wavefronts = VectorParam.Wavefront('Number of wavefronts')
@@ -218,7 +219,7 @@
class Shader(ClockedObject):
type = 'Shader'
- cxx_class = 'Shader'
+ cxx_class = 'gem5::Shader'
cxx_header = 'gpu-compute/shader.hh'
CUs = VectorParam.ComputeUnit('Number of compute units')
gpu_cmd_proc = Param.GPUCommandProcessor('Command processor for GPU')
@@ -239,6 +240,7 @@
class GPUComputeDriver(EmulatedDriver):
type = 'GPUComputeDriver'
+ cxx_class = 'gem5::GPUComputeDriver'
cxx_header = 'gpu-compute/gpu_compute_driver.hh'
device = Param.GPUCommandProcessor('GPU controlled by this driver')
isdGPU = Param.Bool(False, 'Driver is for a dGPU')
@@ -256,14 +258,17 @@
class GPURenderDriver(EmulatedDriver):
type = 'GPURenderDriver'
+ cxx_class = 'gem5::GPURenderDriver'
cxx_header = 'gpu-compute/gpu_render_driver.hh'
class GPUDispatcher(SimObject):
type = 'GPUDispatcher'
+ cxx_class = 'gem5::GPUDispatcher'
cxx_header = 'gpu-compute/dispatcher.hh'
class GPUCommandProcessor(DmaDevice):
type = 'GPUCommandProcessor'
+ cxx_class = 'gem5::GPUCommandProcessor'
cxx_header = 'gpu-compute/gpu_command_processor.hh'
dispatcher = Param.GPUDispatcher('workgroup dispatcher for the GPU')
diff --git a/src/gpu-compute/LdsState.py b/src/gpu-compute/LdsState.py
index 6bd0a7e..e3848a5 100644
--- a/src/gpu-compute/LdsState.py
+++ b/src/gpu-compute/LdsState.py
@@ -37,7 +37,7 @@
class LdsState(ClockedObject):
type = 'LdsState'
- cxx_class = 'LdsState'
+ cxx_class = 'gem5::LdsState'
cxx_header = 'gpu-compute/lds_state.hh'
size = Param.Int(65536, 'the size of the LDS')
range = Param.AddrRange('64kB', "address space of the LDS")
diff --git a/src/gpu-compute/X86GPUTLB.py b/src/gpu-compute/X86GPUTLB.py
index 7e5d932..ce87ea7 100644
--- a/src/gpu-compute/X86GPUTLB.py
+++ b/src/gpu-compute/X86GPUTLB.py
@@ -39,13 +39,13 @@
if buildEnv.get('FULL_SYSTEM', False):
class X86PagetableWalker(SimObject):
type = 'X86PagetableWalker'
- cxx_class = 'X86ISA::Walker'
+ cxx_class = 'gem5::X86ISA::Walker'
port = ResponsePort("Port for the hardware table walker")
system = Param.System(Parent.any, "system object")
class X86GPUTLB(ClockedObject):
type = 'X86GPUTLB'
- cxx_class = 'X86ISA::GpuTLB'
+ cxx_class = 'gem5::X86ISA::GpuTLB'
cxx_header = 'gpu-compute/gpu_tlb.hh'
size = Param.Int(64, "TLB size (number of entries)")
assoc = Param.Int(64, "TLB associativity")
@@ -69,7 +69,7 @@
class TLBCoalescer(ClockedObject):
type = 'TLBCoalescer'
- cxx_class = 'TLBCoalescer'
+ cxx_class = 'gem5::TLBCoalescer'
cxx_header = 'gpu-compute/tlb_coalescer.hh'
probesPerCycle = Param.Int(2, "Number of TLB probes per cycle")
coalescingWindow = Param.Int(1, "Permit coalescing across that many ticks")
diff --git a/src/gpu-compute/comm.cc b/src/gpu-compute/comm.cc
index 2b8a232..d6face2 100644
--- a/src/gpu-compute/comm.cc
+++ b/src/gpu-compute/comm.cc
@@ -38,6 +38,9 @@
#include "gpu-compute/wavefront.hh"
#include "params/ComputeUnit.hh"
+namespace gem5
+{
+
/**
* Scoreboard/Schedule stage interface.
*/
@@ -150,3 +153,5 @@
{
return _dispatchStatus[func_unit_id];
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/comm.hh b/src/gpu-compute/comm.hh
index 2e2720f..d131fee 100644
--- a/src/gpu-compute/comm.hh
+++ b/src/gpu-compute/comm.hh
@@ -40,6 +40,9 @@
#include "gpu-compute/exec_stage.hh"
#include "gpu-compute/misc.hh"
+namespace gem5
+{
+
struct ComputeUnitParams;
class Wavefront;
@@ -118,4 +121,6 @@
std::vector<DISPATCH_STATUS> _dispatchStatus;
};
+} // namespace gem5
+
#endif // __GPU_COMPUTE_COMM_HH__
diff --git a/src/gpu-compute/compute_unit.cc b/src/gpu-compute/compute_unit.cc
index d6fa2b4..7e476b5 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -60,6 +60,9 @@
#include "sim/process.hh"
#include "sim/sim_exit.hh"
+namespace gem5
+{
+
ComputeUnit::ComputeUnit(const Params &p) : ClockedObject(p),
numVectorGlobalMemUnits(p.num_global_mem_pipes),
numVectorSharedMemUnits(p.num_shared_mem_pipes),
@@ -2343,3 +2346,5 @@
numALUInstsExecuted = numInstrExecuted - dynamicGMemInstrCnt -
dynamicLMemInstrCnt;
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/compute_unit.hh b/src/gpu-compute/compute_unit.hh
index 91a2397..30ea418 100644
--- a/src/gpu-compute/compute_unit.hh
+++ b/src/gpu-compute/compute_unit.hh
@@ -60,6 +60,9 @@
#include "mem/token_port.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
class HSAQueueEntry;
class LdsChunk;
class ScalarRegisterFile;
@@ -1088,4 +1091,6 @@
} stats;
};
+} // namespace gem5
+
#endif // __COMPUTE_UNIT_HH__
diff --git a/src/gpu-compute/dispatcher.cc b/src/gpu-compute/dispatcher.cc
index a1c036c..6319da0 100644
--- a/src/gpu-compute/dispatcher.cc
+++ b/src/gpu-compute/dispatcher.cc
@@ -45,6 +45,9 @@
#include "sim/syscall_emul_buf.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
GPUDispatcher::GPUDispatcher(const Params &p)
: SimObject(p), shader(nullptr), gpuCmdProc(nullptr),
tickEvent([this]{ exec(); },
@@ -352,3 +355,5 @@
"wavefronts that are waiting to be dispatched")
{
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/dispatcher.hh b/src/gpu-compute/dispatcher.hh
index 1fce4e5..a9a527b 100644
--- a/src/gpu-compute/dispatcher.hh
+++ b/src/gpu-compute/dispatcher.hh
@@ -53,6 +53,9 @@
#include "params/GPUDispatcher.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class GPUCommandProcessor;
class HSAQueueEntry;
class Shader;
@@ -102,4 +105,6 @@
} stats;
};
+} // namespace gem5
+
#endif // __GPU_COMPUTE_DISPATCHER_HH__
diff --git a/src/gpu-compute/dyn_pool_manager.cc b/src/gpu-compute/dyn_pool_manager.cc
index 19b7cac..22dfd9d 100644
--- a/src/gpu-compute/dyn_pool_manager.cc
+++ b/src/gpu-compute/dyn_pool_manager.cc
@@ -37,6 +37,9 @@
#include "debug/GPUVRF.hh"
#include "gpu-compute/dyn_pool_manager.hh"
+namespace gem5
+{
+
// return the min number of elements that the manager can reserve given
// a request for "size" elements
uint32_t
@@ -158,3 +161,5 @@
return region.second + poolSize() - region.first + 1;
}
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/dyn_pool_manager.hh b/src/gpu-compute/dyn_pool_manager.hh
index 151a33f..623667f 100644
--- a/src/gpu-compute/dyn_pool_manager.hh
+++ b/src/gpu-compute/dyn_pool_manager.hh
@@ -41,6 +41,9 @@
#include "gpu-compute/pool_manager.hh"
#include "params/DynPoolManager.hh"
+namespace gem5
+{
+
// Dynamic Pool Manager: allows multiple WGs on the same pool
class DynPoolManager : public PoolManager
{
@@ -72,4 +75,6 @@
int totalRegSpace;
};
+} // namespace gem5
+
#endif // __DYN_POOL_MANAGER_HH__
diff --git a/src/gpu-compute/exec_stage.cc b/src/gpu-compute/exec_stage.cc
index 5a54b10..da8f2b6 100644
--- a/src/gpu-compute/exec_stage.cc
+++ b/src/gpu-compute/exec_stage.cc
@@ -41,6 +41,9 @@
#include "gpu-compute/vector_register_file.hh"
#include "gpu-compute/wavefront.hh"
+namespace gem5
+{
+
ExecStage::ExecStage(const ComputeUnitParams &p, ComputeUnit &cu,
ScheduleToExecute &from_schedule)
: computeUnit(cu), fromSchedule(from_schedule),
@@ -236,3 +239,5 @@
numCyclesWithNoInstrTypeIssued.subname(c, "SharedMemPipe");
numCyclesWithInstrTypeIssued.subname(c++, "SharedMemPipe");
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/exec_stage.hh b/src/gpu-compute/exec_stage.hh
index 3281f41..71badb8 100644
--- a/src/gpu-compute/exec_stage.hh
+++ b/src/gpu-compute/exec_stage.hh
@@ -42,6 +42,9 @@
#include "base/statistics.hh"
#include "base/stats/group.hh"
+namespace gem5
+{
+
class ComputeUnit;
class ScheduleToExecute;
class Wavefront;
@@ -121,4 +124,6 @@
} stats;
};
+} // namespace gem5
+
#endif // __EXEC_STAGE_HH__
diff --git a/src/gpu-compute/fetch_stage.cc b/src/gpu-compute/fetch_stage.cc
index 27d014b..8ba9a85 100644
--- a/src/gpu-compute/fetch_stage.cc
+++ b/src/gpu-compute/fetch_stage.cc
@@ -36,6 +36,9 @@
#include "gpu-compute/compute_unit.hh"
#include "gpu-compute/wavefront.hh"
+namespace gem5
+{
+
FetchStage::FetchStage(const ComputeUnitParams &p, ComputeUnit &cu)
: numVectorALUs(p.num_SIMDs), computeUnit(cu),
_name(cu.name() + ".FetchStage"), stats(&cu)
@@ -97,3 +100,5 @@
{
instFetchInstReturned.init(1, 32, 1);
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/fetch_stage.hh b/src/gpu-compute/fetch_stage.hh
index dd54c40..86f778c 100644
--- a/src/gpu-compute/fetch_stage.hh
+++ b/src/gpu-compute/fetch_stage.hh
@@ -41,6 +41,9 @@
#include "base/stats/group.hh"
#include "gpu-compute/fetch_unit.hh"
+namespace gem5
+{
+
// Instruction fetch stage.
// All dispatched wavefronts for all SIMDS are analyzed for the
// need to fetch instructions. From the fetch eligible waves,
@@ -82,4 +85,6 @@
} stats;
};
+} // namespace gem5
+
#endif // __FETCH_STAGE_HH__
diff --git a/src/gpu-compute/fetch_unit.cc b/src/gpu-compute/fetch_unit.cc
index 62b9e73..95461dc 100644
--- a/src/gpu-compute/fetch_unit.cc
+++ b/src/gpu-compute/fetch_unit.cc
@@ -44,6 +44,9 @@
#include "gpu-compute/wavefront.hh"
#include "mem/ruby/system/RubySystem.hh"
+namespace gem5
+{
+
uint32_t FetchUnit::globalFetchUnitID;
FetchUnit::FetchUnit(const ComputeUnitParams &p, ComputeUnit &cu)
@@ -639,3 +642,5 @@
assert(bytes_remaining <= bufferedBytes());
return bytes_remaining;
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/fetch_unit.hh b/src/gpu-compute/fetch_unit.hh
index 11583fb..66e3343 100644
--- a/src/gpu-compute/fetch_unit.hh
+++ b/src/gpu-compute/fetch_unit.hh
@@ -47,6 +47,9 @@
#include "gpu-compute/scheduler.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
class ComputeUnit;
class Wavefront;
@@ -269,4 +272,6 @@
int fetchDepth;
};
+} // namespace gem5
+
#endif // __FETCH_UNIT_HH__
diff --git a/src/gpu-compute/global_memory_pipeline.cc b/src/gpu-compute/global_memory_pipeline.cc
index a34faa0..2663ba5 100644
--- a/src/gpu-compute/global_memory_pipeline.cc
+++ b/src/gpu-compute/global_memory_pipeline.cc
@@ -43,6 +43,9 @@
#include "gpu-compute/vector_register_file.hh"
#include "gpu-compute/wavefront.hh"
+namespace gem5
+{
+
GlobalMemPipeline::GlobalMemPipeline(const ComputeUnitParams &p,
ComputeUnit &cu)
: computeUnit(cu), _name(cu.name() + ".GlobalMemPipeline"),
@@ -296,3 +299,5 @@
"are delayed before updating the VRF")
{
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/global_memory_pipeline.hh b/src/gpu-compute/global_memory_pipeline.hh
index 05a0ad5..1a525c3 100644
--- a/src/gpu-compute/global_memory_pipeline.hh
+++ b/src/gpu-compute/global_memory_pipeline.hh
@@ -53,6 +53,9 @@
* returned from the memory sub-system.
*/
+namespace gem5
+{
+
class ComputeUnit;
class GlobalMemPipeline
@@ -154,4 +157,6 @@
} stats;
};
+} // namespace gem5
+
#endif // __GLOBAL_MEMORY_PIPELINE_HH__
diff --git a/src/gpu-compute/gpu_command_processor.cc b/src/gpu-compute/gpu_command_processor.cc
index 78b3235..266a082 100644
--- a/src/gpu-compute/gpu_command_processor.cc
+++ b/src/gpu-compute/gpu_command_processor.cc
@@ -44,6 +44,9 @@
#include "sim/proxy_ptr.hh"
#include "sim/syscall_emul_buf.hh"
+namespace gem5
+{
+
GPUCommandProcessor::GPUCommandProcessor(const Params &p)
: DmaDevice(p), dispatcher(*p.dispatcher), _driver(nullptr), hsaPP(p.hsapp)
{
@@ -404,3 +407,5 @@
{
return _shader;
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/gpu_command_processor.hh b/src/gpu-compute/gpu_command_processor.hh
index 9555e3b..0a793da 100644
--- a/src/gpu-compute/gpu_command_processor.hh
+++ b/src/gpu-compute/gpu_command_processor.hh
@@ -60,6 +60,9 @@
#include "gpu-compute/hsa_queue_entry.hh"
#include "params/GPUCommandProcessor.hh"
+namespace gem5
+{
+
struct GPUCommandProcessorParams;
class GPUComputeDriver;
class GPUDispatcher;
@@ -301,4 +304,6 @@
}
};
+} // namespace gem5
+
#endif // __DEV_HSA_GPU_COMMAND_PROCESSOR_HH__
diff --git a/src/gpu-compute/gpu_compute_driver.cc b/src/gpu-compute/gpu_compute_driver.cc
index 02f1de5..472ced4 100644
--- a/src/gpu-compute/gpu_compute_driver.cc
+++ b/src/gpu-compute/gpu_compute_driver.cc
@@ -51,6 +51,9 @@
#include "sim/process.hh"
#include "sim/syscall_emul_buf.hh"
+namespace gem5
+{
+
GPUComputeDriver::GPUComputeDriver(const Params &p)
: EmulatedDriver(p), device(p.device), queueId(0),
isdGPU(p.isdGPU), gfxVersion(p.gfxVersion), dGPUPoolID(p.dGPUPoolID),
@@ -951,3 +954,5 @@
req->setCacheCoherenceFlags(defaultMtype);
}
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/gpu_compute_driver.hh b/src/gpu-compute/gpu_compute_driver.hh
index 48ca876..4408052 100644
--- a/src/gpu-compute/gpu_compute_driver.hh
+++ b/src/gpu-compute/gpu_compute_driver.hh
@@ -53,6 +53,9 @@
#include "mem/request.hh"
#include "sim/emul_driver.hh"
+namespace gem5
+{
+
struct GPUComputeDriverParams;
class GPUCommandProcessor;
class PortProxy;
@@ -243,4 +246,6 @@
};
+} // namespace gem5
+
#endif // __GPU_COMPUTE_GPU_COMPUTE_DRIVER_HH__
diff --git a/src/gpu-compute/gpu_dyn_inst.cc b/src/gpu-compute/gpu_dyn_inst.cc
index ea64640..fb9bf07 100644
--- a/src/gpu-compute/gpu_dyn_inst.cc
+++ b/src/gpu-compute/gpu_dyn_inst.cc
@@ -40,6 +40,9 @@
#include "gpu-compute/shader.hh"
#include "gpu-compute/wavefront.hh"
+namespace gem5
+{
+
GPUDynInst::GPUDynInst(ComputeUnit *_cu, Wavefront *_wf,
GPUStaticInst *static_inst, InstSeqNum instSeqNum)
: GPUExecContext(_cu, _wf), scalarAddr(0), addr(computeUnit()->wfSize(),
@@ -987,3 +990,5 @@
lineAddressTime.insert(std::make_pair(addr, addressTimeVec));
}
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/gpu_dyn_inst.hh b/src/gpu-compute/gpu_dyn_inst.hh
index ab7ccb8..ae8260e 100644
--- a/src/gpu-compute/gpu_dyn_inst.hh
+++ b/src/gpu-compute/gpu_dyn_inst.hh
@@ -47,6 +47,9 @@
#include "gpu-compute/gpu_exec_context.hh"
#include "gpu-compute/operand_info.hh"
+namespace gem5
+{
+
class GPUStaticInst;
template<typename T>
@@ -489,4 +492,6 @@
std::map<Addr, std::vector<Tick>> lineAddressTime;
};
+} // namespace gem5
+
#endif // __GPU_DYN_INST_HH__
diff --git a/src/gpu-compute/gpu_exec_context.cc b/src/gpu-compute/gpu_exec_context.cc
index 2411e9e..9f059c8 100644
--- a/src/gpu-compute/gpu_exec_context.cc
+++ b/src/gpu-compute/gpu_exec_context.cc
@@ -34,6 +34,9 @@
#include "gpu-compute/gpu_exec_context.hh"
#include "gpu-compute/wavefront.hh"
+namespace gem5
+{
+
GPUExecContext::GPUExecContext(ComputeUnit *_cu, Wavefront *_wf)
: cu(_cu), wf(_wf), gpuISA(_wf ? &_wf->gpuISA() : nullptr)
{
@@ -64,3 +67,5 @@
assert(gpuISA);
gpuISA->writeMiscReg(opIdx, val);
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/gpu_exec_context.hh b/src/gpu-compute/gpu_exec_context.hh
index 15cbd55..372b701 100644
--- a/src/gpu-compute/gpu_exec_context.hh
+++ b/src/gpu-compute/gpu_exec_context.hh
@@ -38,6 +38,9 @@
#include "base/types.hh"
#include "config/the_gpu_isa.hh"
+namespace gem5
+{
+
class ComputeUnit;
class Wavefront;
@@ -63,4 +66,6 @@
TheGpuISA::GPUISA *gpuISA;
};
+} // namespace gem5
+
#endif // __GPU_EXEC_CONTEXT_HH__
diff --git a/src/gpu-compute/gpu_render_driver.cc b/src/gpu-compute/gpu_render_driver.cc
index 1af83cb..260a61f 100644
--- a/src/gpu-compute/gpu_render_driver.cc
+++ b/src/gpu-compute/gpu_render_driver.cc
@@ -31,6 +31,9 @@
#include "params/GPURenderDriver.hh"
#include "sim/fd_entry.hh"
+namespace gem5
+{
+
GPURenderDriver::GPURenderDriver(const GPURenderDriverParams &p)
: EmulatedDriver(p)
{
@@ -48,3 +51,5 @@
int tgt_fd = process->fds->allocFD(device_fd_entry);
return tgt_fd;
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/gpu_render_driver.hh b/src/gpu-compute/gpu_render_driver.hh
index d070668..5a4ce1b 100644
--- a/src/gpu-compute/gpu_render_driver.hh
+++ b/src/gpu-compute/gpu_render_driver.hh
@@ -33,6 +33,9 @@
#include "sim/emul_driver.hh"
#include "sim/process.hh"
+namespace gem5
+{
+
struct GPURenderDriverParams;
class GPURenderDriver final : public EmulatedDriver
@@ -49,4 +52,6 @@
}
};
-#endif
+} // namespace gem5
+
+#endif // __GPU_COMPUTE_GPU_RENDER_DRIVER_HH__
diff --git a/src/gpu-compute/gpu_static_inst.cc b/src/gpu-compute/gpu_static_inst.cc
index 12935b0..c66330c 100644
--- a/src/gpu-compute/gpu_static_inst.cc
+++ b/src/gpu-compute/gpu_static_inst.cc
@@ -35,6 +35,9 @@
#include "debug/GPUInst.hh"
+namespace gem5
+{
+
GPUStaticInst::GPUStaticInst(const std::string &opcode)
: executed_as(enums::SC_NONE), _opcode(opcode),
_instNum(0), _instAddr(0), srcVecDWords(-1), dstVecDWords(-1),
@@ -210,3 +213,5 @@
return maxOpSize;
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/gpu_static_inst.hh b/src/gpu-compute/gpu_static_inst.hh
index ed753c5..7f12f42 100644
--- a/src/gpu-compute/gpu_static_inst.hh
+++ b/src/gpu-compute/gpu_static_inst.hh
@@ -54,6 +54,9 @@
#include "gpu-compute/operand_info.hh"
#include "gpu-compute/wavefront.hh"
+namespace gem5
+{
+
class BaseOperand;
class BaseRegOperand;
@@ -357,4 +360,6 @@
int instSize() const override { return 0; }
};
+} // namespace gem5
+
#endif // __GPU_STATIC_INST_HH__
diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc
index 5f273cd..d234efb 100644
--- a/src/gpu-compute/gpu_tlb.cc
+++ b/src/gpu-compute/gpu_tlb.cc
@@ -60,6 +60,8 @@
#include "sim/process.hh"
#include "sim/pseudo_inst.hh"
+namespace gem5
+{
namespace X86ISA
{
@@ -1455,3 +1457,4 @@
globalTLBMissRate = 100 * globalNumTLBMisses / globalNumTLBAccesses;
}
} // namespace X86ISA
+} // namespace gem5
diff --git a/src/gpu-compute/gpu_tlb.hh b/src/gpu-compute/gpu_tlb.hh
index 00ef905..0913074 100644
--- a/src/gpu-compute/gpu_tlb.hh
+++ b/src/gpu-compute/gpu_tlb.hh
@@ -55,6 +55,9 @@
#include "sim/clocked_object.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class BaseTLB;
class Packet;
class ThreadContext;
@@ -435,4 +438,6 @@
};
}
+} // namespace gem5
+
#endif // __GPU_TLB_HH__
diff --git a/src/gpu-compute/hsa_queue_entry.hh b/src/gpu-compute/hsa_queue_entry.hh
index 6d21d30..4a22791 100644
--- a/src/gpu-compute/hsa_queue_entry.hh
+++ b/src/gpu-compute/hsa_queue_entry.hh
@@ -55,6 +55,9 @@
#include "dev/hsa/hsa_queue.hh"
#include "gpu-compute/kernel_code.hh"
+namespace gem5
+{
+
class HSAQueueEntry
{
public:
@@ -475,4 +478,6 @@
std::bitset<NumScalarInitFields> initialSgprState;
};
+} // namespace gem5
+
#endif // __GPU_COMPUTE_HSA_QUEUE_ENTRY__
diff --git a/src/gpu-compute/kernel_code.hh b/src/gpu-compute/kernel_code.hh
index 1885b40..0e9bade 100644
--- a/src/gpu-compute/kernel_code.hh
+++ b/src/gpu-compute/kernel_code.hh
@@ -37,6 +37,9 @@
#include <bitset>
#include <cstdint>
+namespace gem5
+{
+
/**
* these enums represent the indices into the
* initialRegState bitfields in HsaKernelInfo.
@@ -187,4 +190,6 @@
uint64_t control_directives[16];
};
+} // namespace gem5
+
#endif // __GPU_COMPUTE_KERNEL_CODE_HH__
diff --git a/src/gpu-compute/lds_state.cc b/src/gpu-compute/lds_state.cc
index c3bafb2..0c0b47e 100644
--- a/src/gpu-compute/lds_state.cc
+++ b/src/gpu-compute/lds_state.cc
@@ -41,6 +41,9 @@
#include "gpu-compute/gpu_dyn_inst.hh"
#include "gpu-compute/shader.hh"
+namespace gem5
+{
+
/**
* the default constructor that works with SWIG
*/
@@ -319,3 +322,5 @@
{
ldsState->process();
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/lds_state.hh b/src/gpu-compute/lds_state.hh
index 0daa840..65aec57 100644
--- a/src/gpu-compute/lds_state.hh
+++ b/src/gpu-compute/lds_state.hh
@@ -46,6 +46,9 @@
#include "params/LdsState.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
class ComputeUnit;
/**
@@ -529,4 +532,6 @@
int banks = 0;
};
+} // namespace gem5
+
#endif // __LDS_STATE_HH__
diff --git a/src/gpu-compute/local_memory_pipeline.cc b/src/gpu-compute/local_memory_pipeline.cc
index d55d16d..4ed9689 100644
--- a/src/gpu-compute/local_memory_pipeline.cc
+++ b/src/gpu-compute/local_memory_pipeline.cc
@@ -41,6 +41,9 @@
#include "gpu-compute/vector_register_file.hh"
#include "gpu-compute/wavefront.hh"
+namespace gem5
+{
+
LocalMemPipeline::LocalMemPipeline(const ComputeUnitParams &p, ComputeUnit &cu)
: computeUnit(cu), _name(cu.name() + ".LocalMemPipeline"),
lmQueueSize(p.local_mem_queue_size), stats(&cu)
@@ -132,3 +135,5 @@
"are delayed before updating the VRF")
{
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/local_memory_pipeline.hh b/src/gpu-compute/local_memory_pipeline.hh
index 3af2232..a4e3629 100644
--- a/src/gpu-compute/local_memory_pipeline.hh
+++ b/src/gpu-compute/local_memory_pipeline.hh
@@ -50,6 +50,9 @@
* loads and stores that have returned from the LDS.
*/
+namespace gem5
+{
+
class ComputeUnit;
class Wavefront;
@@ -105,4 +108,6 @@
} stats;
};
+} // namespace gem5
+
#endif // __LOCAL_MEMORY_PIPELINE_HH__
diff --git a/src/gpu-compute/misc.hh b/src/gpu-compute/misc.hh
index 776dd0b..f45786d 100644
--- a/src/gpu-compute/misc.hh
+++ b/src/gpu-compute/misc.hh
@@ -41,6 +41,9 @@
#include "base/logging.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
class GPUDynInst;
typedef std::bitset<std::numeric_limits<unsigned long long>::digits>
@@ -173,4 +176,6 @@
}
};
+} // namespace gem5
+
#endif // __MISC_HH__
diff --git a/src/gpu-compute/of_scheduling_policy.hh b/src/gpu-compute/of_scheduling_policy.hh
index d6b5846..cd60cd0 100644
--- a/src/gpu-compute/of_scheduling_policy.hh
+++ b/src/gpu-compute/of_scheduling_policy.hh
@@ -39,6 +39,9 @@
#include "gpu-compute/scheduling_policy.hh"
#include "gpu-compute/wavefront.hh"
+namespace gem5
+{
+
// oldest first where age is marked by the wave id
class OFSchedulingPolicy final : public __SchedulingPolicy<OFSchedulingPolicy>
{
@@ -77,4 +80,6 @@
}
};
+} // namespace gem5
+
#endif // __GPU_COMPUTE_OF_SCHEDULING_POLICY_HH__
diff --git a/src/gpu-compute/operand_info.hh b/src/gpu-compute/operand_info.hh
index 90409d2..a0a4f6f 100644
--- a/src/gpu-compute/operand_info.hh
+++ b/src/gpu-compute/operand_info.hh
@@ -38,6 +38,9 @@
#include "base/flags.hh"
#include "config/the_gpu_isa.hh"
+namespace gem5
+{
+
class OperandInfo
{
public:
@@ -132,7 +135,7 @@
}
typedef uint32_t FlagsType;
- typedef ::Flags<FlagsType> Flags;
+ typedef gem5::Flags<FlagsType> Flags;
private:
@@ -194,4 +197,6 @@
mutable std::vector<int> _bankReadCounts;
};
+} // namespace gem5
+
#endif // __GPU_COMPUTE_OPERAND_INFO_H__
diff --git a/src/gpu-compute/pool_manager.cc b/src/gpu-compute/pool_manager.cc
index 0a0911f..a331cb5 100644
--- a/src/gpu-compute/pool_manager.cc
+++ b/src/gpu-compute/pool_manager.cc
@@ -33,8 +33,13 @@
#include "gpu-compute/pool_manager.hh"
+namespace gem5
+{
+
PoolManager::PoolManager(const PoolManagerParams &p)
: SimObject(p), _minAllocation(p.min_alloc), _poolSize(p.pool_size)
{
assert(_poolSize > 0);
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/pool_manager.hh b/src/gpu-compute/pool_manager.hh
index 2de8fd2..ffd59f7 100644
--- a/src/gpu-compute/pool_manager.hh
+++ b/src/gpu-compute/pool_manager.hh
@@ -41,6 +41,9 @@
#include "params/PoolManager.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
// Pool Manager Logic
class PoolManager : public SimObject
{
@@ -73,4 +76,6 @@
uint32_t _poolSize;
};
+} // namespace gem5
+
#endif // __POOL_MANAGER_HH__
diff --git a/src/gpu-compute/register_file.cc b/src/gpu-compute/register_file.cc
index f91bbf4..ba9d3e0 100644
--- a/src/gpu-compute/register_file.cc
+++ b/src/gpu-compute/register_file.cc
@@ -45,6 +45,9 @@
#include "gpu-compute/wavefront.hh"
#include "params/RegisterFile.hh"
+namespace gem5
+{
+
RegisterFile::RegisterFile(const RegisterFileParams &p)
: SimObject(p), simdId(p.simd_id), _numRegs(p.num_regs), stats(this)
{
@@ -201,3 +204,5 @@
"Total number of register file bank SRAM activations for writes")
{
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/register_file.hh b/src/gpu-compute/register_file.hh
index 12c4058..9fd4709 100644
--- a/src/gpu-compute/register_file.hh
+++ b/src/gpu-compute/register_file.hh
@@ -42,6 +42,9 @@
#include "gpu-compute/misc.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class ComputeUnit;
class Shader;
class PoolManager;
@@ -169,4 +172,6 @@
} stats;
};
+} // namespace gem5
+
#endif // __REGISTER_FILE_HH__
diff --git a/src/gpu-compute/register_manager.cc b/src/gpu-compute/register_manager.cc
index 781ecc2..ffb0d00 100644
--- a/src/gpu-compute/register_manager.cc
+++ b/src/gpu-compute/register_manager.cc
@@ -44,6 +44,9 @@
#include "gpu-compute/wavefront.hh"
#include "params/RegisterManager.hh"
+namespace gem5
+{
+
RegisterManager::RegisterManager(const RegisterManagerParams &p)
: SimObject(p), srfPoolMgrs(p.srf_pool_managers),
vrfPoolMgrs(p.vrf_pool_managers)
@@ -129,3 +132,5 @@
{
policy->freeRegisters(w);
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/register_manager.hh b/src/gpu-compute/register_manager.hh
index c6ede7f..fb97ff8 100644
--- a/src/gpu-compute/register_manager.hh
+++ b/src/gpu-compute/register_manager.hh
@@ -45,6 +45,9 @@
#include "sim/sim_object.hh"
#include "sim/stats.hh"
+namespace gem5
+{
+
class ComputeUnit;
class Wavefront;
@@ -86,4 +89,6 @@
std::string _name;
};
+} // namespace gem5
+
#endif // __REGISTER_MANAGER_HH__
diff --git a/src/gpu-compute/register_manager_policy.hh b/src/gpu-compute/register_manager_policy.hh
index 99b4df0..6895c99 100644
--- a/src/gpu-compute/register_manager_policy.hh
+++ b/src/gpu-compute/register_manager_policy.hh
@@ -36,6 +36,9 @@
#include <cstdint>
+namespace gem5
+{
+
class ComputeUnit;
class HSAQueueEntry;
class Wavefront;
@@ -78,4 +81,6 @@
ComputeUnit *cu;
};
+} // namespace gem5
+
#endif // __REGISTER_MANAGER_POLICY_HH__
diff --git a/src/gpu-compute/rr_scheduling_policy.hh b/src/gpu-compute/rr_scheduling_policy.hh
index 75a0981..00ba775 100644
--- a/src/gpu-compute/rr_scheduling_policy.hh
+++ b/src/gpu-compute/rr_scheduling_policy.hh
@@ -40,6 +40,9 @@
#include "gpu-compute/scheduling_policy.hh"
#include "gpu-compute/wavefront.hh"
+namespace gem5
+{
+
// round-robin pick among the list of ready waves
class RRSchedulingPolicy final : public __SchedulingPolicy<RRSchedulingPolicy>
{
@@ -71,4 +74,6 @@
}
};
+} // namespace gem5
+
#endif // __GPU_COMPUTE_RR_SCHEDULING_POLICY_HH__
diff --git a/src/gpu-compute/scalar_memory_pipeline.cc b/src/gpu-compute/scalar_memory_pipeline.cc
index 1e296da..f697374 100644
--- a/src/gpu-compute/scalar_memory_pipeline.cc
+++ b/src/gpu-compute/scalar_memory_pipeline.cc
@@ -41,6 +41,9 @@
#include "gpu-compute/shader.hh"
#include "gpu-compute/wavefront.hh"
+namespace gem5
+{
+
ScalarMemPipeline::ScalarMemPipeline(const ComputeUnitParams &p,
ComputeUnit &cu)
: computeUnit(cu), _name(cu.name() + ".ScalarMemPipeline"),
@@ -140,3 +143,5 @@
computeUnit.cu_id, mp->simdId, mp->wfSlotId);
}
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/scalar_memory_pipeline.hh b/src/gpu-compute/scalar_memory_pipeline.hh
index 001436d..d4d0862 100644
--- a/src/gpu-compute/scalar_memory_pipeline.hh
+++ b/src/gpu-compute/scalar_memory_pipeline.hh
@@ -52,6 +52,9 @@
* returned from the memory sub-system.
*/
+namespace gem5
+{
+
class ComputeUnit;
class ScalarMemPipeline
@@ -107,4 +110,6 @@
std::queue<GPUDynInstPtr> returnedLoads;
};
+} // namespace gem5
+
#endif // __GPU_COMPUTE_SCALAR_MEMORY_PIPELINE_HH__
diff --git a/src/gpu-compute/scalar_register_file.cc b/src/gpu-compute/scalar_register_file.cc
index 14ea3fe..52e0a2f 100644
--- a/src/gpu-compute/scalar_register_file.cc
+++ b/src/gpu-compute/scalar_register_file.cc
@@ -41,6 +41,9 @@
#include "gpu-compute/wavefront.hh"
#include "params/ScalarRegisterFile.hh"
+namespace gem5
+{
+
ScalarRegisterFile::ScalarRegisterFile(const ScalarRegisterFileParams &p)
: RegisterFile(p)
{
@@ -107,3 +110,5 @@
stats.registerWrites += ii->numDstScalarDWords();
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/scalar_register_file.hh b/src/gpu-compute/scalar_register_file.hh
index 7d6e893..fa992fd 100644
--- a/src/gpu-compute/scalar_register_file.hh
+++ b/src/gpu-compute/scalar_register_file.hh
@@ -42,6 +42,9 @@
#include "gpu-compute/register_file.hh"
#include "gpu-compute/wavefront.hh"
+namespace gem5
+{
+
struct ScalarRegisterFileParams;
// Scalar Register File
@@ -98,4 +101,6 @@
std::vector<ScalarRegU32> regFile;
};
+} // namespace gem5
+
#endif // __GPU_COMPUTE_SCALAR_REGISTER_FILE_HH__
diff --git a/src/gpu-compute/schedule_stage.cc b/src/gpu-compute/schedule_stage.cc
index 757ea2f..b3c91a8 100644
--- a/src/gpu-compute/schedule_stage.cc
+++ b/src/gpu-compute/schedule_stage.cc
@@ -44,6 +44,9 @@
#include "gpu-compute/vector_register_file.hh"
#include "gpu-compute/wavefront.hh"
+namespace gem5
+{
+
ScheduleStage::ScheduleStage(const ComputeUnitParams &p, ComputeUnit &cu,
ScoreboardCheckToSchedule &from_scoreboard_check,
ScheduleToExecute &to_execute)
@@ -855,3 +858,5 @@
rfAccessStalls.subname(SCH_SRF_WR_ACCESS_NRDY, csprintf("SrfWr"));
rfAccessStalls.subname(SCH_RF_ACCESS_NRDY, csprintf("Any"));
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/schedule_stage.hh b/src/gpu-compute/schedule_stage.hh
index 7959ec4..f6cd1bc 100644
--- a/src/gpu-compute/schedule_stage.hh
+++ b/src/gpu-compute/schedule_stage.hh
@@ -46,6 +46,9 @@
#include "gpu-compute/misc.hh"
#include "gpu-compute/scheduler.hh"
+namespace gem5
+{
+
// Schedule or execution arbitration stage.
// From the pool of ready waves in the ready list,
// one wave is selected for each execution resource.
@@ -230,4 +233,6 @@
} stats;
};
+} // namespace gem5
+
#endif // __SCHEDULE_STAGE_HH__
diff --git a/src/gpu-compute/scheduler.cc b/src/gpu-compute/scheduler.cc
index 6b3de03..4f47386 100644
--- a/src/gpu-compute/scheduler.cc
+++ b/src/gpu-compute/scheduler.cc
@@ -37,6 +37,9 @@
#include "gpu-compute/rr_scheduling_policy.hh"
#include "params/ComputeUnit.hh"
+namespace gem5
+{
+
Scheduler::Scheduler(const ComputeUnitParams &p)
{
if (p.execPolicy == "OLDEST-FIRST") {
@@ -59,3 +62,5 @@
{
scheduleList = sched_list;
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/scheduler.hh b/src/gpu-compute/scheduler.hh
index fbf7206..abb5e10 100644
--- a/src/gpu-compute/scheduler.hh
+++ b/src/gpu-compute/scheduler.hh
@@ -38,6 +38,9 @@
#include "gpu-compute/scheduling_policy.hh"
+namespace gem5
+{
+
struct ComputeUnitParams;
class Scheduler
@@ -56,4 +59,6 @@
std::vector<Wavefront*> *scheduleList;
};
+} // namespace gem5
+
#endif // __GPU_COMPUTE_SCHEDULER_HH__
diff --git a/src/gpu-compute/scheduling_policy.hh b/src/gpu-compute/scheduling_policy.hh
index cba85bb..6566c57 100644
--- a/src/gpu-compute/scheduling_policy.hh
+++ b/src/gpu-compute/scheduling_policy.hh
@@ -36,6 +36,9 @@
#include <vector>
+namespace gem5
+{
+
class Wavefront;
/**
@@ -69,4 +72,6 @@
}
};
+} // namespace gem5
+
#endif // __GPU_COMPUTE_SCHEDULING_POLICY_HH__
diff --git a/src/gpu-compute/scoreboard_check_stage.cc b/src/gpu-compute/scoreboard_check_stage.cc
index f0ff664..9e9277c 100644
--- a/src/gpu-compute/scoreboard_check_stage.cc
+++ b/src/gpu-compute/scoreboard_check_stage.cc
@@ -44,6 +44,9 @@
#include "gpu-compute/wavefront.hh"
#include "params/ComputeUnit.hh"
+namespace gem5
+{
+
ScoreboardCheckStage::ScoreboardCheckStage(const ComputeUnitParams &p,
ComputeUnit &cu,
ScoreboardCheckToSchedule
@@ -291,3 +294,5 @@
stallCycles.subname(NRDY_SGPR_NRDY, csprintf("SgprBusy"));
stallCycles.subname(INST_RDY, csprintf("InstrReady"));
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/scoreboard_check_stage.hh b/src/gpu-compute/scoreboard_check_stage.hh
index b522f38..bed7a7a 100644
--- a/src/gpu-compute/scoreboard_check_stage.hh
+++ b/src/gpu-compute/scoreboard_check_stage.hh
@@ -43,6 +43,9 @@
#include "base/statistics.hh"
#include "base/stats/group.hh"
+namespace gem5
+{
+
class ComputeUnit;
class ScoreboardCheckToSchedule;
class Wavefront;
@@ -107,4 +110,6 @@
} stats;
};
+} // namespace gem5
+
#endif // __SCOREBOARD_CHECK_STAGE_HH__
diff --git a/src/gpu-compute/shader.cc b/src/gpu-compute/shader.cc
index 8f9e59e..7f5467a 100644
--- a/src/gpu-compute/shader.cc
+++ b/src/gpu-compute/shader.cc
@@ -52,6 +52,9 @@
#include "mem/ruby/system/RubySystem.hh"
#include "sim/sim_exit.hh"
+namespace gem5
+{
+
Shader::Shader(const Params &p) : ClockedObject(p),
_activeCus(0), _lastInactiveTick(0), cpuThread(nullptr),
gpuTc(nullptr), cpuPointer(p.cpu_pointer),
@@ -591,3 +594,5 @@
.flags(statistics::pdf | statistics::oneline);
}
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/shader.hh b/src/gpu-compute/shader.hh
index 99616e0..23cb69c 100644
--- a/src/gpu-compute/shader.hh
+++ b/src/gpu-compute/shader.hh
@@ -58,6 +58,9 @@
#include "sim/process.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class BaseTLB;
class GPUCommandProcessor;
class GPUDispatcher;
@@ -315,4 +318,6 @@
} stats;
};
+} // namespace gem5
+
#endif // __SHADER_HH__
diff --git a/src/gpu-compute/simple_pool_manager.cc b/src/gpu-compute/simple_pool_manager.cc
index cccda90..2e3a0ce 100644
--- a/src/gpu-compute/simple_pool_manager.cc
+++ b/src/gpu-compute/simple_pool_manager.cc
@@ -35,6 +35,9 @@
#include "base/logging.hh"
+namespace gem5
+{
+
// return the min number of elements that the manager can reserve given
// a request for "size" elements
uint32_t
@@ -102,3 +105,5 @@
return region.second + poolSize() - region.first + 1;
}
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/simple_pool_manager.hh b/src/gpu-compute/simple_pool_manager.hh
index 06b04e5..5241540 100644
--- a/src/gpu-compute/simple_pool_manager.hh
+++ b/src/gpu-compute/simple_pool_manager.hh
@@ -40,6 +40,9 @@
#include "gpu-compute/pool_manager.hh"
#include "params/SimplePoolManager.hh"
+namespace gem5
+{
+
// Simple Pool Manager: allows one region per pool. No region merging is
// supported.
class SimplePoolManager : public PoolManager
@@ -68,4 +71,6 @@
uint32_t _reservedGroups;
};
+} // namespace gem5
+
#endif // __SIMPLE_POOL_MANAGER_HH__
diff --git a/src/gpu-compute/static_register_manager_policy.cc b/src/gpu-compute/static_register_manager_policy.cc
index 4a869d9..cc32abe 100644
--- a/src/gpu-compute/static_register_manager_policy.cc
+++ b/src/gpu-compute/static_register_manager_policy.cc
@@ -42,6 +42,9 @@
#include "gpu-compute/vector_register_file.hh"
#include "gpu-compute/wavefront.hh"
+namespace gem5
+{
+
StaticRegisterManagerPolicy::StaticRegisterManagerPolicy()
{
}
@@ -178,3 +181,5 @@
w->reservedScalarRegs = 0;
w->startSgprIndex = 0;
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/static_register_manager_policy.hh b/src/gpu-compute/static_register_manager_policy.hh
index a5479e1..a2e9ab8 100644
--- a/src/gpu-compute/static_register_manager_policy.hh
+++ b/src/gpu-compute/static_register_manager_policy.hh
@@ -36,6 +36,9 @@
#include "gpu-compute/register_manager_policy.hh"
+namespace gem5
+{
+
class HSAQueueEntry;
class StaticRegisterManagerPolicy : public RegisterManagerPolicy
@@ -58,4 +61,6 @@
void freeRegisters(Wavefront *w) override;
};
+} // namespace gem5
+
#endif // __STATIC_REGISTER_MANAGER_POLICY_HH__
diff --git a/src/gpu-compute/tlb_coalescer.cc b/src/gpu-compute/tlb_coalescer.cc
index be01114..50876a7 100644
--- a/src/gpu-compute/tlb_coalescer.cc
+++ b/src/gpu-compute/tlb_coalescer.cc
@@ -40,6 +40,9 @@
#include "debug/GPUTLB.hh"
#include "sim/process.hh"
+namespace gem5
+{
+
TLBCoalescer::TLBCoalescer(const Params &p)
: ClockedObject(p),
TLBProbesPerCycle(p.probesPerCycle),
@@ -532,3 +535,5 @@
{
localLatency = localqueuingCycles / uncoalescedAccesses;
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/tlb_coalescer.hh b/src/gpu-compute/tlb_coalescer.hh
index 22d375d..b97801b 100644
--- a/src/gpu-compute/tlb_coalescer.hh
+++ b/src/gpu-compute/tlb_coalescer.hh
@@ -51,6 +51,9 @@
#include "params/TLBCoalescer.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
class BaseTLB;
class Packet;
class ThreadContext;
@@ -218,4 +221,6 @@
} stats;
};
+} // namespace gem5
+
#endif // __TLB_COALESCER_HH__
diff --git a/src/gpu-compute/vector_register_file.cc b/src/gpu-compute/vector_register_file.cc
index 2c55c4e..de2d992 100644
--- a/src/gpu-compute/vector_register_file.cc
+++ b/src/gpu-compute/vector_register_file.cc
@@ -44,6 +44,9 @@
#include "gpu-compute/wavefront.hh"
#include "params/VectorRegisterFile.hh"
+namespace gem5
+{
+
VectorRegisterFile::VectorRegisterFile(const VectorRegisterFileParams &p)
: RegisterFile(p)
{
@@ -163,3 +166,5 @@
mask = mask >> 4;
}
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/vector_register_file.hh b/src/gpu-compute/vector_register_file.hh
index a9f60b4..4743a0f 100644
--- a/src/gpu-compute/vector_register_file.hh
+++ b/src/gpu-compute/vector_register_file.hh
@@ -40,6 +40,9 @@
#include "gpu-compute/register_file.hh"
#include "gpu-compute/wavefront.hh"
+namespace gem5
+{
+
struct VectorRegisterFileParams;
// Vector Register File
@@ -106,4 +109,6 @@
std::vector<VecRegContainer> regFile;
};
+} // namespace gem5
+
#endif // __VECTOR_REGISTER_FILE_HH__
diff --git a/src/gpu-compute/wavefront.cc b/src/gpu-compute/wavefront.cc
index 3dbf15b..cf7b91a 100644
--- a/src/gpu-compute/wavefront.cc
+++ b/src/gpu-compute/wavefront.cc
@@ -44,6 +44,9 @@
#include "gpu-compute/simple_pool_manager.hh"
#include "gpu-compute/vector_register_file.hh"
+namespace gem5
+{
+
Wavefront::Wavefront(const Params &p)
: SimObject(p), wfSlotId(p.wf_slot_id), simdId(p.simdId),
maxIbSize(p.max_ib_size), _gpuISA(*this),
@@ -1462,3 +1465,5 @@
vecRawDistance.init(0, 20, 1);
readsPerWrite.init(0, 4, 1);
}
+
+} // namespace gem5
diff --git a/src/gpu-compute/wavefront.hh b/src/gpu-compute/wavefront.hh
index 84b705e..2cc8bd5 100644
--- a/src/gpu-compute/wavefront.hh
+++ b/src/gpu-compute/wavefront.hh
@@ -56,6 +56,9 @@
#include "params/Wavefront.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class Wavefront : public SimObject
{
public:
@@ -376,4 +379,6 @@
} stats;
};
+} // namespace gem5
+
#endif // __GPU_COMPUTE_WAVEFRONT_HH__
diff --git a/src/kern/freebsd/events.cc b/src/kern/freebsd/events.cc
index e8b4be8..1523227 100644
--- a/src/kern/freebsd/events.cc
+++ b/src/kern/freebsd/events.cc
@@ -40,6 +40,9 @@
#include "kern/system_events.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(FreeBSD, free_bsd);
namespace free_bsd
{
@@ -62,3 +65,4 @@
}
} // namespace free_bsd
+} // namespace gem5
diff --git a/src/kern/freebsd/events.hh b/src/kern/freebsd/events.hh
index 884b36a..c89ad0c 100644
--- a/src/kern/freebsd/events.hh
+++ b/src/kern/freebsd/events.hh
@@ -37,6 +37,9 @@
#include "kern/system_events.hh"
#include "sim/guest_abi.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(FreeBSD, free_bsd);
namespace free_bsd
{
@@ -83,6 +86,7 @@
}
};
-}
+} // namespace free_bsd
+} // namespace gem5
#endif
diff --git a/src/kern/freebsd/freebsd.hh b/src/kern/freebsd/freebsd.hh
index de5da9d..232d707 100644
--- a/src/kern/freebsd/freebsd.hh
+++ b/src/kern/freebsd/freebsd.hh
@@ -38,6 +38,9 @@
#include "base/types.hh"
#include "kern/operatingsystem.hh"
+namespace gem5
+{
+
class ThreadContext;
class Process;
@@ -117,4 +120,6 @@
}; // class FreeBSD
+} // namespace gem5
+
#endif // __FREEBSD_HH__
diff --git a/src/kern/linux/events.cc b/src/kern/linux/events.cc
index 2d5d500..6ec883c 100644
--- a/src/kern/linux/events.cc
+++ b/src/kern/linux/events.cc
@@ -51,6 +51,9 @@
#include "sim/core.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Linux, linux);
namespace linux
{
@@ -95,3 +98,4 @@
}
} // namespace linux
+} // namespace gem5
diff --git a/src/kern/linux/events.hh b/src/kern/linux/events.hh
index 8ce2887..3884c77 100644
--- a/src/kern/linux/events.hh
+++ b/src/kern/linux/events.hh
@@ -52,6 +52,9 @@
#include "mem/se_translating_port_proxy.hh"
#include "sim/guest_abi.hh"
+namespace gem5
+{
+
class ThreadContext;
GEM5_DEPRECATED_NAMESPACE(Linux, linux);
@@ -170,5 +173,6 @@
};
} // namespace linux
+} // namespace gem5
#endif // __KERN_LINUX_EVENTS_HH__
diff --git a/src/kern/linux/flag_tables.hh b/src/kern/linux/flag_tables.hh
index 9b384b7..d2bf55f 100644
--- a/src/kern/linux/flag_tables.hh
+++ b/src/kern/linux/flag_tables.hh
@@ -53,6 +53,9 @@
* See src/arch/<*>/linux/linux.cc.
*/
+namespace gem5
+{
+
// open(2) flags translation table
const std::map<int, int> TARGET::openFlagTable = {
#ifdef _MSC_VER
@@ -105,3 +108,5 @@
#endif
#endif /* _MSC_VER */
};
+
+} // namespace gem5
diff --git a/src/kern/linux/helpers.cc b/src/kern/linux/helpers.cc
index 3f91018..4841809 100644
--- a/src/kern/linux/helpers.cc
+++ b/src/kern/linux/helpers.cc
@@ -43,6 +43,9 @@
#include "sim/byteswap.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
struct GEM5_PACKED DmesgEntry
{
uint64_t ts_nsec;
@@ -148,3 +151,5 @@
cur += ret;
}
}
+
+} // namespace gem5
diff --git a/src/kern/linux/helpers.hh b/src/kern/linux/helpers.hh
index f9c44c7..1ad5b41 100644
--- a/src/kern/linux/helpers.hh
+++ b/src/kern/linux/helpers.hh
@@ -42,6 +42,9 @@
#include "base/compiler.hh"
+namespace gem5
+{
+
class ThreadContext;
GEM5_DEPRECATED_NAMESPACE(Linux, linux);
@@ -57,5 +60,6 @@
void dumpDmesg(ThreadContext *tc, std::ostream &os);
} // namespace linux
+} // namespace gem5
#endif // __KERN_LINUX_HELPERS_HH__
diff --git a/src/kern/linux/linux.cc b/src/kern/linux/linux.cc
index a6d182c..86ea8c7 100644
--- a/src/kern/linux/linux.cc
+++ b/src/kern/linux/linux.cc
@@ -39,6 +39,9 @@
#include "sim/system.hh"
#include "sim/vma.hh"
+namespace gem5
+{
+
// The OS methods are called statically. Instantiate the random number
// generator for access to /dev/urandom here.
Random Linux::random;
@@ -130,3 +133,5 @@
}
return line.str();
}
+
+} // namespace gem5
diff --git a/src/kern/linux/linux.hh b/src/kern/linux/linux.hh
index ef5f72a..7e1df58 100644
--- a/src/kern/linux/linux.hh
+++ b/src/kern/linux/linux.hh
@@ -36,6 +36,9 @@
#include "kern/operatingsystem.hh"
#include "sim/process.hh"
+namespace gem5
+{
+
class ThreadContext;
///
@@ -318,4 +321,6 @@
static const unsigned TGT_WNOWAIT = 0x01000000;
}; // class Linux
+} // namespace gem5
+
#endif // __LINUX_HH__
diff --git a/src/kern/linux/printk.cc b/src/kern/linux/printk.cc
index 9cb02a6..e8b26e8 100644
--- a/src/kern/linux/printk.cc
+++ b/src/kern/linux/printk.cc
@@ -38,6 +38,9 @@
#include "cpu/thread_context.hh"
#include "mem/port_proxy.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Linux, linux);
namespace linux
{
@@ -250,3 +253,4 @@
}
} // namespace linux
+} // namespace gem5
diff --git a/src/kern/linux/printk.hh b/src/kern/linux/printk.hh
index de3cbc9..7b545bc 100644
--- a/src/kern/linux/printk.hh
+++ b/src/kern/linux/printk.hh
@@ -35,6 +35,9 @@
#include "base/types.hh"
#include "sim/guest_abi.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Linux, linux);
namespace linux
{
@@ -45,5 +48,6 @@
PrintkVarArgs args);
} // namespace linux
+} // namespace gem5
#endif // __KERN_LINUX_PRINTK_HH__
diff --git a/src/kern/operatingsystem.cc b/src/kern/operatingsystem.cc
index fd72e11..68ef76f 100644
--- a/src/kern/operatingsystem.cc
+++ b/src/kern/operatingsystem.cc
@@ -31,6 +31,9 @@
#include "base/logging.hh"
+namespace gem5
+{
+
int
OperatingSystem::openSpecialFile(std::string path, Process *process,
ThreadContext *tc)
@@ -41,4 +44,4 @@
return -1;
}
-
+} // namespace gem5
diff --git a/src/kern/operatingsystem.hh b/src/kern/operatingsystem.hh
index 084eceb..014397e 100644
--- a/src/kern/operatingsystem.hh
+++ b/src/kern/operatingsystem.hh
@@ -33,6 +33,9 @@
#include <string>
+namespace gem5
+{
+
class Process;
class ThreadContext;
@@ -115,4 +118,6 @@
}; // class OperatingSystem
+} // namespace gem5
+
#endif // __OPERATINGSYSTEM_HH__
diff --git a/src/kern/solaris/solaris.hh b/src/kern/solaris/solaris.hh
index b891a7d..6944bc5 100644
--- a/src/kern/solaris/solaris.hh
+++ b/src/kern/solaris/solaris.hh
@@ -32,6 +32,9 @@
#include "base/types.hh"
#include "kern/operatingsystem.hh"
+namespace gem5
+{
+
///
/// This class encapsulates the types, structures, constants,
/// functions, and syscall-number mappings specific to the Solaris
@@ -121,4 +124,6 @@
}; // class Solaris
+} // namespace gem5
+
#endif // __SOLARIS_HH__
diff --git a/src/kern/system_events.cc b/src/kern/system_events.cc
index 3ce20f5..e0c7e88 100644
--- a/src/kern/system_events.cc
+++ b/src/kern/system_events.cc
@@ -33,6 +33,9 @@
#include "cpu/thread_context.hh"
#include "debug/PCEvent.hh"
+namespace gem5
+{
+
void
SkipFuncBase::process(ThreadContext *tc)
{
@@ -43,3 +46,5 @@
DPRINTF(PCEvent, "skipping %s: pc = %s, newpc = %s\n", description,
oldPC, tc->pcState());
}
+
+} // namespace gem5
diff --git a/src/kern/system_events.hh b/src/kern/system_events.hh
index 96eda7f..2173af5 100644
--- a/src/kern/system_events.hh
+++ b/src/kern/system_events.hh
@@ -31,6 +31,9 @@
#include "cpu/pc_event.hh"
+namespace gem5
+{
+
class SkipFuncBase : public PCEvent
{
protected:
@@ -44,4 +47,6 @@
void process(ThreadContext *tc) override;
};
+} // namespace gem5
+
#endif // __KERN_SYSTEM_EVENTS_HH__
diff --git a/src/learning_gem5/part2/HelloObject.py b/src/learning_gem5/part2/HelloObject.py
index 91b4125..c7daf10 100644
--- a/src/learning_gem5/part2/HelloObject.py
+++ b/src/learning_gem5/part2/HelloObject.py
@@ -31,6 +31,7 @@
class HelloObject(SimObject):
type = 'HelloObject'
cxx_header = "learning_gem5/part2/hello_object.hh"
+ cxx_class = 'gem5::HelloObject'
time_to_wait = Param.Latency("Time before firing the event")
number_of_fires = Param.Int(1, "Number of times to fire the event before "
@@ -41,6 +42,7 @@
class GoodbyeObject(SimObject):
type = 'GoodbyeObject'
cxx_header = "learning_gem5/part2/goodbye_object.hh"
+ cxx_class = 'gem5::GoodbyeObject'
buffer_size = Param.MemorySize('1kB',
"Size of buffer to fill with goodbye")
diff --git a/src/learning_gem5/part2/SimpleCache.py b/src/learning_gem5/part2/SimpleCache.py
index ad94b50..40a075c 100644
--- a/src/learning_gem5/part2/SimpleCache.py
+++ b/src/learning_gem5/part2/SimpleCache.py
@@ -32,6 +32,7 @@
class SimpleCache(ClockedObject):
type = 'SimpleCache'
cxx_header = "learning_gem5/part2/simple_cache.hh"
+ cxx_class = 'gem5::SimpleCache'
# Vector port example. Both the instruction and data ports connect to this
# port which is automatically split out into two ports.
diff --git a/src/learning_gem5/part2/SimpleMemobj.py b/src/learning_gem5/part2/SimpleMemobj.py
index b72ebe2..0231b1f 100644
--- a/src/learning_gem5/part2/SimpleMemobj.py
+++ b/src/learning_gem5/part2/SimpleMemobj.py
@@ -31,6 +31,7 @@
class SimpleMemobj(SimObject):
type = 'SimpleMemobj'
cxx_header = "learning_gem5/part2/simple_memobj.hh"
+ cxx_class = 'gem5::SimpleMemobj'
inst_port = ResponsePort("CPU side port, receives requests")
data_port = ResponsePort("CPU side port, receives requests")
diff --git a/src/learning_gem5/part2/SimpleObject.py b/src/learning_gem5/part2/SimpleObject.py
index 23fcf5f..28555dd 100644
--- a/src/learning_gem5/part2/SimpleObject.py
+++ b/src/learning_gem5/part2/SimpleObject.py
@@ -31,3 +31,4 @@
class SimpleObject(SimObject):
type = 'SimpleObject'
cxx_header = "learning_gem5/part2/simple_object.hh"
+ cxx_class = 'gem5::SimpleObject'
diff --git a/src/learning_gem5/part2/goodbye_object.cc b/src/learning_gem5/part2/goodbye_object.cc
index 6d2f904..d7c3985 100644
--- a/src/learning_gem5/part2/goodbye_object.cc
+++ b/src/learning_gem5/part2/goodbye_object.cc
@@ -32,6 +32,9 @@
#include "debug/HelloExample.hh"
#include "sim/sim_exit.hh"
+namespace gem5
+{
+
GoodbyeObject::GoodbyeObject(const GoodbyeObjectParams ¶ms) :
SimObject(params), event([this]{ processEvent(); }, name() + ".event"),
bandwidth(params.write_bandwidth), bufferSize(params.buffer_size),
@@ -94,3 +97,5 @@
exitSimLoop(buffer, 0, curTick() + bandwidth * bytes_copied);
}
}
+
+} // namespace gem5
diff --git a/src/learning_gem5/part2/goodbye_object.hh b/src/learning_gem5/part2/goodbye_object.hh
index eaf3c5c..235fec2 100644
--- a/src/learning_gem5/part2/goodbye_object.hh
+++ b/src/learning_gem5/part2/goodbye_object.hh
@@ -34,6 +34,9 @@
#include "params/GoodbyeObject.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class GoodbyeObject : public SimObject
{
private:
@@ -79,4 +82,6 @@
void sayGoodbye(std::string name);
};
+} // namespace gem5
+
#endif // __LEARNING_GEM5_GOODBYE_OBJECT_HH__
diff --git a/src/learning_gem5/part2/hello_object.cc b/src/learning_gem5/part2/hello_object.cc
index e156cac..af4f8f9 100644
--- a/src/learning_gem5/part2/hello_object.cc
+++ b/src/learning_gem5/part2/hello_object.cc
@@ -32,6 +32,9 @@
#include "base/trace.hh"
#include "debug/HelloExample.hh"
+namespace gem5
+{
+
HelloObject::HelloObject(const HelloObjectParams ¶ms) :
SimObject(params),
// This is a C++ lambda. When the event is triggered, it will call the
@@ -68,3 +71,5 @@
schedule(event, curTick() + latency);
}
}
+
+} // namespace gem5
diff --git a/src/learning_gem5/part2/hello_object.hh b/src/learning_gem5/part2/hello_object.hh
index ce167ff..c34dde3 100644
--- a/src/learning_gem5/part2/hello_object.hh
+++ b/src/learning_gem5/part2/hello_object.hh
@@ -35,6 +35,9 @@
#include "params/HelloObject.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class HelloObject : public SimObject
{
private:
@@ -69,4 +72,6 @@
void startup();
};
+} // namespace gem5
+
#endif // __LEARNING_GEM5_HELLO_OBJECT_HH__
diff --git a/src/learning_gem5/part2/simple_cache.cc b/src/learning_gem5/part2/simple_cache.cc
index aafafd2..b07f939 100644
--- a/src/learning_gem5/part2/simple_cache.cc
+++ b/src/learning_gem5/part2/simple_cache.cc
@@ -33,6 +33,9 @@
#include "debug/SimpleCache.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
SimpleCache::SimpleCache(const SimpleCacheParams ¶ms) :
ClockedObject(params),
latency(params.latency),
@@ -434,3 +437,5 @@
{
missLatency.init(16); // number of buckets
}
+
+} // namespace gem5
diff --git a/src/learning_gem5/part2/simple_cache.hh b/src/learning_gem5/part2/simple_cache.hh
index 7ec4305..8869985 100644
--- a/src/learning_gem5/part2/simple_cache.hh
+++ b/src/learning_gem5/part2/simple_cache.hh
@@ -36,6 +36,9 @@
#include "params/SimpleCache.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
/**
* A very simple cache object. Has a fully-associative data store with random
* replacement.
@@ -323,5 +326,6 @@
};
+} // namespace gem5
#endif // __LEARNING_GEM5_SIMPLE_CACHE_SIMPLE_CACHE_HH__
diff --git a/src/learning_gem5/part2/simple_memobj.cc b/src/learning_gem5/part2/simple_memobj.cc
index a970789..93e923b 100644
--- a/src/learning_gem5/part2/simple_memobj.cc
+++ b/src/learning_gem5/part2/simple_memobj.cc
@@ -31,6 +31,9 @@
#include "base/trace.hh"
#include "debug/SimpleMemobj.hh"
+namespace gem5
+{
+
SimpleMemobj::SimpleMemobj(const SimpleMemobjParams ¶ms) :
SimObject(params),
instPort(params.name + ".inst_port", this),
@@ -228,3 +231,5 @@
instPort.sendRangeChange();
dataPort.sendRangeChange();
}
+
+} // namespace gem5
diff --git a/src/learning_gem5/part2/simple_memobj.hh b/src/learning_gem5/part2/simple_memobj.hh
index fb5295b..37afeb1 100644
--- a/src/learning_gem5/part2/simple_memobj.hh
+++ b/src/learning_gem5/part2/simple_memobj.hh
@@ -33,6 +33,9 @@
#include "params/SimpleMemobj.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
/**
* A very simple memory object. Current implementation doesn't even cache
* anything it just forwards requests and responses.
@@ -247,5 +250,6 @@
PortID idx=InvalidPortID) override;
};
+} // namespace gem5
#endif // __LEARNING_GEM5_PART2_SIMPLE_MEMOBJ_HH__
diff --git a/src/learning_gem5/part2/simple_object.cc b/src/learning_gem5/part2/simple_object.cc
index 6ae7f46..1ee9045 100644
--- a/src/learning_gem5/part2/simple_object.cc
+++ b/src/learning_gem5/part2/simple_object.cc
@@ -30,8 +30,13 @@
#include <iostream>
+namespace gem5
+{
+
SimpleObject::SimpleObject(const SimpleObjectParams ¶ms) :
SimObject(params)
{
std::cout << "Hello World! From a SimObject!" << std::endl;
}
+
+} // namespace gem5
diff --git a/src/learning_gem5/part2/simple_object.hh b/src/learning_gem5/part2/simple_object.hh
index 7d49fc8..c6ca957 100644
--- a/src/learning_gem5/part2/simple_object.hh
+++ b/src/learning_gem5/part2/simple_object.hh
@@ -32,10 +32,15 @@
#include "params/SimpleObject.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class SimpleObject : public SimObject
{
public:
SimpleObject(const SimpleObjectParams &p);
};
+} // namespace gem5
+
#endif // __LEARNING_GEM5_SIMPLE_OBJECT_HH__
diff --git a/src/mem/AbstractMemory.py b/src/mem/AbstractMemory.py
index e1941c3..3fe94f3 100644
--- a/src/mem/AbstractMemory.py
+++ b/src/mem/AbstractMemory.py
@@ -43,6 +43,7 @@
type = 'AbstractMemory'
abstract = True
cxx_header = "mem/abstract_mem.hh"
+ cxx_class = 'gem5::AbstractMemory'
# A default memory size of 128 MiB (starting at 0) is used to
# simplify the regressions
diff --git a/src/mem/AddrMapper.py b/src/mem/AddrMapper.py
index 60ef3be..bd6b08e 100644
--- a/src/mem/AddrMapper.py
+++ b/src/mem/AddrMapper.py
@@ -45,6 +45,7 @@
class AddrMapper(SimObject):
type = 'AddrMapper'
cxx_header = 'mem/addr_mapper.hh'
+ cxx_class = 'gem5::AddrMapper'
abstract = True
# one port in each direction
@@ -63,6 +64,7 @@
class RangeAddrMapper(AddrMapper):
type = 'RangeAddrMapper'
cxx_header = 'mem/addr_mapper.hh'
+ cxx_class = 'gem5::RangeAddrMapper'
# These two vectors should be the exact same length and each range
# should be the exact same size. Each range in original_ranges is
diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py
index b4eb1d0..691e703 100644
--- a/src/mem/Bridge.py
+++ b/src/mem/Bridge.py
@@ -42,6 +42,7 @@
class Bridge(ClockedObject):
type = 'Bridge'
cxx_header = "mem/bridge.hh"
+ cxx_class = 'gem5::Bridge'
mem_side_port = RequestPort("This port sends requests and "
"receives responses")
diff --git a/src/mem/CfiMemory.py b/src/mem/CfiMemory.py
index e888e6f..6ac539e 100644
--- a/src/mem/CfiMemory.py
+++ b/src/mem/CfiMemory.py
@@ -43,6 +43,7 @@
class CfiMemory(AbstractMemory):
type = 'CfiMemory'
cxx_header = "mem/cfi_mem.hh"
+ cxx_class = 'gem5::CfiMemory'
port = ResponsePort("Response port")
diff --git a/src/mem/CommMonitor.py b/src/mem/CommMonitor.py
index 851e5a3..ff02b61 100644
--- a/src/mem/CommMonitor.py
+++ b/src/mem/CommMonitor.py
@@ -43,6 +43,7 @@
class CommMonitor(SimObject):
type = 'CommMonitor'
cxx_header = "mem/comm_monitor.hh"
+ cxx_class = 'gem5::CommMonitor'
system = Param.System(Parent.any, "System that the monitor belongs to.")
diff --git a/src/mem/DRAMInterface.py b/src/mem/DRAMInterface.py
index ff85043..91e1540 100644
--- a/src/mem/DRAMInterface.py
+++ b/src/mem/DRAMInterface.py
@@ -49,6 +49,7 @@
class DRAMInterface(MemInterface):
type = 'DRAMInterface'
cxx_header = "mem/mem_interface.hh"
+ cxx_class = 'gem5::DRAMInterface'
# scheduler page policy
page_policy = Param.PageManage('open_adaptive', "Page management policy")
diff --git a/src/mem/DRAMSim2.py b/src/mem/DRAMSim2.py
index d5147b1..d6f92ef 100644
--- a/src/mem/DRAMSim2.py
+++ b/src/mem/DRAMSim2.py
@@ -40,6 +40,7 @@
class DRAMSim2(AbstractMemory):
type = 'DRAMSim2'
cxx_header = "mem/dramsim2.hh"
+ cxx_class = 'gem5::DRAMSim2'
# A single port for now
port = ResponsePort("This port sends responses and receives requests")
diff --git a/src/mem/DRAMsim3.py b/src/mem/DRAMsim3.py
index ba92c85..65cd0ba 100644
--- a/src/mem/DRAMsim3.py
+++ b/src/mem/DRAMsim3.py
@@ -40,6 +40,7 @@
class DRAMsim3(AbstractMemory):
type = 'DRAMsim3'
cxx_header = "mem/dramsim3.hh"
+ cxx_class = 'gem5::DRAMsim3'
# A single port for now
port = ResponsePort("port for receiving requests from"
diff --git a/src/mem/ExternalMaster.py b/src/mem/ExternalMaster.py
index 6d8b5df..0377591 100644
--- a/src/mem/ExternalMaster.py
+++ b/src/mem/ExternalMaster.py
@@ -40,6 +40,7 @@
class ExternalMaster(SimObject):
type = 'ExternalMaster'
cxx_header = "mem/external_master.hh"
+ cxx_class = 'gem5::ExternalMaster'
port = RequestPort("Master port")
diff --git a/src/mem/ExternalSlave.py b/src/mem/ExternalSlave.py
index 426a856..fcce505 100644
--- a/src/mem/ExternalSlave.py
+++ b/src/mem/ExternalSlave.py
@@ -39,6 +39,7 @@
class ExternalSlave(SimObject):
type = 'ExternalSlave'
cxx_header = "mem/external_slave.hh"
+ cxx_class = 'gem5::ExternalSlave'
port = SlavePort("Slave port")
diff --git a/src/mem/HMCController.py b/src/mem/HMCController.py
index a6794ee..dee1f57 100644
--- a/src/mem/HMCController.py
+++ b/src/mem/HMCController.py
@@ -67,5 +67,6 @@
# address space.
class HMCController(NoncoherentXBar):
- type = 'HMCController'
- cxx_header = "mem/hmc_controller.hh"
+ type = 'HMCController'
+ cxx_header = "mem/hmc_controller.hh"
+ cxx_class = 'gem5::HMCController'
diff --git a/src/mem/MemChecker.py b/src/mem/MemChecker.py
index 69dae52..42e4bce 100644
--- a/src/mem/MemChecker.py
+++ b/src/mem/MemChecker.py
@@ -40,10 +40,12 @@
class MemChecker(SimObject):
type = 'MemChecker'
cxx_header = "mem/mem_checker.hh"
+ cxx_class = 'gem5::MemChecker'
class MemCheckerMonitor(SimObject):
type = 'MemCheckerMonitor'
cxx_header = "mem/mem_checker_monitor.hh"
+ cxx_class = 'gem5::MemCheckerMonitor'
# one port in each direction
mem_side_port = RequestPort("This port sends requests and receives "
diff --git a/src/mem/MemCtrl.py b/src/mem/MemCtrl.py
index 6736bb0..5e559da 100644
--- a/src/mem/MemCtrl.py
+++ b/src/mem/MemCtrl.py
@@ -53,6 +53,7 @@
class MemCtrl(QoSMemCtrl):
type = 'MemCtrl'
cxx_header = "mem/mem_ctrl.hh"
+ cxx_class = 'gem5::MemCtrl'
# single-ported on the system interface side, instantiate with a
# bus in front of the controller for multiple ports
diff --git a/src/mem/MemDelay.py b/src/mem/MemDelay.py
index 4b322af..9c50ab6 100644
--- a/src/mem/MemDelay.py
+++ b/src/mem/MemDelay.py
@@ -39,6 +39,7 @@
class MemDelay(ClockedObject):
type = 'MemDelay'
cxx_header = 'mem/mem_delay.hh'
+ cxx_class = 'gem5::MemDelay'
abstract = True
mem_side_port = RequestPort("This port sends requests and "
@@ -53,6 +54,7 @@
class SimpleMemDelay(MemDelay):
type = 'SimpleMemDelay'
cxx_header = 'mem/mem_delay.hh'
+ cxx_class = 'gem5::SimpleMemDelay'
read_req = Param.Latency("0t", "Read request delay")
read_resp = Param.Latency("0t", "Read response delay")
diff --git a/src/mem/MemInterface.py b/src/mem/MemInterface.py
index 85fe0a0..720b66b 100644
--- a/src/mem/MemInterface.py
+++ b/src/mem/MemInterface.py
@@ -55,6 +55,7 @@
type = 'MemInterface'
abstract = True
cxx_header = "mem/mem_interface.hh"
+ cxx_class = 'gem5::MemInterface'
# Allow the interface to set required controller buffer sizes
# each entry corresponds to a burst for the specific memory channel
diff --git a/src/mem/NVMInterface.py b/src/mem/NVMInterface.py
index 20f51fc..9c4ec8b 100644
--- a/src/mem/NVMInterface.py
+++ b/src/mem/NVMInterface.py
@@ -44,6 +44,7 @@
class NVMInterface(MemInterface):
type = 'NVMInterface'
cxx_header = "mem/mem_interface.hh"
+ cxx_class = 'gem5::NVMInterface'
# NVM DIMM could have write buffer to offload writes
# define buffer depth, which will limit the number of pending writes
diff --git a/src/mem/SerialLink.py b/src/mem/SerialLink.py
index 7cde69f..cc33daa 100644
--- a/src/mem/SerialLink.py
+++ b/src/mem/SerialLink.py
@@ -46,6 +46,8 @@
class SerialLink(ClockedObject):
type = 'SerialLink'
cxx_header = "mem/serial_link.hh"
+ cxx_class = 'gem5::SerialLink'
+
mem_side_port = RequestPort("This port sends requests and "
"receives responses")
master = DeprecatedParam(mem_side_port,
diff --git a/src/mem/SimpleMemory.py b/src/mem/SimpleMemory.py
index 0e059e8..c1e0c27 100644
--- a/src/mem/SimpleMemory.py
+++ b/src/mem/SimpleMemory.py
@@ -42,6 +42,8 @@
class SimpleMemory(AbstractMemory):
type = 'SimpleMemory'
cxx_header = "mem/simple_mem.hh"
+ cxx_class = 'gem5::SimpleMemory'
+
port = ResponsePort("This port sends responses and receives requests")
latency = Param.Latency('30ns', "Request to response latency")
latency_var = Param.Latency('0ns', "Request to response latency variance")
diff --git a/src/mem/XBar.py b/src/mem/XBar.py
index 2dfe7c1..a424c6f 100644
--- a/src/mem/XBar.py
+++ b/src/mem/XBar.py
@@ -47,6 +47,7 @@
type = 'BaseXBar'
abstract = True
cxx_header = "mem/xbar.hh"
+ cxx_class = 'gem5::BaseXBar'
cpu_side_ports = VectorResponsePort("Vector port for connecting "
"mem side ports")
@@ -97,10 +98,12 @@
class NoncoherentXBar(BaseXBar):
type = 'NoncoherentXBar'
cxx_header = "mem/noncoherent_xbar.hh"
+ cxx_class = 'gem5::NoncoherentXBar'
class CoherentXBar(BaseXBar):
type = 'CoherentXBar'
cxx_header = "mem/coherent_xbar.hh"
+ cxx_class = 'gem5::CoherentXBar'
# The coherent crossbar additionally has snoop responses that are
# forwarded after a specific latency.
@@ -130,6 +133,7 @@
class SnoopFilter(SimObject):
type = 'SnoopFilter'
cxx_header = "mem/snoop_filter.hh"
+ cxx_class = 'gem5::SnoopFilter'
# Lookup latency of the snoop filter, added to requests that pass
# through a coherent crossbar.
diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index 720ebfe..902af59 100644
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -51,6 +51,9 @@
#include "mem/packet_access.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
AbstractMemory::AbstractMemory(const Params &p) :
ClockedObject(p), range(p.range), pmemAddr(NULL),
backdoor(params().range, nullptr,
@@ -505,3 +508,5 @@
pkt->cmdString());
}
}
+
+} // namespace gem5
diff --git a/src/mem/abstract_mem.hh b/src/mem/abstract_mem.hh
index 4ec91ad..2f3a980 100644
--- a/src/mem/abstract_mem.hh
+++ b/src/mem/abstract_mem.hh
@@ -52,6 +52,8 @@
#include "sim/clocked_object.hh"
#include "sim/stats.hh"
+namespace gem5
+{
class System;
@@ -346,4 +348,6 @@
void functionalAccess(PacketPtr pkt);
};
+} // namespace gem5
+
#endif //__MEM_ABSTRACT_MEMORY_HH__
diff --git a/src/mem/addr_mapper.cc b/src/mem/addr_mapper.cc
index 8fdefdc..091b9d5 100644
--- a/src/mem/addr_mapper.cc
+++ b/src/mem/addr_mapper.cc
@@ -37,6 +37,9 @@
#include "mem/addr_mapper.hh"
+namespace gem5
+{
+
AddrMapper::AddrMapper(const AddrMapperParams &p)
: SimObject(p),
memSidePort(name() + "-mem_side_port", *this),
@@ -237,4 +240,4 @@
return ranges;
}
-
+} // namespace gem5
diff --git a/src/mem/addr_mapper.hh b/src/mem/addr_mapper.hh
index de601a1..2f37bba 100644
--- a/src/mem/addr_mapper.hh
+++ b/src/mem/addr_mapper.hh
@@ -43,6 +43,9 @@
#include "params/RangeAddrMapper.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
/**
* An address mapper changes the packet addresses in going from the
* response port side of the mapper to the request port side. When the
@@ -274,4 +277,6 @@
}
};
+} // namespace gem5
+
#endif //__MEM_ADDR_MAPPER_HH__
diff --git a/src/mem/backdoor.hh b/src/mem/backdoor.hh
index 43f9b39..73e6670 100644
--- a/src/mem/backdoor.hh
+++ b/src/mem/backdoor.hh
@@ -35,6 +35,9 @@
#include "base/addr_range.hh"
#include "base/callback.hh"
+namespace gem5
+{
+
class MemBackdoor
{
public:
@@ -123,4 +126,6 @@
typedef MemBackdoor *MemBackdoorPtr;
+} // namespace gem5
+
#endif //__MEM_BACKDOOR_HH__
diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index d43190a..0f744f7 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -50,6 +50,9 @@
#include "debug/Bridge.hh"
#include "params/Bridge.hh"
+namespace gem5
+{
+
Bridge::BridgeResponsePort::BridgeResponsePort(const std::string& _name,
Bridge& _bridge,
BridgeRequestPort& _memSidePort,
@@ -390,3 +393,5 @@
{
return ranges;
}
+
+} // namespace gem5
diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh
index 8f74478..f56cef1 100644
--- a/src/mem/bridge.hh
+++ b/src/mem/bridge.hh
@@ -54,6 +54,9 @@
#include "params/Bridge.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
/**
* A bridge is used to interface two different crossbars (or in general a
* memory-mapped requestor and responder), with buffering for requests and
@@ -325,4 +328,6 @@
Bridge(const Params &p);
};
+} // namespace gem5
+
#endif //__MEM_BRIDGE_HH__
diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py
index a99d549..b4df2a0 100644
--- a/src/mem/cache/Cache.py
+++ b/src/mem/cache/Cache.py
@@ -53,6 +53,7 @@
class WriteAllocator(SimObject):
type = 'WriteAllocator'
cxx_header = "mem/cache/cache.hh"
+ cxx_class = 'gem5::WriteAllocator'
# Control the limits for when the cache introduces extra delays to
# allow whole-line write coalescing, and eventually switches to a
@@ -73,6 +74,7 @@
type = 'BaseCache'
abstract = True
cxx_header = "mem/cache/base.hh"
+ cxx_class = 'gem5::BaseCache'
size = Param.MemorySize("Capacity")
assoc = Param.Unsigned("Associativity")
@@ -151,11 +153,12 @@
class Cache(BaseCache):
type = 'Cache'
cxx_header = 'mem/cache/cache.hh'
-
+ cxx_class = 'gem5::Cache'
class NoncoherentCache(BaseCache):
type = 'NoncoherentCache'
cxx_header = 'mem/cache/noncoherent_cache.hh'
+ cxx_class = 'gem5::NoncoherentCache'
# This is typically a last level cache and any clean
# writebacks would be unnecessary traffic to the main memory.
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 04e127d..61396f0 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -62,6 +62,9 @@
#include "params/WriteAllocator.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
BaseCache::CacheResponsePort::CacheResponsePort(const std::string &_name,
BaseCache *_cache,
const std::string &_label)
@@ -2606,3 +2609,5 @@
}
nextAddr = write_addr + write_size;
}
+
+} // namespace gem5
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index b18284e..581edf9 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -76,6 +76,9 @@
#include "sim/sim_exit.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
namespace prefetch
{
@@ -1486,4 +1489,6 @@
std::unordered_map<Addr, Counter> delayCtr;
};
+} // namespace gem5
+
#endif //__MEM_CACHE_BASE_HH__
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index dbebc55..7ea8a8c 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -63,6 +63,9 @@
#include "mem/request.hh"
#include "params/Cache.hh"
+namespace gem5
+{
+
Cache::Cache(const CacheParams &p)
: BaseCache(p, p.system->cacheLineSize()),
doFastWrites(true)
@@ -1429,3 +1432,5 @@
return BaseCache::sendMSHRQueuePacket(mshr);
}
+
+} // namespace gem5
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 1c6e1c2..b820062 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -54,6 +54,9 @@
#include "mem/cache/base.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
class CacheBlk;
struct CacheParams;
class MSHR;
@@ -169,4 +172,6 @@
bool sendMSHRQueuePacket(MSHR* mshr) override;
};
+} // namespace gem5
+
#endif // __MEM_CACHE_CACHE_HH__
diff --git a/src/mem/cache/cache_blk.cc b/src/mem/cache/cache_blk.cc
index e4bcc63..3ae37c1 100644
--- a/src/mem/cache/cache_blk.cc
+++ b/src/mem/cache/cache_blk.cc
@@ -43,6 +43,9 @@
#include "base/cprintf.hh"
+namespace gem5
+{
+
void
CacheBlk::insert(const Addr tag, const bool is_secure,
const int src_requestor_ID, const uint32_t task_ID)
@@ -76,3 +79,4 @@
blk->isSecure() ? 'S' : '-');
}
+} // namespace gem5
diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/cache_blk.hh
index ad1c052..d28d7e3 100644
--- a/src/mem/cache/cache_blk.hh
+++ b/src/mem/cache/cache_blk.hh
@@ -59,6 +59,9 @@
#include "mem/request.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
/**
* A Basic Cache block.
* Contains information regarding its coherence, prefetching status, as
@@ -557,4 +560,6 @@
const std::string &prefix = "") const;
};
+} // namespace gem5
+
#endif //__MEM_CACHE_CACHE_BLK_HH__
diff --git a/src/mem/cache/compressors/Compressors.py b/src/mem/cache/compressors/Compressors.py
index eb5b406..ec93900 100644
--- a/src/mem/cache/compressors/Compressors.py
+++ b/src/mem/cache/compressors/Compressors.py
@@ -34,7 +34,7 @@
class BaseCacheCompressor(SimObject):
type = 'BaseCacheCompressor'
abstract = True
- cxx_class = 'compression::Base'
+ cxx_class = 'gem5::compression::Base'
cxx_header = "mem/cache/compressors/base.hh"
block_size = Param.Int(Parent.cache_line_size, "Block size in bytes")
@@ -56,7 +56,7 @@
class BaseDictionaryCompressor(BaseCacheCompressor):
type = 'BaseDictionaryCompressor'
abstract = True
- cxx_class = 'compression::BaseDictionaryCompressor'
+ cxx_class = 'gem5::compression::BaseDictionaryCompressor'
cxx_header = "mem/cache/compressors/dictionary_compressor.hh"
dictionary_size = Param.Int(Parent.cache_line_size,
@@ -64,7 +64,7 @@
class Base64Delta8(BaseDictionaryCompressor):
type = 'Base64Delta8'
- cxx_class = 'compression::Base64Delta8'
+ cxx_class = 'gem5::compression::Base64Delta8'
cxx_header = "mem/cache/compressors/base_delta.hh"
chunk_size_bits = 64
@@ -77,7 +77,7 @@
class Base64Delta16(BaseDictionaryCompressor):
type = 'Base64Delta16'
- cxx_class = 'compression::Base64Delta16'
+ cxx_class = 'gem5::compression::Base64Delta16'
cxx_header = "mem/cache/compressors/base_delta.hh"
chunk_size_bits = 64
@@ -90,7 +90,7 @@
class Base64Delta32(BaseDictionaryCompressor):
type = 'Base64Delta32'
- cxx_class = 'compression::Base64Delta32'
+ cxx_class = 'gem5::compression::Base64Delta32'
cxx_header = "mem/cache/compressors/base_delta.hh"
chunk_size_bits = 64
@@ -103,7 +103,7 @@
class Base32Delta8(BaseDictionaryCompressor):
type = 'Base32Delta8'
- cxx_class = 'compression::Base32Delta8'
+ cxx_class = 'gem5::compression::Base32Delta8'
cxx_header = "mem/cache/compressors/base_delta.hh"
chunk_size_bits = 32
@@ -116,7 +116,7 @@
class Base32Delta16(BaseDictionaryCompressor):
type = 'Base32Delta16'
- cxx_class = 'compression::Base32Delta16'
+ cxx_class = 'gem5::compression::Base32Delta16'
cxx_header = "mem/cache/compressors/base_delta.hh"
chunk_size_bits = 32
@@ -129,7 +129,7 @@
class Base16Delta8(BaseDictionaryCompressor):
type = 'Base16Delta8'
- cxx_class = 'compression::Base16Delta8'
+ cxx_class = 'gem5::compression::Base16Delta8'
cxx_header = "mem/cache/compressors/base_delta.hh"
chunk_size_bits = 16
@@ -142,7 +142,7 @@
class CPack(BaseDictionaryCompressor):
type = 'CPack'
- cxx_class = 'compression::CPack'
+ cxx_class = 'gem5::compression::CPack'
cxx_header = "mem/cache/compressors/cpack.hh"
comp_chunks_per_cycle = 2
@@ -153,7 +153,7 @@
class FPC(BaseDictionaryCompressor):
type = 'FPC'
- cxx_class = 'compression::FPC'
+ cxx_class = 'gem5::compression::FPC'
cxx_header = "mem/cache/compressors/fpc.hh"
comp_chunks_per_cycle = 8
@@ -168,7 +168,7 @@
class FPCD(BaseDictionaryCompressor):
type = 'FPCD'
- cxx_class = 'compression::FPCD'
+ cxx_class = 'gem5::compression::FPCD'
cxx_header = "mem/cache/compressors/fpcd.hh"
# Accounts for checking all patterns, selecting patterns, and shifting
@@ -183,7 +183,7 @@
class FrequentValuesCompressor(BaseCacheCompressor):
type = 'FrequentValuesCompressor'
- cxx_class = 'compression::FrequentValues'
+ cxx_class = 'gem5::compression::FrequentValues'
cxx_header = "mem/cache/compressors/frequent_values.hh"
chunk_size_bits = 32
@@ -215,7 +215,7 @@
class MultiCompressor(BaseCacheCompressor):
type = 'MultiCompressor'
- cxx_class = 'compression::Multi'
+ cxx_class = 'gem5::compression::Multi'
cxx_header = "mem/cache/compressors/multi.hh"
# Dummy default compressor list. This might not be an optimal choice,
@@ -239,7 +239,7 @@
class PerfectCompressor(BaseCacheCompressor):
type = 'PerfectCompressor'
- cxx_class = 'compression::Perfect'
+ cxx_class = 'gem5::compression::Perfect'
cxx_header = "mem/cache/compressors/perfect.hh"
chunk_size_bits = 64
@@ -254,7 +254,7 @@
class RepeatedQwordsCompressor(BaseDictionaryCompressor):
type = 'RepeatedQwordsCompressor'
- cxx_class = 'compression::RepeatedQwords'
+ cxx_class = 'gem5::compression::RepeatedQwords'
cxx_header = "mem/cache/compressors/repeated_qwords.hh"
chunk_size_bits = 64
@@ -267,7 +267,7 @@
class ZeroCompressor(BaseDictionaryCompressor):
type = 'ZeroCompressor'
- cxx_class = 'compression::Zero'
+ cxx_class = 'gem5::compression::Zero'
cxx_header = "mem/cache/compressors/zero.hh"
chunk_size_bits = 64
diff --git a/src/mem/cache/compressors/base.cc b/src/mem/cache/compressors/base.cc
index c17fc7d..cafd691 100644
--- a/src/mem/cache/compressors/base.cc
+++ b/src/mem/cache/compressors/base.cc
@@ -45,6 +45,9 @@
#include "mem/cache/tags/super_blk.hh"
#include "params/BaseCacheCompressor.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
namespace compression
{
@@ -270,3 +273,4 @@
}
} // namespace compression
+} // namespace gem5
diff --git a/src/mem/cache/compressors/base.hh b/src/mem/cache/compressors/base.hh
index c6b116b..4945176 100644
--- a/src/mem/cache/compressors/base.hh
+++ b/src/mem/cache/compressors/base.hh
@@ -43,6 +43,9 @@
#include "base/types.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class BaseCache;
class CacheBlk;
struct BaseCacheCompressorParams;
@@ -282,5 +285,6 @@
};
} // namespace compression
+} // namespace gem5
#endif //__MEM_CACHE_COMPRESSORS_BASE_HH__
diff --git a/src/mem/cache/compressors/base_delta.cc b/src/mem/cache/compressors/base_delta.cc
index 98c9536..9b2e67c 100644
--- a/src/mem/cache/compressors/base_delta.cc
+++ b/src/mem/cache/compressors/base_delta.cc
@@ -39,6 +39,9 @@
#include "params/Base64Delta32.hh"
#include "params/Base64Delta8.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
namespace compression
{
@@ -74,3 +77,4 @@
}
} // namespace compression
+} // namespace gem5
diff --git a/src/mem/cache/compressors/base_delta.hh b/src/mem/cache/compressors/base_delta.hh
index e323c55..93539da 100644
--- a/src/mem/cache/compressors/base_delta.hh
+++ b/src/mem/cache/compressors/base_delta.hh
@@ -41,6 +41,9 @@
#include "base/bitfield.hh"
#include "mem/cache/compressors/dictionary_compressor.hh"
+namespace gem5
+{
+
struct BaseDictionaryCompressorParams;
struct Base64Delta8Params;
struct Base64Delta16Params;
@@ -207,5 +210,6 @@
};
} // namespace compression
+} // namespace gem5
#endif //__MEM_CACHE_COMPRESSORS_BASE_DELTA_HH__
diff --git a/src/mem/cache/compressors/base_delta_impl.hh b/src/mem/cache/compressors/base_delta_impl.hh
index 5107aef..c4a841d 100644
--- a/src/mem/cache/compressors/base_delta_impl.hh
+++ b/src/mem/cache/compressors/base_delta_impl.hh
@@ -37,6 +37,9 @@
#include "mem/cache/compressors/base_delta.hh"
#include "mem/cache/compressors/dictionary_compressor_impl.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
namespace compression
{
@@ -96,5 +99,6 @@
}
} // namespace compression
+} // namespace gem5
#endif //__MEM_CACHE_COMPRESSORS_BASE_DELTA_IMPL_HH__
diff --git a/src/mem/cache/compressors/base_dictionary_compressor.cc b/src/mem/cache/compressors/base_dictionary_compressor.cc
index dc4461e..6a1ed92 100644
--- a/src/mem/cache/compressors/base_dictionary_compressor.cc
+++ b/src/mem/cache/compressors/base_dictionary_compressor.cc
@@ -34,6 +34,9 @@
#include "mem/cache/compressors/dictionary_compressor.hh"
#include "params/BaseDictionaryCompressor.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
namespace compression
{
@@ -68,3 +71,4 @@
}
} // namespace compression
+} // namespace gem5
diff --git a/src/mem/cache/compressors/cpack.cc b/src/mem/cache/compressors/cpack.cc
index 456647b..64376b9 100644
--- a/src/mem/cache/compressors/cpack.cc
+++ b/src/mem/cache/compressors/cpack.cc
@@ -35,6 +35,9 @@
#include "mem/cache/compressors/dictionary_compressor_impl.hh"
#include "params/CPack.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
namespace compression
{
@@ -52,3 +55,4 @@
}
} // namespace compression
+} // namespace gem5
diff --git a/src/mem/cache/compressors/cpack.hh b/src/mem/cache/compressors/cpack.hh
index 6382d4d..ecfcb25 100644
--- a/src/mem/cache/compressors/cpack.hh
+++ b/src/mem/cache/compressors/cpack.hh
@@ -41,6 +41,9 @@
#include "base/types.hh"
#include "mem/cache/compressors/dictionary_compressor.hh"
+namespace gem5
+{
+
struct CPackParams;
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
@@ -173,5 +176,6 @@
};
} // namespace compression
+} // namespace gem5
#endif //__MEM_CACHE_COMPRESSORS_CPACK_HH__
diff --git a/src/mem/cache/compressors/dictionary_compressor.hh b/src/mem/cache/compressors/dictionary_compressor.hh
index 0f1c388..b743aa0 100644
--- a/src/mem/cache/compressors/dictionary_compressor.hh
+++ b/src/mem/cache/compressors/dictionary_compressor.hh
@@ -56,6 +56,9 @@
#include "base/types.hh"
#include "mem/cache/compressors/base.hh"
+namespace gem5
+{
+
struct BaseDictionaryCompressorParams;
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
@@ -789,5 +792,6 @@
};
} // namespace compression
+} // namespace gem5
#endif //__MEM_CACHE_COMPRESSORS_DICTIONARY_COMPRESSOR_HH__
diff --git a/src/mem/cache/compressors/dictionary_compressor_impl.hh b/src/mem/cache/compressors/dictionary_compressor_impl.hh
index e763389..9eb265b 100644
--- a/src/mem/cache/compressors/dictionary_compressor_impl.hh
+++ b/src/mem/cache/compressors/dictionary_compressor_impl.hh
@@ -40,6 +40,9 @@
#include "mem/cache/compressors/dictionary_compressor.hh"
#include "params/BaseDictionaryCompressor.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
namespace compression
{
@@ -235,5 +238,6 @@
}
} // namespace compression
+} // namespace gem5
#endif //__MEM_CACHE_COMPRESSORS_DICTIONARY_COMPRESSOR_IMPL_HH__
diff --git a/src/mem/cache/compressors/encoders/base.hh b/src/mem/cache/compressors/encoders/base.hh
index b7ab2b9..92971af 100644
--- a/src/mem/cache/compressors/encoders/base.hh
+++ b/src/mem/cache/compressors/encoders/base.hh
@@ -33,6 +33,9 @@
#include "base/compiler.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
namespace compression
{
@@ -81,5 +84,6 @@
} // namespace encoder
} // namespace compression
+} // namespace gem5
#endif //__MEM_CACHE_COMPRESSORS_ENCODERS_BASE_HH__
diff --git a/src/mem/cache/compressors/encoders/huffman.cc b/src/mem/cache/compressors/encoders/huffman.cc
index b2f8ce2..7a47aa9 100644
--- a/src/mem/cache/compressors/encoders/huffman.cc
+++ b/src/mem/cache/compressors/encoders/huffman.cc
@@ -32,6 +32,9 @@
#include "base/logging.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
namespace compression
{
@@ -136,3 +139,4 @@
} // namespace encoder
} // namespace compression
+} // namespace gem5
diff --git a/src/mem/cache/compressors/encoders/huffman.hh b/src/mem/cache/compressors/encoders/huffman.hh
index a34c408..3f29f2c 100644
--- a/src/mem/cache/compressors/encoders/huffman.hh
+++ b/src/mem/cache/compressors/encoders/huffman.hh
@@ -39,6 +39,9 @@
#include "base/compiler.hh"
#include "mem/cache/compressors/encoders/base.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
namespace compression
{
@@ -181,5 +184,6 @@
} // namespace encoder
} // namespace compression
+} // namespace gem5
#endif //__MEM_CACHE_COMPRESSORS_ENCODERS_HUFFMAN_HH__
diff --git a/src/mem/cache/compressors/fpc.cc b/src/mem/cache/compressors/fpc.cc
index 3fb1b36..8071355 100644
--- a/src/mem/cache/compressors/fpc.cc
+++ b/src/mem/cache/compressors/fpc.cc
@@ -31,6 +31,9 @@
#include "mem/cache/compressors/dictionary_compressor_impl.hh"
#include "params/FPC.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
namespace compression
{
@@ -97,3 +100,4 @@
}
} // namespace compression
+} // namespace gem5
diff --git a/src/mem/cache/compressors/fpc.hh b/src/mem/cache/compressors/fpc.hh
index 6f26f29..bfe5089 100644
--- a/src/mem/cache/compressors/fpc.hh
+++ b/src/mem/cache/compressors/fpc.hh
@@ -46,6 +46,9 @@
#include "base/types.hh"
#include "mem/cache/compressors/dictionary_compressor.hh"
+namespace gem5
+{
+
struct FPCParams;
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
@@ -303,5 +306,6 @@
};
} // namespace compression
+} // namespace gem5
#endif //__MEM_CACHE_COMPRESSORS_FPC_HH__
diff --git a/src/mem/cache/compressors/fpcd.cc b/src/mem/cache/compressors/fpcd.cc
index 0cd1a1f..480d34f 100644
--- a/src/mem/cache/compressors/fpcd.cc
+++ b/src/mem/cache/compressors/fpcd.cc
@@ -35,6 +35,9 @@
#include "mem/cache/compressors/dictionary_compressor_impl.hh"
#include "params/FPCD.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
namespace compression
{
@@ -57,3 +60,4 @@
}
} // namespace compression
+} // namespace gem5
diff --git a/src/mem/cache/compressors/fpcd.hh b/src/mem/cache/compressors/fpcd.hh
index a21619d..b424bef 100644
--- a/src/mem/cache/compressors/fpcd.hh
+++ b/src/mem/cache/compressors/fpcd.hh
@@ -47,6 +47,9 @@
#include "base/types.hh"
#include "mem/cache/compressors/dictionary_compressor.hh"
+namespace gem5
+{
+
struct FPCDParams;
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
@@ -321,5 +324,6 @@
};
} // namespace compression
+} // namespace gem5
#endif //__MEM_CACHE_COMPRESSORS_FPCD_HH__
diff --git a/src/mem/cache/compressors/frequent_values.cc b/src/mem/cache/compressors/frequent_values.cc
index 2a21124..252b685 100644
--- a/src/mem/cache/compressors/frequent_values.cc
+++ b/src/mem/cache/compressors/frequent_values.cc
@@ -39,6 +39,9 @@
#include "mem/cache/prefetch/associative_set_impl.hh"
#include "params/FrequentValuesCompressor.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
namespace compression
{
@@ -298,3 +301,4 @@
}
} // namespace compression
+} // namespace gem5
diff --git a/src/mem/cache/compressors/frequent_values.hh b/src/mem/cache/compressors/frequent_values.hh
index d005c4e..c2874e9 100644
--- a/src/mem/cache/compressors/frequent_values.hh
+++ b/src/mem/cache/compressors/frequent_values.hh
@@ -43,6 +43,9 @@
#include "sim/eventq.hh"
#include "sim/probe/probe.hh"
+namespace gem5
+{
+
struct FrequentValuesCompressorParams;
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
@@ -221,5 +224,6 @@
};
} // namespace compression
+} // namespace gem5
#endif //__MEM_CACHE_COMPRESSORS_FREQUENT_VALUES_HH__
diff --git a/src/mem/cache/compressors/multi.cc b/src/mem/cache/compressors/multi.cc
index c016142..cbc307a 100644
--- a/src/mem/cache/compressors/multi.cc
+++ b/src/mem/cache/compressors/multi.cc
@@ -42,6 +42,9 @@
#include "debug/CacheComp.hh"
#include "params/MultiCompressor.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
namespace compression
{
@@ -213,3 +216,4 @@
}
} // namespace compression
+} // namespace gem5
diff --git a/src/mem/cache/compressors/multi.hh b/src/mem/cache/compressors/multi.hh
index c73661a..2cdf78f 100644
--- a/src/mem/cache/compressors/multi.hh
+++ b/src/mem/cache/compressors/multi.hh
@@ -41,6 +41,9 @@
#include "base/types.hh"
#include "mem/cache/compressors/base.hh"
+namespace gem5
+{
+
struct MultiCompressorParams;
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
@@ -139,5 +142,6 @@
};
} // namespace compression
+} // namespace gem5
#endif //__MEM_CACHE_COMPRESSORS_MULTI_HH__
diff --git a/src/mem/cache/compressors/perfect.cc b/src/mem/cache/compressors/perfect.cc
index 03f070b..e271fa0 100644
--- a/src/mem/cache/compressors/perfect.cc
+++ b/src/mem/cache/compressors/perfect.cc
@@ -38,6 +38,9 @@
#include "debug/CacheComp.hh"
#include "params/PerfectCompressor.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
namespace compression
{
@@ -75,3 +78,4 @@
}
} // namespace compression
+} // namespace gem5
diff --git a/src/mem/cache/compressors/perfect.hh b/src/mem/cache/compressors/perfect.hh
index 743d653..0d91c50 100644
--- a/src/mem/cache/compressors/perfect.hh
+++ b/src/mem/cache/compressors/perfect.hh
@@ -41,6 +41,9 @@
#include "base/types.hh"
#include "mem/cache/compressors/base.hh"
+namespace gem5
+{
+
struct PerfectCompressorParams;
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
@@ -92,5 +95,6 @@
};
} // namespace compression
+} // namespace gem5
#endif //__MEM_CACHE_COMPRESSORS_PERFECT_COMPRESSOR_HH__
diff --git a/src/mem/cache/compressors/repeated_qwords.cc b/src/mem/cache/compressors/repeated_qwords.cc
index 84a7407..8d5c32d 100644
--- a/src/mem/cache/compressors/repeated_qwords.cc
+++ b/src/mem/cache/compressors/repeated_qwords.cc
@@ -38,6 +38,9 @@
#include "mem/cache/compressors/dictionary_compressor_impl.hh"
#include "params/RepeatedQwordsCompressor.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
namespace compression
{
@@ -80,3 +83,4 @@
}
} // namespace compression
+} // namespace gem5
diff --git a/src/mem/cache/compressors/repeated_qwords.hh b/src/mem/cache/compressors/repeated_qwords.hh
index b0f33ad..5f2ec30 100644
--- a/src/mem/cache/compressors/repeated_qwords.hh
+++ b/src/mem/cache/compressors/repeated_qwords.hh
@@ -41,6 +41,9 @@
#include "mem/cache/compressors/dictionary_compressor.hh"
+namespace gem5
+{
+
struct RepeatedQwordsCompressorParams;
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
@@ -126,5 +129,6 @@
};
} // namespace compression
+} // namespace gem5
#endif //__MEM_CACHE_COMPRESSORS_REPEATED_QWORDS_HH__
diff --git a/src/mem/cache/compressors/zero.cc b/src/mem/cache/compressors/zero.cc
index 8347a90..42a3c7c 100644
--- a/src/mem/cache/compressors/zero.cc
+++ b/src/mem/cache/compressors/zero.cc
@@ -38,6 +38,9 @@
#include "mem/cache/compressors/dictionary_compressor_impl.hh"
#include "params/ZeroCompressor.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
namespace compression
{
@@ -78,3 +81,4 @@
}
} // namespace compression
+} // namespace gem5
diff --git a/src/mem/cache/compressors/zero.hh b/src/mem/cache/compressors/zero.hh
index 255518c..d6996ea 100644
--- a/src/mem/cache/compressors/zero.hh
+++ b/src/mem/cache/compressors/zero.hh
@@ -41,6 +41,9 @@
#include "mem/cache/compressors/dictionary_compressor.hh"
+namespace gem5
+{
+
struct ZeroCompressorParams;
GEM5_DEPRECATED_NAMESPACE(Compressor, compression);
@@ -127,5 +130,6 @@
};
} // namespace compression
+} // namespace gem5
#endif //__MEM_CACHE_COMPRESSORS_ZERO_HH__
diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index 71bf6ae..44b98c2 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -57,6 +57,9 @@
#include "mem/request.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
MSHR::MSHR(const std::string &name)
: QueueEntry(name),
downstreamPending(false),
@@ -760,3 +763,5 @@
assert(hasTargets());
return entry->matchBlockAddr(blkAddr, isSecure);
}
+
+} // namespace gem5
diff --git a/src/mem/cache/mshr.hh b/src/mem/cache/mshr.hh
index c8fc5da..0b7c5a6 100644
--- a/src/mem/cache/mshr.hh
+++ b/src/mem/cache/mshr.hh
@@ -61,6 +61,9 @@
#include "mem/request.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
class BaseCache;
/**
@@ -519,4 +522,6 @@
bool conflictAddr(const QueueEntry* entry) const override;
};
+} // namespace gem5
+
#endif // __MEM_CACHE_MSHR_HH__
diff --git a/src/mem/cache/mshr_queue.cc b/src/mem/cache/mshr_queue.cc
index 4a32d90..5f02b6f 100644
--- a/src/mem/cache/mshr_queue.cc
+++ b/src/mem/cache/mshr_queue.cc
@@ -49,6 +49,9 @@
#include "debug/MSHR.hh"
#include "mem/cache/mshr.hh"
+namespace gem5
+{
+
MSHRQueue::MSHRQueue(const std::string &_label,
int num_entries, int reserve,
int demand_reserve, std::string cache_name = "")
@@ -144,3 +147,5 @@
// Notify if MSHR queue no longer full
return was_full && !isFull();
}
+
+} // namespace gem5
diff --git a/src/mem/cache/mshr_queue.hh b/src/mem/cache/mshr_queue.hh
index 253ffd0..74aaa0d 100644
--- a/src/mem/cache/mshr_queue.hh
+++ b/src/mem/cache/mshr_queue.hh
@@ -52,6 +52,9 @@
#include "mem/cache/queue.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
/**
* A Class for maintaining a list of pending and allocated memory requests.
*/
@@ -160,4 +163,6 @@
}
};
+} // namespace gem5
+
#endif //__MEM_CACHE_MSHR_QUEUE_HH__
diff --git a/src/mem/cache/noncoherent_cache.cc b/src/mem/cache/noncoherent_cache.cc
index 0810369..314025f 100644
--- a/src/mem/cache/noncoherent_cache.cc
+++ b/src/mem/cache/noncoherent_cache.cc
@@ -56,6 +56,9 @@
#include "mem/cache/mshr.hh"
#include "params/NoncoherentCache.hh"
+namespace gem5
+{
+
NoncoherentCache::NoncoherentCache(const NoncoherentCacheParams &p)
: BaseCache(p, p.system->cacheLineSize())
{
@@ -349,3 +352,5 @@
return pkt;
}
+
+} // namespace gem5
diff --git a/src/mem/cache/noncoherent_cache.hh b/src/mem/cache/noncoherent_cache.hh
index 1cd9e9a..2d3d61f 100644
--- a/src/mem/cache/noncoherent_cache.hh
+++ b/src/mem/cache/noncoherent_cache.hh
@@ -55,6 +55,9 @@
#include "mem/cache/base.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
class CacheBlk;
class MSHR;
struct NoncoherentCacheParams;
@@ -123,4 +126,6 @@
NoncoherentCache(const NoncoherentCacheParams &p);
};
+} // namespace gem5
+
#endif // __MEM_CACHE_NONCOHERENTCACHE_HH__
diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py
index 0098763..fbae086 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -59,7 +59,7 @@
class BasePrefetcher(ClockedObject):
type = 'BasePrefetcher'
abstract = True
- cxx_class = 'prefetch::Base'
+ cxx_class = 'gem5::prefetch::Base'
cxx_header = "mem/cache/prefetch/base.hh"
cxx_exports = [
PyBindMethod("addEventProbe"),
@@ -111,7 +111,7 @@
class MultiPrefetcher(BasePrefetcher):
type = 'MultiPrefetcher'
- cxx_class = 'prefetch::Multi'
+ cxx_class = 'gem5::prefetch::Multi'
cxx_header = 'mem/cache/prefetch/multi.hh'
prefetchers = VectorParam.BasePrefetcher([], "Array of prefetchers")
@@ -119,7 +119,7 @@
class QueuedPrefetcher(BasePrefetcher):
type = "QueuedPrefetcher"
abstract = True
- cxx_class = "prefetch::Queued"
+ cxx_class = 'gem5::prefetch::Queued'
cxx_header = "mem/cache/prefetch/queued.hh"
latency = Param.Int(1, "Latency for generated prefetches")
queue_size = Param.Int(32, "Maximum number of queued prefetches")
@@ -145,12 +145,12 @@
class StridePrefetcherHashedSetAssociative(SetAssociative):
type = 'StridePrefetcherHashedSetAssociative'
- cxx_class = 'prefetch::StridePrefetcherHashedSetAssociative'
+ cxx_class = 'gem5::prefetch::StridePrefetcherHashedSetAssociative'
cxx_header = "mem/cache/prefetch/stride.hh"
class StridePrefetcher(QueuedPrefetcher):
type = 'StridePrefetcher'
- cxx_class = 'prefetch::Stride'
+ cxx_class = 'gem5::prefetch::Stride'
cxx_header = "mem/cache/prefetch/stride.hh"
# Do not consult stride prefetcher on instruction accesses
@@ -178,14 +178,14 @@
class TaggedPrefetcher(QueuedPrefetcher):
type = 'TaggedPrefetcher'
- cxx_class = 'prefetch::Tagged'
+ cxx_class = 'gem5::prefetch::Tagged'
cxx_header = "mem/cache/prefetch/tagged.hh"
degree = Param.Int(2, "Number of prefetches to generate")
class IndirectMemoryPrefetcher(QueuedPrefetcher):
type = 'IndirectMemoryPrefetcher'
- cxx_class = 'prefetch::IndirectMemory'
+ cxx_class = 'gem5::prefetch::IndirectMemory'
cxx_header = "mem/cache/prefetch/indirect_memory.hh"
pt_table_entries = Param.MemorySize("16",
"Number of entries of the Prefetch Table")
@@ -220,7 +220,7 @@
class SignaturePathPrefetcher(QueuedPrefetcher):
type = 'SignaturePathPrefetcher'
- cxx_class = 'prefetch::SignaturePath'
+ cxx_class = 'gem5::prefetch::SignaturePath'
cxx_header = "mem/cache/prefetch/signature_path.hh"
signature_shift = Param.UInt8(3,
@@ -260,7 +260,7 @@
class SignaturePathPrefetcherV2(SignaturePathPrefetcher):
type = 'SignaturePathPrefetcherV2'
- cxx_class = 'prefetch::SignaturePathV2'
+ cxx_class = 'gem5::prefetch::SignaturePathV2'
cxx_header = "mem/cache/prefetch/signature_path_v2.hh"
signature_table_entries = "256"
@@ -283,7 +283,7 @@
class AccessMapPatternMatching(ClockedObject):
type = 'AccessMapPatternMatching'
- cxx_class = 'prefetch::AccessMapPatternMatching'
+ cxx_class = 'gem5::prefetch::AccessMapPatternMatching'
cxx_header = "mem/cache/prefetch/access_map_pattern_matching.hh"
block_size = Param.Unsigned(Parent.block_size,
@@ -322,14 +322,14 @@
class AMPMPrefetcher(QueuedPrefetcher):
type = 'AMPMPrefetcher'
- cxx_class = 'prefetch::AMPM'
+ cxx_class = 'gem5::prefetch::AMPM'
cxx_header = "mem/cache/prefetch/access_map_pattern_matching.hh"
ampm = Param.AccessMapPatternMatching( AccessMapPatternMatching(),
"Access Map Pattern Matching object")
class DeltaCorrelatingPredictionTables(SimObject):
type = 'DeltaCorrelatingPredictionTables'
- cxx_class = 'prefetch::DeltaCorrelatingPredictionTables'
+ cxx_class = 'gem5::prefetch::DeltaCorrelatingPredictionTables'
cxx_header = "mem/cache/prefetch/delta_correlating_prediction_tables.hh"
deltas_per_entry = Param.Unsigned(20,
"Number of deltas stored in each table entry")
@@ -349,7 +349,7 @@
class DCPTPrefetcher(QueuedPrefetcher):
type = 'DCPTPrefetcher'
- cxx_class = 'prefetch::DCPT'
+ cxx_class = 'gem5::prefetch::DCPT'
cxx_header = "mem/cache/prefetch/delta_correlating_prediction_tables.hh"
dcpt = Param.DeltaCorrelatingPredictionTables(
DeltaCorrelatingPredictionTables(),
@@ -357,7 +357,7 @@
class IrregularStreamBufferPrefetcher(QueuedPrefetcher):
type = "IrregularStreamBufferPrefetcher"
- cxx_class = "prefetch::IrregularStreamBuffer"
+ cxx_class = 'gem5::prefetch::IrregularStreamBuffer'
cxx_header = "mem/cache/prefetch/irregular_stream_buffer.hh"
num_counter_bits = Param.Unsigned(2,
@@ -410,7 +410,7 @@
class SlimAMPMPrefetcher(QueuedPrefetcher):
type = 'SlimAMPMPrefetcher'
- cxx_class = 'prefetch::SlimAMPM'
+ cxx_class = 'gem5::prefetch::SlimAMPM'
cxx_header = "mem/cache/prefetch/slim_ampm.hh"
ampm = Param.AccessMapPatternMatching(SlimAccessMapPatternMatching(),
@@ -421,7 +421,7 @@
class BOPPrefetcher(QueuedPrefetcher):
type = "BOPPrefetcher"
- cxx_class = "prefetch::BOP"
+ cxx_class = 'gem5::prefetch::BOP'
cxx_header = "mem/cache/prefetch/bop.hh"
score_max = Param.Unsigned(31, "Max. score to update the best offset")
round_max = Param.Unsigned(100, "Max. round to update the best offset")
@@ -443,7 +443,7 @@
class SBOOEPrefetcher(QueuedPrefetcher):
type = 'SBOOEPrefetcher'
- cxx_class = 'prefetch::SBOOE'
+ cxx_class = 'gem5::prefetch::SBOOE'
cxx_header = "mem/cache/prefetch/sbooe.hh"
latency_buffer_size = Param.Int(32, "Entries in the latency buffer")
sequential_prefetchers = Param.Int(9, "Number of sequential prefetchers")
@@ -453,7 +453,7 @@
class STeMSPrefetcher(QueuedPrefetcher):
type = "STeMSPrefetcher"
- cxx_class = "prefetch::STeMS"
+ cxx_class = 'gem5::prefetch::STeMS'
cxx_header = "mem/cache/prefetch/spatio_temporal_memory_streaming.hh"
spatial_region_size = Param.MemorySize("2KiB",
@@ -496,7 +496,7 @@
class PIFPrefetcher(QueuedPrefetcher):
type = 'PIFPrefetcher'
- cxx_class = 'prefetch::PIF'
+ cxx_class = 'gem5::prefetch::PIF'
cxx_header = "mem/cache/prefetch/pif.hh"
cxx_exports = [
PyBindMethod("addEventProbeRetiredInsts"),
diff --git a/src/mem/cache/prefetch/access_map_pattern_matching.cc b/src/mem/cache/prefetch/access_map_pattern_matching.cc
index 89418a0..6bf5d9b 100644
--- a/src/mem/cache/prefetch/access_map_pattern_matching.cc
+++ b/src/mem/cache/prefetch/access_map_pattern_matching.cc
@@ -33,6 +33,9 @@
#include "params/AMPMPrefetcher.hh"
#include "params/AccessMapPatternMatching.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
namespace prefetch
{
@@ -266,3 +269,4 @@
}
} // namespace prefetch
+} // namespace gem5
diff --git a/src/mem/cache/prefetch/access_map_pattern_matching.hh b/src/mem/cache/prefetch/access_map_pattern_matching.hh
index 929f78e..3b0bc28 100644
--- a/src/mem/cache/prefetch/access_map_pattern_matching.hh
+++ b/src/mem/cache/prefetch/access_map_pattern_matching.hh
@@ -43,6 +43,9 @@
#include "mem/packet.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
struct AccessMapPatternMatchingParams;
struct AMPMPrefetcherParams;
@@ -203,5 +206,6 @@
};
} // namespace prefetch
+} // namespace gem5
#endif//__MEM_CACHE_PREFETCH_ACCESS_MAP_PATTERN_MATCHING_HH__
diff --git a/src/mem/cache/prefetch/associative_set.hh b/src/mem/cache/prefetch/associative_set.hh
index d349dc0..f7d68a3 100644
--- a/src/mem/cache/prefetch/associative_set.hh
+++ b/src/mem/cache/prefetch/associative_set.hh
@@ -33,6 +33,9 @@
#include "mem/cache/tags/indexing_policies/base.hh"
#include "mem/cache/tags/tagged_entry.hh"
+namespace gem5
+{
+
/**
* Associative container based on the previosuly defined Entry type
* Each element is indexed by a key of type Addr, an additional
@@ -161,4 +164,6 @@
}
};
+} // namespace gem5
+
#endif//__CACHE_PREFETCH_ASSOCIATIVE_SET_HH__
diff --git a/src/mem/cache/prefetch/associative_set_impl.hh b/src/mem/cache/prefetch/associative_set_impl.hh
index 6118009..c53b19a 100644
--- a/src/mem/cache/prefetch/associative_set_impl.hh
+++ b/src/mem/cache/prefetch/associative_set_impl.hh
@@ -32,6 +32,9 @@
#include "base/intmath.hh"
#include "mem/cache/prefetch/associative_set.hh"
+namespace gem5
+{
+
template<class Entry>
AssociativeSet<Entry>::AssociativeSet(int assoc, int num_entries,
BaseIndexingPolicy *idx_policy, replacement_policy::Base *rpl_policy,
@@ -121,4 +124,6 @@
replacementPolicy->invalidate(entry->replacementData);
}
+} // namespace gem5
+
#endif//__CACHE_PREFETCH_ASSOCIATIVE_SET_IMPL_HH__
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index 7536231..b5be0f9 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -52,6 +52,9 @@
#include "params/BasePrefetcher.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
namespace prefetch
{
@@ -261,3 +264,4 @@
}
} // namespace prefetch
+} // namespace gem5
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index 4e08034..059f814 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -58,6 +58,9 @@
#include "sim/clocked_object.hh"
#include "sim/probe/probe.hh"
+namespace gem5
+{
+
class BaseCache;
struct BasePrefetcherParams;
@@ -385,5 +388,6 @@
};
} // namespace prefetch
+} // namespace gem5
#endif //__MEM_CACHE_PREFETCH_BASE_HH__
diff --git a/src/mem/cache/prefetch/bop.cc b/src/mem/cache/prefetch/bop.cc
index 9a4afd2..a60c1fe 100644
--- a/src/mem/cache/prefetch/bop.cc
+++ b/src/mem/cache/prefetch/bop.cc
@@ -31,6 +31,9 @@
#include "debug/HWPrefetch.hh"
#include "params/BOPPrefetcher.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
namespace prefetch
{
@@ -263,3 +266,4 @@
}
} // namespace prefetch
+} // namespace gem5
diff --git a/src/mem/cache/prefetch/bop.hh b/src/mem/cache/prefetch/bop.hh
index d7539a9..7fdba2b 100644
--- a/src/mem/cache/prefetch/bop.hh
+++ b/src/mem/cache/prefetch/bop.hh
@@ -41,6 +41,9 @@
#include "mem/cache/prefetch/queued.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
struct BOPPrefetcherParams;
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
@@ -158,5 +161,6 @@
};
} // namespace prefetch
+} // namespace gem5
#endif /* __MEM_CACHE_PREFETCH_BOP_HH__ */
diff --git a/src/mem/cache/prefetch/delta_correlating_prediction_tables.cc b/src/mem/cache/prefetch/delta_correlating_prediction_tables.cc
index 5d6c882..c5e126c 100644
--- a/src/mem/cache/prefetch/delta_correlating_prediction_tables.cc
+++ b/src/mem/cache/prefetch/delta_correlating_prediction_tables.cc
@@ -33,6 +33,9 @@
#include "params/DCPTPrefetcher.hh"
#include "params/DeltaCorrelatingPredictionTables.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
namespace prefetch
{
@@ -160,3 +163,4 @@
}
} // namespace prefetch
+} // namespace gem5
diff --git a/src/mem/cache/prefetch/delta_correlating_prediction_tables.hh b/src/mem/cache/prefetch/delta_correlating_prediction_tables.hh
index c60af20..8ad21a6 100644
--- a/src/mem/cache/prefetch/delta_correlating_prediction_tables.hh
+++ b/src/mem/cache/prefetch/delta_correlating_prediction_tables.hh
@@ -33,6 +33,9 @@
#include "mem/cache/prefetch/associative_set.hh"
#include "mem/cache/prefetch/queued.hh"
+namespace gem5
+{
+
struct DeltaCorrelatingPredictionTablesParams;
struct DCPTPrefetcherParams;
@@ -132,5 +135,6 @@
};
} // namespace prefetch
+} // namespace gem5
#endif//__MEM_CACHE_PREFETCH_DELTA_CORRELATING_PREDICTION_TABLES_HH_
diff --git a/src/mem/cache/prefetch/indirect_memory.cc b/src/mem/cache/prefetch/indirect_memory.cc
index 4f336b5..7bb1545 100644
--- a/src/mem/cache/prefetch/indirect_memory.cc
+++ b/src/mem/cache/prefetch/indirect_memory.cc
@@ -32,6 +32,9 @@
#include "mem/cache/prefetch/associative_set_impl.hh"
#include "params/IndirectMemoryPrefetcher.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
namespace prefetch
{
@@ -257,3 +260,4 @@
}
} // namespace prefetch
+} // namespace gem5
diff --git a/src/mem/cache/prefetch/indirect_memory.hh b/src/mem/cache/prefetch/indirect_memory.hh
index aae6185..85fb50e 100644
--- a/src/mem/cache/prefetch/indirect_memory.hh
+++ b/src/mem/cache/prefetch/indirect_memory.hh
@@ -45,6 +45,9 @@
#include "mem/cache/prefetch/associative_set.hh"
#include "mem/cache/prefetch/queued.hh"
+namespace gem5
+{
+
struct IndirectMemoryPrefetcherParams;
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
@@ -203,5 +206,6 @@
};
} // namespace prefetch
+} // namespace gem5
#endif//__MEM_CACHE_PREFETCH_INDIRECT_MEMORY_HH__
diff --git a/src/mem/cache/prefetch/irregular_stream_buffer.cc b/src/mem/cache/prefetch/irregular_stream_buffer.cc
index fa02d5e..fc0d71f 100644
--- a/src/mem/cache/prefetch/irregular_stream_buffer.cc
+++ b/src/mem/cache/prefetch/irregular_stream_buffer.cc
@@ -32,6 +32,9 @@
#include "mem/cache/prefetch/associative_set_impl.hh"
#include "params/IrregularStreamBufferPrefetcher.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
namespace prefetch
{
@@ -211,3 +214,4 @@
}
} // namespace prefetch
+} // namespace gem5
diff --git a/src/mem/cache/prefetch/irregular_stream_buffer.hh b/src/mem/cache/prefetch/irregular_stream_buffer.hh
index d9de292..20dadd6 100644
--- a/src/mem/cache/prefetch/irregular_stream_buffer.hh
+++ b/src/mem/cache/prefetch/irregular_stream_buffer.hh
@@ -43,6 +43,9 @@
#include "mem/cache/prefetch/associative_set.hh"
#include "mem/cache/prefetch/queued.hh"
+namespace gem5
+{
+
struct IrregularStreamBufferPrefetcherParams;
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
@@ -139,5 +142,6 @@
};
} // namespace prefetch
+} // namespace gem5
#endif//__MEM_CACHE_PREFETCH_IRREGULAR_STREAM_BUFFER_HH__
diff --git a/src/mem/cache/prefetch/multi.cc b/src/mem/cache/prefetch/multi.cc
index 74328cb..ab3a90d 100644
--- a/src/mem/cache/prefetch/multi.cc
+++ b/src/mem/cache/prefetch/multi.cc
@@ -39,6 +39,9 @@
#include "params/MultiPrefetcher.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
namespace prefetch
{
@@ -82,3 +85,4 @@
}
} // namespace prefetch
+} // namespace gem5
diff --git a/src/mem/cache/prefetch/multi.hh b/src/mem/cache/prefetch/multi.hh
index 0206ffe..037d23e 100644
--- a/src/mem/cache/prefetch/multi.hh
+++ b/src/mem/cache/prefetch/multi.hh
@@ -40,6 +40,9 @@
#include "mem/cache/prefetch/base.hh"
+namespace gem5
+{
+
struct MultiPrefetcherParams;
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
@@ -71,5 +74,6 @@
};
} // namespace prefetch
+} // namespace gem5
#endif //__MEM_CACHE_PREFETCH_MULTI_HH__
diff --git a/src/mem/cache/prefetch/pif.cc b/src/mem/cache/prefetch/pif.cc
index e28f7d0..95b9f4f 100644
--- a/src/mem/cache/prefetch/pif.cc
+++ b/src/mem/cache/prefetch/pif.cc
@@ -34,6 +34,9 @@
#include "mem/cache/prefetch/associative_set_impl.hh"
#include "params/PIFPrefetcher.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
namespace prefetch
{
@@ -246,3 +249,4 @@
}
} // namespace prefetch
+} // namespace gem5
diff --git a/src/mem/cache/prefetch/pif.hh b/src/mem/cache/prefetch/pif.hh
index 1867924..e48d8fb 100644
--- a/src/mem/cache/prefetch/pif.hh
+++ b/src/mem/cache/prefetch/pif.hh
@@ -44,6 +44,9 @@
#include "mem/cache/prefetch/associative_set.hh"
#include "mem/cache/prefetch/queued.hh"
+namespace gem5
+{
+
struct PIFPrefetcherParams;
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
@@ -191,5 +194,6 @@
};
} // namespace prefetch
+} // namespace gem5
#endif // __MEM_CACHE_PREFETCH_PIF_HH__
diff --git a/src/mem/cache/prefetch/queued.cc b/src/mem/cache/prefetch/queued.cc
index db3ba2f..8608522 100644
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -47,6 +47,9 @@
#include "mem/request.hh"
#include "params/QueuedPrefetcher.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
namespace prefetch
{
@@ -488,3 +491,4 @@
}
} // namespace prefetch
+} // namespace gem5
diff --git a/src/mem/cache/prefetch/queued.hh b/src/mem/cache/prefetch/queued.hh
index 07b6940..7de11bf 100644
--- a/src/mem/cache/prefetch/queued.hh
+++ b/src/mem/cache/prefetch/queued.hh
@@ -47,6 +47,9 @@
#include "mem/cache/prefetch/base.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
struct QueuedPrefetcherParams;
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
@@ -253,6 +256,6 @@
};
} // namespace prefetch
+} // namespace gem5
#endif //__MEM_CACHE_PREFETCH_QUEUED_HH__
-
diff --git a/src/mem/cache/prefetch/sbooe.cc b/src/mem/cache/prefetch/sbooe.cc
index 5d64348..a3f0231 100644
--- a/src/mem/cache/prefetch/sbooe.cc
+++ b/src/mem/cache/prefetch/sbooe.cc
@@ -31,6 +31,9 @@
#include "debug/HWPrefetch.hh"
#include "params/SBOOEPrefetcher.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
namespace prefetch
{
@@ -135,3 +138,4 @@
}
} // namespace prefetch
+} // namespace gem5
diff --git a/src/mem/cache/prefetch/sbooe.hh b/src/mem/cache/prefetch/sbooe.hh
index ee22085..9b25816 100644
--- a/src/mem/cache/prefetch/sbooe.hh
+++ b/src/mem/cache/prefetch/sbooe.hh
@@ -42,6 +42,9 @@
#include "mem/cache/prefetch/queued.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
struct SBOOEPrefetcherParams;
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
@@ -161,5 +164,6 @@
};
} // namespace prefetch
+} // namespace gem5
#endif // __MEM_CACHE_PREFETCH_SBOOE_HH__
diff --git a/src/mem/cache/prefetch/signature_path.cc b/src/mem/cache/prefetch/signature_path.cc
index e0f9de1..2f9477b 100644
--- a/src/mem/cache/prefetch/signature_path.cc
+++ b/src/mem/cache/prefetch/signature_path.cc
@@ -35,6 +35,9 @@
#include "mem/cache/prefetch/associative_set_impl.hh"
#include "params/SignaturePathPrefetcher.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
namespace prefetch
{
@@ -319,3 +322,4 @@
}
} // namespace prefetch
+} // namespace gem5
diff --git a/src/mem/cache/prefetch/signature_path.hh b/src/mem/cache/prefetch/signature_path.hh
index 2deb2ed..9cffa33 100644
--- a/src/mem/cache/prefetch/signature_path.hh
+++ b/src/mem/cache/prefetch/signature_path.hh
@@ -45,6 +45,9 @@
#include "mem/cache/prefetch/queued.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
struct SignaturePathPrefetcherParams;
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
@@ -289,5 +292,6 @@
};
} // namespace prefetch
+} // namespace gem5
#endif//__MEM_CACHE_PREFETCH_SIGNATURE_PATH_HH__
diff --git a/src/mem/cache/prefetch/signature_path_v2.cc b/src/mem/cache/prefetch/signature_path_v2.cc
index f1f5928..230bc76 100644
--- a/src/mem/cache/prefetch/signature_path_v2.cc
+++ b/src/mem/cache/prefetch/signature_path_v2.cc
@@ -34,6 +34,9 @@
#include "mem/cache/prefetch/associative_set_impl.hh"
#include "params/SignaturePathPrefetcherV2.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
namespace prefetch
{
@@ -131,3 +134,4 @@
}
} // namespace prefetch
+} // namespace gem5
diff --git a/src/mem/cache/prefetch/signature_path_v2.hh b/src/mem/cache/prefetch/signature_path_v2.hh
index 02efedc..b7f745c 100644
--- a/src/mem/cache/prefetch/signature_path_v2.hh
+++ b/src/mem/cache/prefetch/signature_path_v2.hh
@@ -45,6 +45,9 @@
#include "mem/cache/prefetch/signature_path.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
struct SignaturePathPrefetcherV2Params;
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
@@ -97,5 +100,6 @@
};
} // namespace prefetch
+} // namespace gem5
#endif//__MEM_CACHE_PREFETCH_SIGNATURE_PATH_V2_HH__
diff --git a/src/mem/cache/prefetch/slim_ampm.cc b/src/mem/cache/prefetch/slim_ampm.cc
index 462fc78..85f8966 100644
--- a/src/mem/cache/prefetch/slim_ampm.cc
+++ b/src/mem/cache/prefetch/slim_ampm.cc
@@ -30,6 +30,9 @@
#include "params/SlimAMPMPrefetcher.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
namespace prefetch
{
@@ -50,3 +53,4 @@
}
} // namespace prefetch
+} // namespace gem5
diff --git a/src/mem/cache/prefetch/slim_ampm.hh b/src/mem/cache/prefetch/slim_ampm.hh
index f67c72f..4a07b9b 100644
--- a/src/mem/cache/prefetch/slim_ampm.hh
+++ b/src/mem/cache/prefetch/slim_ampm.hh
@@ -43,6 +43,9 @@
* This prefetcher uses two other prefetchers, the AMPM and the DCPT.
*/
+namespace gem5
+{
+
struct SlimAMPMPrefetcherParams;
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
@@ -64,5 +67,6 @@
};
} // namespace prefetch
+} // namespace gem5
#endif//__MEM_CACHE_PREFETCH_SLIM_AMPM_HH__
diff --git a/src/mem/cache/prefetch/spatio_temporal_memory_streaming.cc b/src/mem/cache/prefetch/spatio_temporal_memory_streaming.cc
index ac3d8fd..d0f4119 100644
--- a/src/mem/cache/prefetch/spatio_temporal_memory_streaming.cc
+++ b/src/mem/cache/prefetch/spatio_temporal_memory_streaming.cc
@@ -32,6 +32,9 @@
#include "mem/cache/prefetch/associative_set_impl.hh"
#include "params/STeMSPrefetcher.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
namespace prefetch
{
@@ -249,3 +252,4 @@
}
} // namespace prefetch
+} // namespace gem5
diff --git a/src/mem/cache/prefetch/spatio_temporal_memory_streaming.hh b/src/mem/cache/prefetch/spatio_temporal_memory_streaming.hh
index 071dcbb..e5914b4 100644
--- a/src/mem/cache/prefetch/spatio_temporal_memory_streaming.hh
+++ b/src/mem/cache/prefetch/spatio_temporal_memory_streaming.hh
@@ -48,6 +48,9 @@
#include "mem/cache/prefetch/associative_set.hh"
#include "mem/cache/prefetch/queued.hh"
+namespace gem5
+{
+
struct STeMSPrefetcherParams;
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
@@ -205,5 +208,6 @@
};
} // namespace prefetch
+} // namespace gem5
#endif//__MEM_CACHE_PREFETCH_SPATIO_TEMPORAL_MEMORY_STREAMING_HH__
diff --git a/src/mem/cache/prefetch/stride.cc b/src/mem/cache/prefetch/stride.cc
index 394aea2..1d375a6 100644
--- a/src/mem/cache/prefetch/stride.cc
+++ b/src/mem/cache/prefetch/stride.cc
@@ -57,6 +57,9 @@
#include "mem/cache/replacement_policies/base.hh"
#include "params/StridePrefetcher.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
namespace prefetch
{
@@ -204,3 +207,4 @@
}
} // namespace prefetch
+} // namespace gem5
diff --git a/src/mem/cache/prefetch/stride.hh b/src/mem/cache/prefetch/stride.hh
index 11b1d02..2b70765 100644
--- a/src/mem/cache/prefetch/stride.hh
+++ b/src/mem/cache/prefetch/stride.hh
@@ -60,6 +60,9 @@
#include "mem/packet.hh"
#include "params/StridePrefetcherHashedSetAssociative.hh"
+namespace gem5
+{
+
class BaseIndexingPolicy;
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
namespace replacement_policy
@@ -163,5 +166,6 @@
};
} // namespace prefetch
+} // namespace gem5
#endif // __MEM_CACHE_PREFETCH_STRIDE_HH__
diff --git a/src/mem/cache/prefetch/tagged.cc b/src/mem/cache/prefetch/tagged.cc
index 75a12ab..d385ac0 100644
--- a/src/mem/cache/prefetch/tagged.cc
+++ b/src/mem/cache/prefetch/tagged.cc
@@ -35,6 +35,9 @@
#include "params/TaggedPrefetcher.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
namespace prefetch
{
@@ -58,3 +61,4 @@
}
} // namespace prefetch
+} // namespace gem5
diff --git a/src/mem/cache/prefetch/tagged.hh b/src/mem/cache/prefetch/tagged.hh
index 97a3d1c..d7f77a8 100644
--- a/src/mem/cache/prefetch/tagged.hh
+++ b/src/mem/cache/prefetch/tagged.hh
@@ -37,6 +37,9 @@
#include "mem/cache/prefetch/queued.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
struct TaggedPrefetcherParams;
GEM5_DEPRECATED_NAMESPACE(Prefetcher, prefetch);
@@ -57,5 +60,6 @@
};
} // namespace prefetch
+} // namespace gem5
#endif // __MEM_CACHE_PREFETCH_TAGGED_HH__
diff --git a/src/mem/cache/queue.hh b/src/mem/cache/queue.hh
index a725016..3b6bab6 100644
--- a/src/mem/cache/queue.hh
+++ b/src/mem/cache/queue.hh
@@ -59,6 +59,9 @@
#include "sim/core.hh"
#include "sim/drain.hh"
+namespace gem5
+{
+
/**
* A high-level queue interface, to be used by both the MSHR queue and
* the write buffer.
@@ -261,4 +264,6 @@
}
};
+} // namespace gem5
+
#endif //__MEM_CACHE_QUEUE_HH__
diff --git a/src/mem/cache/queue_entry.hh b/src/mem/cache/queue_entry.hh
index 9e528da..d891365 100644
--- a/src/mem/cache/queue_entry.hh
+++ b/src/mem/cache/queue_entry.hh
@@ -50,6 +50,9 @@
#include "base/types.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
class BaseCache;
/**
@@ -167,4 +170,6 @@
virtual Target* getTarget() = 0;
};
+} // namespace gem5
+
#endif // __MEM_CACHE_QUEUE_ENTRY_HH__
diff --git a/src/mem/cache/replacement_policies/ReplacementPolicies.py b/src/mem/cache/replacement_policies/ReplacementPolicies.py
index 7003abe..3676a39 100644
--- a/src/mem/cache/replacement_policies/ReplacementPolicies.py
+++ b/src/mem/cache/replacement_policies/ReplacementPolicies.py
@@ -31,12 +31,12 @@
class BaseReplacementPolicy(SimObject):
type = 'BaseReplacementPolicy'
abstract = True
- cxx_class = 'replacement_policy::Base'
+ cxx_class = 'gem5::replacement_policy::Base'
cxx_header = "mem/cache/replacement_policies/base.hh"
class DuelingRP(BaseReplacementPolicy):
type = 'DuelingRP'
- cxx_class = 'replacement_policy::Dueling'
+ cxx_class = 'gem5::replacement_policy::Dueling'
cxx_header = "mem/cache/replacement_policies/dueling_rp.hh"
constituency_size = Param.Unsigned(
@@ -50,27 +50,27 @@
class FIFORP(BaseReplacementPolicy):
type = 'FIFORP'
- cxx_class = 'replacement_policy::FIFO'
+ cxx_class = 'gem5::replacement_policy::FIFO'
cxx_header = "mem/cache/replacement_policies/fifo_rp.hh"
class SecondChanceRP(FIFORP):
type = 'SecondChanceRP'
- cxx_class = 'replacement_policy::SecondChance'
+ cxx_class = 'gem5::replacement_policy::SecondChance'
cxx_header = "mem/cache/replacement_policies/second_chance_rp.hh"
class LFURP(BaseReplacementPolicy):
type = 'LFURP'
- cxx_class = 'replacement_policy::LFU'
+ cxx_class = 'gem5::replacement_policy::LFU'
cxx_header = "mem/cache/replacement_policies/lfu_rp.hh"
class LRURP(BaseReplacementPolicy):
type = 'LRURP'
- cxx_class = 'replacement_policy::LRU'
+ cxx_class = 'gem5::replacement_policy::LRU'
cxx_header = "mem/cache/replacement_policies/lru_rp.hh"
class BIPRP(LRURP):
type = 'BIPRP'
- cxx_class = 'replacement_policy::BIP'
+ cxx_class = 'gem5::replacement_policy::BIP'
cxx_header = "mem/cache/replacement_policies/bip_rp.hh"
btp = Param.Percent(3, "Percentage of blocks to be inserted as MRU")
@@ -79,17 +79,17 @@
class MRURP(BaseReplacementPolicy):
type = 'MRURP'
- cxx_class = 'replacement_policy::MRU'
+ cxx_class = 'gem5::replacement_policy::MRU'
cxx_header = "mem/cache/replacement_policies/mru_rp.hh"
class RandomRP(BaseReplacementPolicy):
type = 'RandomRP'
- cxx_class = 'replacement_policy::Random'
+ cxx_class = 'gem5::replacement_policy::Random'
cxx_header = "mem/cache/replacement_policies/random_rp.hh"
class BRRIPRP(BaseReplacementPolicy):
type = 'BRRIPRP'
- cxx_class = 'replacement_policy::BRRIP'
+ cxx_class = 'gem5::replacement_policy::BRRIP'
cxx_header = "mem/cache/replacement_policies/brrip_rp.hh"
num_bits = Param.Int(2, "Number of bits per RRPV")
hit_priority = Param.Bool(False,
@@ -117,7 +117,7 @@
class SHiPRP(BRRIPRP):
type = 'SHiPRP'
abstract = True
- cxx_class = 'replacement_policy::SHiP'
+ cxx_class = 'gem5::replacement_policy::SHiP'
cxx_header = "mem/cache/replacement_policies/ship_rp.hh"
shct_size = Param.Unsigned(16384, "Number of SHCT entries")
@@ -131,21 +131,21 @@
class SHiPMemRP(SHiPRP):
type = 'SHiPMemRP'
- cxx_class = 'replacement_policy::SHiPMem'
+ cxx_class = 'gem5::replacement_policy::SHiPMem'
cxx_header = "mem/cache/replacement_policies/ship_rp.hh"
class SHiPPCRP(SHiPRP):
type = 'SHiPPCRP'
- cxx_class = 'replacement_policy::SHiPPC'
+ cxx_class = 'gem5::replacement_policy::SHiPPC'
cxx_header = "mem/cache/replacement_policies/ship_rp.hh"
class TreePLRURP(BaseReplacementPolicy):
type = 'TreePLRURP'
- cxx_class = 'replacement_policy::TreePLRU'
+ cxx_class = 'gem5::replacement_policy::TreePLRU'
cxx_header = "mem/cache/replacement_policies/tree_plru_rp.hh"
num_leaves = Param.Int(Parent.assoc, "Number of leaves in each tree")
class WeightedLRURP(LRURP):
type = "WeightedLRURP"
- cxx_class = "replacement_policy::WeightedLRU"
+ cxx_class = 'gem5::replacement_policy::WeightedLRU'
cxx_header = "mem/cache/replacement_policies/weighted_lru_rp.hh"
diff --git a/src/mem/cache/replacement_policies/base.hh b/src/mem/cache/replacement_policies/base.hh
index 0851287..fc92ecb 100644
--- a/src/mem/cache/replacement_policies/base.hh
+++ b/src/mem/cache/replacement_policies/base.hh
@@ -37,6 +37,9 @@
#include "params/BaseReplacementPolicy.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
/**
* Replacement candidates as chosen by the indexing policy.
*/
@@ -110,5 +113,6 @@
};
} // namespace replacement_policy
+} // namespace gem5
#endif // __MEM_CACHE_REPLACEMENT_POLICIES_BASE_HH__
diff --git a/src/mem/cache/replacement_policies/bip_rp.cc b/src/mem/cache/replacement_policies/bip_rp.cc
index b2e6299..f7c8cb2 100644
--- a/src/mem/cache/replacement_policies/bip_rp.cc
+++ b/src/mem/cache/replacement_policies/bip_rp.cc
@@ -34,6 +34,9 @@
#include "params/BIPRP.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
namespace replacement_policy
{
@@ -59,3 +62,4 @@
}
} // namespace replacement_policy
+} // namespace gem5
diff --git a/src/mem/cache/replacement_policies/bip_rp.hh b/src/mem/cache/replacement_policies/bip_rp.hh
index e3648ce..486f459 100644
--- a/src/mem/cache/replacement_policies/bip_rp.hh
+++ b/src/mem/cache/replacement_policies/bip_rp.hh
@@ -44,6 +44,9 @@
#include "mem/cache/replacement_policies/lru_rp.hh"
+namespace gem5
+{
+
struct BIPRPParams;
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
@@ -76,5 +79,6 @@
};
} // namespace replacement_policy
+} // namespace gem5
#endif // __MEM_CACHE_REPLACEMENT_POLICIES_BIP_RP_HH__
diff --git a/src/mem/cache/replacement_policies/brrip_rp.cc b/src/mem/cache/replacement_policies/brrip_rp.cc
index d735a5a..a28ad33 100644
--- a/src/mem/cache/replacement_policies/brrip_rp.cc
+++ b/src/mem/cache/replacement_policies/brrip_rp.cc
@@ -35,6 +35,9 @@
#include "base/random.hh"
#include "params/BRRIPRP.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
namespace replacement_policy
{
@@ -146,3 +149,4 @@
}
} // namespace replacement_policy
+} // namespace gem5
diff --git a/src/mem/cache/replacement_policies/brrip_rp.hh b/src/mem/cache/replacement_policies/brrip_rp.hh
index 7a32adb..f4f815e 100644
--- a/src/mem/cache/replacement_policies/brrip_rp.hh
+++ b/src/mem/cache/replacement_policies/brrip_rp.hh
@@ -55,6 +55,9 @@
#include "base/sat_counter.hh"
#include "mem/cache/replacement_policies/base.hh"
+namespace gem5
+{
+
struct BRRIPRPParams;
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
@@ -158,5 +161,6 @@
};
} // namespace replacement_policy
+} // namespace gem5
#endif // __MEM_CACHE_REPLACEMENT_POLICIES_BRRIP_RP_HH__
diff --git a/src/mem/cache/replacement_policies/dueling_rp.cc b/src/mem/cache/replacement_policies/dueling_rp.cc
index 3565017..9a2ce23 100644
--- a/src/mem/cache/replacement_policies/dueling_rp.cc
+++ b/src/mem/cache/replacement_policies/dueling_rp.cc
@@ -31,6 +31,9 @@
#include "base/logging.hh"
#include "params/DuelingRP.hh"
+namespace gem5
+{
+
namespace replacement_policy
{
@@ -187,3 +190,4 @@
}
} // namespace replacement_policy
+} // namespace gem5
diff --git a/src/mem/cache/replacement_policies/dueling_rp.hh b/src/mem/cache/replacement_policies/dueling_rp.hh
index 314042e..a451050 100644
--- a/src/mem/cache/replacement_policies/dueling_rp.hh
+++ b/src/mem/cache/replacement_policies/dueling_rp.hh
@@ -36,6 +36,9 @@
#include "mem/cache/replacement_policies/base.hh"
#include "mem/cache/tags/dueling.hh"
+namespace gem5
+{
+
struct DuelingRPParams;
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
@@ -111,5 +114,6 @@
};
} // namespace replacement_policy
+} // namespace gem5
#endif // __MEM_CACHE_REPLACEMENT_POLICIES_DUELING_RP_HH__
diff --git a/src/mem/cache/replacement_policies/fifo_rp.cc b/src/mem/cache/replacement_policies/fifo_rp.cc
index 69cad9b..e1907d3 100644
--- a/src/mem/cache/replacement_policies/fifo_rp.cc
+++ b/src/mem/cache/replacement_policies/fifo_rp.cc
@@ -34,6 +34,9 @@
#include "params/FIFORP.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
namespace replacement_policy
{
@@ -93,3 +96,4 @@
}
} // namespace replacement_policy
+} // namespace gem5
diff --git a/src/mem/cache/replacement_policies/fifo_rp.hh b/src/mem/cache/replacement_policies/fifo_rp.hh
index 8b895dd..f4703d1 100644
--- a/src/mem/cache/replacement_policies/fifo_rp.hh
+++ b/src/mem/cache/replacement_policies/fifo_rp.hh
@@ -39,6 +39,9 @@
#include "base/types.hh"
#include "mem/cache/replacement_policies/base.hh"
+namespace gem5
+{
+
struct FIFORPParams;
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
@@ -110,5 +113,6 @@
};
} // namespace replacement_policy
+} // namespace gem5
#endif // __MEM_CACHE_REPLACEMENT_POLICIES_FIFO_RP_HH__
diff --git a/src/mem/cache/replacement_policies/lfu_rp.cc b/src/mem/cache/replacement_policies/lfu_rp.cc
index fa6516c..a715f7d 100644
--- a/src/mem/cache/replacement_policies/lfu_rp.cc
+++ b/src/mem/cache/replacement_policies/lfu_rp.cc
@@ -33,6 +33,9 @@
#include "params/LFURP.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
namespace replacement_policy
{
@@ -91,3 +94,4 @@
}
} // namespace replacement_policy
+} // namespace gem5
diff --git a/src/mem/cache/replacement_policies/lfu_rp.hh b/src/mem/cache/replacement_policies/lfu_rp.hh
index 0259764..aa058c4 100644
--- a/src/mem/cache/replacement_policies/lfu_rp.hh
+++ b/src/mem/cache/replacement_policies/lfu_rp.hh
@@ -39,6 +39,9 @@
#include "mem/cache/replacement_policies/base.hh"
+namespace gem5
+{
+
struct LFURPParams;
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
@@ -110,5 +113,6 @@
};
} // namespace replacement_policy
+} // namespace gem5
#endif // __MEM_CACHE_REPLACEMENT_POLICIES_LFU_RP_HH__
diff --git a/src/mem/cache/replacement_policies/lru_rp.cc b/src/mem/cache/replacement_policies/lru_rp.cc
index 3b4be86..3d6a11b 100644
--- a/src/mem/cache/replacement_policies/lru_rp.cc
+++ b/src/mem/cache/replacement_policies/lru_rp.cc
@@ -34,6 +34,9 @@
#include "params/LRURP.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
namespace replacement_policy
{
@@ -95,3 +98,4 @@
}
} // namespace replacement_policy
+} // namespace gem5
diff --git a/src/mem/cache/replacement_policies/lru_rp.hh b/src/mem/cache/replacement_policies/lru_rp.hh
index 2184406..620117d 100644
--- a/src/mem/cache/replacement_policies/lru_rp.hh
+++ b/src/mem/cache/replacement_policies/lru_rp.hh
@@ -37,6 +37,9 @@
#include "mem/cache/replacement_policies/base.hh"
+namespace gem5
+{
+
struct LRURPParams;
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
@@ -108,5 +111,6 @@
};
} // namespace replacement_policy
+} // namespace gem5
#endif // __MEM_CACHE_REPLACEMENT_POLICIES_LRU_RP_HH__
diff --git a/src/mem/cache/replacement_policies/mru_rp.cc b/src/mem/cache/replacement_policies/mru_rp.cc
index db5a191..96791cd 100644
--- a/src/mem/cache/replacement_policies/mru_rp.cc
+++ b/src/mem/cache/replacement_policies/mru_rp.cc
@@ -34,6 +34,9 @@
#include "params/MRURP.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
namespace replacement_policy
{
@@ -100,3 +103,4 @@
}
} // namespace replacement_policy
+} // namespace gem5
diff --git a/src/mem/cache/replacement_policies/mru_rp.hh b/src/mem/cache/replacement_policies/mru_rp.hh
index 0e3f5bc..1657ace 100644
--- a/src/mem/cache/replacement_policies/mru_rp.hh
+++ b/src/mem/cache/replacement_policies/mru_rp.hh
@@ -39,6 +39,9 @@
#include "base/types.hh"
#include "mem/cache/replacement_policies/base.hh"
+namespace gem5
+{
+
struct MRURPParams;
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
@@ -110,5 +113,6 @@
};
} // namespace replacement_policy
+} // namespace gem5
#endif // __MEM_CACHE_REPLACEMENT_POLICIES_MRU_RP_HH__
diff --git a/src/mem/cache/replacement_policies/random_rp.cc b/src/mem/cache/replacement_policies/random_rp.cc
index e21e991..fc6c431 100644
--- a/src/mem/cache/replacement_policies/random_rp.cc
+++ b/src/mem/cache/replacement_policies/random_rp.cc
@@ -34,6 +34,9 @@
#include "base/random.hh"
#include "params/RandomRP.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
namespace replacement_policy
{
@@ -94,3 +97,4 @@
}
} // namespace replacement_policy
+} // namespace gem5
diff --git a/src/mem/cache/replacement_policies/random_rp.hh b/src/mem/cache/replacement_policies/random_rp.hh
index bd593eb..9c383d5 100644
--- a/src/mem/cache/replacement_policies/random_rp.hh
+++ b/src/mem/cache/replacement_policies/random_rp.hh
@@ -37,6 +37,9 @@
#include "mem/cache/replacement_policies/base.hh"
+namespace gem5
+{
+
struct RandomRPParams;
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
@@ -111,5 +114,6 @@
};
} // namespace replacement_policy
+} // namespace gem5
#endif // __MEM_CACHE_REPLACEMENT_POLICIES_RANDOM_RP_HH__
diff --git a/src/mem/cache/replacement_policies/replaceable_entry.hh b/src/mem/cache/replacement_policies/replaceable_entry.hh
index 27655af..6c56bca 100644
--- a/src/mem/cache/replacement_policies/replaceable_entry.hh
+++ b/src/mem/cache/replacement_policies/replaceable_entry.hh
@@ -35,6 +35,9 @@
#include "base/compiler.hh"
#include "base/cprintf.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
namespace replacement_policy
{
@@ -119,4 +122,6 @@
}
};
+} // namespace gem5
+
#endif // __MEM_CACHE_REPLACEMENT_POLICIES_REPLACEABLE_ENTRY_HH_
diff --git a/src/mem/cache/replacement_policies/second_chance_rp.cc b/src/mem/cache/replacement_policies/second_chance_rp.cc
index af872cf..df506c6 100644
--- a/src/mem/cache/replacement_policies/second_chance_rp.cc
+++ b/src/mem/cache/replacement_policies/second_chance_rp.cc
@@ -32,6 +32,9 @@
#include "params/SecondChanceRP.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
namespace replacement_policy
{
@@ -136,3 +139,4 @@
}
} // namespace replacement_policy
+} // namespace gem5
diff --git a/src/mem/cache/replacement_policies/second_chance_rp.hh b/src/mem/cache/replacement_policies/second_chance_rp.hh
index 651bb16..4d0a36c 100644
--- a/src/mem/cache/replacement_policies/second_chance_rp.hh
+++ b/src/mem/cache/replacement_policies/second_chance_rp.hh
@@ -41,6 +41,9 @@
#include "mem/cache/replacement_policies/base.hh"
#include "mem/cache/replacement_policies/fifo_rp.hh"
+namespace gem5
+{
+
struct SecondChanceRPParams;
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
@@ -126,5 +129,6 @@
};
} // namespace replacement_policy
+} // namespace gem5
#endif // __MEM_CACHE_REPLACEMENT_POLICIES_SECOND_CHANCE_RP_HH__
diff --git a/src/mem/cache/replacement_policies/ship_rp.cc b/src/mem/cache/replacement_policies/ship_rp.cc
index 7e16306..5243abb 100644
--- a/src/mem/cache/replacement_policies/ship_rp.cc
+++ b/src/mem/cache/replacement_policies/ship_rp.cc
@@ -33,6 +33,9 @@
#include "params/SHiPPCRP.hh"
#include "params/SHiPRP.hh"
+namespace gem5
+{
+
namespace replacement_policy
{
@@ -169,3 +172,4 @@
}
} // namespace replacement_policy
+} // namespace gem5
diff --git a/src/mem/cache/replacement_policies/ship_rp.hh b/src/mem/cache/replacement_policies/ship_rp.hh
index 1001a7b..fa27540 100644
--- a/src/mem/cache/replacement_policies/ship_rp.hh
+++ b/src/mem/cache/replacement_policies/ship_rp.hh
@@ -44,6 +44,9 @@
#include "mem/cache/replacement_policies/brrip_rp.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
struct SHiPRPParams;
struct SHiPMemRPParams;
struct SHiPPCRPParams;
@@ -185,5 +188,6 @@
};
} // namespace replacement_policy
+} // namespace gem5
#endif // __MEM_CACHE_REPLACEMENT_POLICIES_SHIP_RP_HH__
diff --git a/src/mem/cache/replacement_policies/tree_plru_rp.cc b/src/mem/cache/replacement_policies/tree_plru_rp.cc
index 9d4a96d..2ee987c 100644
--- a/src/mem/cache/replacement_policies/tree_plru_rp.cc
+++ b/src/mem/cache/replacement_policies/tree_plru_rp.cc
@@ -40,6 +40,9 @@
#include "base/logging.hh"
#include "params/TreePLRURP.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
namespace replacement_policy
{
@@ -213,3 +216,4 @@
}
} // namespace replacement_policy
+} // namespace gem5
diff --git a/src/mem/cache/replacement_policies/tree_plru_rp.hh b/src/mem/cache/replacement_policies/tree_plru_rp.hh
index 0e1cf53..3356704 100644
--- a/src/mem/cache/replacement_policies/tree_plru_rp.hh
+++ b/src/mem/cache/replacement_policies/tree_plru_rp.hh
@@ -75,6 +75,9 @@
#include "mem/cache/replacement_policies/base.hh"
+namespace gem5
+{
+
struct TreePLRURPParams;
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
@@ -208,5 +211,6 @@
};
} // namespace replacement_policy
+} // namespace gem5
#endif // __MEM_CACHE_REPLACEMENT_POLICIES_TREE_PLRU_RP_HH__
diff --git a/src/mem/cache/replacement_policies/weighted_lru_rp.cc b/src/mem/cache/replacement_policies/weighted_lru_rp.cc
index 334a128..40e1979 100644
--- a/src/mem/cache/replacement_policies/weighted_lru_rp.cc
+++ b/src/mem/cache/replacement_policies/weighted_lru_rp.cc
@@ -38,6 +38,9 @@
#include "params/WeightedLRURP.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
namespace replacement_policy
{
@@ -97,3 +100,4 @@
}
} // namespace replacement_policy
+} // namespace gem5
diff --git a/src/mem/cache/replacement_policies/weighted_lru_rp.hh b/src/mem/cache/replacement_policies/weighted_lru_rp.hh
index 2279683..613592a 100644
--- a/src/mem/cache/replacement_policies/weighted_lru_rp.hh
+++ b/src/mem/cache/replacement_policies/weighted_lru_rp.hh
@@ -39,6 +39,9 @@
#include "base/types.hh"
#include "mem/cache/replacement_policies/lru_rp.hh"
+namespace gem5
+{
+
struct WeightedLRURPParams;
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
@@ -86,5 +89,6 @@
};
} // namespace replacement_policy
+} // namespace gem5
#endif // __MEM_CACHE_REPLACEMENT_POLICIES_WEIGHTED_LRU_RP_HH__
diff --git a/src/mem/cache/tags/Tags.py b/src/mem/cache/tags/Tags.py
index 1e5b355..0bc11bb 100644
--- a/src/mem/cache/tags/Tags.py
+++ b/src/mem/cache/tags/Tags.py
@@ -42,6 +42,7 @@
type = 'BaseTags'
abstract = True
cxx_header = "mem/cache/tags/base.hh"
+ cxx_class = 'gem5::BaseTags'
# Get system to which it belongs
system = Param.System(Parent.any, "System we belong to")
@@ -74,6 +75,7 @@
class BaseSetAssoc(BaseTags):
type = 'BaseSetAssoc'
cxx_header = "mem/cache/tags/base_set_assoc.hh"
+ cxx_class = 'gem5::BaseSetAssoc'
# Get the cache associativity
assoc = Param.Int(Parent.assoc, "associativity")
@@ -85,6 +87,7 @@
class SectorTags(BaseTags):
type = 'SectorTags'
cxx_header = "mem/cache/tags/sector_tags.hh"
+ cxx_class = 'gem5::SectorTags'
# Get the cache associativity
assoc = Param.Int(Parent.assoc, "associativity")
@@ -102,6 +105,7 @@
class CompressedTags(SectorTags):
type = 'CompressedTags'
cxx_header = "mem/cache/tags/compressed_tags.hh"
+ cxx_class = 'gem5::CompressedTags'
# Maximum number of compressed blocks per tag
max_compression_ratio = Param.Int(2,
@@ -116,8 +120,8 @@
class FALRU(BaseTags):
type = 'FALRU'
- cxx_class = 'FALRU'
cxx_header = "mem/cache/tags/fa_lru.hh"
+ cxx_class = 'gem5::FALRU'
min_tracked_cache_size = Param.MemorySize("128KiB", "Minimum cache size"
" for which we track statistics")
diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc
index 1c0a6a7..560b041 100644
--- a/src/mem/cache/tags/base.cc
+++ b/src/mem/cache/tags/base.cc
@@ -55,6 +55,9 @@
#include "sim/sim_exit.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
BaseTags::BaseTags(const Params &p)
: ClockedObject(p), blkSize(p.block_size), blkMask(blkSize - 1),
size(p.size), lookupLatency(p.tag_latency),
@@ -295,3 +298,5 @@
tags.computeStats();
}
+
+} // namespace gem5
diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index 77d6f9d..e270277 100644
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -60,6 +60,9 @@
#include "params/BaseTags.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
class System;
class IndexingPolicy;
class ReplaceableEntry;
@@ -362,4 +365,6 @@
void computeStatsVisitor(CacheBlk &blk);
};
+} // namespace gem5
+
#endif //__MEM_CACHE_TAGS_BASE_HH__
diff --git a/src/mem/cache/tags/base_set_assoc.cc b/src/mem/cache/tags/base_set_assoc.cc
index 6663533..b0cae8e 100644
--- a/src/mem/cache/tags/base_set_assoc.cc
+++ b/src/mem/cache/tags/base_set_assoc.cc
@@ -49,6 +49,9 @@
#include "base/intmath.hh"
+namespace gem5
+{
+
BaseSetAssoc::BaseSetAssoc(const Params &p)
:BaseTags(p), allocAssoc(p.assoc), blks(p.size / p.block_size),
sequentialAccess(p.sequential_access),
@@ -105,3 +108,5 @@
replacementPolicy->invalidate(src_blk->replacementData);
replacementPolicy->reset(dest_blk->replacementData);
}
+
+} // namespace gem5
diff --git a/src/mem/cache/tags/base_set_assoc.hh b/src/mem/cache/tags/base_set_assoc.hh
index 7ca702b..22695d2 100644
--- a/src/mem/cache/tags/base_set_assoc.hh
+++ b/src/mem/cache/tags/base_set_assoc.hh
@@ -62,6 +62,9 @@
#include "mem/packet.hh"
#include "params/BaseSetAssoc.hh"
+namespace gem5
+{
+
/**
* A basic cache tag store.
* @sa \ref gem5MemorySystem "gem5 Memory System"
@@ -246,4 +249,6 @@
}
};
+} // namespace gem5
+
#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
diff --git a/src/mem/cache/tags/compressed_tags.cc b/src/mem/cache/tags/compressed_tags.cc
index 33d822a..32d7401 100644
--- a/src/mem/cache/tags/compressed_tags.cc
+++ b/src/mem/cache/tags/compressed_tags.cc
@@ -41,6 +41,9 @@
#include "mem/packet.hh"
#include "params/CompressedTags.hh"
+namespace gem5
+{
+
CompressedTags::CompressedTags(const Params &p)
: SectorTags(p)
{
@@ -178,3 +181,5 @@
}
return false;
}
+
+} // namespace gem5
diff --git a/src/mem/cache/tags/compressed_tags.hh b/src/mem/cache/tags/compressed_tags.hh
index e391538..b54efb0 100644
--- a/src/mem/cache/tags/compressed_tags.hh
+++ b/src/mem/cache/tags/compressed_tags.hh
@@ -39,6 +39,9 @@
#include "mem/cache/tags/sector_tags.hh"
#include "mem/cache/tags/super_blk.hh"
+namespace gem5
+{
+
class BaseCache;
class CacheBlk;
struct CompressedTagsParams;
@@ -127,4 +130,6 @@
bool anyBlk(std::function<bool(CacheBlk &)> visitor) override;
};
+} // namespace gem5
+
#endif //__MEM_CACHE_TAGS_COMPRESSED_TAGS_HH__
diff --git a/src/mem/cache/tags/dueling.cc b/src/mem/cache/tags/dueling.cc
index 7a36e30..b8b3a52 100644
--- a/src/mem/cache/tags/dueling.cc
+++ b/src/mem/cache/tags/dueling.cc
@@ -31,6 +31,9 @@
#include "base/bitfield.hh"
#include "base/logging.hh"
+namespace gem5
+{
+
unsigned DuelingMonitor::numInstances = 0;
Dueler::Dueler()
@@ -134,3 +137,5 @@
regionCounter = 0;
}
}
+
+} // namespace gem5
diff --git a/src/mem/cache/tags/dueling.hh b/src/mem/cache/tags/dueling.hh
index 2a82157..aebefb5 100644
--- a/src/mem/cache/tags/dueling.hh
+++ b/src/mem/cache/tags/dueling.hh
@@ -34,6 +34,9 @@
#include "base/sat_counter.hh"
+namespace gem5
+{
+
/**
* A dueler is an entry that may or may not be accounted for sampling.
* Whenever an action triggers sampling, the dueling monitor will check
@@ -201,4 +204,6 @@
void initEntry(Dueler* dueler);
};
+} // namespace gem5
+
#endif // __BASE_DUELING_HH__
diff --git a/src/mem/cache/tags/dueling.test.cc b/src/mem/cache/tags/dueling.test.cc
index ba252e2..4b6ed68 100644
--- a/src/mem/cache/tags/dueling.test.cc
+++ b/src/mem/cache/tags/dueling.test.cc
@@ -37,6 +37,8 @@
#include "base/sat_counter.hh"
#include "mem/cache/tags/dueling.hh"
+using namespace gem5;
+
/**
* Test whether dueler provides correct sampling functionality and assigns
* teams correctly.
diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc
index 5fea07e..9eb7d5b 100644
--- a/src/mem/cache/tags/fa_lru.cc
+++ b/src/mem/cache/tags/fa_lru.cc
@@ -55,6 +55,9 @@
#include "mem/cache/base.hh"
#include "mem/cache/replacement_policies/replaceable_entry.hh"
+namespace gem5
+{
+
std::string
FALRUBlk::print() const
{
@@ -455,3 +458,4 @@
accesses++;
}
+} // namespace gem5
diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh
index b96a1a0..deffd72 100644
--- a/src/mem/cache/tags/fa_lru.hh
+++ b/src/mem/cache/tags/fa_lru.hh
@@ -62,6 +62,9 @@
#include "mem/packet.hh"
#include "params/FALRU.hh"
+namespace gem5
+{
+
// Uncomment to enable sanity checks for the FALRU cache and the
// TrackedCaches class
//#define FALRU_DEBUG
@@ -368,4 +371,6 @@
CacheTracking cacheTracking;
};
+} // namespace gem5
+
#endif // __MEM_CACHE_TAGS_FA_LRU_HH__
diff --git a/src/mem/cache/tags/indexing_policies/IndexingPolicies.py b/src/mem/cache/tags/indexing_policies/IndexingPolicies.py
index 7414ddf..c25a762 100644
--- a/src/mem/cache/tags/indexing_policies/IndexingPolicies.py
+++ b/src/mem/cache/tags/indexing_policies/IndexingPolicies.py
@@ -31,6 +31,7 @@
class BaseIndexingPolicy(SimObject):
type = 'BaseIndexingPolicy'
abstract = True
+ cxx_class = 'gem5::BaseIndexingPolicy'
cxx_header = "mem/cache/tags/indexing_policies/base.hh"
# Get the size from the parent (cache)
@@ -44,10 +45,10 @@
class SetAssociative(BaseIndexingPolicy):
type = 'SetAssociative'
- cxx_class = 'SetAssociative'
+ cxx_class = 'gem5::SetAssociative'
cxx_header = "mem/cache/tags/indexing_policies/set_associative.hh"
class SkewedAssociative(BaseIndexingPolicy):
type = 'SkewedAssociative'
- cxx_class = 'SkewedAssociative'
+ cxx_class = 'gem5::SkewedAssociative'
cxx_header = "mem/cache/tags/indexing_policies/skewed_associative.hh"
diff --git a/src/mem/cache/tags/indexing_policies/base.cc b/src/mem/cache/tags/indexing_policies/base.cc
index 7b63c3d..f4f7155 100644
--- a/src/mem/cache/tags/indexing_policies/base.cc
+++ b/src/mem/cache/tags/indexing_policies/base.cc
@@ -52,6 +52,9 @@
#include "base/logging.hh"
#include "mem/cache/replacement_policies/replaceable_entry.hh"
+namespace gem5
+{
+
BaseIndexingPolicy::BaseIndexingPolicy(const Params &p)
: SimObject(p), assoc(p.assoc),
numSets(p.size / (p.entry_size * assoc)),
@@ -97,3 +100,5 @@
{
return (addr >> tagShift);
}
+
+} // namespace gem5
diff --git a/src/mem/cache/tags/indexing_policies/base.hh b/src/mem/cache/tags/indexing_policies/base.hh
index 20b0390..6cd3e72 100644
--- a/src/mem/cache/tags/indexing_policies/base.hh
+++ b/src/mem/cache/tags/indexing_policies/base.hh
@@ -52,6 +52,9 @@
#include "params/BaseIndexingPolicy.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class ReplaceableEntry;
/**
@@ -157,4 +160,6 @@
const = 0;
};
+} // namespace gem5
+
#endif //__MEM_CACHE_INDEXING_POLICIES_BASE_HH__
diff --git a/src/mem/cache/tags/indexing_policies/set_associative.cc b/src/mem/cache/tags/indexing_policies/set_associative.cc
index d08b807..d41a885 100644
--- a/src/mem/cache/tags/indexing_policies/set_associative.cc
+++ b/src/mem/cache/tags/indexing_policies/set_associative.cc
@@ -48,6 +48,9 @@
#include "mem/cache/replacement_policies/replaceable_entry.hh"
+namespace gem5
+{
+
SetAssociative::SetAssociative(const Params &p)
: BaseIndexingPolicy(p)
{
@@ -71,3 +74,5 @@
{
return sets[extractSet(addr)];
}
+
+} // namespace gem5
diff --git a/src/mem/cache/tags/indexing_policies/set_associative.hh b/src/mem/cache/tags/indexing_policies/set_associative.hh
index 75b45f6..c47848a 100644
--- a/src/mem/cache/tags/indexing_policies/set_associative.hh
+++ b/src/mem/cache/tags/indexing_policies/set_associative.hh
@@ -52,6 +52,9 @@
#include "mem/cache/tags/indexing_policies/base.hh"
#include "params/SetAssociative.hh"
+namespace gem5
+{
+
class ReplaceableEntry;
/**
@@ -126,4 +129,6 @@
override;
};
+} // namespace gem5
+
#endif //__MEM_CACHE_INDEXING_POLICIES_SET_ASSOCIATIVE_HH__
diff --git a/src/mem/cache/tags/indexing_policies/skewed_associative.cc b/src/mem/cache/tags/indexing_policies/skewed_associative.cc
index 62af87e..bd6573b 100644
--- a/src/mem/cache/tags/indexing_policies/skewed_associative.cc
+++ b/src/mem/cache/tags/indexing_policies/skewed_associative.cc
@@ -38,6 +38,9 @@
#include "base/logging.hh"
#include "mem/cache/replacement_policies/replaceable_entry.hh"
+namespace gem5
+{
+
SkewedAssociative::SkewedAssociative(const Params &p)
: BaseIndexingPolicy(p), msbShift(floorLog2(numSets) - 1)
{
@@ -216,3 +219,5 @@
return entries;
}
+
+} // namespace gem5
diff --git a/src/mem/cache/tags/indexing_policies/skewed_associative.hh b/src/mem/cache/tags/indexing_policies/skewed_associative.hh
index 6992c71..887087e 100644
--- a/src/mem/cache/tags/indexing_policies/skewed_associative.hh
+++ b/src/mem/cache/tags/indexing_policies/skewed_associative.hh
@@ -39,6 +39,9 @@
#include "mem/cache/tags/indexing_policies/base.hh"
#include "params/SkewedAssociative.hh"
+namespace gem5
+{
+
class ReplaceableEntry;
/**
@@ -172,4 +175,6 @@
override;
};
+} // namespace gem5
+
#endif //__MEM_CACHE_INDEXING_POLICIES_SKEWED_ASSOCIATIVE_HH__
diff --git a/src/mem/cache/tags/sector_blk.cc b/src/mem/cache/tags/sector_blk.cc
index c1c5f6a..57cbeb9 100644
--- a/src/mem/cache/tags/sector_blk.cc
+++ b/src/mem/cache/tags/sector_blk.cc
@@ -38,6 +38,9 @@
#include "base/cprintf.hh"
#include "base/logging.hh"
+namespace gem5
+{
+
void
SectorSubBlk::setSectorBlock(SectorBlk* sector_blk)
{
@@ -163,3 +166,5 @@
return csprintf("%s valid sub-blks (%d):\n%s",
TaggedEntry::print(), getNumValid(), sub_blk_print);
}
+
+} // namespace gem5
diff --git a/src/mem/cache/tags/sector_blk.hh b/src/mem/cache/tags/sector_blk.hh
index ba32450..dae8741 100644
--- a/src/mem/cache/tags/sector_blk.hh
+++ b/src/mem/cache/tags/sector_blk.hh
@@ -39,6 +39,9 @@
#include "mem/cache/cache_blk.hh"
#include "mem/cache/replacement_policies/replaceable_entry.hh"
+namespace gem5
+{
+
class SectorBlk;
/**
@@ -186,4 +189,6 @@
std::string print() const override;
};
+} // namespace gem5
+
#endif //__MEM_CACHE_TAGS_SECTOR_BLK_HH__
diff --git a/src/mem/cache/tags/sector_tags.cc b/src/mem/cache/tags/sector_tags.cc
index d63773b..cb121eb 100644
--- a/src/mem/cache/tags/sector_tags.cc
+++ b/src/mem/cache/tags/sector_tags.cc
@@ -45,6 +45,9 @@
#include "mem/cache/replacement_policies/replaceable_entry.hh"
#include "mem/cache/tags/indexing_policies/base.hh"
+namespace gem5
+{
+
SectorTags::SectorTags(const SectorTagsParams &p)
: BaseTags(p), allocAssoc(p.assoc),
sequentialAccess(p.sequential_access),
@@ -374,3 +377,5 @@
}
return false;
}
+
+} // namespace gem5
diff --git a/src/mem/cache/tags/sector_tags.hh b/src/mem/cache/tags/sector_tags.hh
index 2284b77..c646212 100644
--- a/src/mem/cache/tags/sector_tags.hh
+++ b/src/mem/cache/tags/sector_tags.hh
@@ -44,6 +44,9 @@
#include "mem/packet.hh"
#include "params/SectorTags.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
namespace replacement_policy
{
@@ -213,4 +216,6 @@
bool anyBlk(std::function<bool(CacheBlk &)> visitor) override;
};
+} // namespace gem5
+
#endif //__MEM_CACHE_TAGS_SECTOR_TAGS_HH__
diff --git a/src/mem/cache/tags/super_blk.cc b/src/mem/cache/tags/super_blk.cc
index 9a1de45..4ce3ef1 100644
--- a/src/mem/cache/tags/super_blk.cc
+++ b/src/mem/cache/tags/super_blk.cc
@@ -39,6 +39,9 @@
#include "base/bitfield.hh"
+namespace gem5
+{
+
CompressionBlk::CompressionBlk()
: SectorSubBlk(), _size(0), _decompressionLatency(0), _compressed(false)
{
@@ -242,3 +245,5 @@
{
return csprintf("CF: %d %s", getCompressionFactor(), SectorBlk::print());
}
+
+} // namespace gem5
diff --git a/src/mem/cache/tags/super_blk.hh b/src/mem/cache/tags/super_blk.hh
index 1ffd0f7..9057c24 100644
--- a/src/mem/cache/tags/super_blk.hh
+++ b/src/mem/cache/tags/super_blk.hh
@@ -37,6 +37,9 @@
#include "mem/cache/tags/sector_blk.hh"
+namespace gem5
+{
+
class SuperBlk;
/**
@@ -240,4 +243,6 @@
std::string print() const override;
};
+} // namespace gem5
+
#endif //__MEM_CACHE_TAGS_SUPER_BLK_HH__
diff --git a/src/mem/cache/tags/tagged_entry.hh b/src/mem/cache/tags/tagged_entry.hh
index be927a4..f6166f6 100644
--- a/src/mem/cache/tags/tagged_entry.hh
+++ b/src/mem/cache/tags/tagged_entry.hh
@@ -35,6 +35,9 @@
#include "base/types.hh"
#include "mem/cache/replacement_policies/replaceable_entry.hh"
+namespace gem5
+{
+
/**
* A tagged entry is an entry containing a tag. Each tag is accompanied by a
* secure bit, which informs whether it belongs to a secure address space.
@@ -151,4 +154,6 @@
void clearSecure() { _secure = false; }
};
+} // namespace gem5
+
#endif//__CACHE_TAGGED_ENTRY_HH__
diff --git a/src/mem/cache/write_queue.cc b/src/mem/cache/write_queue.cc
index fd55257..a6c6888 100644
--- a/src/mem/cache/write_queue.cc
+++ b/src/mem/cache/write_queue.cc
@@ -48,6 +48,9 @@
#include "mem/cache/write_queue_entry.hh"
+namespace gem5
+{
+
WriteQueue::WriteQueue(const std::string &_label,
int num_entries, int reserve, const std::string &name)
: Queue<WriteQueueEntry>(_label, num_entries, reserve,
@@ -81,3 +84,5 @@
entry->popTarget();
deallocate(entry);
}
+
+} // namespace gem5
diff --git a/src/mem/cache/write_queue.hh b/src/mem/cache/write_queue.hh
index 2705232..0690c84 100644
--- a/src/mem/cache/write_queue.hh
+++ b/src/mem/cache/write_queue.hh
@@ -50,6 +50,9 @@
#include "mem/cache/write_queue_entry.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
/**
* A write queue for all eviction packets, i.e. writebacks and clean
* evictions, as well as uncacheable writes.
@@ -95,4 +98,6 @@
void markInService(WriteQueueEntry *entry);
};
+} // namespace gem5
+
#endif //__MEM_CACHE_WRITE_QUEUE_HH__
diff --git a/src/mem/cache/write_queue_entry.cc b/src/mem/cache/write_queue_entry.cc
index 582d282..f71fd1b 100644
--- a/src/mem/cache/write_queue_entry.cc
+++ b/src/mem/cache/write_queue_entry.cc
@@ -54,6 +54,9 @@
#include "mem/cache/base.hh"
#include "mem/request.hh"
+namespace gem5
+{
+
inline void
WriteQueueEntry::TargetList::add(PacketPtr pkt, Tick readyTime,
Counter order)
@@ -182,3 +185,5 @@
print(str);
return str.str();
}
+
+} // namespace gem5
diff --git a/src/mem/cache/write_queue_entry.hh b/src/mem/cache/write_queue_entry.hh
index cfb4a11..480b7cd 100644
--- a/src/mem/cache/write_queue_entry.hh
+++ b/src/mem/cache/write_queue_entry.hh
@@ -57,6 +57,9 @@
#include "mem/packet.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
class BaseCache;
/**
@@ -185,4 +188,6 @@
bool conflictAddr(const QueueEntry* entry) const override;
};
+} // namespace gem5
+
#endif // __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__
diff --git a/src/mem/cfi_mem.cc b/src/mem/cfi_mem.cc
index de1348e..22face1 100644
--- a/src/mem/cfi_mem.cc
+++ b/src/mem/cfi_mem.cc
@@ -48,6 +48,9 @@
#include "debug/CFI.hh"
#include "debug/Drain.hh"
+namespace gem5
+{
+
bool
CfiMemory::BlockData::isLocked(Addr block_address) const
{
@@ -728,3 +731,5 @@
auto host_address = parent.toHostAddr(pkt->getAddr());
std::memset(host_address, 0xff, blockSize);
}
+
+} // namespace gem5
diff --git a/src/mem/cfi_mem.hh b/src/mem/cfi_mem.hh
index e49a154..89998b8 100644
--- a/src/mem/cfi_mem.hh
+++ b/src/mem/cfi_mem.hh
@@ -44,6 +44,9 @@
#include "mem/abstract_mem.hh"
#include "params/CfiMemory.hh"
+namespace gem5
+{
+
/**
* CfiMemory: This is modelling a flash memory adhering to the
* Common Flash Interface (CFI):
@@ -392,4 +395,6 @@
uint64_t cfiQuery(Addr addr);
};
+} // namespace gem5
+
#endif
diff --git a/src/mem/coherent_xbar.cc b/src/mem/coherent_xbar.cc
index a44fa73..d6378c1 100644
--- a/src/mem/coherent_xbar.cc
+++ b/src/mem/coherent_xbar.cc
@@ -52,6 +52,9 @@
#include "debug/CoherentXBar.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
CoherentXBar::CoherentXBar(const CoherentXBarParams &p)
: BaseXBar(p), system(p.system), snoopFilter(p.snoop_filter),
snoopResponseLatency(p.snoop_response_latency),
@@ -1119,3 +1122,5 @@
snoopFanout.init(0, snoopPorts.size(), 1);
}
+
+} // namespace gem5
diff --git a/src/mem/coherent_xbar.hh b/src/mem/coherent_xbar.hh
index b657a11..1c55cc0 100644
--- a/src/mem/coherent_xbar.hh
+++ b/src/mem/coherent_xbar.hh
@@ -53,6 +53,9 @@
#include "mem/xbar.hh"
#include "params/CoherentXBar.hh"
+namespace gem5
+{
+
/**
* A coherent crossbar connects a number of (potentially) snooping
* requestors and responders, and routes the request and response packets
@@ -430,4 +433,6 @@
virtual void regStats();
};
+} // namespace gem5
+
#endif //__MEM_COHERENT_XBAR_HH__
diff --git a/src/mem/comm_monitor.cc b/src/mem/comm_monitor.cc
index 0032a8b..ccc3d1e 100644
--- a/src/mem/comm_monitor.cc
+++ b/src/mem/comm_monitor.cc
@@ -43,6 +43,9 @@
#include "debug/CommMonitor.hh"
#include "sim/stats.hh"
+namespace gem5
+{
+
CommMonitor::CommMonitor(const Params ¶ms)
: SimObject(params),
memSidePort(name() + "-mem_side_port", *this),
@@ -565,3 +568,5 @@
{
schedule(samplePeriodicEvent, curTick() + samplePeriodTicks);
}
+
+} // namespace gem5
diff --git a/src/mem/comm_monitor.hh b/src/mem/comm_monitor.hh
index 80664c7..b924109 100644
--- a/src/mem/comm_monitor.hh
+++ b/src/mem/comm_monitor.hh
@@ -46,6 +46,9 @@
#include "sim/probe/mem.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
/**
* The communication monitor is a SimObject which can monitor statistics of
* the communication happening between two ports in the memory system.
@@ -425,4 +428,6 @@
/** @} */
};
+} // namespace gem5
+
#endif //__MEM_COMM_MONITOR_HH__
diff --git a/src/mem/drampower.cc b/src/mem/drampower.cc
index 1656892..170a2dc 100644
--- a/src/mem/drampower.cc
+++ b/src/mem/drampower.cc
@@ -40,6 +40,9 @@
#include "base/intmath.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
DRAMPower::DRAMPower(const DRAMInterfaceParams &p, bool include_io) :
powerlib(libDRAMPower(getMemSpec(p), include_io))
{
@@ -157,3 +160,5 @@
fatal("Got unexpected data rate %d, should be 1 or 2 or 4 or 8\n");
return data_rate;
}
+
+} // namespace gem5
diff --git a/src/mem/drampower.hh b/src/mem/drampower.hh
index 0d73666..8da200a 100644
--- a/src/mem/drampower.hh
+++ b/src/mem/drampower.hh
@@ -46,6 +46,9 @@
#include "libdrampower/LibDRAMPower.h"
#include "params/DRAMInterface.hh"
+namespace gem5
+{
+
/**
* DRAMPower is a standalone tool which calculates the power consumed by a
* DRAM in the system. This class wraps the DRAMPower library.
@@ -98,5 +101,6 @@
};
-#endif //__MEM_DRAM_POWER_HH__
+} // namespace gem5
+#endif //__MEM_DRAM_POWER_HH__
diff --git a/src/mem/dramsim2.cc b/src/mem/dramsim2.cc
index c4ca097..aac4aea 100644
--- a/src/mem/dramsim2.cc
+++ b/src/mem/dramsim2.cc
@@ -44,6 +44,9 @@
#include "debug/Drain.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
DRAMSim2::DRAMSim2(const Params &p) :
AbstractMemory(p),
port(name() + ".port", *this),
@@ -388,3 +391,5 @@
{
mem.recvRespRetry();
}
+
+} // namespace gem5
diff --git a/src/mem/dramsim2.hh b/src/mem/dramsim2.hh
index f3792ae..ca55dea 100644
--- a/src/mem/dramsim2.hh
+++ b/src/mem/dramsim2.hh
@@ -50,6 +50,9 @@
#include "mem/qport.hh"
#include "params/DRAMSim2.hh"
+namespace gem5
+{
+
class DRAMSim2 : public AbstractMemory
{
private:
@@ -204,4 +207,6 @@
};
+} // namespace gem5
+
#endif // __MEM_DRAMSIM2_HH__
diff --git a/src/mem/dramsim2_wrapper.cc b/src/mem/dramsim2_wrapper.cc
index 9e3a961..7ea0de6 100644
--- a/src/mem/dramsim2_wrapper.cc
+++ b/src/mem/dramsim2_wrapper.cc
@@ -54,6 +54,9 @@
#include "base/compiler.hh"
#include "base/logging.hh"
+namespace gem5
+{
+
/**
* DRAMSim2 requires SHOW_SIM_OUTPUT to be defined (declared extern in
* the DRAMSim2 print macros), otherwise we get linking errors due to
@@ -196,3 +199,5 @@
{
dramsim->update();
}
+
+} // namespace gem5
diff --git a/src/mem/dramsim2_wrapper.hh b/src/mem/dramsim2_wrapper.hh
index b30bf07..f96a78b 100644
--- a/src/mem/dramsim2_wrapper.hh
+++ b/src/mem/dramsim2_wrapper.hh
@@ -56,6 +56,9 @@
}
+namespace gem5
+{
+
/**
* Wrapper class to avoid having DRAMSim2 names like ClockDomain etc
* clashing with the normal gem5 world. Many of the DRAMSim2 headers
@@ -158,4 +161,6 @@
void tick();
};
+} // namespace gem5
+
#endif //__MEM_DRAMSIM2_WRAPPER_HH__
diff --git a/src/mem/dramsim3.cc b/src/mem/dramsim3.cc
index 0027a85..172b5d0 100644
--- a/src/mem/dramsim3.cc
+++ b/src/mem/dramsim3.cc
@@ -43,6 +43,9 @@
#include "debug/Drain.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
DRAMsim3::DRAMsim3(const Params &p) :
AbstractMemory(p),
port(name() + ".port", *this),
@@ -386,3 +389,5 @@
{
mem.recvRespRetry();
}
+
+} // namespace gem5
diff --git a/src/mem/dramsim3.hh b/src/mem/dramsim3.hh
index ca34d6d..43e34e4 100644
--- a/src/mem/dramsim3.hh
+++ b/src/mem/dramsim3.hh
@@ -52,6 +52,9 @@
#include "mem/qport.hh"
#include "params/DRAMsim3.hh"
+namespace gem5
+{
+
class DRAMsim3 : public AbstractMemory
{
private:
@@ -215,4 +218,6 @@
};
+} // namespace gem5
+
#endif // __MEM_DRAMSIM3_HH__
diff --git a/src/mem/dramsim3_wrapper.cc b/src/mem/dramsim3_wrapper.cc
index f45b250..703a1eb 100644
--- a/src/mem/dramsim3_wrapper.cc
+++ b/src/mem/dramsim3_wrapper.cc
@@ -55,6 +55,9 @@
#include "base/compiler.hh"
#include "base/logging.hh"
+namespace gem5
+{
+
DRAMsim3Wrapper::DRAMsim3Wrapper(const std::string& config_file,
const std::string& working_dir,
std::function<void(uint64_t)> read_cb,
@@ -151,3 +154,4 @@
dramsim->ClockTick();
}
+} // namespace gem5
diff --git a/src/mem/dramsim3_wrapper.hh b/src/mem/dramsim3_wrapper.hh
index 0c4f6d0..45276c9 100644
--- a/src/mem/dramsim3_wrapper.hh
+++ b/src/mem/dramsim3_wrapper.hh
@@ -56,6 +56,9 @@
}
+namespace gem5
+{
+
/**
* Wrapper class to avoid having DRAMsim3 names like ClockDomain etc
* clashing with the normal gem5 world. Many of the DRAMsim3 headers
@@ -157,4 +160,6 @@
void tick();
};
+} // namespace gem5
+
#endif //__MEM_DRAMSIM3_WRAPPER_HH__
diff --git a/src/mem/external_master.cc b/src/mem/external_master.cc
index 2af175d..07c3f4c 100644
--- a/src/mem/external_master.cc
+++ b/src/mem/external_master.cc
@@ -44,6 +44,9 @@
#include "debug/ExternalPort.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
std::map<std::string, ExternalMaster::Handler *>
ExternalMaster::portHandlers;
@@ -99,3 +102,5 @@
{
portHandlers[handler_name] = handler;
}
+
+} // namespace gem5
diff --git a/src/mem/external_master.hh b/src/mem/external_master.hh
index 0ca1936..61c4166 100644
--- a/src/mem/external_master.hh
+++ b/src/mem/external_master.hh
@@ -60,6 +60,9 @@
#include "params/ExternalMaster.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class ExternalMaster : public SimObject
{
public:
@@ -131,5 +134,6 @@
const RequestorID id;
};
+} // namespace gem5
#endif //__MEM_EXTERNAL_MASTER_HH__
diff --git a/src/mem/external_slave.cc b/src/mem/external_slave.cc
index b772b80..6ed739b 100644
--- a/src/mem/external_slave.cc
+++ b/src/mem/external_slave.cc
@@ -44,6 +44,9 @@
#include "base/trace.hh"
#include "debug/ExternalPort.hh"
+namespace gem5
+{
+
/** Implement a `stub' port which just responds to requests by printing
* a message. The stub port can be used to configure and test a system
* where the external port is used for a peripheral before connecting
@@ -237,3 +240,5 @@
{
portHandlers[handler_name] = handler;
}
+
+} // namespace gem5
diff --git a/src/mem/external_slave.hh b/src/mem/external_slave.hh
index ebb3554..51c884b 100644
--- a/src/mem/external_slave.hh
+++ b/src/mem/external_slave.hh
@@ -62,6 +62,9 @@
#include "params/ExternalSlave.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class ExternalSlave : public SimObject
{
public:
@@ -137,5 +140,6 @@
void init() override;
};
+} // namespace gem5
#endif //__MEM_EXTERNAL_SLAVE_HH__
diff --git a/src/mem/hmc_controller.cc b/src/mem/hmc_controller.cc
index b9487c5..398f6a0 100644
--- a/src/mem/hmc_controller.cc
+++ b/src/mem/hmc_controller.cc
@@ -4,6 +4,9 @@
#include "base/trace.hh"
#include "debug/HMCController.hh"
+namespace gem5
+{
+
HMCController::HMCController(const HMCControllerParams &p) :
NoncoherentXBar(p),
numMemSidePorts(p.port_mem_side_ports_connection_count),
@@ -111,3 +114,5 @@
return true;
}
+
+} // namespace gem5
diff --git a/src/mem/hmc_controller.hh b/src/mem/hmc_controller.hh
index 8474277..9925733 100644
--- a/src/mem/hmc_controller.hh
+++ b/src/mem/hmc_controller.hh
@@ -51,6 +51,9 @@
#include "mem/port.hh"
#include "params/HMCController.hh"
+namespace gem5
+{
+
/**
* HMC Controller, in general, is responsible for translating the host
* protocol (AXI for example) to serial links protocol. Plus, it should have
@@ -98,4 +101,6 @@
int rotate_counter();
};
+} // namespace gem5
+
#endif //__MEM_HMC_CONTROLLER_HH__
diff --git a/src/mem/htm.cc b/src/mem/htm.cc
index fae0149..dac6d8d 100644
--- a/src/mem/htm.cc
+++ b/src/mem/htm.cc
@@ -37,6 +37,9 @@
#include "mem/htm.hh"
+namespace gem5
+{
+
std::string
htmFailureToStr(HtmFailureFaultCause cause)
{
@@ -66,3 +69,5 @@
auto it = rc_to_str.find(rc);
return it == rc_to_str.end() ? "Unrecognized Failure" : it->second;
}
+
+} // namespace gem5
diff --git a/src/mem/htm.hh b/src/mem/htm.hh
index 7fa8a70..1f90ca0 100644
--- a/src/mem/htm.hh
+++ b/src/mem/htm.hh
@@ -41,6 +41,9 @@
#include <map>
#include <string>
+namespace gem5
+{
+
enum class HtmFailureFaultCause : int
{
INVALID = -1,
@@ -67,4 +70,6 @@
/** Convert enum into string to be used for debug purposes */
std::string htmFailureToStr(HtmCacheFailure rc);
+} // namespace gem5
+
#endif // __MEM_HTM_HH__
diff --git a/src/mem/mem_checker.cc b/src/mem/mem_checker.cc
index 5e839fb..8fc95e3 100644
--- a/src/mem/mem_checker.cc
+++ b/src/mem/mem_checker.cc
@@ -39,6 +39,9 @@
#include "base/logging.hh"
+namespace gem5
+{
+
void
MemChecker::WriteCluster::startWrite(MemChecker::Serial serial, Tick _start,
uint8_t data)
@@ -346,3 +349,5 @@
byte_trackers.erase(addr + i);
}
}
+
+} // namespace gem5
diff --git a/src/mem/mem_checker.hh b/src/mem/mem_checker.hh
index 101da4f..ae5e447 100644
--- a/src/mem/mem_checker.hh
+++ b/src/mem/mem_checker.hh
@@ -55,6 +55,9 @@
#include "sim/core.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
/**
* MemChecker. Verifies that reads observe the values from permissible writes.
* As memory operations have a start and completion time, we consider them as
@@ -566,4 +569,6 @@
}
}
+} // namespace gem5
+
#endif // __MEM_MEM_CHECKER_HH__
diff --git a/src/mem/mem_checker_monitor.cc b/src/mem/mem_checker_monitor.cc
index 8f343e5..23b3fa6 100644
--- a/src/mem/mem_checker_monitor.cc
+++ b/src/mem/mem_checker_monitor.cc
@@ -44,6 +44,9 @@
#include "base/trace.hh"
#include "debug/MemCheckerMonitor.hh"
+namespace gem5
+{
+
MemCheckerMonitor::MemCheckerMonitor(const Params ¶ms)
: SimObject(params),
memSidePort(name() + "-memSidePort", *this),
@@ -352,3 +355,5 @@
{
cpuSidePort.sendRangeChange();
}
+
+} // namespace gem5
diff --git a/src/mem/mem_checker_monitor.hh b/src/mem/mem_checker_monitor.hh
index a1d5fd3..17fd8ee 100644
--- a/src/mem/mem_checker_monitor.hh
+++ b/src/mem/mem_checker_monitor.hh
@@ -44,6 +44,9 @@
#include "sim/sim_object.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
/**
* Implements a MemChecker monitor, to be inserted between two ports.
*/
@@ -228,4 +231,6 @@
MemChecker *memchecker;
};
+} // namespace gem5
+
#endif //__MEM_MEM_CHECKER_MONITOR_HH__
diff --git a/src/mem/mem_ctrl.cc b/src/mem/mem_ctrl.cc
index 58ccd17..8e3545b 100644
--- a/src/mem/mem_ctrl.cc
+++ b/src/mem/mem_ctrl.cc
@@ -49,6 +49,9 @@
#include "mem/mem_interface.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
MemCtrl::MemCtrl(const MemCtrlParams &p) :
qos::MemCtrl(p),
port(name() + ".port", *this), isTimingMode(false),
@@ -1510,3 +1513,5 @@
// pass it to the memory controller
return ctrl.recvTimingReq(pkt);
}
+
+} // namespace gem5
diff --git a/src/mem/mem_ctrl.hh b/src/mem/mem_ctrl.hh
index c96f536..b78796f 100644
--- a/src/mem/mem_ctrl.hh
+++ b/src/mem/mem_ctrl.hh
@@ -60,6 +60,9 @@
#include "params/MemCtrl.hh"
#include "sim/eventq.hh"
+namespace gem5
+{
+
class DRAMInterface;
class NVMInterface;
@@ -709,4 +712,6 @@
};
+} // namespace gem5
+
#endif //__MEM_CTRL_HH__
diff --git a/src/mem/mem_delay.cc b/src/mem/mem_delay.cc
index d5db9f2..81d40c7 100644
--- a/src/mem/mem_delay.cc
+++ b/src/mem/mem_delay.cc
@@ -40,6 +40,9 @@
#include "params/MemDelay.hh"
#include "params/SimpleMemDelay.hh"
+namespace gem5
+{
+
MemDelay::MemDelay(const MemDelayParams &p)
: ClockedObject(p),
requestPort(name() + "-mem_side_port", *this),
@@ -209,3 +212,5 @@
return 0;
}
}
+
+} // namespace gem5
diff --git a/src/mem/mem_delay.hh b/src/mem/mem_delay.hh
index 9bdb3c3..9528a51 100644
--- a/src/mem/mem_delay.hh
+++ b/src/mem/mem_delay.hh
@@ -41,6 +41,9 @@
#include "mem/qport.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
struct MemDelayParams;
struct SimpleMemDelayParams;
@@ -177,4 +180,6 @@
const Tick writeRespDelay;
};
+} // namespace gem5
+
#endif //__MEM_MEM_DELAY_HH__
diff --git a/src/mem/mem_interface.cc b/src/mem/mem_interface.cc
index 12bd187..e9c35d2 100644
--- a/src/mem/mem_interface.cc
+++ b/src/mem/mem_interface.cc
@@ -49,6 +49,9 @@
#include "debug/NVM.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace Data;
MemInterface::MemInterface(const MemInterfaceParams &_p)
@@ -2620,3 +2623,5 @@
busUtilRead = avgRdBW / peakBW * 100;
busUtilWrite = avgWrBW / peakBW * 100;
}
+
+} // namespace gem5
diff --git a/src/mem/mem_interface.hh b/src/mem/mem_interface.hh
index f580642..03e5582 100644
--- a/src/mem/mem_interface.hh
+++ b/src/mem/mem_interface.hh
@@ -64,6 +64,9 @@
#include "params/NVMInterface.hh"
#include "sim/eventq.hh"
+namespace gem5
+{
+
/**
* General interface to memory device
* Includes functions and parameters shared across media types
@@ -1260,4 +1263,6 @@
NVMInterface(const NVMInterfaceParams &_p);
};
+} // namespace gem5
+
#endif //__MEM_INTERFACE_HH__
diff --git a/src/mem/mem_requestor.hh b/src/mem/mem_requestor.hh
index 9a52d87..7b66689 100644
--- a/src/mem/mem_requestor.hh
+++ b/src/mem/mem_requestor.hh
@@ -46,6 +46,9 @@
#include "mem/request.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
/**
* The RequestorInfo class contains data about a specific requestor.
*/
@@ -67,4 +70,6 @@
RequestorID id;
};
+} // namespace gem5
+
#endif // __MEM_MEM_REQUESTOR_HH__
diff --git a/src/mem/multi_level_page_table.hh b/src/mem/multi_level_page_table.hh
index afa67d0..b8f8d4b 100644
--- a/src/mem/multi_level_page_table.hh
+++ b/src/mem/multi_level_page_table.hh
@@ -41,6 +41,9 @@
#include "mem/page_table.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
/**
* This class implements an in-memory multi-level page table that can be
* configured to follow ISA specifications. It can be used instead of the
@@ -289,4 +292,7 @@
paramIn(cp, "ptable.pointer", _basePtr);
}
};
+
+} // namespace gem5
+
#endif // __MEM_MULTI_LEVEL_PAGE_TABLE_HH__
diff --git a/src/mem/noncoherent_xbar.cc b/src/mem/noncoherent_xbar.cc
index d9e56c1..67efdba 100644
--- a/src/mem/noncoherent_xbar.cc
+++ b/src/mem/noncoherent_xbar.cc
@@ -50,6 +50,9 @@
#include "debug/NoncoherentXBar.hh"
#include "debug/XBar.hh"
+namespace gem5
+{
+
NoncoherentXBar::NoncoherentXBar(const NoncoherentXBarParams &p)
: BaseXBar(p)
{
@@ -310,3 +313,5 @@
// forward the request to the appropriate destination
memSidePorts[dest_id]->sendFunctional(pkt);
}
+
+} // namespace gem5
diff --git a/src/mem/noncoherent_xbar.hh b/src/mem/noncoherent_xbar.hh
index dc527dd..ab83314 100644
--- a/src/mem/noncoherent_xbar.hh
+++ b/src/mem/noncoherent_xbar.hh
@@ -49,6 +49,9 @@
#include "mem/xbar.hh"
#include "params/NoncoherentXBar.hh"
+namespace gem5
+{
+
/**
* A non-coherent crossbar connects a number of non-snooping memory-side ports
* and cpu_sides, and routes the request and response packets based on
@@ -184,4 +187,6 @@
virtual ~NoncoherentXBar();
};
+} // namespace gem5
+
#endif //__MEM_NONCOHERENT_XBAR_HH__
diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index 820a4bf..219bc76 100644
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -58,6 +58,9 @@
#include "base/trace.hh"
#include "mem/packet_access.hh"
+namespace gem5
+{
+
const MemCmd::CommandInfo
MemCmd::commandInfo[] =
{
@@ -533,3 +536,5 @@
assert(flags.isSet(FROM_TRANSACTION));
return htmTransactionUid;
}
+
+} // namespace gem5
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index d689bbe..7ae6626 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -64,6 +64,9 @@
#include "sim/byteswap.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
class Packet;
typedef Packet *PacketPtr;
typedef uint8_t* PacketDataPtr;
@@ -274,7 +277,7 @@
{
public:
typedef uint32_t FlagsType;
- typedef ::Flags<FlagsType> Flags;
+ typedef gem5::Flags<FlagsType> Flags;
private:
enum : FlagsType
@@ -1486,4 +1489,6 @@
HtmCacheFailure getHtmTransactionFailedInCacheRC() const;
};
+} // namespace gem5
+
#endif //__MEM_PACKET_HH
diff --git a/src/mem/packet_access.hh b/src/mem/packet_access.hh
index 2190840..6b48478 100644
--- a/src/mem/packet_access.hh
+++ b/src/mem/packet_access.hh
@@ -44,6 +44,9 @@
#include "mem/packet.hh"
#include "sim/byteswap.hh"
+namespace gem5
+{
+
template <typename T>
inline T
Packet::getRaw() const
@@ -123,4 +126,6 @@
};
}
+} // namespace gem5
+
#endif //__MEM_PACKET_ACCESS_HH__
diff --git a/src/mem/packet_queue.cc b/src/mem/packet_queue.cc
index ecc6653..535764f 100644
--- a/src/mem/packet_queue.cc
+++ b/src/mem/packet_queue.cc
@@ -44,6 +44,9 @@
#include "debug/Drain.hh"
#include "debug/PacketQueue.hh"
+namespace gem5
+{
+
PacketQueue::PacketQueue(EventManager& _em, const std::string& _label,
const std::string& _sendEventName,
bool force_order,
@@ -274,3 +277,5 @@
{
return cpuSidePort.sendTimingResp(pkt);
}
+
+} // namespace gem5
diff --git a/src/mem/packet_queue.hh b/src/mem/packet_queue.hh
index 1509862..2bd47ad 100644
--- a/src/mem/packet_queue.hh
+++ b/src/mem/packet_queue.hh
@@ -55,6 +55,9 @@
#include "sim/drain.hh"
#include "sim/eventq.hh"
+namespace gem5
+{
+
/**
* A packet queue is a class that holds deferred packets and later
* sends them using the associated CPU-side port or memory-side port.
@@ -332,4 +335,6 @@
};
+} // namespace gem5
+
#endif // __MEM_PACKET_QUEUE_HH__
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index b7cfd62..a311a0a 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -41,6 +41,9 @@
#include "sim/faults.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
void
EmulationPageTable::map(Addr vaddr, Addr paddr, int64_t size, uint64_t flags)
{
@@ -203,3 +206,4 @@
}
}
+} // namespace gem5
diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index 9870c7e..900d446 100644
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -44,6 +44,9 @@
#include "mem/request.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
class ThreadContext;
class EmulationPageTable : public Serializable
@@ -165,4 +168,6 @@
void unserialize(CheckpointIn &cp) override;
};
+} // namespace gem5
+
#endif // __MEM_PAGE_TABLE_HH__
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index ee77e62..bd7b2de 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -68,6 +68,9 @@
#endif
#endif
+namespace gem5
+{
+
PhysicalMemory::PhysicalMemory(const std::string& _name,
const std::vector<AbstractMemory*>& _memories,
bool mmap_using_noreserve,
@@ -467,3 +470,5 @@
fatal("Close failed on physical memory checkpoint file '%s'\n",
filename);
}
+
+} // namespace gem5
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index 3e8ba28..6a39e01 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -47,6 +47,9 @@
#include "mem/packet.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
/**
* Forward declaration to avoid header dependencies.
*/
@@ -274,4 +277,6 @@
};
+} // namespace gem5
+
#endif //__MEM_PHYSICAL_HH__
diff --git a/src/mem/port.cc b/src/mem/port.cc
index e5d8308..ac586c2 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -47,6 +47,9 @@
#include "base/trace.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
namespace
{
@@ -199,3 +202,5 @@
}
return recvAtomic(pkt);
}
+
+} // namespace gem5
diff --git a/src/mem/port.hh b/src/mem/port.hh
index 357a10e..33ff117 100644
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -53,6 +53,9 @@
#include "mem/protocol/timing.hh"
#include "sim/port.hh"
+namespace gem5
+{
+
class SimObject;
/** Forward declaration */
@@ -528,4 +531,6 @@
}
}
+} // namespace gem5
+
#endif //__MEM_PORT_HH__
diff --git a/src/mem/port_proxy.cc b/src/mem/port_proxy.cc
index 34612f0..19e1a53 100644
--- a/src/mem/port_proxy.cc
+++ b/src/mem/port_proxy.cc
@@ -41,6 +41,9 @@
#include "cpu/thread_context.hh"
#include "mem/port.hh"
+namespace gem5
+{
+
PortProxy::PortProxy(ThreadContext *tc, unsigned int cache_line_size) :
PortProxy([tc](PacketPtr pkt)->void { tc->sendFunctional(pkt); },
cache_line_size)
@@ -135,3 +138,5 @@
*--str = '\0';
return true;
}
+
+} // namespace gem5
diff --git a/src/mem/port_proxy.hh b/src/mem/port_proxy.hh
index cad9271..29f6ba6 100644
--- a/src/mem/port_proxy.hh
+++ b/src/mem/port_proxy.hh
@@ -63,6 +63,9 @@
#include "mem/protocol/functional.hh"
#include "sim/byteswap.hh"
+namespace gem5
+{
+
class RequestPort;
class ThreadContext;
@@ -312,4 +315,6 @@
writeBlob(address, &data, sizeof(T));
}
+} // namespace gem5
+
#endif // __MEM_PORT_PROXY_HH__
diff --git a/src/mem/probes/BaseMemProbe.py b/src/mem/probes/BaseMemProbe.py
index 796ab36..4ed022b 100644
--- a/src/mem/probes/BaseMemProbe.py
+++ b/src/mem/probes/BaseMemProbe.py
@@ -41,6 +41,7 @@
type = 'BaseMemProbe'
abstract = True
cxx_header = "mem/probes/base.hh"
+ cxx_class = 'gem5::BaseMemProbe'
manager = VectorParam.SimObject(Parent.any,
"Probe manager(s) to instrument")
diff --git a/src/mem/probes/MemFootprintProbe.py b/src/mem/probes/MemFootprintProbe.py
index ba6e8e1..551f808 100644
--- a/src/mem/probes/MemFootprintProbe.py
+++ b/src/mem/probes/MemFootprintProbe.py
@@ -42,6 +42,8 @@
class MemFootprintProbe(BaseMemProbe):
type = "MemFootprintProbe"
cxx_header = "mem/probes/mem_footprint.hh"
+ cxx_class = 'gem5::MemFootprintProbe'
+
system = Param.System(Parent.any,
"System pointer to get cache line and mem size")
page_size = Param.Unsigned(4096, "Page size for page-level footprint")
diff --git a/src/mem/probes/MemTraceProbe.py b/src/mem/probes/MemTraceProbe.py
index 2225c36..a5254a1 100644
--- a/src/mem/probes/MemTraceProbe.py
+++ b/src/mem/probes/MemTraceProbe.py
@@ -40,6 +40,7 @@
class MemTraceProbe(BaseMemProbe):
type = 'MemTraceProbe'
cxx_header = "mem/probes/mem_trace.hh"
+ cxx_class = 'gem5::MemTraceProbe'
# Boolean to compress the trace or not.
trace_compress = Param.Bool(True, "Enable trace compression")
diff --git a/src/mem/probes/StackDistProbe.py b/src/mem/probes/StackDistProbe.py
index b326fce..132c9fa 100644
--- a/src/mem/probes/StackDistProbe.py
+++ b/src/mem/probes/StackDistProbe.py
@@ -40,6 +40,7 @@
class StackDistProbe(BaseMemProbe):
type = 'StackDistProbe'
cxx_header = "mem/probes/stack_dist.hh"
+ cxx_class = 'gem5::StackDistProbe'
system = Param.System(Parent.any,
"System to use when determining system cache "
diff --git a/src/mem/probes/base.cc b/src/mem/probes/base.cc
index 7ea63dc..0ac25bd 100644
--- a/src/mem/probes/base.cc
+++ b/src/mem/probes/base.cc
@@ -39,6 +39,9 @@
#include "params/BaseMemProbe.hh"
+namespace gem5
+{
+
BaseMemProbe::BaseMemProbe(const BaseMemProbeParams &p)
: SimObject(p)
{
@@ -56,3 +59,5 @@
listeners[i].reset(new PacketListener(*this, mgr, p.probe_name));
}
}
+
+} // namespace gem5
diff --git a/src/mem/probes/base.hh b/src/mem/probes/base.hh
index 6320dd3..2adb5d2 100644
--- a/src/mem/probes/base.hh
+++ b/src/mem/probes/base.hh
@@ -44,6 +44,9 @@
#include "sim/probe/mem.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
struct BaseMemProbeParams;
/**
@@ -91,4 +94,6 @@
std::vector<std::unique_ptr<PacketListener>> listeners;
};
+} // namespace gem5
+
#endif // __MEM_PROBES_BASE_HH__
diff --git a/src/mem/probes/mem_footprint.cc b/src/mem/probes/mem_footprint.cc
index 93aab4c..2961736 100644
--- a/src/mem/probes/mem_footprint.cc
+++ b/src/mem/probes/mem_footprint.cc
@@ -41,6 +41,9 @@
#include "base/intmath.hh"
#include "params/MemFootprintProbe.hh"
+namespace gem5
+{
+
MemFootprintProbe::MemFootprintProbe(const MemFootprintProbeParams &p)
: BaseMemProbe(p),
cacheLineSizeLg2(floorLog2(p.system->cacheLineSize())),
@@ -119,3 +122,5 @@
cacheLines.clear();
pages.clear();
}
+
+} // namespace gem5
diff --git a/src/mem/probes/mem_footprint.hh b/src/mem/probes/mem_footprint.hh
index bdfb17d..2acab51 100644
--- a/src/mem/probes/mem_footprint.hh
+++ b/src/mem/probes/mem_footprint.hh
@@ -47,6 +47,9 @@
#include "sim/stats.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
struct MemFootprintProbeParams;
/// Probe to track footprint of accessed memory
@@ -98,4 +101,6 @@
MemFootprintProbeStats stats;
};
+} // namespace gem5
+
#endif //__MEM_PROBES_MEM_FOOTPRINT_HH__
diff --git a/src/mem/probes/mem_trace.cc b/src/mem/probes/mem_trace.cc
index c8394fc..35a3557 100644
--- a/src/mem/probes/mem_trace.cc
+++ b/src/mem/probes/mem_trace.cc
@@ -43,6 +43,9 @@
#include "proto/packet.pb.h"
#include "sim/system.hh"
+namespace gem5
+{
+
MemTraceProbe::MemTraceProbe(const MemTraceProbeParams &p)
: BaseMemProbe(p),
traceStream(nullptr),
@@ -118,3 +121,5 @@
traceStream->write(pkt_msg);
}
+
+} // namespace gem5
diff --git a/src/mem/probes/mem_trace.hh b/src/mem/probes/mem_trace.hh
index 46c36b5..d63831b 100644
--- a/src/mem/probes/mem_trace.hh
+++ b/src/mem/probes/mem_trace.hh
@@ -42,6 +42,9 @@
#include "mem/probes/base.hh"
#include "proto/protoio.hh"
+namespace gem5
+{
+
struct MemTraceProbeParams;
class System;
@@ -74,4 +77,6 @@
const bool withPC;
};
+} // namespace gem5
+
#endif //__MEM_PROBES_MEM_TRACE_HH__
diff --git a/src/mem/probes/stack_dist.cc b/src/mem/probes/stack_dist.cc
index d763231..ca78dff 100644
--- a/src/mem/probes/stack_dist.cc
+++ b/src/mem/probes/stack_dist.cc
@@ -40,6 +40,9 @@
#include "params/StackDistProbe.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
StackDistProbe::StackDistProbe(const StackDistProbeParams &p)
: BaseMemProbe(p),
lineSize(p.line_size),
@@ -128,3 +131,5 @@
stats.writeLogHist.sample(sd_lg2);
}
}
+
+} // namespace gem5
diff --git a/src/mem/probes/stack_dist.hh b/src/mem/probes/stack_dist.hh
index 48be93c..5bd6ce2 100644
--- a/src/mem/probes/stack_dist.hh
+++ b/src/mem/probes/stack_dist.hh
@@ -43,6 +43,9 @@
#include "mem/stack_dist_calc.hh"
#include "sim/stats.hh"
+namespace gem5
+{
+
struct StackDistProbeParams;
class StackDistProbe : public BaseMemProbe
@@ -87,5 +90,6 @@
} stats;
};
+} // namespace gem5
#endif //__MEM_PROBES_STACK_DIST_HH__
diff --git a/src/mem/protocol/atomic.cc b/src/mem/protocol/atomic.cc
index 08d676d..31e0bb8 100644
--- a/src/mem/protocol/atomic.cc
+++ b/src/mem/protocol/atomic.cc
@@ -42,6 +42,9 @@
#include "base/trace.hh"
+namespace gem5
+{
+
/* The request protocol. */
Tick
@@ -67,3 +70,5 @@
assert(pkt->isRequest());
return peer->recvAtomicSnoop(pkt);
}
+
+} // namespace gem5
diff --git a/src/mem/protocol/atomic.hh b/src/mem/protocol/atomic.hh
index 73e165d..2451a3a 100644
--- a/src/mem/protocol/atomic.hh
+++ b/src/mem/protocol/atomic.hh
@@ -44,6 +44,9 @@
#include "mem/backdoor.hh"
#include "mem/packet.hh"
+namespace gem5
+{
+
class AtomicResponseProtocol;
class AtomicRequestProtocol
@@ -113,4 +116,6 @@
PacketPtr pkt, MemBackdoorPtr &backdoor) = 0;
};
+} // namespace gem5
+
#endif //__MEM_GEM5_PROTOCOL_ATOMIC_HH__
diff --git a/src/mem/protocol/functional.cc b/src/mem/protocol/functional.cc
index 139ab4c..0f54d92 100644
--- a/src/mem/protocol/functional.cc
+++ b/src/mem/protocol/functional.cc
@@ -40,6 +40,9 @@
#include "mem/protocol/functional.hh"
+namespace gem5
+{
+
/* The request protocol. */
void
@@ -59,3 +62,5 @@
assert(pkt->isRequest());
return peer->recvFunctionalSnoop(pkt);
}
+
+} // namespace gem5
diff --git a/src/mem/protocol/functional.hh b/src/mem/protocol/functional.hh
index dc3c665..27db171 100644
--- a/src/mem/protocol/functional.hh
+++ b/src/mem/protocol/functional.hh
@@ -43,6 +43,9 @@
#include "mem/packet.hh"
+namespace gem5
+{
+
class FunctionalResponseProtocol;
class FunctionalRequestProtocol
@@ -85,4 +88,6 @@
virtual void recvFunctional(PacketPtr pkt) = 0;
};
+} // namespace gem5
+
#endif //__MEM_GEM5_PROTOCOL_FUNCTIONAL_HH__
diff --git a/src/mem/protocol/timing.cc b/src/mem/protocol/timing.cc
index d713db2..802dec9 100644
--- a/src/mem/protocol/timing.cc
+++ b/src/mem/protocol/timing.cc
@@ -40,6 +40,9 @@
#include "mem/protocol/timing.hh"
+namespace gem5
+{
+
/* The request protocol. */
bool
@@ -99,3 +102,5 @@
{
peer->recvRetrySnoopResp();
}
+
+} // namespace gem5
diff --git a/src/mem/protocol/timing.hh b/src/mem/protocol/timing.hh
index f02792b..81fbf5d 100644
--- a/src/mem/protocol/timing.hh
+++ b/src/mem/protocol/timing.hh
@@ -43,6 +43,9 @@
#include "mem/packet.hh"
+namespace gem5
+{
+
class TimingResponseProtocol;
class TimingRequestProtocol
@@ -183,4 +186,6 @@
virtual void recvRespRetry() = 0;
};
+} // namespace gem5
+
#endif //__MEM_GEM5_PROTOCOL_TIMING_HH__
diff --git a/src/mem/qos/QoSMemCtrl.py b/src/mem/qos/QoSMemCtrl.py
index 71cb903..b3391fb 100644
--- a/src/mem/qos/QoSMemCtrl.py
+++ b/src/mem/qos/QoSMemCtrl.py
@@ -44,7 +44,7 @@
class QoSMemCtrl(ClockedObject):
type = 'QoSMemCtrl'
cxx_header = "mem/qos/mem_ctrl.hh"
- cxx_class = 'qos::MemCtrl'
+ cxx_class = 'gem5::qos::MemCtrl'
abstract = True
system = Param.System(Parent.any, "System that the controller belongs to.")
diff --git a/src/mem/qos/QoSMemSinkCtrl.py b/src/mem/qos/QoSMemSinkCtrl.py
index 42a4ea7..234d8bc 100644
--- a/src/mem/qos/QoSMemSinkCtrl.py
+++ b/src/mem/qos/QoSMemSinkCtrl.py
@@ -42,7 +42,7 @@
class QoSMemSinkCtrl(QoSMemCtrl):
type = 'QoSMemSinkCtrl'
cxx_header = "mem/qos/mem_sink.hh"
- cxx_class = "qos::MemSinkCtrl"
+ cxx_class = 'gem5::qos::MemSinkCtrl'
port = ResponsePort("Response ports")
diff --git a/src/mem/qos/QoSMemSinkInterface.py b/src/mem/qos/QoSMemSinkInterface.py
index 9b3b89e..d493dce 100644
--- a/src/mem/qos/QoSMemSinkInterface.py
+++ b/src/mem/qos/QoSMemSinkInterface.py
@@ -38,7 +38,7 @@
class QoSMemSinkInterface(AbstractMemory):
type = 'QoSMemSinkInterface'
cxx_header = "mem/qos/mem_sink.hh"
- cxx_class = 'qos::MemSinkInterface'
+ cxx_class = 'gem5::qos::MemSinkInterface'
def controller(self):
"""
diff --git a/src/mem/qos/QoSPolicy.py b/src/mem/qos/QoSPolicy.py
index f202413..fba2e86 100644
--- a/src/mem/qos/QoSPolicy.py
+++ b/src/mem/qos/QoSPolicy.py
@@ -41,12 +41,12 @@
type = 'QoSPolicy'
abstract = True
cxx_header = "mem/qos/policy.hh"
- cxx_class = 'qos::Policy'
+ cxx_class = 'gem5::qos::Policy'
class QoSFixedPriorityPolicy(QoSPolicy):
type = 'QoSFixedPriorityPolicy'
cxx_header = "mem/qos/policy_fixed_prio.hh"
- cxx_class = 'qos::FixedPriorityPolicy'
+ cxx_class = 'gem5::qos::FixedPriorityPolicy'
cxx_exports = [
PyBindMethod('initRequestorName'),
@@ -90,7 +90,7 @@
class QoSPropFairPolicy(QoSPolicy):
type = 'QoSPropFairPolicy'
cxx_header = "mem/qos/policy_pf.hh"
- cxx_class = 'qos::PropFairPolicy'
+ cxx_class = 'gem5::qos::PropFairPolicy'
cxx_exports = [
PyBindMethod('initRequestorName'),
diff --git a/src/mem/qos/QoSTurnaround.py b/src/mem/qos/QoSTurnaround.py
index 4ea9c26..c74f5e8 100644
--- a/src/mem/qos/QoSTurnaround.py
+++ b/src/mem/qos/QoSTurnaround.py
@@ -39,10 +39,10 @@
class QoSTurnaroundPolicy(SimObject):
type = 'QoSTurnaroundPolicy'
cxx_header = "mem/qos/turnaround_policy.hh"
- cxx_class = 'qos::TurnaroundPolicy'
+ cxx_class = 'gem5::qos::TurnaroundPolicy'
abstract = True
class QoSTurnaroundPolicyIdeal(QoSTurnaroundPolicy):
type = 'QoSTurnaroundPolicyIdeal'
cxx_header = "mem/qos/turnaround_policy_ideal.hh"
- cxx_class = 'qos::TurnaroundPolicyIdeal'
+ cxx_class = 'gem5::qos::TurnaroundPolicyIdeal'
diff --git a/src/mem/qos/mem_ctrl.cc b/src/mem/qos/mem_ctrl.cc
index 62c67f1..f35d9b3 100644
--- a/src/mem/qos/mem_ctrl.cc
+++ b/src/mem/qos/mem_ctrl.cc
@@ -42,6 +42,9 @@
#include "mem/qos/turnaround_policy.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(QoS, qos);
namespace qos
{
@@ -368,3 +371,4 @@
}
} // namespace qos
+} // namespace gem5
diff --git a/src/mem/qos/mem_ctrl.hh b/src/mem/qos/mem_ctrl.hh
index 9fc2c1d..a332f69 100644
--- a/src/mem/qos/mem_ctrl.hh
+++ b/src/mem/qos/mem_ctrl.hh
@@ -58,6 +58,9 @@
#include "sim/cur_tick.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(QoS, qos);
namespace qos
{
@@ -534,5 +537,6 @@
}
} // namespace qos
+} // namespace gem5
#endif /* __MEM_QOS_MEM_CTRL_HH__ */
diff --git a/src/mem/qos/mem_sink.cc b/src/mem/qos/mem_sink.cc
index f9be06c..f49ca7b 100644
--- a/src/mem/qos/mem_sink.cc
+++ b/src/mem/qos/mem_sink.cc
@@ -44,6 +44,9 @@
#include "mem/qos/q_policy.hh"
#include "params/QoSMemSinkInterface.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(QoS, qos);
namespace qos
{
@@ -392,3 +395,4 @@
}
} // namespace qos
+} // namespace gem5
diff --git a/src/mem/qos/mem_sink.hh b/src/mem/qos/mem_sink.hh
index 247db22..9cdb62d 100644
--- a/src/mem/qos/mem_sink.hh
+++ b/src/mem/qos/mem_sink.hh
@@ -51,6 +51,9 @@
#include "params/QoSMemSinkCtrl.hh"
#include "sim/eventq.hh"
+namespace gem5
+{
+
struct QoSMemSinkInterfaceParams;
GEM5_DEPRECATED_NAMESPACE(QoS, qos);
@@ -276,5 +279,6 @@
};
} // namespace qos
+} // namespace gem5
-#endif /* __MEM_QOS_MEM_SINK_HH__ */
+#endif // __MEM_QOS_MEM_SINK_HH__
diff --git a/src/mem/qos/policy.cc b/src/mem/qos/policy.cc
index 67b30b1..1753bb0 100644
--- a/src/mem/qos/policy.cc
+++ b/src/mem/qos/policy.cc
@@ -39,6 +39,9 @@
#include "params/QoSPolicy.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(QoS, qos);
namespace qos
{
@@ -57,3 +60,4 @@
}
} // namespace qos
+} // namespace gem5
diff --git a/src/mem/qos/policy.hh b/src/mem/qos/policy.hh
index 939f08d..883eab6 100644
--- a/src/mem/qos/policy.hh
+++ b/src/mem/qos/policy.hh
@@ -49,6 +49,9 @@
#include "mem/packet.hh"
#include "mem/request.hh"
+namespace gem5
+{
+
struct QoSPolicyParams;
GEM5_DEPRECATED_NAMESPACE(QoS, qos);
@@ -135,5 +138,6 @@
}
} // namespace qos
+} // namespace gem5
#endif /* __MEM_QOS_POLICY_HH__ */
diff --git a/src/mem/qos/policy_fixed_prio.cc b/src/mem/qos/policy_fixed_prio.cc
index d0ac2f6..360365c 100644
--- a/src/mem/qos/policy_fixed_prio.cc
+++ b/src/mem/qos/policy_fixed_prio.cc
@@ -45,6 +45,9 @@
#include "mem/request.hh"
#include "params/QoSFixedPriorityPolicy.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(QoS, qos);
namespace qos
{
@@ -97,3 +100,4 @@
}
} // namespace qos
+} // namespace gem5
diff --git a/src/mem/qos/policy_fixed_prio.hh b/src/mem/qos/policy_fixed_prio.hh
index 3d945c9..260798d 100644
--- a/src/mem/qos/policy_fixed_prio.hh
+++ b/src/mem/qos/policy_fixed_prio.hh
@@ -44,6 +44,9 @@
#include "base/compiler.hh"
#include "mem/qos/policy.hh"
+namespace gem5
+{
+
struct QoSFixedPriorityPolicyParams;
GEM5_DEPRECATED_NAMESPACE(QoS, qos);
@@ -106,5 +109,6 @@
};
} // namespace qos
+} // namespace gem5
#endif // __MEM_QOS_POLICY_FIXED_PRIO_HH__
diff --git a/src/mem/qos/policy_pf.cc b/src/mem/qos/policy_pf.cc
index e419467..0c150ff 100644
--- a/src/mem/qos/policy_pf.cc
+++ b/src/mem/qos/policy_pf.cc
@@ -42,6 +42,9 @@
#include "base/logging.hh"
#include "params/QoSPropFairPolicy.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(QoS, qos);
namespace qos
{
@@ -125,3 +128,4 @@
}
} // namespace qos
+} // namespace gem5
diff --git a/src/mem/qos/policy_pf.hh b/src/mem/qos/policy_pf.hh
index d203870..65c543f 100644
--- a/src/mem/qos/policy_pf.hh
+++ b/src/mem/qos/policy_pf.hh
@@ -44,6 +44,9 @@
#include "mem/qos/policy.hh"
#include "mem/request.hh"
+namespace gem5
+{
+
struct QoSPropFairPolicyParams;
GEM5_DEPRECATED_NAMESPACE(QoS, qos);
@@ -116,5 +119,6 @@
};
} // namespace qos
+} // namespace gem5
#endif // __MEM_QOS_POLICY_PF_HH__
diff --git a/src/mem/qos/q_policy.cc b/src/mem/qos/q_policy.cc
index 133818d..742dc12 100644
--- a/src/mem/qos/q_policy.cc
+++ b/src/mem/qos/q_policy.cc
@@ -46,6 +46,9 @@
#include "enums/QoSQPolicy.hh"
#include "mem/request.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(QoS, qos);
namespace qos
{
@@ -147,3 +150,4 @@
};
} // namespace qos
+} // namespace gem5
diff --git a/src/mem/qos/q_policy.hh b/src/mem/qos/q_policy.hh
index 3b4d69d..d4389e1 100644
--- a/src/mem/qos/q_policy.hh
+++ b/src/mem/qos/q_policy.hh
@@ -47,6 +47,9 @@
#include "mem/qos/mem_ctrl.hh"
#include "params/QoSMemCtrl.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(QoS, qos);
namespace qos
{
@@ -187,5 +190,6 @@
};
} // namespace qos
+} // namespace gem5
#endif /* __MEM_QOS_Q_POLICY_HH__ */
diff --git a/src/mem/qos/turnaround_policy.hh b/src/mem/qos/turnaround_policy.hh
index 85edae8..324ef8a 100644
--- a/src/mem/qos/turnaround_policy.hh
+++ b/src/mem/qos/turnaround_policy.hh
@@ -43,6 +43,9 @@
#include "params/QoSTurnaroundPolicy.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(QoS, qos);
namespace qos
{
@@ -79,5 +82,6 @@
};
} // namespace qos
+} // namespace gem5
#endif /* __MEM_QOS_TURNAROUND_POLICY_HH__ */
diff --git a/src/mem/qos/turnaround_policy_ideal.cc b/src/mem/qos/turnaround_policy_ideal.cc
index 00b8a81..b6279b9 100644
--- a/src/mem/qos/turnaround_policy_ideal.cc
+++ b/src/mem/qos/turnaround_policy_ideal.cc
@@ -42,6 +42,9 @@
#include "base/trace.hh"
#include "params/QoSTurnaroundPolicyIdeal.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(QoS, qos);
namespace qos
{
@@ -101,3 +104,4 @@
}
} // namespace qos
+} // namespace gem5
diff --git a/src/mem/qos/turnaround_policy_ideal.hh b/src/mem/qos/turnaround_policy_ideal.hh
index 81dbcdb..29548e6 100644
--- a/src/mem/qos/turnaround_policy_ideal.hh
+++ b/src/mem/qos/turnaround_policy_ideal.hh
@@ -41,6 +41,9 @@
#include "base/compiler.hh"
#include "mem/qos/turnaround_policy.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(QoS, qos);
namespace qos
{
@@ -69,5 +72,6 @@
};
} // namespace qos
+} // namespace gem5
#endif /* __MEM_QOS_TURNAROUND_POLICY_IDEAL_HH_ */
diff --git a/src/mem/qport.hh b/src/mem/qport.hh
index a70fbd3..4758f66 100644
--- a/src/mem/qport.hh
+++ b/src/mem/qport.hh
@@ -47,6 +47,9 @@
#include "mem/port.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
/**
* A queued port is a port that has an infinite queue for outgoing
* packets and thus decouples the module that wants to send
@@ -164,4 +167,6 @@
}
};
+} // namespace gem5
+
#endif // __MEM_QPORT_HH__
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 440f415..b61f6cd 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -64,6 +64,9 @@
#include "mem/htm.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
/**
* Special TaskIds that are used for per-context-switch stats dumps
* and Cache Occupancy. Having too many tasks seems to be a problem
@@ -96,7 +99,7 @@
public:
typedef uint64_t FlagsType;
typedef uint8_t ArchFlagsType;
- typedef ::Flags<FlagsType> Flags;
+ typedef gem5::Flags<FlagsType> Flags;
enum : FlagsType
{
@@ -266,7 +269,7 @@
/** @} */
typedef uint64_t CacheCoherenceFlagsType;
- typedef ::Flags<CacheCoherenceFlagsType> CacheCoherenceFlags;
+ typedef gem5::Flags<CacheCoherenceFlagsType> CacheCoherenceFlags;
/**
* These bits are used to set the coherence policy for the GPU and are
@@ -322,7 +325,7 @@
private:
typedef uint16_t PrivateFlagsType;
- typedef ::Flags<PrivateFlagsType> PrivateFlags;
+ typedef gem5::Flags<PrivateFlagsType> PrivateFlags;
enum : PrivateFlagsType
{
@@ -1013,4 +1016,6 @@
/** @} */
};
+} // namespace gem5
+
#endif // __MEM_REQUEST_HH__
diff --git a/src/mem/ruby/common/Address.cc b/src/mem/ruby/common/Address.cc
index fd3c43e..31f5736 100644
--- a/src/mem/ruby/common/Address.cc
+++ b/src/mem/ruby/common/Address.cc
@@ -31,6 +31,9 @@
#include "base/bitfield.hh"
#include "mem/ruby/system/RubySystem.hh"
+namespace gem5
+{
+
Addr
bitSelect(Addr addr, unsigned int small, unsigned int big)
{
@@ -78,3 +81,5 @@
<< makeLineAddress(addr) << std::dec << "]";
return out.str();
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/common/Address.hh b/src/mem/ruby/common/Address.hh
index e5e320f..936c1d2 100644
--- a/src/mem/ruby/common/Address.hh
+++ b/src/mem/ruby/common/Address.hh
@@ -35,6 +35,9 @@
#include "base/types.hh"
+namespace gem5
+{
+
// selects bits inclusive
Addr bitSelect(Addr addr, unsigned int small, unsigned int big);
Addr maskLowOrderBits(Addr addr, unsigned int number);
@@ -44,4 +47,6 @@
Addr makeNextStrideAddress(Addr addr, int stride);
std::string printAddress(Addr addr);
+} // namespace gem5
+
#endif // __MEM_RUBY_COMMON_ADDRESS_HH__
diff --git a/src/mem/ruby/common/BoolVec.cc b/src/mem/ruby/common/BoolVec.cc
index 1c29532..838cf87 100644
--- a/src/mem/ruby/common/BoolVec.cc
+++ b/src/mem/ruby/common/BoolVec.cc
@@ -40,9 +40,14 @@
#include <iostream>
#include <vector>
+namespace gem5
+{
+
std::ostream& operator<<(std::ostream& os, const BoolVec& myvector) {
for (const bool e: myvector) {
os << " " << e;
}
return os;
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/common/BoolVec.hh b/src/mem/ruby/common/BoolVec.hh
index 94b3689..21e2427 100644
--- a/src/mem/ruby/common/BoolVec.hh
+++ b/src/mem/ruby/common/BoolVec.hh
@@ -41,8 +41,13 @@
#include <ostream>
#include <vector>
+namespace gem5
+{
+
typedef std::vector<bool> BoolVec;
std::ostream& operator<<(std::ostream& os, const std::vector<bool>& myvector);
+} // namespace gem5
+
#endif //__MEM_RUBY_COMMON_BOOLVEC_HH__
diff --git a/src/mem/ruby/common/Consumer.cc b/src/mem/ruby/common/Consumer.cc
index fcaa132..9263fc5 100644
--- a/src/mem/ruby/common/Consumer.cc
+++ b/src/mem/ruby/common/Consumer.cc
@@ -40,6 +40,9 @@
#include "mem/ruby/common/Consumer.hh"
+namespace gem5
+{
+
Consumer::Consumer(ClockedObject *_em)
: m_wakeup_event([this]{ processCurrentEvent(); },
"Consumer Event", false),
@@ -88,3 +91,5 @@
wakeup();
scheduleNextWakeup();
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/common/Consumer.hh b/src/mem/ruby/common/Consumer.hh
index 2c7065b..07f153a 100644
--- a/src/mem/ruby/common/Consumer.hh
+++ b/src/mem/ruby/common/Consumer.hh
@@ -52,6 +52,9 @@
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
class Consumer
{
public:
@@ -98,4 +101,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_COMMON_CONSUMER_HH__
diff --git a/src/mem/ruby/common/DataBlock.cc b/src/mem/ruby/common/DataBlock.cc
index 5ce9e52..3e4ae39 100644
--- a/src/mem/ruby/common/DataBlock.cc
+++ b/src/mem/ruby/common/DataBlock.cc
@@ -43,6 +43,9 @@
#include "mem/ruby/common/WriteMask.hh"
#include "mem/ruby/system/RubySystem.hh"
+namespace gem5
+{
+
DataBlock::DataBlock(const DataBlock &cp)
{
m_data = new uint8_t[RubySystem::getBlockSizeBytes()];
@@ -134,3 +137,5 @@
memcpy(m_data, obj.m_data, RubySystem::getBlockSizeBytes());
return *this;
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/common/DataBlock.hh b/src/mem/ruby/common/DataBlock.hh
index 0cb6cef..6363507 100644
--- a/src/mem/ruby/common/DataBlock.hh
+++ b/src/mem/ruby/common/DataBlock.hh
@@ -49,6 +49,9 @@
#include "mem/packet.hh"
+namespace gem5
+{
+
class WriteMask;
class DataBlock
@@ -133,4 +136,6 @@
return obj1.equal(obj2);
}
+} // namespace gem5
+
#endif // __MEM_RUBY_COMMON_DATABLOCK_HH__
diff --git a/src/mem/ruby/common/ExpectedMap.hh b/src/mem/ruby/common/ExpectedMap.hh
index a1889b7..44f19b8 100644
--- a/src/mem/ruby/common/ExpectedMap.hh
+++ b/src/mem/ruby/common/ExpectedMap.hh
@@ -42,6 +42,9 @@
#include <iostream>
#include <unordered_map>
+namespace gem5
+{
+
// ExpectedMap helper class is used to facilitate tracking of pending
// response and data messages in the CHI protocol. It offers additional
// functionality when compared to plain counters:
@@ -228,5 +231,6 @@
return out;
}
+} // namespace gem5
#endif // __MEM_RUBY_COMMON_EXPECTEDMAP_HH__
diff --git a/src/mem/ruby/common/Histogram.cc b/src/mem/ruby/common/Histogram.cc
index 5c7630e..ea8d906 100644
--- a/src/mem/ruby/common/Histogram.cc
+++ b/src/mem/ruby/common/Histogram.cc
@@ -34,6 +34,9 @@
#include "base/intmath.hh"
#include "base/logging.hh"
+namespace gem5
+{
+
Histogram::Histogram(int binsize, uint32_t bins)
{
m_binsize = binsize;
@@ -234,3 +237,5 @@
{
return (n1->size() > n2->size());
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/common/Histogram.hh b/src/mem/ruby/common/Histogram.hh
index f02c4be..c337c6e 100644
--- a/src/mem/ruby/common/Histogram.hh
+++ b/src/mem/ruby/common/Histogram.hh
@@ -34,6 +34,9 @@
#include "mem/ruby/common/TypeDefines.hh"
+namespace gem5
+{
+
class Histogram
{
public:
@@ -83,4 +86,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_COMMON_HISTOGRAM_HH__
diff --git a/src/mem/ruby/common/IntVec.cc b/src/mem/ruby/common/IntVec.cc
index 9003293..326d7f9 100644
--- a/src/mem/ruby/common/IntVec.cc
+++ b/src/mem/ruby/common/IntVec.cc
@@ -36,8 +36,13 @@
#include <ostream>
#include <vector>
+namespace gem5
+{
+
std::ostream& operator<<(std::ostream& os, const IntVec& myvector) {
for (auto& it : myvector)
os << " " << it;
return os;
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/common/IntVec.hh b/src/mem/ruby/common/IntVec.hh
index feec252..482d308 100644
--- a/src/mem/ruby/common/IntVec.hh
+++ b/src/mem/ruby/common/IntVec.hh
@@ -37,8 +37,13 @@
#include <ostream>
#include <vector>
+namespace gem5
+{
+
typedef std::vector<int> IntVec;
std::ostream& operator<<(std::ostream& os, const std::vector<int>& myvector);
+} // namespace gem5
+
#endif //__MEM_RUBY_COMMON_INTVEC_HH__
diff --git a/src/mem/ruby/common/MachineID.hh b/src/mem/ruby/common/MachineID.hh
index 2e12c4b..3e24c9b 100644
--- a/src/mem/ruby/common/MachineID.hh
+++ b/src/mem/ruby/common/MachineID.hh
@@ -47,6 +47,9 @@
#include "base/cprintf.hh"
#include "mem/ruby/protocol/MachineType.hh"
+namespace gem5
+{
+
struct MachineID
{
MachineID() : type(MachineType_NUM), num(0) { }
@@ -81,22 +84,11 @@
return (obj1.type != obj2.type || obj1.num != obj2.num);
}
-namespace std {
- template<>
- struct hash<MachineID>
- {
- inline size_t operator()(const MachineID& id) const {
- size_t hval = MachineType_base_level(id.type) << 16 | id.num;
- return hval;
- }
- };
-}
-
// Output operator declaration
-std::ostream& operator<<(std::ostream& out, const MachineID& obj);
+::std::ostream& operator<<(::std::ostream& out, const MachineID& obj);
-inline std::ostream&
-operator<<(std::ostream& out, const MachineID& obj)
+inline ::std::ostream&
+operator<<(::std::ostream& out, const MachineID& obj)
{
if ((obj.type < MachineType_NUM) && (obj.type >= MachineType_FIRST)) {
out << MachineType_to_string(obj.type);
@@ -105,8 +97,23 @@
}
out << "-";
out << obj.num;
- out << std::flush;
+ out << ::std::flush;
return out;
}
+} // namespace gem5
+
+namespace std
+{
+ template<>
+ struct hash<gem5::MachineID>
+ {
+ inline size_t operator()(const gem5::MachineID& id) const
+ {
+ size_t hval = gem5::MachineType_base_level(id.type) << 16 | id.num;
+ return hval;
+ }
+ };
+} // namespace std
+
#endif // __MEM_RUBY_COMMON_MACHINEID_HH__
diff --git a/src/mem/ruby/common/NetDest.cc b/src/mem/ruby/common/NetDest.cc
index 3a28646..9d8c06c 100644
--- a/src/mem/ruby/common/NetDest.cc
+++ b/src/mem/ruby/common/NetDest.cc
@@ -30,6 +30,9 @@
#include <algorithm>
+namespace gem5
+{
+
NetDest::NetDest()
{
resize();
@@ -278,3 +281,5 @@
}
return true;
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/common/NetDest.hh b/src/mem/ruby/common/NetDest.hh
index 69bfa8a..39eb9ed 100644
--- a/src/mem/ruby/common/NetDest.hh
+++ b/src/mem/ruby/common/NetDest.hh
@@ -35,6 +35,9 @@
#include "mem/ruby/common/Set.hh"
#include "mem/ruby/common/MachineID.hh"
+namespace gem5
+{
+
// NetDest specifies the network destination of a Message
class NetDest
{
@@ -116,4 +119,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_COMMON_NETDEST_HH__
diff --git a/src/mem/ruby/common/Set.hh b/src/mem/ruby/common/Set.hh
index aba38f5..fb501f0 100644
--- a/src/mem/ruby/common/Set.hh
+++ b/src/mem/ruby/common/Set.hh
@@ -39,6 +39,9 @@
#include "base/logging.hh"
#include "mem/ruby/common/TypeDefines.hh"
+namespace gem5
+{
+
class Set
{
private:
@@ -226,4 +229,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_COMMON_SET_HH__
diff --git a/src/mem/ruby/common/SubBlock.cc b/src/mem/ruby/common/SubBlock.cc
index e889a55..36d970a 100644
--- a/src/mem/ruby/common/SubBlock.cc
+++ b/src/mem/ruby/common/SubBlock.cc
@@ -30,7 +30,10 @@
#include "base/stl_helpers.hh"
-using gem5::stl_helpers::operator<<;
+namespace gem5
+{
+
+using stl_helpers::operator<<;
SubBlock::SubBlock(Addr addr, int size)
{
@@ -70,5 +73,4 @@
out << "[" << m_address << ", " << getSize() << ", " << m_data << "]";
}
-
-
+} // namespace gem5
diff --git a/src/mem/ruby/common/SubBlock.hh b/src/mem/ruby/common/SubBlock.hh
index ad1d68a..b340973 100644
--- a/src/mem/ruby/common/SubBlock.hh
+++ b/src/mem/ruby/common/SubBlock.hh
@@ -35,6 +35,9 @@
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/DataBlock.hh"
+namespace gem5
+{
+
class SubBlock
{
public:
@@ -78,4 +81,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_COMMON_SUBBLOCK_HH__
diff --git a/src/mem/ruby/common/TriggerQueue.hh b/src/mem/ruby/common/TriggerQueue.hh
index 0f6482e..e1d9891 100644
--- a/src/mem/ruby/common/TriggerQueue.hh
+++ b/src/mem/ruby/common/TriggerQueue.hh
@@ -41,6 +41,9 @@
#include <deque>
#include <iostream>
+namespace gem5
+{
+
// TriggerQueue helper class is used keep a list of events that trigger the
// actions that need to be executed before an ouststanding transaction
// completes in the CHI protocol. When a transaction no longer has pending
@@ -123,4 +126,6 @@
{
}
+} // namespace gem5
+
#endif // __MEM_RUBY_COMMON_QUEUE_HH__
diff --git a/src/mem/ruby/common/TypeDefines.hh b/src/mem/ruby/common/TypeDefines.hh
index 90be1c6..6e6c260 100644
--- a/src/mem/ruby/common/TypeDefines.hh
+++ b/src/mem/ruby/common/TypeDefines.hh
@@ -30,8 +30,13 @@
#ifndef __MEM_RUBY_COMMON_TYPEDEFINES_HH__
#define __MEM_RUBY_COMMON_TYPEDEFINES_HH__
+namespace gem5
+{
+
typedef unsigned int LinkID;
typedef unsigned int NodeID;
typedef unsigned int SwitchID;
+} // namespace gem5
+
#endif //__MEM_RUBY_COMMON_TYPEDEFINES_HH__
diff --git a/src/mem/ruby/common/WriteMask.cc b/src/mem/ruby/common/WriteMask.cc
index 54ba8ff..a3fb8bc 100644
--- a/src/mem/ruby/common/WriteMask.cc
+++ b/src/mem/ruby/common/WriteMask.cc
@@ -32,6 +32,9 @@
#include "mem/ruby/system/RubySystem.hh"
+namespace gem5
+{
+
WriteMask::WriteMask()
: mSize(RubySystem::getBlockSizeBytes()), mMask(mSize, false),
mAtomic(false)
@@ -49,3 +52,4 @@
<< std::flush;
}
+} // namespace gem5
diff --git a/src/mem/ruby/common/WriteMask.hh b/src/mem/ruby/common/WriteMask.hh
index 1cb3f46..4d38201 100644
--- a/src/mem/ruby/common/WriteMask.hh
+++ b/src/mem/ruby/common/WriteMask.hh
@@ -50,6 +50,9 @@
#include "mem/ruby/common/DataBlock.hh"
#include "mem/ruby/common/TypeDefines.hh"
+namespace gem5
+{
+
class WriteMask
{
public:
@@ -265,4 +268,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_COMMON_WRITEMASK_HH__
diff --git a/src/mem/ruby/network/BasicLink.cc b/src/mem/ruby/network/BasicLink.cc
index 613b6ed..7e291ad 100644
--- a/src/mem/ruby/network/BasicLink.cc
+++ b/src/mem/ruby/network/BasicLink.cc
@@ -28,6 +28,9 @@
#include "mem/ruby/network/BasicLink.hh"
+namespace gem5
+{
+
BasicLink::BasicLink(const Params &p)
: SimObject(p)
{
@@ -57,3 +60,5 @@
: BasicLink(p)
{
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/BasicLink.hh b/src/mem/ruby/network/BasicLink.hh
index f59f95a..1900757 100644
--- a/src/mem/ruby/network/BasicLink.hh
+++ b/src/mem/ruby/network/BasicLink.hh
@@ -40,6 +40,9 @@
#include "params/BasicLink.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class Topology;
class BasicLink : public SimObject
@@ -84,4 +87,6 @@
friend class Topology;
};
+} // namespace gem5
+
#endif //__MEM_RUBY_NETWORK_BASICLINK_HH__
diff --git a/src/mem/ruby/network/BasicLink.py b/src/mem/ruby/network/BasicLink.py
index 9d6a7bb..b3d9df5 100644
--- a/src/mem/ruby/network/BasicLink.py
+++ b/src/mem/ruby/network/BasicLink.py
@@ -30,6 +30,8 @@
class BasicLink(SimObject):
type = 'BasicLink'
cxx_header = "mem/ruby/network/BasicLink.hh"
+ cxx_class = 'gem5::BasicLink'
+
link_id = Param.Int("ID in relation to other links")
latency = Param.Cycles(1, "latency")
# Width of the link in bytes
@@ -42,6 +44,8 @@
class BasicExtLink(BasicLink):
type = 'BasicExtLink'
cxx_header = "mem/ruby/network/BasicLink.hh"
+ cxx_class = 'gem5::BasicExtLink'
+
ext_node = Param.RubyController("External node")
int_node = Param.BasicRouter("ID of internal node")
bandwidth_factor = 16 # only used by simple network
@@ -49,6 +53,8 @@
class BasicIntLink(BasicLink):
type = 'BasicIntLink'
cxx_header = "mem/ruby/network/BasicLink.hh"
+ cxx_class = 'gem5::BasicIntLink'
+
src_node = Param.BasicRouter("Router on src end")
dst_node = Param.BasicRouter("Router on dst end")
diff --git a/src/mem/ruby/network/BasicRouter.cc b/src/mem/ruby/network/BasicRouter.cc
index 8895ae8..7227450 100644
--- a/src/mem/ruby/network/BasicRouter.cc
+++ b/src/mem/ruby/network/BasicRouter.cc
@@ -28,6 +28,9 @@
#include "mem/ruby/network/BasicRouter.hh"
+namespace gem5
+{
+
BasicRouter::BasicRouter(const Params &p)
: ClockedObject(p)
{
@@ -45,3 +48,5 @@
{
out << name();
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/BasicRouter.hh b/src/mem/ruby/network/BasicRouter.hh
index 9417342..3aa9a74 100644
--- a/src/mem/ruby/network/BasicRouter.hh
+++ b/src/mem/ruby/network/BasicRouter.hh
@@ -36,6 +36,9 @@
#include "params/BasicRouter.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
class BasicRouter : public ClockedObject
{
public:
@@ -61,4 +64,6 @@
return out;
}
+} // namespace gem5
+
#endif //__MEM_RUBY_NETWORK_BASICROUTER_HH__
diff --git a/src/mem/ruby/network/BasicRouter.py b/src/mem/ruby/network/BasicRouter.py
index 74bbaac..a16bb91 100644
--- a/src/mem/ruby/network/BasicRouter.py
+++ b/src/mem/ruby/network/BasicRouter.py
@@ -31,6 +31,8 @@
class BasicRouter(ClockedObject):
type = 'BasicRouter'
cxx_header = "mem/ruby/network/BasicRouter.hh"
+ cxx_class = 'gem5::BasicRouter'
+
router_id = Param.Int("ID in relation to other routers")
# only used by garnet
diff --git a/src/mem/ruby/network/MessageBuffer.cc b/src/mem/ruby/network/MessageBuffer.cc
index 6642fbc..24ee693 100644
--- a/src/mem/ruby/network/MessageBuffer.cc
+++ b/src/mem/ruby/network/MessageBuffer.cc
@@ -49,7 +49,10 @@
#include "debug/RubyQueue.hh"
#include "mem/ruby/system/RubySystem.hh"
-using gem5::stl_helpers::operator<<;
+namespace gem5
+{
+
+using stl_helpers::operator<<;
MessageBuffer::MessageBuffer(const Params &p)
: SimObject(p), m_stall_map_size(0),
@@ -526,3 +529,5 @@
return num_functional_accesses;
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/MessageBuffer.hh b/src/mem/ruby/network/MessageBuffer.hh
index e2d38512..5dc731e 100644
--- a/src/mem/ruby/network/MessageBuffer.hh
+++ b/src/mem/ruby/network/MessageBuffer.hh
@@ -65,6 +65,9 @@
#include "params/MessageBuffer.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class MessageBuffer : public SimObject
{
public:
@@ -274,4 +277,6 @@
return out;
}
+} // namespace gem5
+
#endif //__MEM_RUBY_NETWORK_MESSAGEBUFFER_HH__
diff --git a/src/mem/ruby/network/MessageBuffer.py b/src/mem/ruby/network/MessageBuffer.py
index 807ffb4..d25b7db 100644
--- a/src/mem/ruby/network/MessageBuffer.py
+++ b/src/mem/ruby/network/MessageBuffer.py
@@ -49,8 +49,9 @@
class MessageBuffer(SimObject):
type = 'MessageBuffer'
- cxx_class = 'MessageBuffer'
+ cxx_class = 'gem5::MessageBuffer'
cxx_header = "mem/ruby/network/MessageBuffer.hh"
+
ordered = Param.Bool(False, "Whether the buffer is ordered")
buffer_size = Param.Unsigned(0, "Maximum number of entries to buffer \
(0 allows infinite entries)")
diff --git a/src/mem/ruby/network/Network.cc b/src/mem/ruby/network/Network.cc
index 58b8ac1..bf0af62 100644
--- a/src/mem/ruby/network/Network.cc
+++ b/src/mem/ruby/network/Network.cc
@@ -45,6 +45,9 @@
#include "mem/ruby/network/BasicLink.hh"
#include "mem/ruby/system/RubySystem.hh"
+namespace gem5
+{
+
uint32_t Network::m_virtual_networks;
uint32_t Network::m_control_msg_size;
uint32_t Network::m_data_msg_size;
@@ -249,3 +252,5 @@
assert(globalToLocalMap.count(global_id));
return globalToLocalMap.at(global_id);
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/Network.hh b/src/mem/ruby/network/Network.hh
index 23e3e9a..3534564 100644
--- a/src/mem/ruby/network/Network.hh
+++ b/src/mem/ruby/network/Network.hh
@@ -70,6 +70,9 @@
#include "params/RubyNetwork.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
class NetDest;
class MessageBuffer;
@@ -180,4 +183,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_NETWORK_NETWORK_HH__
diff --git a/src/mem/ruby/network/Network.py b/src/mem/ruby/network/Network.py
index 5febaad..344ddae 100644
--- a/src/mem/ruby/network/Network.py
+++ b/src/mem/ruby/network/Network.py
@@ -31,9 +31,10 @@
class RubyNetwork(ClockedObject):
type = 'RubyNetwork'
- cxx_class = 'Network'
+ cxx_class = 'gem5::Network'
cxx_header = "mem/ruby/network/Network.hh"
abstract = True
+
topology = Param.String("Not Specified",
"the name of the imported topology module")
diff --git a/src/mem/ruby/network/Topology.cc b/src/mem/ruby/network/Topology.cc
index 9216f6f..639006c 100644
--- a/src/mem/ruby/network/Topology.cc
+++ b/src/mem/ruby/network/Topology.cc
@@ -38,6 +38,9 @@
#include "mem/ruby/network/Network.hh"
#include "mem/ruby/slicc_interface/AbstractController.hh"
+namespace gem5
+{
+
const int INFINITE_LATENCY = 10000; // Yes, this is a big hack
// Note: In this file, we use the first 2*m_nodes SwitchIDs to
@@ -439,3 +442,5 @@
return result;
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/Topology.hh b/src/mem/ruby/network/Topology.hh
index 40b8a86..8d9574e 100644
--- a/src/mem/ruby/network/Topology.hh
+++ b/src/mem/ruby/network/Topology.hh
@@ -49,6 +49,9 @@
#include "mem/ruby/network/BasicLink.hh"
#include "mem/ruby/protocol/LinkDirection.hh"
+namespace gem5
+{
+
class NetDest;
class Network;
@@ -122,4 +125,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_NETWORK_TOPOLOGY_HH__
diff --git a/src/mem/ruby/network/dummy_port.hh b/src/mem/ruby/network/dummy_port.hh
index 0d02635..cf14924 100644
--- a/src/mem/ruby/network/dummy_port.hh
+++ b/src/mem/ruby/network/dummy_port.hh
@@ -30,6 +30,9 @@
#include "mem/port.hh"
+namespace gem5
+{
+
class RubyDummyPort : public Port
{
public:
@@ -54,4 +57,6 @@
}
};
+} // namespace gem5
+
#endif //__MEM_RUBY_NETWORK_DUMMY_PORT_HH__
diff --git a/src/mem/ruby/network/fault_model/FaultModel.cc b/src/mem/ruby/network/fault_model/FaultModel.cc
index 38ca76b..8fab5f0 100644
--- a/src/mem/ruby/network/fault_model/FaultModel.cc
+++ b/src/mem/ruby/network/fault_model/FaultModel.cc
@@ -47,6 +47,8 @@
#define MAX(a,b) ((a > b) ? (a) : (b))
+namespace gem5
+{
FaultModel::FaultModel(const Params &p) : SimObject(p)
{
@@ -266,3 +268,5 @@
std::cout << "\n";
}
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/fault_model/FaultModel.hh b/src/mem/ruby/network/fault_model/FaultModel.hh
index 42759ad..0cb0ab4 100644
--- a/src/mem/ruby/network/fault_model/FaultModel.hh
+++ b/src/mem/ruby/network/fault_model/FaultModel.hh
@@ -50,6 +50,9 @@
#include "params/FaultModel.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class FaultModel : public SimObject
{
public:
@@ -135,4 +138,6 @@
std::vector <int> temperature_weights;
};
+} // namespace gem5
+
#endif //__MEM_RUBY_NETWORK_FAULT_MODEL_FAULTMODEL_HH__
diff --git a/src/mem/ruby/network/fault_model/FaultModel.py b/src/mem/ruby/network/fault_model/FaultModel.py
index 7064817..e49f986 100644
--- a/src/mem/ruby/network/fault_model/FaultModel.py
+++ b/src/mem/ruby/network/fault_model/FaultModel.py
@@ -36,7 +36,7 @@
class FaultModel(SimObject):
type = 'FaultModel'
- cxx_class = 'FaultModel'
+ cxx_class = 'gem5::FaultModel'
cxx_header = "mem/ruby/network/fault_model/FaultModel.hh"
baseline_fault_vector_database = VectorParam.Float([
diff --git a/src/mem/ruby/network/garnet/CommonTypes.hh b/src/mem/ruby/network/garnet/CommonTypes.hh
index affbccc..c0d8af2 100644
--- a/src/mem/ruby/network/garnet/CommonTypes.hh
+++ b/src/mem/ruby/network/garnet/CommonTypes.hh
@@ -33,6 +33,9 @@
#include "mem/ruby/common/NetDest.hh"
+namespace gem5
+{
+
// All common enums and typedefs go here
enum flit_type {HEAD_, BODY_, TAIL_, HEAD_TAIL_,
@@ -65,4 +68,6 @@
#define INFINITE_ 10000
+} // namespace gem5
+
#endif //__MEM_RUBY_NETWORK_GARNET_0_COMMONTYPES_HH__
diff --git a/src/mem/ruby/network/garnet/Credit.cc b/src/mem/ruby/network/garnet/Credit.cc
index b24003f..5624005 100644
--- a/src/mem/ruby/network/garnet/Credit.cc
+++ b/src/mem/ruby/network/garnet/Credit.cc
@@ -32,6 +32,9 @@
#include "base/trace.hh"
#include "debug/RubyNetwork.hh"
+namespace gem5
+{
+
// Credit Signal for buffers inside VC
// Carries m_vc (inherits from flit.hh)
// and m_is_free_signal (whether VC is free or not)
@@ -80,5 +83,4 @@
out << "]";
}
-
-
+} // namespace gem5
diff --git a/src/mem/ruby/network/garnet/Credit.hh b/src/mem/ruby/network/garnet/Credit.hh
index db5823c..2db47d0 100644
--- a/src/mem/ruby/network/garnet/Credit.hh
+++ b/src/mem/ruby/network/garnet/Credit.hh
@@ -38,6 +38,9 @@
#include "mem/ruby/network/garnet/CommonTypes.hh"
#include "mem/ruby/network/garnet/flit.hh"
+namespace gem5
+{
+
// Credit Signal for buffers inside VC
// Carries m_vc (inherits from flit.hh)
// and m_is_free_signal (whether VC is free or not)
@@ -61,4 +64,6 @@
bool m_is_free_signal;
};
+} // namespace gem5
+
#endif // __MEM_RUBY_NETWORK_GARNET_0_CREDIT_HH__
diff --git a/src/mem/ruby/network/garnet/CreditLink.hh b/src/mem/ruby/network/garnet/CreditLink.hh
index 998a004..96842dc 100644
--- a/src/mem/ruby/network/garnet/CreditLink.hh
+++ b/src/mem/ruby/network/garnet/CreditLink.hh
@@ -34,6 +34,9 @@
#include "mem/ruby/network/garnet/NetworkLink.hh"
#include "params/CreditLink.hh"
+namespace gem5
+{
+
class CreditLink : public NetworkLink
{
public:
@@ -41,4 +44,6 @@
CreditLink(const Params &p) : NetworkLink(p) {}
};
+} // namespace gem5
+
#endif // __MEM_RUBY_NETWORK_GARNET_0_CREDITLINK_HH__
diff --git a/src/mem/ruby/network/garnet/CrossbarSwitch.cc b/src/mem/ruby/network/garnet/CrossbarSwitch.cc
index 6b158df..2e6c29d 100644
--- a/src/mem/ruby/network/garnet/CrossbarSwitch.cc
+++ b/src/mem/ruby/network/garnet/CrossbarSwitch.cc
@@ -35,6 +35,9 @@
#include "mem/ruby/network/garnet/OutputUnit.hh"
#include "mem/ruby/network/garnet/Router.hh"
+namespace gem5
+{
+
CrossbarSwitch::CrossbarSwitch(Router *router)
: Consumer(router), m_router(router), m_num_vcs(m_router->get_num_vcs()),
m_crossbar_activity(0), switchBuffers(0)
@@ -99,3 +102,5 @@
{
m_crossbar_activity = 0;
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/garnet/CrossbarSwitch.hh b/src/mem/ruby/network/garnet/CrossbarSwitch.hh
index ee3a5ec..6eefe40 100644
--- a/src/mem/ruby/network/garnet/CrossbarSwitch.hh
+++ b/src/mem/ruby/network/garnet/CrossbarSwitch.hh
@@ -39,6 +39,9 @@
#include "mem/ruby/network/garnet/CommonTypes.hh"
#include "mem/ruby/network/garnet/flitBuffer.hh"
+namespace gem5
+{
+
class Router;
class CrossbarSwitch : public Consumer
@@ -68,4 +71,6 @@
std::vector<flitBuffer> switchBuffers;
};
+} // namespace gem5
+
#endif // __MEM_RUBY_NETWORK_GARNET_0_CROSSBARSWITCH_HH__
diff --git a/src/mem/ruby/network/garnet/GarnetLink.cc b/src/mem/ruby/network/garnet/GarnetLink.cc
index 42dc394..1606814 100644
--- a/src/mem/ruby/network/garnet/GarnetLink.cc
+++ b/src/mem/ruby/network/garnet/GarnetLink.cc
@@ -35,6 +35,9 @@
#include "mem/ruby/network/garnet/NetworkBridge.hh"
#include "mem/ruby/network/garnet/NetworkLink.hh"
+namespace gem5
+{
+
GarnetIntLink::GarnetIntLink(const Params &p)
: BasicIntLink(p)
{
@@ -153,3 +156,5 @@
{
out << name();
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/garnet/GarnetLink.hh b/src/mem/ruby/network/garnet/GarnetLink.hh
index 6abecd0..300479a 100644
--- a/src/mem/ruby/network/garnet/GarnetLink.hh
+++ b/src/mem/ruby/network/garnet/GarnetLink.hh
@@ -42,6 +42,9 @@
#include "params/GarnetExtLink.hh"
#include "params/GarnetIntLink.hh"
+namespace gem5
+{
+
class GarnetIntLink : public BasicIntLink
{
public:
@@ -123,4 +126,6 @@
return out;
}
+} // namespace gem5
+
#endif //__MEM_RUBY_NETWORK_GARNET_0_GARNETLINK_HH__
diff --git a/src/mem/ruby/network/garnet/GarnetLink.py b/src/mem/ruby/network/garnet/GarnetLink.py
index 45350b5..af3320e 100644
--- a/src/mem/ruby/network/garnet/GarnetLink.py
+++ b/src/mem/ruby/network/garnet/GarnetLink.py
@@ -38,6 +38,8 @@
class NetworkLink(ClockedObject):
type = 'NetworkLink'
cxx_header = "mem/ruby/network/garnet/NetworkLink.hh"
+ cxx_class = 'gem5::NetworkLink'
+
link_id = Param.Int(Parent.link_id, "link id")
link_latency = Param.Cycles(Parent.latency, "link latency")
vcs_per_vnet = Param.Int(Parent.vcs_per_vnet,
@@ -51,10 +53,13 @@
class CreditLink(NetworkLink):
type = 'CreditLink'
cxx_header = "mem/ruby/network/garnet/CreditLink.hh"
+ cxx_class = 'gem5::CreditLink'
class NetworkBridge(CreditLink):
type = 'NetworkBridge'
cxx_header = "mem/ruby/network/garnet/NetworkBridge.hh"
+ cxx_class = 'gem5::NetworkBridge'
+
link = Param.NetworkLink("Associated Network Link")
vtype = Param.CDCType('LINK_OBJECT',
"Direction of CDC LINK->OBJECT or OBJECT->LINK")
@@ -65,6 +70,8 @@
class GarnetIntLink(BasicIntLink):
type = 'GarnetIntLink'
cxx_header = "mem/ruby/network/garnet/GarnetLink.hh"
+ cxx_class = 'gem5::GarnetIntLink'
+
# The internal link includes one forward link (for flit)
# and one backward flow-control link (for credit)
network_link = Param.NetworkLink(NetworkLink(), "forward link")
@@ -102,6 +109,8 @@
class GarnetExtLink(BasicExtLink):
type = 'GarnetExtLink'
cxx_header = "mem/ruby/network/garnet/GarnetLink.hh"
+ cxx_class = 'gem5::GarnetExtLink'
+
# The external link is bi-directional.
# It includes two forward links (for flits)
# and two backward flow-control links (for credits),
diff --git a/src/mem/ruby/network/garnet/GarnetNetwork.cc b/src/mem/ruby/network/garnet/GarnetNetwork.cc
index d7a761c..13d841d 100644
--- a/src/mem/ruby/network/garnet/GarnetNetwork.cc
+++ b/src/mem/ruby/network/garnet/GarnetNetwork.cc
@@ -46,6 +46,9 @@
#include "mem/ruby/network/garnet/Router.hh"
#include "mem/ruby/system/RubySystem.hh"
+namespace gem5
+{
+
/*
* GarnetNetwork sets up the routers and links and collects stats.
* Default parameters (GarnetNetwork.py) can be overwritten from command line
@@ -613,3 +616,5 @@
return num_functional_writes;
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/garnet/GarnetNetwork.hh b/src/mem/ruby/network/garnet/GarnetNetwork.hh
index 3f6ebd9..65a7eb6 100644
--- a/src/mem/ruby/network/garnet/GarnetNetwork.hh
+++ b/src/mem/ruby/network/garnet/GarnetNetwork.hh
@@ -40,6 +40,9 @@
#include "mem/ruby/network/garnet/CommonTypes.hh"
#include "params/GarnetNetwork.hh"
+namespace gem5
+{
+
class FaultModel;
class NetworkInterface;
class Router;
@@ -209,4 +212,6 @@
return out;
}
+} // namespace gem5
+
#endif //__MEM_RUBY_NETWORK_GARNET_0_GARNETNETWORK_HH__
diff --git a/src/mem/ruby/network/garnet/GarnetNetwork.py b/src/mem/ruby/network/garnet/GarnetNetwork.py
index d7a3f0d..749fdb9 100644
--- a/src/mem/ruby/network/garnet/GarnetNetwork.py
+++ b/src/mem/ruby/network/garnet/GarnetNetwork.py
@@ -37,6 +37,8 @@
class GarnetNetwork(RubyNetwork):
type = 'GarnetNetwork'
cxx_header = "mem/ruby/network/garnet/GarnetNetwork.hh"
+ cxx_class = 'gem5::GarnetNetwork'
+
num_rows = Param.Int(0, "number of rows if 2D (mesh/torus/..) topology");
ni_flit_size = Param.UInt32(16, "network interface flit size in bytes")
vcs_per_vnet = Param.UInt32(4, "virtual channels per virtual network");
@@ -51,7 +53,7 @@
class GarnetNetworkInterface(ClockedObject):
type = 'GarnetNetworkInterface'
- cxx_class = 'NetworkInterface'
+ cxx_class = 'gem5::NetworkInterface'
cxx_header = "mem/ruby/network/garnet/NetworkInterface.hh"
id = Param.UInt32("ID in relation to other network interfaces")
@@ -64,7 +66,7 @@
class GarnetRouter(BasicRouter):
type = 'GarnetRouter'
- cxx_class = 'Router'
+ cxx_class = 'gem5::Router'
cxx_header = "mem/ruby/network/garnet/Router.hh"
vcs_per_vnet = Param.UInt32(Parent.vcs_per_vnet,
"virtual channels per virtual network")
diff --git a/src/mem/ruby/network/garnet/InputUnit.cc b/src/mem/ruby/network/garnet/InputUnit.cc
index acb5f4d..aa3128c 100644
--- a/src/mem/ruby/network/garnet/InputUnit.cc
+++ b/src/mem/ruby/network/garnet/InputUnit.cc
@@ -35,6 +35,9 @@
#include "mem/ruby/network/garnet/Credit.hh"
#include "mem/ruby/network/garnet/Router.hh"
+namespace gem5
+{
+
InputUnit::InputUnit(int id, PortDirection direction, Router *router)
: Consumer(router), m_router(router), m_id(id), m_direction(direction),
m_vc_per_vnet(m_router->get_vc_per_vnet())
@@ -162,3 +165,5 @@
m_num_buffer_writes[j] = 0;
}
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/garnet/InputUnit.hh b/src/mem/ruby/network/garnet/InputUnit.hh
index e57f0be..e418840 100644
--- a/src/mem/ruby/network/garnet/InputUnit.hh
+++ b/src/mem/ruby/network/garnet/InputUnit.hh
@@ -43,6 +43,9 @@
#include "mem/ruby/network/garnet/VirtualChannel.hh"
#include "mem/ruby/network/garnet/flitBuffer.hh"
+namespace gem5
+{
+
class InputUnit : public Consumer
{
public:
@@ -163,4 +166,6 @@
std::vector<double> m_num_buffer_reads;
};
+} // namespace gem5
+
#endif // __MEM_RUBY_NETWORK_GARNET_0_INPUTUNIT_HH__
diff --git a/src/mem/ruby/network/garnet/NetworkBridge.cc b/src/mem/ruby/network/garnet/NetworkBridge.cc
index 22fb229..73261d2 100644
--- a/src/mem/ruby/network/garnet/NetworkBridge.cc
+++ b/src/mem/ruby/network/garnet/NetworkBridge.cc
@@ -39,6 +39,9 @@
#include "debug/RubyNetwork.hh"
#include "params/GarnetIntLink.hh"
+namespace gem5
+{
+
NetworkBridge::NetworkBridge(const Params &p)
:CreditLink(p)
{
@@ -264,3 +267,5 @@
scheduleEvent(Cycles(1));
}
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/garnet/NetworkBridge.hh b/src/mem/ruby/network/garnet/NetworkBridge.hh
index 14ae22d..42435cb 100644
--- a/src/mem/ruby/network/garnet/NetworkBridge.hh
+++ b/src/mem/ruby/network/garnet/NetworkBridge.hh
@@ -46,6 +46,9 @@
#include "mem/ruby/network/garnet/flitBuffer.hh"
#include "params/NetworkBridge.hh"
+namespace gem5
+{
+
class GarnetNetwork;
class NetworkBridge: public CreditLink
@@ -95,4 +98,6 @@
};
+} // namespace gem5
+
#endif // __MEM_RUBY_NETWORK_GARNET_0_NETWORK_BRIDGE_HH__
diff --git a/src/mem/ruby/network/garnet/NetworkInterface.cc b/src/mem/ruby/network/garnet/NetworkInterface.cc
index 5c0216a..5190c9d 100644
--- a/src/mem/ruby/network/garnet/NetworkInterface.cc
+++ b/src/mem/ruby/network/garnet/NetworkInterface.cc
@@ -42,6 +42,9 @@
#include "mem/ruby/network/garnet/flitBuffer.hh"
#include "mem/ruby/slicc_interface/Message.hh"
+namespace gem5
+{
+
NetworkInterface::NetworkInterface(const Params &p)
: ClockedObject(p), Consumer(this), m_id(p.id),
m_virtual_networks(p.virt_nets), m_vc_per_vnet(0),
@@ -670,3 +673,5 @@
}
return num_functional_writes;
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/garnet/NetworkInterface.hh b/src/mem/ruby/network/garnet/NetworkInterface.hh
index 51347cc..15becbd 100644
--- a/src/mem/ruby/network/garnet/NetworkInterface.hh
+++ b/src/mem/ruby/network/garnet/NetworkInterface.hh
@@ -46,6 +46,9 @@
#include "mem/ruby/slicc_interface/Message.hh"
#include "params/GarnetNetworkInterface.hh"
+namespace gem5
+{
+
class MessageBuffer;
class flitBuffer;
@@ -297,4 +300,6 @@
OutputPort *getOutportForVnet(int vnet);
};
+} // namespace gem5
+
#endif // __MEM_RUBY_NETWORK_GARNET_0_NETWORKINTERFACE_HH__
diff --git a/src/mem/ruby/network/garnet/NetworkLink.cc b/src/mem/ruby/network/garnet/NetworkLink.cc
index 8634e7d..4145ea4 100644
--- a/src/mem/ruby/network/garnet/NetworkLink.cc
+++ b/src/mem/ruby/network/garnet/NetworkLink.cc
@@ -36,6 +36,9 @@
#include "debug/RubyNetwork.hh"
#include "mem/ruby/network/garnet/CreditLink.hh"
+namespace gem5
+{
+
NetworkLink::NetworkLink(const Params &p)
: ClockedObject(p), Consumer(this), m_id(p.link_id),
m_type(NUM_LINK_TYPES_),
@@ -115,3 +118,5 @@
{
return linkBuffer.functionalWrite(pkt);
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/garnet/NetworkLink.hh b/src/mem/ruby/network/garnet/NetworkLink.hh
index 20e0904..5fc8a58 100644
--- a/src/mem/ruby/network/garnet/NetworkLink.hh
+++ b/src/mem/ruby/network/garnet/NetworkLink.hh
@@ -42,6 +42,9 @@
#include "params/NetworkLink.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
class GarnetNetwork;
class NetworkLink : public ClockedObject, public Consumer
@@ -97,4 +100,6 @@
};
+} // namespace gem5
+
#endif // __MEM_RUBY_NETWORK_GARNET_0_NETWORKLINK_HH__
diff --git a/src/mem/ruby/network/garnet/OutVcState.cc b/src/mem/ruby/network/garnet/OutVcState.cc
index 1bb8698..88ae9ef 100644
--- a/src/mem/ruby/network/garnet/OutVcState.cc
+++ b/src/mem/ruby/network/garnet/OutVcState.cc
@@ -32,6 +32,9 @@
#include "mem/ruby/system/RubySystem.hh"
+namespace gem5
+{
+
OutVcState::OutVcState(int id, GarnetNetwork *network_ptr,
uint32_t consumerVcs)
: m_time(0)
@@ -67,3 +70,5 @@
m_credit_count--;
assert(m_credit_count >= 0);
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/garnet/OutVcState.hh b/src/mem/ruby/network/garnet/OutVcState.hh
index c78af08..f8c36da 100644
--- a/src/mem/ruby/network/garnet/OutVcState.hh
+++ b/src/mem/ruby/network/garnet/OutVcState.hh
@@ -34,6 +34,9 @@
#include "mem/ruby/network/garnet/CommonTypes.hh"
#include "mem/ruby/network/garnet/GarnetNetwork.hh"
+namespace gem5
+{
+
class OutVcState
{
public:
@@ -64,4 +67,6 @@
int m_max_credit_count;
};
+} // namespace gem5
+
#endif //__MEM_RUBY_NETWORK_GARNET_0_OUTVCSTATE_HH__
diff --git a/src/mem/ruby/network/garnet/OutputUnit.cc b/src/mem/ruby/network/garnet/OutputUnit.cc
index ac9673c..f903f5b 100644
--- a/src/mem/ruby/network/garnet/OutputUnit.cc
+++ b/src/mem/ruby/network/garnet/OutputUnit.cc
@@ -37,6 +37,9 @@
#include "mem/ruby/network/garnet/Router.hh"
#include "mem/ruby/network/garnet/flitBuffer.hh"
+namespace gem5
+{
+
OutputUnit::OutputUnit(int id, PortDirection direction, Router *router,
uint32_t consumerVcs)
: Consumer(router), m_router(router), m_id(id), m_direction(direction),
@@ -168,3 +171,5 @@
{
return outBuffer.functionalWrite(pkt);
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/garnet/OutputUnit.hh b/src/mem/ruby/network/garnet/OutputUnit.hh
index fe7f889..16c686b 100644
--- a/src/mem/ruby/network/garnet/OutputUnit.hh
+++ b/src/mem/ruby/network/garnet/OutputUnit.hh
@@ -41,6 +41,9 @@
#include "mem/ruby/network/garnet/NetworkLink.hh"
#include "mem/ruby/network/garnet/OutVcState.hh"
+namespace gem5
+{
+
class CreditLink;
class Router;
@@ -111,4 +114,6 @@
std::vector<OutVcState> outVcState;
};
+} // namespace gem5
+
#endif // __MEM_RUBY_NETWORK_GARNET_0_OUTPUTUNIT_HH__
diff --git a/src/mem/ruby/network/garnet/Router.cc b/src/mem/ruby/network/garnet/Router.cc
index 3295989..8fa20aa 100644
--- a/src/mem/ruby/network/garnet/Router.cc
+++ b/src/mem/ruby/network/garnet/Router.cc
@@ -39,6 +39,9 @@
#include "mem/ruby/network/garnet/NetworkLink.hh"
#include "mem/ruby/network/garnet/OutputUnit.hh"
+namespace gem5
+{
+
Router::Router(const Params &p)
: BasicRouter(p), Consumer(this), m_latency(p.latency),
m_virtual_networks(p.virt_nets), m_vc_per_vnet(p.vcs_per_vnet),
@@ -281,3 +284,5 @@
return num_functional_writes;
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/garnet/Router.hh b/src/mem/ruby/network/garnet/Router.hh
index b93da6f..fb63611 100644
--- a/src/mem/ruby/network/garnet/Router.hh
+++ b/src/mem/ruby/network/garnet/Router.hh
@@ -47,6 +47,9 @@
#include "mem/ruby/network/garnet/flit.hh"
#include "params/GarnetRouter.hh"
+namespace gem5
+{
+
class NetworkLink;
class CreditLink;
class InputUnit;
@@ -154,4 +157,6 @@
statistics::Scalar m_crossbar_activity;
};
+} // namespace gem5
+
#endif // __MEM_RUBY_NETWORK_GARNET_0_ROUTER_HH__
diff --git a/src/mem/ruby/network/garnet/RoutingUnit.cc b/src/mem/ruby/network/garnet/RoutingUnit.cc
index 5cee6b5..a850c2d 100644
--- a/src/mem/ruby/network/garnet/RoutingUnit.cc
+++ b/src/mem/ruby/network/garnet/RoutingUnit.cc
@@ -37,6 +37,9 @@
#include "mem/ruby/network/garnet/Router.hh"
#include "mem/ruby/slicc_interface/Message.hh"
+namespace gem5
+{
+
RoutingUnit::RoutingUnit(Router *router)
{
m_router = router;
@@ -260,3 +263,5 @@
{
panic("%s placeholder executed", __FUNCTION__);
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/garnet/RoutingUnit.hh b/src/mem/ruby/network/garnet/RoutingUnit.hh
index 8881ea4..25a801a 100644
--- a/src/mem/ruby/network/garnet/RoutingUnit.hh
+++ b/src/mem/ruby/network/garnet/RoutingUnit.hh
@@ -37,6 +37,9 @@
#include "mem/ruby/network/garnet/GarnetNetwork.hh"
#include "mem/ruby/network/garnet/flit.hh"
+namespace gem5
+{
+
class InputUnit;
class Router;
@@ -88,4 +91,6 @@
std::map<PortDirection, int> m_outports_dirn2idx;
};
+} // namespace gem5
+
#endif // __MEM_RUBY_NETWORK_GARNET_0_ROUTINGUNIT_HH__
diff --git a/src/mem/ruby/network/garnet/SwitchAllocator.cc b/src/mem/ruby/network/garnet/SwitchAllocator.cc
index 316e5b1..e413406 100644
--- a/src/mem/ruby/network/garnet/SwitchAllocator.cc
+++ b/src/mem/ruby/network/garnet/SwitchAllocator.cc
@@ -37,6 +37,9 @@
#include "mem/ruby/network/garnet/OutputUnit.hh"
#include "mem/ruby/network/garnet/Router.hh"
+namespace gem5
+{
+
SwitchAllocator::SwitchAllocator(Router *router)
: Consumer(router)
{
@@ -386,3 +389,5 @@
m_input_arbiter_activity = 0;
m_output_arbiter_activity = 0;
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/garnet/SwitchAllocator.hh b/src/mem/ruby/network/garnet/SwitchAllocator.hh
index e17bc6f..90089f3 100644
--- a/src/mem/ruby/network/garnet/SwitchAllocator.hh
+++ b/src/mem/ruby/network/garnet/SwitchAllocator.hh
@@ -38,6 +38,9 @@
#include "mem/ruby/common/Consumer.hh"
#include "mem/ruby/network/garnet/CommonTypes.hh"
+namespace gem5
+{
+
class Router;
class InputUnit;
class OutputUnit;
@@ -83,4 +86,6 @@
std::vector<int> m_vc_winners;
};
+} // namespace gem5
+
#endif // __MEM_RUBY_NETWORK_GARNET_0_SWITCHALLOCATOR_HH__
diff --git a/src/mem/ruby/network/garnet/VirtualChannel.cc b/src/mem/ruby/network/garnet/VirtualChannel.cc
index 1035660..b4fc288 100644
--- a/src/mem/ruby/network/garnet/VirtualChannel.cc
+++ b/src/mem/ruby/network/garnet/VirtualChannel.cc
@@ -31,6 +31,9 @@
#include "mem/ruby/network/garnet/VirtualChannel.hh"
+namespace gem5
+{
+
VirtualChannel::VirtualChannel()
: inputBuffer(), m_vc_state(IDLE_, Tick(0)), m_output_port(-1),
m_enqueue_time(INFINITE_), m_output_vc(-1)
@@ -71,3 +74,5 @@
{
return inputBuffer.functionalWrite(pkt);
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/garnet/VirtualChannel.hh b/src/mem/ruby/network/garnet/VirtualChannel.hh
index c538451..2bee8ec 100644
--- a/src/mem/ruby/network/garnet/VirtualChannel.hh
+++ b/src/mem/ruby/network/garnet/VirtualChannel.hh
@@ -37,6 +37,9 @@
#include "mem/ruby/network/garnet/CommonTypes.hh"
#include "mem/ruby/network/garnet/flitBuffer.hh"
+namespace gem5
+{
+
class VirtualChannel
{
public:
@@ -96,4 +99,6 @@
int m_output_vc;
};
+} // namespace gem5
+
#endif // __MEM_RUBY_NETWORK_GARNET_0_VIRTUALCHANNEL_HH__
diff --git a/src/mem/ruby/network/garnet/flit.cc b/src/mem/ruby/network/garnet/flit.cc
index 50a8911..f188ad9 100644
--- a/src/mem/ruby/network/garnet/flit.cc
+++ b/src/mem/ruby/network/garnet/flit.cc
@@ -33,6 +33,9 @@
#include "base/intmath.hh"
#include "debug/RubyNetwork.hh"
+namespace gem5
+{
+
// Constructor for the flit
flit::flit(int id, int vc, int vnet, RouteInfo route, int size,
MsgPtr msg_ptr, int MsgSize, uint32_t bWidth, Tick curTime)
@@ -120,3 +123,5 @@
Message *msg = m_msg_ptr.get();
return msg->functionalWrite(pkt);
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/garnet/flit.hh b/src/mem/ruby/network/garnet/flit.hh
index 0396c97..ffad7eb 100644
--- a/src/mem/ruby/network/garnet/flit.hh
+++ b/src/mem/ruby/network/garnet/flit.hh
@@ -38,6 +38,9 @@
#include "mem/ruby/network/garnet/CommonTypes.hh"
#include "mem/ruby/slicc_interface/Message.hh"
+namespace gem5
+{
+
class flit
{
public:
@@ -127,4 +130,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_NETWORK_GARNET_0_FLIT_HH__
diff --git a/src/mem/ruby/network/garnet/flitBuffer.cc b/src/mem/ruby/network/garnet/flitBuffer.cc
index 6c0c1ad..96e14f5 100644
--- a/src/mem/ruby/network/garnet/flitBuffer.cc
+++ b/src/mem/ruby/network/garnet/flitBuffer.cc
@@ -31,6 +31,9 @@
#include "mem/ruby/network/garnet/flitBuffer.hh"
+namespace gem5
+{
+
flitBuffer::flitBuffer()
{
max_size = INFINITE_;
@@ -89,3 +92,5 @@
return num_functional_writes;
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/garnet/flitBuffer.hh b/src/mem/ruby/network/garnet/flitBuffer.hh
index 91a3a86..dbe92c0 100644
--- a/src/mem/ruby/network/garnet/flitBuffer.hh
+++ b/src/mem/ruby/network/garnet/flitBuffer.hh
@@ -38,6 +38,9 @@
#include "mem/ruby/network/garnet/CommonTypes.hh"
#include "mem/ruby/network/garnet/flit.hh"
+namespace gem5
+{
+
class flitBuffer
{
public:
@@ -86,4 +89,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_NETWORK_GARNET_0_FLITBUFFER_HH__
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.cc b/src/mem/ruby/network/simple/PerfectSwitch.cc
index b90fd73..2d4c729 100644
--- a/src/mem/ruby/network/simple/PerfectSwitch.cc
+++ b/src/mem/ruby/network/simple/PerfectSwitch.cc
@@ -39,6 +39,9 @@
#include "mem/ruby/network/simple/Switch.hh"
#include "mem/ruby/slicc_interface/Message.hh"
+namespace gem5
+{
+
const int PRIORITY_SWITCH_LIMIT = 128;
// Operator for helper class
@@ -326,3 +329,5 @@
{
out << "[PerfectSwitch " << m_switch_id << "]";
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.hh b/src/mem/ruby/network/simple/PerfectSwitch.hh
index 12d5e46..df069e5 100644
--- a/src/mem/ruby/network/simple/PerfectSwitch.hh
+++ b/src/mem/ruby/network/simple/PerfectSwitch.hh
@@ -43,6 +43,9 @@
#include "mem/ruby/common/Consumer.hh"
#include "mem/ruby/common/TypeDefines.hh"
+namespace gem5
+{
+
class MessageBuffer;
class NetDest;
class SimpleNetwork;
@@ -114,4 +117,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_NETWORK_SIMPLE_PERFECTSWITCH_HH__
diff --git a/src/mem/ruby/network/simple/SimpleLink.cc b/src/mem/ruby/network/simple/SimpleLink.cc
index 52d5822..f78421d 100644
--- a/src/mem/ruby/network/simple/SimpleLink.cc
+++ b/src/mem/ruby/network/simple/SimpleLink.cc
@@ -28,6 +28,9 @@
#include "mem/ruby/network/simple/SimpleLink.hh"
+namespace gem5
+{
+
SimpleExtLink::SimpleExtLink(const Params &p)
: BasicExtLink(p)
{
@@ -59,3 +62,5 @@
{
out << name();
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/simple/SimpleLink.hh b/src/mem/ruby/network/simple/SimpleLink.hh
index d3050b2..d2872f2 100644
--- a/src/mem/ruby/network/simple/SimpleLink.hh
+++ b/src/mem/ruby/network/simple/SimpleLink.hh
@@ -37,6 +37,9 @@
#include "params/SimpleIntLink.hh"
#include "mem/ruby/network/BasicLink.hh"
+namespace gem5
+{
+
class SimpleExtLink : public BasicExtLink
{
public:
@@ -77,4 +80,6 @@
return out;
}
+} // namespace gem5
+
#endif //__MEM_RUBY_NETWORK_SIMPLE_SIMPLELINK_HH__
diff --git a/src/mem/ruby/network/simple/SimpleLink.py b/src/mem/ruby/network/simple/SimpleLink.py
index 89d823b..7188589 100644
--- a/src/mem/ruby/network/simple/SimpleLink.py
+++ b/src/mem/ruby/network/simple/SimpleLink.py
@@ -32,7 +32,9 @@
class SimpleExtLink(BasicExtLink):
type = 'SimpleExtLink'
cxx_header = "mem/ruby/network/simple/SimpleLink.hh"
+ cxx_class = 'gem5::SimpleExtLink'
class SimpleIntLink(BasicIntLink):
type = 'SimpleIntLink'
cxx_header = "mem/ruby/network/simple/SimpleLink.hh"
+ cxx_class = 'gem5::SimpleIntLink'
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc b/src/mem/ruby/network/simple/SimpleNetwork.cc
index fa1df25..647fd7e 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.cc
+++ b/src/mem/ruby/network/simple/SimpleNetwork.cc
@@ -52,6 +52,9 @@
#include "mem/ruby/network/simple/Throttle.hh"
#include "mem/ruby/profiler/Profiler.hh"
+namespace gem5
+{
+
SimpleNetwork::SimpleNetwork(const Params &p)
: Network(p), m_buffer_size(p.buffer_size),
m_endpoint_bandwidth(p.endpoint_bandwidth),
@@ -239,3 +242,5 @@
{
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.hh b/src/mem/ruby/network/simple/SimpleNetwork.hh
index f6b7d2e..da7ce50 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.hh
+++ b/src/mem/ruby/network/simple/SimpleNetwork.hh
@@ -47,6 +47,9 @@
#include "mem/ruby/network/Network.hh"
#include "params/SimpleNetwork.hh"
+namespace gem5
+{
+
class NetDest;
class MessageBuffer;
class Throttle;
@@ -122,4 +125,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_NETWORK_SIMPLE_SIMPLENETWORK_HH__
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.py b/src/mem/ruby/network/simple/SimpleNetwork.py
index b4fd81f..f7d3306 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.py
+++ b/src/mem/ruby/network/simple/SimpleNetwork.py
@@ -34,6 +34,8 @@
class SimpleNetwork(RubyNetwork):
type = 'SimpleNetwork'
cxx_header = "mem/ruby/network/simple/SimpleNetwork.hh"
+ cxx_class = 'gem5::SimpleNetwork'
+
buffer_size = Param.Int(0,
"default buffer size; 0 indicates infinite buffering");
endpoint_bandwidth = Param.Int(1000, "bandwidth adjustment factor");
@@ -72,6 +74,8 @@
class Switch(BasicRouter):
type = 'Switch'
cxx_header = 'mem/ruby/network/simple/Switch.hh'
+ cxx_class = 'gem5::Switch'
+
virt_nets = Param.Int(Parent.number_of_virtual_networks,
"number of virtual networks")
port_buffers = VectorParam.MessageBuffer("Port buffers")
diff --git a/src/mem/ruby/network/simple/Switch.cc b/src/mem/ruby/network/simple/Switch.cc
index b10f27c..b6daa4b 100644
--- a/src/mem/ruby/network/simple/Switch.cc
+++ b/src/mem/ruby/network/simple/Switch.cc
@@ -48,7 +48,10 @@
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/network/simple/SimpleNetwork.hh"
-using gem5::stl_helpers::operator<<;
+namespace gem5
+{
+
+using stl_helpers::operator<<;
Switch::Switch(const Params &p)
: BasicRouter(p),
@@ -205,3 +208,5 @@
{
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/simple/Switch.hh b/src/mem/ruby/network/simple/Switch.hh
index b131b4d..69db80c 100644
--- a/src/mem/ruby/network/simple/Switch.hh
+++ b/src/mem/ruby/network/simple/Switch.hh
@@ -64,6 +64,9 @@
#include "mem/ruby/protocol/MessageSizeType.hh"
#include "params/Switch.hh"
+namespace gem5
+{
+
class MessageBuffer;
class NetDest;
class SimpleNetwork;
@@ -127,4 +130,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__
diff --git a/src/mem/ruby/network/simple/Throttle.cc b/src/mem/ruby/network/simple/Throttle.cc
index a39a061..8f1ce10 100644
--- a/src/mem/ruby/network/simple/Throttle.cc
+++ b/src/mem/ruby/network/simple/Throttle.cc
@@ -39,6 +39,9 @@
#include "mem/ruby/slicc_interface/Message.hh"
#include "mem/ruby/system/RubySystem.hh"
+namespace gem5
+{
+
const int MESSAGE_SIZE_MULTIPLIER = 1000;
//const int BROADCAST_SCALING = 4; // Have a 16p system act like a 64p systems
const int BROADCAST_SCALING = 1;
@@ -270,3 +273,5 @@
{
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/network/simple/Throttle.hh b/src/mem/ruby/network/simple/Throttle.hh
index b8e90b7..7145145 100644
--- a/src/mem/ruby/network/simple/Throttle.hh
+++ b/src/mem/ruby/network/simple/Throttle.hh
@@ -46,6 +46,9 @@
#include "mem/ruby/network/Network.hh"
#include "mem/ruby/system/RubySystem.hh"
+namespace gem5
+{
+
class MessageBuffer;
class Switch;
@@ -127,4 +130,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_NETWORK_SIMPLE_THROTTLE_HH__
diff --git a/src/mem/ruby/profiler/AccessTraceForAddress.cc b/src/mem/ruby/profiler/AccessTraceForAddress.cc
index 5822766..6c587de 100644
--- a/src/mem/ruby/profiler/AccessTraceForAddress.cc
+++ b/src/mem/ruby/profiler/AccessTraceForAddress.cc
@@ -30,6 +30,9 @@
#include "mem/ruby/common/Histogram.hh"
+namespace gem5
+{
+
AccessTraceForAddress::~AccessTraceForAddress()
{
if (m_histogram_ptr) {
@@ -103,3 +106,5 @@
}
m_histogram_ptr->add(value);
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/profiler/AccessTraceForAddress.hh b/src/mem/ruby/profiler/AccessTraceForAddress.hh
index 0d6f71e..41cfa16 100644
--- a/src/mem/ruby/profiler/AccessTraceForAddress.hh
+++ b/src/mem/ruby/profiler/AccessTraceForAddress.hh
@@ -36,6 +36,9 @@
#include "mem/ruby/protocol/RubyAccessMode.hh"
#include "mem/ruby/protocol/RubyRequestType.hh"
+namespace gem5
+{
+
class Histogram;
class AccessTraceForAddress
@@ -85,4 +88,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_PROFILER_ACCESSTRACEFORADDRESS_HH__
diff --git a/src/mem/ruby/profiler/AddressProfiler.cc b/src/mem/ruby/profiler/AddressProfiler.cc
index 5e68c6d..0a2c9f0 100644
--- a/src/mem/ruby/profiler/AddressProfiler.cc
+++ b/src/mem/ruby/profiler/AddressProfiler.cc
@@ -35,6 +35,9 @@
#include "mem/ruby/profiler/Profiler.hh"
#include "mem/ruby/protocol/RubyRequest.hh"
+namespace gem5
+{
+
typedef AddressProfiler::AddressMap AddressMap;
using gem5::stl_helpers::operator<<;
@@ -339,3 +342,5 @@
lookupTraceForAddress(data_addr, m_retryProfileMap).addSample(count);
}
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/profiler/AddressProfiler.hh b/src/mem/ruby/profiler/AddressProfiler.hh
index 14d015c..314623d 100644
--- a/src/mem/ruby/profiler/AddressProfiler.hh
+++ b/src/mem/ruby/profiler/AddressProfiler.hh
@@ -39,6 +39,9 @@
#include "mem/ruby/protocol/AccessType.hh"
#include "mem/ruby/protocol/RubyRequest.hh"
+namespace gem5
+{
+
class Set;
class AddressProfiler
@@ -112,4 +115,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_PROFILER_ADDRESSPROFILER_HH__
diff --git a/src/mem/ruby/profiler/Profiler.cc b/src/mem/ruby/profiler/Profiler.cc
index 01512e6..a013da2 100644
--- a/src/mem/ruby/profiler/Profiler.cc
+++ b/src/mem/ruby/profiler/Profiler.cc
@@ -78,7 +78,10 @@
#include "mem/ruby/system/Sequencer.hh"
-using gem5::stl_helpers::operator<<;
+namespace gem5
+{
+
+using stl_helpers::operator<<;
Profiler::Profiler(const RubySystemParams &p, RubySystem *rs)
: m_ruby_system(rs), m_hot_lines(p.hot_lines),
@@ -578,3 +581,4 @@
}
}
+} // namespace gem5
diff --git a/src/mem/ruby/profiler/Profiler.hh b/src/mem/ruby/profiler/Profiler.hh
index 7004c94..9162c4b 100644
--- a/src/mem/ruby/profiler/Profiler.hh
+++ b/src/mem/ruby/profiler/Profiler.hh
@@ -59,6 +59,9 @@
#include "mem/ruby/protocol/RubyRequestType.hh"
#include "params/RubySystem.hh"
+namespace gem5
+{
+
class RubyRequest;
class AddressProfiler;
@@ -193,4 +196,6 @@
ProfilerStats rubyProfilerStats;
};
+} // namespace gem5
+
#endif // __MEM_RUBY_PROFILER_PROFILER_HH__
diff --git a/src/mem/ruby/profiler/StoreTrace.cc b/src/mem/ruby/profiler/StoreTrace.cc
index c0f070d..625d618 100644
--- a/src/mem/ruby/profiler/StoreTrace.cc
+++ b/src/mem/ruby/profiler/StoreTrace.cc
@@ -30,6 +30,9 @@
#include "sim/core.hh"
+namespace gem5
+{
+
bool StoreTrace::s_init = false; // Total number of store lifetimes of
// all lines
int64_t StoreTrace::s_total_samples = 0; // Total number of store
@@ -157,3 +160,5 @@
m_last_writer = -1;
}
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/profiler/StoreTrace.hh b/src/mem/ruby/profiler/StoreTrace.hh
index a686594..876052e 100644
--- a/src/mem/ruby/profiler/StoreTrace.hh
+++ b/src/mem/ruby/profiler/StoreTrace.hh
@@ -35,6 +35,9 @@
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Histogram.hh"
+namespace gem5
+{
+
class StoreTrace
{
public:
@@ -87,4 +90,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_PROFILER_STORETRACE_HH__
diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc b/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
index c669b1c..86746a0 100644
--- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
+++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
@@ -43,6 +43,9 @@
#include "base/trace.hh"
#include "debug/RubyCache.hh"
+namespace gem5
+{
+
AbstractCacheEntry::AbstractCacheEntry() : ReplaceableEntry()
{
m_Permission = AccessPermission_NotPresent;
@@ -119,3 +122,5 @@
{
return m_htmInWriteSet;
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
index 48e3b9d..befba8f 100644
--- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
+++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
@@ -53,6 +53,9 @@
#include "mem/ruby/common/DataBlock.hh"
#include "mem/ruby/protocol/AccessPermission.hh"
+namespace gem5
+{
+
class AbstractCacheEntry : public ReplaceableEntry
{
private:
@@ -130,4 +133,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCACHEENTRY_HH__
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index 2e323d3..f3651bb 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -47,6 +47,9 @@
#include "mem/ruby/system/Sequencer.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
AbstractController::AbstractController(const Params &p)
: ClockedObject(p), Consumer(this), m_version(p.version),
m_clusterID(p.cluster_id),
@@ -457,3 +460,5 @@
delayHistogram
.flags(statistics::nozero);
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index 4af3136..e031135 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -62,6 +62,9 @@
#include "params/RubyController.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
class Network;
class GPUCoalescer;
class DMASequencer;
@@ -398,4 +401,6 @@
};
+} // namespace gem5
+
#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
diff --git a/src/mem/ruby/slicc_interface/Controller.py b/src/mem/ruby/slicc_interface/Controller.py
index ee6ca60..eefdc81 100644
--- a/src/mem/ruby/slicc_interface/Controller.py
+++ b/src/mem/ruby/slicc_interface/Controller.py
@@ -42,9 +42,10 @@
class RubyController(ClockedObject):
type = 'RubyController'
- cxx_class = 'AbstractController'
+ cxx_class = 'gem5::AbstractController'
cxx_header = "mem/ruby/slicc_interface/AbstractController.hh"
abstract = True
+
version = Param.Int("")
addr_ranges = VectorParam.AddrRange([AllMemory], "Address range this "
"controller responds to")
diff --git a/src/mem/ruby/slicc_interface/Message.hh b/src/mem/ruby/slicc_interface/Message.hh
index b8449e7..1a5f211 100644
--- a/src/mem/ruby/slicc_interface/Message.hh
+++ b/src/mem/ruby/slicc_interface/Message.hh
@@ -50,6 +50,9 @@
#include "mem/ruby/common/WriteMask.hh"
#include "mem/ruby/protocol/MessageSizeType.hh"
+namespace gem5
+{
+
class Message;
typedef std::shared_ptr<Message> MsgPtr;
@@ -146,4 +149,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_SLICC_INTERFACE_MESSAGE_HH__
diff --git a/src/mem/ruby/slicc_interface/RubyRequest.cc b/src/mem/ruby/slicc_interface/RubyRequest.cc
index af91aca..a18b433 100644
--- a/src/mem/ruby/slicc_interface/RubyRequest.cc
+++ b/src/mem/ruby/slicc_interface/RubyRequest.cc
@@ -44,6 +44,9 @@
#include "mem/ruby/slicc_interface/RubySlicc_Util.hh"
+namespace gem5
+{
+
void
RubyRequest::print(std::ostream& out) const
{
@@ -116,3 +119,5 @@
return cBase < cTail;
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/slicc_interface/RubyRequest.hh b/src/mem/ruby/slicc_interface/RubyRequest.hh
index 3a2f486..60a29e9 100644
--- a/src/mem/ruby/slicc_interface/RubyRequest.hh
+++ b/src/mem/ruby/slicc_interface/RubyRequest.hh
@@ -52,6 +52,9 @@
#include "mem/ruby/protocol/RubyAccessMode.hh"
#include "mem/ruby/protocol/RubyRequestType.hh"
+namespace gem5
+{
+
class RubyRequest : public Message
{
public:
@@ -170,4 +173,6 @@
return out;
}
+} // namespace gem5
+
#endif //__MEM_RUBY_SLICC_INTERFACE_RUBYREQUEST_HH__
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
index a48405d..b416c37 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
@@ -35,6 +35,9 @@
#include "mem/ruby/protocol/MachineType.hh"
#include "mem/ruby/structures/DirectoryMemory.hh"
+namespace gem5
+{
+
inline NetDest
broadcast(MachineType type)
{
@@ -91,4 +94,6 @@
return mach;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_SLICC_INTERFACE_COMPONENTMAPPINGS_HH__
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
index 187f5fe..83a81e7 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
@@ -58,6 +58,9 @@
#include "mem/ruby/common/WriteMask.hh"
#include "mem/ruby/protocol/RubyRequestType.hh"
+namespace gem5
+{
+
inline Cycles zero_time() { return Cycles(0); }
inline Cycles intToCycles(int c) { return Cycles(c); }
@@ -280,4 +283,6 @@
return count;
}
+} // namespace gem5
+
#endif //__MEM_RUBY_SLICC_INTERFACE_RUBYSLICC_UTIL_HH__
diff --git a/src/mem/ruby/structures/BankedArray.cc b/src/mem/ruby/structures/BankedArray.cc
index 091bcbd..c925967 100644
--- a/src/mem/ruby/structures/BankedArray.cc
+++ b/src/mem/ruby/structures/BankedArray.cc
@@ -34,6 +34,9 @@
#include "base/intmath.hh"
#include "mem/ruby/system/RubySystem.hh"
+namespace gem5
+{
+
BankedArray::BankedArray(unsigned int banks, Cycles accessLatency,
unsigned int startIndexBit, RubySystem *rs)
: m_ruby_system(rs)
@@ -99,3 +102,5 @@
}
return idx % banks;
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/structures/BankedArray.hh b/src/mem/ruby/structures/BankedArray.hh
index e2359af..c5687bb 100644
--- a/src/mem/ruby/structures/BankedArray.hh
+++ b/src/mem/ruby/structures/BankedArray.hh
@@ -38,6 +38,9 @@
#include "mem/ruby/system/RubySystem.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
class BankedArray
{
private:
@@ -75,4 +78,6 @@
Cycles getLatency() const { return accessLatency; }
};
+} // namespace gem5
+
#endif
diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc
index fbb9d36..f162bf6 100644
--- a/src/mem/ruby/structures/CacheMemory.cc
+++ b/src/mem/ruby/structures/CacheMemory.cc
@@ -53,6 +53,9 @@
#include "mem/ruby/protocol/AccessPermission.hh"
#include "mem/ruby/system/RubySystem.hh"
+namespace gem5
+{
+
std::ostream&
operator<<(std::ostream& out, const CacheMemory& obj)
{
@@ -765,3 +768,4 @@
cacheMemoryStats.m_prefetch_misses++;
}
+} // namespace gem5
diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh
index 86029db..1e9867c 100644
--- a/src/mem/ruby/structures/CacheMemory.hh
+++ b/src/mem/ruby/structures/CacheMemory.hh
@@ -60,6 +60,9 @@
#include "params/RubyCache.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class CacheMemory : public SimObject
{
public:
@@ -246,4 +249,6 @@
std::ostream& operator<<(std::ostream& out, const CacheMemory& obj);
+} // namespace gem5
+
#endif // __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
diff --git a/src/mem/ruby/structures/DirectoryMemory.cc b/src/mem/ruby/structures/DirectoryMemory.cc
index c73ceba..61c2220 100644
--- a/src/mem/ruby/structures/DirectoryMemory.cc
+++ b/src/mem/ruby/structures/DirectoryMemory.cc
@@ -49,6 +49,9 @@
#include "mem/ruby/system/RubySystem.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
DirectoryMemory::DirectoryMemory(const Params &p)
: SimObject(p), addrRanges(p.addr_ranges.begin(), p.addr_ranges.end())
{
@@ -156,3 +159,5 @@
DPRINTF(RubyStats, "Recorded statistic: %s\n",
DirectoryRequestType_to_string(requestType));
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/structures/DirectoryMemory.hh b/src/mem/ruby/structures/DirectoryMemory.hh
index 80ed6ab..c9a83c8 100644
--- a/src/mem/ruby/structures/DirectoryMemory.hh
+++ b/src/mem/ruby/structures/DirectoryMemory.hh
@@ -51,6 +51,9 @@
#include "params/RubyDirectoryMemory.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class DirectoryMemory : public SimObject
{
public:
@@ -114,4 +117,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_STRUCTURES_DIRECTORYMEMORY_HH__
diff --git a/src/mem/ruby/structures/DirectoryMemory.py b/src/mem/ruby/structures/DirectoryMemory.py
index 0d6203f..b0e19da 100644
--- a/src/mem/ruby/structures/DirectoryMemory.py
+++ b/src/mem/ruby/structures/DirectoryMemory.py
@@ -42,7 +42,8 @@
class RubyDirectoryMemory(SimObject):
type = 'RubyDirectoryMemory'
- cxx_class = 'DirectoryMemory'
+ cxx_class = 'gem5::DirectoryMemory'
cxx_header = "mem/ruby/structures/DirectoryMemory.hh"
+
addr_ranges = VectorParam.AddrRange(
Parent.addr_ranges, "Address range this directory responds to")
diff --git a/src/mem/ruby/structures/PerfectCacheMemory.hh b/src/mem/ruby/structures/PerfectCacheMemory.hh
index 136d0da..fe1106e 100644
--- a/src/mem/ruby/structures/PerfectCacheMemory.hh
+++ b/src/mem/ruby/structures/PerfectCacheMemory.hh
@@ -47,6 +47,9 @@
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/protocol/AccessPermission.hh"
+namespace gem5
+{
+
template<class ENTRY>
struct PerfectCacheLineState
{
@@ -203,4 +206,6 @@
{
}
+} // namespace gem5
+
#endif // __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__
diff --git a/src/mem/ruby/structures/PersistentTable.cc b/src/mem/ruby/structures/PersistentTable.cc
index 58b0b4f..832770f 100644
--- a/src/mem/ruby/structures/PersistentTable.cc
+++ b/src/mem/ruby/structures/PersistentTable.cc
@@ -28,6 +28,9 @@
#include "mem/ruby/structures/PersistentTable.hh"
+namespace gem5
+{
+
PersistentTable::PersistentTable()
{
}
@@ -191,3 +194,4 @@
{
}
+} // namespace gem5
diff --git a/src/mem/ruby/structures/PersistentTable.hh b/src/mem/ruby/structures/PersistentTable.hh
index bc1d79e..32aaf5c 100644
--- a/src/mem/ruby/structures/PersistentTable.hh
+++ b/src/mem/ruby/structures/PersistentTable.hh
@@ -37,6 +37,9 @@
#include "mem/ruby/common/NetDest.hh"
#include "mem/ruby/protocol/AccessType.hh"
+namespace gem5
+{
+
class PersistentTableEntry
{
public:
@@ -97,4 +100,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_STRUCTURES_PERSISTENTTABLE_HH__
diff --git a/src/mem/ruby/structures/RubyCache.py b/src/mem/ruby/structures/RubyCache.py
index 294d30c..91be23e 100644
--- a/src/mem/ruby/structures/RubyCache.py
+++ b/src/mem/ruby/structures/RubyCache.py
@@ -31,8 +31,9 @@
class RubyCache(SimObject):
type = 'RubyCache'
- cxx_class = 'CacheMemory'
+ cxx_class = 'gem5::CacheMemory'
cxx_header = "mem/ruby/structures/CacheMemory.hh"
+
size = Param.MemorySize("capacity in bytes");
assoc = Param.Int("");
replacement_policy = Param.BaseReplacementPolicy(TreePLRURP(), "")
diff --git a/src/mem/ruby/structures/RubyPrefetcher.cc b/src/mem/ruby/structures/RubyPrefetcher.cc
index d52b2f5..495f915 100644
--- a/src/mem/ruby/structures/RubyPrefetcher.cc
+++ b/src/mem/ruby/structures/RubyPrefetcher.cc
@@ -48,6 +48,9 @@
#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
#include "mem/ruby/system/RubySystem.hh"
+namespace gem5
+{
+
RubyPrefetcher::RubyPrefetcher(const Params &p)
: SimObject(p), m_num_streams(p.num_streams),
m_array(p.num_streams), m_train_misses(p.train_misses),
@@ -374,3 +377,5 @@
{
return mbits<Addr>(addr, 63, m_page_shift);
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/structures/RubyPrefetcher.hh b/src/mem/ruby/structures/RubyPrefetcher.hh
index 13989f1..9cdf3a5 100644
--- a/src/mem/ruby/structures/RubyPrefetcher.hh
+++ b/src/mem/ruby/structures/RubyPrefetcher.hh
@@ -59,6 +59,9 @@
#define MAX_PF_INFLIGHT 8
+namespace gem5
+{
+
class PrefetchEntry
{
public:
@@ -255,4 +258,6 @@
} rubyPrefetcherStats;
};
+} // namespace gem5
+
#endif // __MEM_RUBY_STRUCTURES_PREFETCHER_HH__
diff --git a/src/mem/ruby/structures/RubyPrefetcher.py b/src/mem/ruby/structures/RubyPrefetcher.py
index 38397c3..764272d 100644
--- a/src/mem/ruby/structures/RubyPrefetcher.py
+++ b/src/mem/ruby/structures/RubyPrefetcher.py
@@ -44,7 +44,7 @@
class RubyPrefetcher(SimObject):
type = 'RubyPrefetcher'
- cxx_class = 'RubyPrefetcher'
+ cxx_class = 'gem5::RubyPrefetcher'
cxx_header = "mem/ruby/structures/RubyPrefetcher.hh"
num_streams = Param.UInt32(4,
diff --git a/src/mem/ruby/structures/TBEStorage.cc b/src/mem/ruby/structures/TBEStorage.cc
index 8684352..36b7a5d 100644
--- a/src/mem/ruby/structures/TBEStorage.cc
+++ b/src/mem/ruby/structures/TBEStorage.cc
@@ -37,6 +37,9 @@
#include <mem/ruby/structures/TBEStorage.hh>
+namespace gem5
+{
+
TBEStorage::TBEStorage(statistics::Group *parent, int number_of_TBEs)
: m_reserved(0), m_stats(parent)
{
@@ -51,3 +54,5 @@
ADD_STAT(avg_reserved, "Avg. number of slots reserved")
{
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/structures/TBEStorage.hh b/src/mem/ruby/structures/TBEStorage.hh
index 3e29a52..49b7db6 100644
--- a/src/mem/ruby/structures/TBEStorage.hh
+++ b/src/mem/ruby/structures/TBEStorage.hh
@@ -44,6 +44,9 @@
#include <base/statistics.hh>
+namespace gem5
+{
+
// The TBEStorage is used to track the resources consumed by the TBETable,
// i.e. the number of available TBE slots.
//
@@ -186,4 +189,6 @@
m_stats.avg_util = utilization();
}
+} // namespace gem5
+
#endif
diff --git a/src/mem/ruby/structures/TBETable.hh b/src/mem/ruby/structures/TBETable.hh
index b4a723b..c65a27d 100644
--- a/src/mem/ruby/structures/TBETable.hh
+++ b/src/mem/ruby/structures/TBETable.hh
@@ -46,6 +46,9 @@
#include "mem/ruby/common/Address.hh"
+namespace gem5
+{
+
template<class ENTRY>
class TBETable
{
@@ -141,4 +144,6 @@
{
}
+} // namespace gem5
+
#endif // __MEM_RUBY_STRUCTURES_TBETABLE_HH__
diff --git a/src/mem/ruby/structures/TimerTable.cc b/src/mem/ruby/structures/TimerTable.cc
index 4809c8a..c264ca1 100644
--- a/src/mem/ruby/structures/TimerTable.cc
+++ b/src/mem/ruby/structures/TimerTable.cc
@@ -30,6 +30,9 @@
#include "mem/ruby/system/RubySystem.hh"
+namespace gem5
+{
+
TimerTable::TimerTable()
: m_next_time(0)
{
@@ -120,3 +123,5 @@
m_next_valid = true;
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/structures/TimerTable.hh b/src/mem/ruby/structures/TimerTable.hh
index 9efe7ca..344e97a 100644
--- a/src/mem/ruby/structures/TimerTable.hh
+++ b/src/mem/ruby/structures/TimerTable.hh
@@ -37,6 +37,9 @@
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Consumer.hh"
+namespace gem5
+{
+
class TimerTable
{
public:
@@ -93,4 +96,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_STRUCTURES_TIMERTABLE_HH__
diff --git a/src/mem/ruby/structures/WireBuffer.cc b/src/mem/ruby/structures/WireBuffer.cc
index ac3ecbd..a663ba8 100644
--- a/src/mem/ruby/structures/WireBuffer.cc
+++ b/src/mem/ruby/structures/WireBuffer.cc
@@ -38,6 +38,9 @@
#include "base/stl_helpers.hh"
#include "mem/ruby/system/RubySystem.hh"
+namespace gem5
+{
+
// Output operator definition
std::ostream&
@@ -140,3 +143,5 @@
WireBuffer::wakeup()
{
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/structures/WireBuffer.hh b/src/mem/ruby/structures/WireBuffer.hh
index be861ec..eb44888 100644
--- a/src/mem/ruby/structures/WireBuffer.hh
+++ b/src/mem/ruby/structures/WireBuffer.hh
@@ -41,6 +41,9 @@
#include "params/RubyWireBuffer.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
//////////////////////////////////////////////////////////////////////////////
// This object was written to literally mimic a Wire in Ruby, in the sense
// that there is no way for messages to get reordered en route on the WireBuffer.
@@ -98,4 +101,6 @@
std::ostream& operator<<(std::ostream& out, const WireBuffer& obj);
+} // namespace gem5
+
#endif // __MEM_RUBY_STRUCTURES_WireBuffer_HH__
diff --git a/src/mem/ruby/structures/WireBuffer.py b/src/mem/ruby/structures/WireBuffer.py
index 9a55390..b040ebf 100644
--- a/src/mem/ruby/structures/WireBuffer.py
+++ b/src/mem/ruby/structures/WireBuffer.py
@@ -32,6 +32,7 @@
class RubyWireBuffer(SimObject):
type = 'RubyWireBuffer'
- cxx_class = 'WireBuffer'
+ cxx_class = 'gem5::WireBuffer'
cxx_header = "mem/ruby/structures/WireBuffer.hh"
+
ruby_system = Param.RubySystem(Parent.any, "")
diff --git a/src/mem/ruby/system/CacheRecorder.cc b/src/mem/ruby/system/CacheRecorder.cc
index 6207b76..dfe5a53 100644
--- a/src/mem/ruby/system/CacheRecorder.cc
+++ b/src/mem/ruby/system/CacheRecorder.cc
@@ -33,6 +33,9 @@
#include "mem/ruby/system/RubySystem.hh"
#include "mem/ruby/system/Sequencer.hh"
+namespace gem5
+{
+
void
TraceRecord::print(std::ostream& out) const
{
@@ -200,3 +203,5 @@
m_records.clear();
return current_size;
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/system/CacheRecorder.hh b/src/mem/ruby/system/CacheRecorder.hh
index b295be6..94dfdff 100644
--- a/src/mem/ruby/system/CacheRecorder.hh
+++ b/src/mem/ruby/system/CacheRecorder.hh
@@ -43,6 +43,9 @@
#include "mem/ruby/common/TypeDefines.hh"
#include "mem/ruby/protocol/RubyRequestType.hh"
+namespace gem5
+{
+
class Sequencer;
/*!
@@ -127,4 +130,6 @@
return out;
}
+} // namespace gem5
+
#endif //__MEM_RUBY_SYSTEM_CACHERECORDER_HH__
diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index fe9456a..ddc932a 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -48,6 +48,9 @@
#include "mem/ruby/protocol/SequencerRequestType.hh"
#include "mem/ruby/system/RubySystem.hh"
+namespace gem5
+{
+
DMARequest::DMARequest(uint64_t start_paddr, int len, bool write,
int bytes_completed, int bytes_issued, uint8_t *data,
PacketPtr pkt)
@@ -261,3 +264,5 @@
DPRINTF(RubyStats, "Recorded statistic: %s\n",
DMASequencerRequestType_to_string(requestType));
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh
index be19979..0394393 100644
--- a/src/mem/ruby/system/DMASequencer.hh
+++ b/src/mem/ruby/system/DMASequencer.hh
@@ -39,6 +39,9 @@
#include "mem/ruby/system/RubyPort.hh"
#include "params/DMASequencer.hh"
+namespace gem5
+{
+
struct DMARequest
{
DMARequest(uint64_t start_paddr, int len, bool write, int bytes_completed,
@@ -86,4 +89,6 @@
int m_max_outstanding_requests;
};
+} // namespace gem5
+
#endif // __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
diff --git a/src/mem/ruby/system/GPUCoalescer.cc b/src/mem/ruby/system/GPUCoalescer.cc
index d3e44e1..e5d0523 100644
--- a/src/mem/ruby/system/GPUCoalescer.cc
+++ b/src/mem/ruby/system/GPUCoalescer.cc
@@ -54,6 +54,9 @@
#include "mem/ruby/system/RubySystem.hh"
#include "params/RubyGPUCoalescer.hh"
+namespace gem5
+{
+
UncoalescedTable::UncoalescedTable(GPUCoalescer *gc)
: coalescer(gc)
{
@@ -952,3 +955,4 @@
{
}
+} // namespace gem5
diff --git a/src/mem/ruby/system/GPUCoalescer.hh b/src/mem/ruby/system/GPUCoalescer.hh
index d19fc22..489ef04 100644
--- a/src/mem/ruby/system/GPUCoalescer.hh
+++ b/src/mem/ruby/system/GPUCoalescer.hh
@@ -50,6 +50,9 @@
#include "mem/ruby/system/Sequencer.hh"
#include "mem/token_port.hh"
+namespace gem5
+{
+
class DataBlock;
class CacheMsg;
struct MachineID;
@@ -536,4 +539,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_SYSTEM_GPU_COALESCER_HH__
diff --git a/src/mem/ruby/system/GPUCoalescer.py b/src/mem/ruby/system/GPUCoalescer.py
index 0bb5628..aa26766 100644
--- a/src/mem/ruby/system/GPUCoalescer.py
+++ b/src/mem/ruby/system/GPUCoalescer.py
@@ -37,7 +37,7 @@
class RubyGPUCoalescer(RubyPort):
type = 'RubyGPUCoalescer'
abstract = True
- cxx_class = 'GPUCoalescer'
+ cxx_class = 'gem5::GPUCoalescer'
cxx_header = "mem/ruby/system/GPUCoalescer.hh"
# max_outstanding_requests = (wave front slots) x (wave front size)
diff --git a/src/mem/ruby/system/HTMSequencer.cc b/src/mem/ruby/system/HTMSequencer.cc
index f968c25..5e46692 100644
--- a/src/mem/ruby/system/HTMSequencer.cc
+++ b/src/mem/ruby/system/HTMSequencer.cc
@@ -42,6 +42,9 @@
#include "mem/ruby/slicc_interface/RubySlicc_Util.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
HtmCacheFailure
HTMSequencer::htmRetCodeConversion(
const HtmFailedInCacheReason ruby_ret_code)
@@ -358,3 +361,5 @@
return Sequencer::insertRequest(pkt, primary_type, secondary_type);
}
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/system/HTMSequencer.hh b/src/mem/ruby/system/HTMSequencer.hh
index f1c6519..bbdcd9d 100644
--- a/src/mem/ruby/system/HTMSequencer.hh
+++ b/src/mem/ruby/system/HTMSequencer.hh
@@ -48,6 +48,9 @@
#include "mem/ruby/system/Sequencer.hh"
#include "params/RubyHTMSequencer.hh"
+namespace gem5
+{
+
class HTMSequencer : public Sequencer
{
public:
@@ -110,4 +113,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_SYSTEM_HTMSEQUENCER_HH__
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index d1305c4..e836b74 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -52,6 +52,9 @@
#include "sim/full_system.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
RubyPort::RubyPort(const Params &p)
: ClockedObject(p), m_ruby_system(p.ruby_system), m_version(p.version),
m_controller(NULL), m_mandatory_q_ptr(NULL),
@@ -675,3 +678,5 @@
}
return num_written;
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh
index e28dc6e..3af78f7 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -53,6 +53,9 @@
#include "params/RubyPort.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
class AbstractController;
class RubyPort : public ClockedObject
@@ -226,4 +229,6 @@
bool m_isCPUSequencer;
};
+} // namespace gem5
+
#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
diff --git a/src/mem/ruby/system/RubyPortProxy.cc b/src/mem/ruby/system/RubyPortProxy.cc
index 4d0ac68..bc5db38 100644
--- a/src/mem/ruby/system/RubyPortProxy.cc
+++ b/src/mem/ruby/system/RubyPortProxy.cc
@@ -37,6 +37,11 @@
#include "mem/ruby/system/RubyPortProxy.hh"
+#include "base/logging.hh"
+
+namespace gem5
+{
+
RubyPortProxy::RubyPortProxy(const RubyPortProxyParams &p) :
RubyPort(p)
{
@@ -61,3 +66,5 @@
panic("RubyPortProxy::makeRequest should not be called");
return RequestStatus_NULL;
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/system/RubyPortProxy.hh b/src/mem/ruby/system/RubyPortProxy.hh
index 5967317..7860c7a 100644
--- a/src/mem/ruby/system/RubyPortProxy.hh
+++ b/src/mem/ruby/system/RubyPortProxy.hh
@@ -49,6 +49,9 @@
#include "mem/ruby/system/RubyPort.hh"
#include "params/RubyPortProxy.hh"
+namespace gem5
+{
+
class RubyPortProxy : public RubyPort
{
@@ -109,4 +112,6 @@
};
+} // namespace gem5
+
#endif // __MEM_RUBY_SYSTEM_RUBYPORTPROXY_HH__
diff --git a/src/mem/ruby/system/RubySystem.cc b/src/mem/ruby/system/RubySystem.cc
index caee770..ae570f8 100644
--- a/src/mem/ruby/system/RubySystem.cc
+++ b/src/mem/ruby/system/RubySystem.cc
@@ -60,6 +60,9 @@
#include "sim/simulate.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
bool RubySystem::m_randomization;
uint32_t RubySystem::m_block_size_bytes;
uint32_t RubySystem::m_block_size_bits;
@@ -736,3 +739,5 @@
return true;
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/system/RubySystem.hh b/src/mem/ruby/system/RubySystem.hh
index 1440744..8c09f39 100644
--- a/src/mem/ruby/system/RubySystem.hh
+++ b/src/mem/ruby/system/RubySystem.hh
@@ -46,6 +46,9 @@
#include "params/RubySystem.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
class Network;
class AbstractController;
@@ -149,4 +152,6 @@
std::vector<std::map<uint32_t, AbstractController *> > m_abstract_controls;
};
+} // namespace gem5
+
#endif //__MEM_RUBY_SYSTEM_RUBYSYSTEM_HH__
diff --git a/src/mem/ruby/system/RubySystem.py b/src/mem/ruby/system/RubySystem.py
index 347896f..085f5ab 100644
--- a/src/mem/ruby/system/RubySystem.py
+++ b/src/mem/ruby/system/RubySystem.py
@@ -32,6 +32,8 @@
class RubySystem(ClockedObject):
type = 'RubySystem'
cxx_header = "mem/ruby/system/RubySystem.hh"
+ cxx_class = 'gem5::RubySystem'
+
randomization = Param.Bool(False,
"insert random delays on message enqueue times (if True, all message \
buffers are enforced to have randomization; otherwise, a message \
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index af1149a..438b6d0 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -59,6 +59,9 @@
#include "mem/ruby/system/RubySystem.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
Sequencer::Sequencer(const Params &p)
: RubyPort(p), m_IncompleteTimes(MachineType_NUM),
deadlockCheckEvent([this]{ wakeup(); }, "Sequencer deadlock check")
@@ -843,3 +846,5 @@
llscClearMonitor(address);
ruby_eviction_callback(address);
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index 6b6aa1f..a7fa53e 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -53,6 +53,9 @@
#include "mem/ruby/system/RubyPort.hh"
#include "params/RubySequencer.hh"
+namespace gem5
+{
+
struct SequencerRequest
{
PacketPtr pkt;
@@ -322,4 +325,6 @@
return out;
}
+} // namespace gem5
+
#endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__
diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py
index f56574c..e5af16f 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -45,6 +45,8 @@
type = 'RubyPort'
abstract = True
cxx_header = "mem/ruby/system/RubyPort.hh"
+ cxx_class = 'gem5::RubyPort'
+
version = Param.Int(0, "")
in_ports = VectorResponsePort("CPU side of this RubyPort/Sequencer. "
@@ -82,10 +84,11 @@
class RubyPortProxy(RubyPort):
type = 'RubyPortProxy'
cxx_header = "mem/ruby/system/RubyPortProxy.hh"
+ cxx_class = 'gem5::RubyPortProxy'
class RubySequencer(RubyPort):
type = 'RubySequencer'
- cxx_class = 'Sequencer'
+ cxx_class = 'gem5::Sequencer'
cxx_header = "mem/ruby/system/Sequencer.hh"
dcache = Param.RubyCache("")
@@ -127,10 +130,12 @@
class RubyHTMSequencer(RubySequencer):
type = 'RubyHTMSequencer'
- cxx_class = 'HTMSequencer'
+ cxx_class = 'gem5::HTMSequencer'
cxx_header = "mem/ruby/system/HTMSequencer.hh"
class DMASequencer(RubyPort):
type = 'DMASequencer'
cxx_header = "mem/ruby/system/DMASequencer.hh"
+ cxx_class = 'gem5::DMASequencer'
+
max_outstanding_requests = Param.Int(64, "max outstanding requests")
diff --git a/src/mem/ruby/system/VIPERCoalescer.cc b/src/mem/ruby/system/VIPERCoalescer.cc
index df631b1..4d8ef1d 100644
--- a/src/mem/ruby/system/VIPERCoalescer.cc
+++ b/src/mem/ruby/system/VIPERCoalescer.cc
@@ -50,6 +50,9 @@
#include "mem/ruby/system/RubySystem.hh"
#include "params/VIPERCoalescer.hh"
+namespace gem5
+{
+
VIPERCoalescer::VIPERCoalescer(const Params &p)
: GPUCoalescer(p),
m_cache_inv_pkt(nullptr),
@@ -299,3 +302,5 @@
"There are %d Invalidatons outstanding after Cache Walk\n",
m_num_pending_invs);
}
+
+} // namespace gem5
diff --git a/src/mem/ruby/system/VIPERCoalescer.hh b/src/mem/ruby/system/VIPERCoalescer.hh
index 40b32cc..fc588be 100644
--- a/src/mem/ruby/system/VIPERCoalescer.hh
+++ b/src/mem/ruby/system/VIPERCoalescer.hh
@@ -44,6 +44,9 @@
#include "mem/ruby/system/GPUCoalescer.hh"
#include "mem/ruby/system/RubyPort.hh"
+namespace gem5
+{
+
class DataBlock;
class CacheMsg;
struct MachineID;
@@ -84,4 +87,7 @@
// compute unit.
std::unordered_map<uint64_t, std::vector<PacketPtr>> m_writeCompletePktMap;
};
+
+} // namespace gem5
+
#endif //__MEM_RUBY_SYSTEM_VIPERCOALESCER_HH__
diff --git a/src/mem/ruby/system/VIPERCoalescer.py b/src/mem/ruby/system/VIPERCoalescer.py
index d4af1be..2f73ef7 100644
--- a/src/mem/ruby/system/VIPERCoalescer.py
+++ b/src/mem/ruby/system/VIPERCoalescer.py
@@ -35,7 +35,8 @@
class VIPERCoalescer(RubyGPUCoalescer):
type = 'VIPERCoalescer'
- cxx_class = 'VIPERCoalescer'
+ cxx_class = 'gem5::VIPERCoalescer'
cxx_header = "mem/ruby/system/VIPERCoalescer.hh"
+
max_inv_per_cycle = Param.Int(32, "max invalidations per cycle")
max_wb_per_cycle = Param.Int(32, "max writebacks per cycle")
diff --git a/src/mem/se_translating_port_proxy.cc b/src/mem/se_translating_port_proxy.cc
index a8a42d0..c6ba1ff 100644
--- a/src/mem/se_translating_port_proxy.cc
+++ b/src/mem/se_translating_port_proxy.cc
@@ -43,6 +43,9 @@
#include "sim/process.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
SETranslatingPortProxy::SETranslatingPortProxy(
ThreadContext *tc, AllocType alloc, Request::Flags _flags) :
TranslatingPortProxy(tc, _flags), allocating(alloc)
@@ -64,3 +67,5 @@
}
return false;
}
+
+} // namespace gem5
diff --git a/src/mem/se_translating_port_proxy.hh b/src/mem/se_translating_port_proxy.hh
index d684c20..f0ad5af 100644
--- a/src/mem/se_translating_port_proxy.hh
+++ b/src/mem/se_translating_port_proxy.hh
@@ -43,6 +43,9 @@
#include "mem/translating_port_proxy.hh"
+namespace gem5
+{
+
class SETranslatingPortProxy : public TranslatingPortProxy
{
@@ -65,4 +68,6 @@
Request::Flags _flags=0);
};
+} // namespace gem5
+
#endif // __MEM_SE_TRANSLATING_PORT_PROXY_HH__
diff --git a/src/mem/serial_link.cc b/src/mem/serial_link.cc
index 12309ef..7847e4a 100644
--- a/src/mem/serial_link.cc
+++ b/src/mem/serial_link.cc
@@ -51,6 +51,9 @@
#include "debug/SerialLink.hh"
#include "params/SerialLink.hh"
+namespace gem5
+{
+
SerialLink::SerialLinkResponsePort::
SerialLinkResponsePort(const std::string& _name,
SerialLink& _serial_link,
@@ -420,3 +423,5 @@
{
return ranges;
}
+
+} // namespace gem5
diff --git a/src/mem/serial_link.hh b/src/mem/serial_link.hh
index ad76c9e..064fe4e 100644
--- a/src/mem/serial_link.hh
+++ b/src/mem/serial_link.hh
@@ -55,6 +55,9 @@
#include "params/SerialLink.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
/**
* SerialLink is a simple variation of the Bridge class, with the ability to
* account for the latency of packet serialization. We assume that the
@@ -322,4 +325,6 @@
SerialLink(const SerialLinkParams &p);
};
+} // namespace gem5
+
#endif //__MEM_SERIAL_LINK_HH__
diff --git a/src/mem/simple_mem.cc b/src/mem/simple_mem.cc
index 332ee5b..ec46702 100644
--- a/src/mem/simple_mem.cc
+++ b/src/mem/simple_mem.cc
@@ -44,6 +44,9 @@
#include "base/trace.hh"
#include "debug/Drain.hh"
+namespace gem5
+{
+
SimpleMemory::SimpleMemory(const SimpleMemoryParams &p) :
AbstractMemory(p),
port(name() + ".port", *this), latency(p.latency),
@@ -299,3 +302,5 @@
{
mem.recvRespRetry();
}
+
+} // namespace gem5
diff --git a/src/mem/simple_mem.hh b/src/mem/simple_mem.hh
index 716bd41..153ea10 100644
--- a/src/mem/simple_mem.hh
+++ b/src/mem/simple_mem.hh
@@ -52,6 +52,9 @@
#include "mem/port.hh"
#include "params/SimpleMemory.hh"
+namespace gem5
+{
+
/**
* The simple memory is a basic single-ported memory controller with
* a configurable throughput and latency.
@@ -189,4 +192,6 @@
void recvRespRetry();
};
+} // namespace gem5
+
#endif //__MEM_SIMPLE_MEMORY_HH__
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index 42b5553..9aae680 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -244,6 +244,7 @@
class $py_ident(RubyController):
type = '$py_ident'
cxx_header = 'mem/ruby/protocol/${c_ident}.hh'
+ cxx_class = 'gem5::$py_ident'
''')
code.indent()
for param in self.config_parameters:
@@ -297,6 +298,9 @@
# for adding information to the protocol debug trace
code('''
+namespace gem5
+{
+
extern std::stringstream ${ident}_transitionComment;
class $c_ident : public AbstractController
@@ -451,8 +455,14 @@
code('${{var.type.c_ident}}$th* m_${{var.ident}}_ptr;')
code.dedent()
- code('};')
- code('#endif // __${ident}_CONTROLLER_H__')
+ code('''
+};
+
+} // namespace gem5
+
+#endif // __${ident}_CONTROLLER_H__
+''')
+
code.write(path, '%s.hh' % c_ident)
def printControllerCC(self, path, includes):
@@ -527,6 +537,9 @@
num_in_ports = len(self.in_ports)
code('''
+namespace gem5
+{
+
int $c_ident::m_num_controllers = 0;
std::vector<statistics::Vector *> $c_ident::eventVec;
std::vector<std::vector<statistics::Vector *> > $c_ident::transVec;
@@ -1197,6 +1210,8 @@
code('''
return read;
}
+
+} // namespace gem5
''')
code.write(path, "%s.cc" % c_ident)
@@ -1248,6 +1263,8 @@
port_to_buf_map, in_msg_bufs, msg_bufs = self.getBufferMaps(ident)
code('''
+namespace gem5
+{
void
${ident}_Controller::wakeup()
@@ -1323,6 +1340,8 @@
break;
}
}
+
+} // namespace gem5
''')
code.write(path, "%s_Wakeup.cc" % self.ident)
@@ -1353,6 +1372,9 @@
#define GET_TRANSITION_COMMENT() (${ident}_transitionComment.str())
#define CLEAR_TRANSITION_COMMENT() (${ident}_transitionComment.str(""))
+namespace gem5
+{
+
TransitionResult
${ident}_Controller::doTransition(${ident}_Event event,
''')
@@ -1580,6 +1602,8 @@
return TransitionResult_Valid;
}
+
+} // namespace gem5
''')
code.write(path, "%s_Transitions.cc" % self.ident)
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index c6013f8..639adff 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -222,6 +222,11 @@
code('#include "mem/ruby/protocol/$0.hh"', self["interface"])
parent = " : public %s" % self["interface"]
+ code('')
+ code('namespace gem5')
+ code('{')
+ code('')
+
code('''
$klass ${{self.c_ident}}$parent
{
@@ -381,14 +386,16 @@
code('};')
code('''
-inline std::ostream&
-operator<<(std::ostream& out, const ${{self.c_ident}}& obj)
+inline ::std::ostream&
+operator<<(::std::ostream& out, const ${{self.c_ident}}& obj)
{
obj.print(out);
- out << std::flush;
+ out << ::std::flush;
return out;
}
+} // namespace gem5
+
#endif // __${{self.c_ident}}_HH__
''')
@@ -405,6 +412,11 @@
#include "mem/ruby/system/RubySystem.hh"
''')
+ code('')
+ code('namespace gem5')
+ code('{')
+ code('')
+
code('''
/** \\brief Print the state of this object */
void
@@ -433,6 +445,10 @@
for item in self.methods:
code(self.methods[item].generateCode())
+ code('')
+ code('} // namespace gem5')
+ code('')
+
code.write(path, "%s.cc" % self.c_ident)
def printEnumHH(self, path):
@@ -453,6 +469,13 @@
code('#include "base/logging.hh"')
code('#include "mem/ruby/common/Address.hh"')
code('#include "mem/ruby/common/TypeDefines.hh"')
+
+ code('')
+ code('namespace gem5')
+ code('{')
+ code('')
+
+ if self.isMachineType:
code('struct MachineID;')
code('''
@@ -480,30 +503,15 @@
};
// Code to convert from a string to the enumeration
-${{self.c_ident}} string_to_${{self.c_ident}}(const std::string& str);
+${{self.c_ident}} string_to_${{self.c_ident}}(const ::std::string& str);
// Code to convert state to a string
-std::string ${{self.c_ident}}_to_string(const ${{self.c_ident}}& obj);
+::std::string ${{self.c_ident}}_to_string(const ${{self.c_ident}}& obj);
// Code to increment an enumeration type
${{self.c_ident}} &operator++(${{self.c_ident}} &e);
''')
- if self.isMachineType:
- code('''
-
-// define a hash function for the MachineType class
-namespace std {
-template<>
-struct hash<MachineType>
-{
- std::size_t operator()(const MachineType &mtype) const {
- return hash<size_t>()(static_cast<size_t>(mtype));
- }
-};
-}
-
-''')
# MachineType hack used to set the base component id for each Machine
if self.isMachineType:
code('''
@@ -527,10 +535,34 @@
''')
+ code('''
+
+::std::ostream&
+operator<<(::std::ostream& out, const ${{self.c_ident}}& obj);
+
+} // namespace gem5
+''')
+
+ if self.isMachineType:
+ code('''
+
+// define a hash function for the MachineType class
+namespace std {
+template<>
+struct hash<gem5::MachineType>
+{
+ std::size_t
+ operator()(const gem5::MachineType &mtype) const
+ {
+ return hash<size_t>()(static_cast<size_t>(mtype));
+ }
+};
+}
+
+''')
+
# Trailer
code('''
-std::ostream& operator<<(std::ostream& out, const ${{self.c_ident}}& obj);
-
#endif // __${{self.c_ident}}_HH__
''')
@@ -550,6 +582,9 @@
if self.isStateDecl:
code('''
+namespace gem5
+{
+
// Code to convert the current state to an access permission
AccessPermission ${{self.c_ident}}_to_permission(const ${{self.c_ident}}& obj)
{
@@ -569,6 +604,8 @@
return AccessPermission_Invalid;
}
+} // namespace gem5
+
''')
if self.isMachineType:
@@ -579,12 +616,15 @@
code('#include "mem/ruby/common/MachineID.hh"')
code('''
+namespace gem5
+{
+
// Code for output operator
-std::ostream&
-operator<<(std::ostream& out, const ${{self.c_ident}}& obj)
+::std::ostream&
+operator<<(::std::ostream& out, const ${{self.c_ident}}& obj)
{
out << ${{self.c_ident}}_to_string(obj);
- out << std::flush;
+ out << ::std::flush;
return out;
}
@@ -773,6 +813,10 @@
}
''')
+ code('')
+ code('} // namespace gem5')
+ code('')
+
# Write the file
code.write(path, "%s.cc" % self.c_ident)
diff --git a/src/mem/snoop_filter.cc b/src/mem/snoop_filter.cc
index 90fec6f..e2568b6 100644
--- a/src/mem/snoop_filter.cc
+++ b/src/mem/snoop_filter.cc
@@ -47,6 +47,9 @@
#include "debug/SnoopFilter.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
const int SnoopFilter::SNOOP_MASK_SIZE;
void
@@ -412,3 +415,5 @@
{
SimObject::regStats();
}
+
+} // namespace gem5
diff --git a/src/mem/snoop_filter.hh b/src/mem/snoop_filter.hh
index d85b3f5..7d4a222 100644
--- a/src/mem/snoop_filter.hh
+++ b/src/mem/snoop_filter.hh
@@ -54,6 +54,9 @@
#include "sim/sim_object.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
/**
* This snoop filter keeps track of which connected port has a
* particular line of data. It can be queried (through lookup*) on
@@ -348,4 +351,6 @@
return res;
}
+} // namespace gem5
+
#endif // __MEM_SNOOP_FILTER_HH__
diff --git a/src/mem/stack_dist_calc.cc b/src/mem/stack_dist_calc.cc
index 280e9cd..6912486 100644
--- a/src/mem/stack_dist_calc.cc
+++ b/src/mem/stack_dist_calc.cc
@@ -43,6 +43,9 @@
#include "base/trace.hh"
#include "debug/StackDist.hh"
+namespace gem5
+{
+
StackDistCalc::StackDistCalc(bool verify_stack)
: index(0),
verifyStack(verify_stack)
@@ -595,3 +598,5 @@
}
}
}
+
+} // namespace gem5
diff --git a/src/mem/stack_dist_calc.hh b/src/mem/stack_dist_calc.hh
index 81ff4e1..f62326a 100644
--- a/src/mem/stack_dist_calc.hh
+++ b/src/mem/stack_dist_calc.hh
@@ -44,6 +44,9 @@
#include "base/types.hh"
+namespace gem5
+{
+
/**
* The stack distance calculator is a passive object that merely
* observes the addresses pass to it. It calculates stack distances
@@ -411,5 +414,6 @@
const bool verifyStack;
};
+} // namespace gem5
#endif //__STACK_DIST_CALC_HH__
diff --git a/src/mem/token_port.cc b/src/mem/token_port.cc
index 2ab8f11..46032f2 100644
--- a/src/mem/token_port.cc
+++ b/src/mem/token_port.cc
@@ -37,6 +37,9 @@
#include "base/trace.hh"
#include "debug/TokenPort.hh"
+namespace gem5
+{
+
void
TokenRequestPort::bind(Port &peer)
{
@@ -179,3 +182,5 @@
DPRINTF(TokenPort, "Acquired %d tokens, have %d\n",
num_tokens, availableTokens);
}
+
+} // namespace gem5
diff --git a/src/mem/token_port.hh b/src/mem/token_port.hh
index 617b9f9..53e32a7 100644
--- a/src/mem/token_port.hh
+++ b/src/mem/token_port.hh
@@ -37,6 +37,9 @@
#include "mem/port.hh"
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
class TokenManager;
class TokenResponsePort;
@@ -160,4 +163,6 @@
void acquireTokens(int num_tokens);
};
+} // namespace gem5
+
#endif
diff --git a/src/mem/tport.cc b/src/mem/tport.cc
index 301dfb1..ad8512c 100644
--- a/src/mem/tport.cc
+++ b/src/mem/tport.cc
@@ -41,6 +41,9 @@
#include "mem/tport.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
SimpleTimingPort::SimpleTimingPort(const std::string& _name,
SimObject* _owner) :
QueuedResponsePort(_name, _owner, queueImpl), queueImpl(*_owner, *this)
@@ -81,3 +84,5 @@
return true;
}
+
+} // namespace gem5
diff --git a/src/mem/tport.hh b/src/mem/tport.hh
index fe32872..15efd31 100644
--- a/src/mem/tport.hh
+++ b/src/mem/tport.hh
@@ -49,6 +49,9 @@
#include "mem/qport.hh"
+namespace gem5
+{
+
class SimObject;
/**
@@ -104,4 +107,6 @@
};
+} // namespace gem5
+
#endif // __MEM_TPORT_HH__
diff --git a/src/mem/translating_port_proxy.cc b/src/mem/translating_port_proxy.cc
index e5117d0..97adcd1 100644
--- a/src/mem/translating_port_proxy.cc
+++ b/src/mem/translating_port_proxy.cc
@@ -51,6 +51,9 @@
#include "cpu/thread_context.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
TranslatingPortProxy::TranslatingPortProxy(
ThreadContext *tc, Request::Flags _flags) :
PortProxy(tc, tc->getSystemPtr()->cacheLineSize()), _tc(tc),
@@ -135,3 +138,5 @@
}
return true;
}
+
+} // namespace gem5
diff --git a/src/mem/translating_port_proxy.hh b/src/mem/translating_port_proxy.hh
index a5dfe7f..8d4c2e5 100644
--- a/src/mem/translating_port_proxy.hh
+++ b/src/mem/translating_port_proxy.hh
@@ -44,6 +44,9 @@
#include "arch/generic/tlb.hh"
#include "mem/port_proxy.hh"
+namespace gem5
+{
+
class ThreadContext;
/**
@@ -88,4 +91,6 @@
bool tryMemsetBlob(Addr address, uint8_t v, int size) const override;
};
+} // namespace gem5
+
#endif //__MEM_TRANSLATING_PORT_PROXY_HH__
diff --git a/src/mem/xbar.cc b/src/mem/xbar.cc
index ca746f5..e1b2a8b 100644
--- a/src/mem/xbar.cc
+++ b/src/mem/xbar.cc
@@ -51,6 +51,9 @@
#include "debug/Drain.hh"
#include "debug/XBar.hh"
+namespace gem5
+{
+
BaseXBar::BaseXBar(const BaseXBarParams &p)
: ClockedObject(p),
frontendLatency(p.frontend_latency),
@@ -602,3 +605,5 @@
*/
template class BaseXBar::Layer<ResponsePort, RequestPort>;
template class BaseXBar::Layer<RequestPort, ResponsePort>;
+
+} // namespace gem5
diff --git a/src/mem/xbar.hh b/src/mem/xbar.hh
index 640cacf..1df8b7e 100644
--- a/src/mem/xbar.hh
+++ b/src/mem/xbar.hh
@@ -56,6 +56,9 @@
#include "sim/clocked_object.hh"
#include "sim/stats.hh"
+namespace gem5
+{
+
/**
* The base crossbar contains the common elements of the non-coherent
* and coherent crossbar. It is an abstract class that does not have
@@ -411,4 +414,6 @@
void regStats() override;
};
+} // namespace gem5
+
#endif //__MEM_XBAR_HH__
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 2223cee..8d057c6 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -135,6 +135,9 @@
end_of_decl = ';'
code('#include "sim/cxx_config.hh"')
code()
+ code('namespace gem5')
+ code('{')
+ code()
code('class ${param_class} : public CxxConfigParams,'
' public ${name}Params')
code('{')
@@ -161,6 +164,8 @@
code('#include "base/str.hh"')
code('#include "cxx_config/${name}.hh"')
+ code('namespace gem5')
+ code('{')
code()
code('${member_prefix}DirectoryEntry::DirectoryEntry()');
code('{')
@@ -384,6 +389,8 @@
code.dedent()
code('};')
+ code('} // namespace gem5')
+
# The metaclass for SimObject. This class controls how new classes
# that derive from SimObject are instantiated, and provides inherited
# class behavior (just like a class controls how instances of that
@@ -745,6 +752,9 @@
code('''namespace py = pybind11;
+namespace gem5
+{
+
static void
module_init(py::module_ &m_internal)
{
@@ -813,11 +823,16 @@
code('static EmbeddedPyBind '
'embed_obj("${0}", module_init, "${1}");',
cls, cls._base.type if cls._base else "")
+ code()
+ code('} // namespace gem5')
# include the create() methods whether or not python is enabled.
if not hasattr(cls, 'abstract') or not cls.abstract:
if 'type' in cls.__dict__:
code()
+ code('namespace gem5')
+ code('{')
+ code()
code('namespace')
code('{')
code()
@@ -881,6 +896,8 @@
code(' return Dummy${cls}Shunt<${{cls.cxx_class}}>::')
code(' create(*this);')
code('}')
+ code()
+ code('} // namespace gem5')
_warned_about_nested_templates = False
@@ -1009,6 +1026,10 @@
code('#include "enums/${{ptype.__name__}}.hh"')
code()
+ code('namespace gem5')
+ code('{')
+ code('')
+
# now generate the actual param struct
code("struct ${cls}Params")
if cls._base:
@@ -1034,6 +1055,8 @@
code.dedent()
code('};')
+ code()
+ code('} // namespace gem5')
code()
code('#endif // __PARAMS__${cls}__')
@@ -1192,6 +1215,7 @@
abstract = True
cxx_header = "sim/sim_object.hh"
+ cxx_class = 'gem5::SimObject'
cxx_extra_bases = [ "Drainable", "Serializable", "statistics::Group" ]
eventq_index = Param.UInt32(Parent.eventq_index, "Event Queue Index")
diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index bcc2d96..67bba65 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -1325,6 +1325,8 @@
#ifndef $idem_macro
#define $idem_macro
+namespace gem5
+{
''')
if cls.is_class:
code('''\
@@ -1356,7 +1358,10 @@
if not cls.is_class:
code.dedent(1)
- code('};')
+ code('}; // $wrapper_name')
+
+ code()
+ code('} // namespace gem5')
code()
code('#endif // $idem_macro')
@@ -1368,6 +1373,12 @@
code('#include "base/compiler.hh"')
code('#include "enums/$file_name.hh"')
+
+ code()
+ code('namespace gem5')
+ code('{')
+ code()
+
if cls.wrapper_is_struct:
code('const char *${wrapper_name}::${name}Strings'
'[Num_${name}] =')
@@ -1392,7 +1403,9 @@
if not cls.wrapper_is_struct and not cls.is_class:
code.dedent(1)
- code('} // namespace $wrapper_name')
+ code('} // namespace enums')
+
+ code('} // namespace gem5')
def pybind_def(cls, code):
@@ -1407,6 +1420,9 @@
namespace py = pybind11;
+namespace gem5
+{
+
static void
module_init(py::module_ &m_internal)
{
@@ -1432,6 +1448,8 @@
code.dedent()
code()
code('static EmbeddedPyBind embed_enum("enum_${name}", module_init);')
+ code()
+ code('} // namespace gem5')
# Base class for enum types.
diff --git a/src/python/pybind11/core.cc b/src/python/pybind11/core.cc
index a000ccc..48878ca 100644
--- a/src/python/pybind11/core.cc
+++ b/src/python/pybind11/core.cc
@@ -61,6 +61,9 @@
namespace py = pybind11;
+namespace gem5
+{
+
/** Resolve a SimObject name using the Pybind configuration */
class PybindSimObjectResolver : public SimObjectResolver
{
@@ -323,3 +326,4 @@
init_loader(m_native);
}
+} // namespace gem5
diff --git a/src/python/pybind11/core.hh b/src/python/pybind11/core.hh
index 33562e8..d90854f 100644
--- a/src/python/pybind11/core.hh
+++ b/src/python/pybind11/core.hh
@@ -45,6 +45,6 @@
#include "base/addr_range.hh"
-PYBIND11_MAKE_OPAQUE(std::vector<AddrRange>);
+PYBIND11_MAKE_OPAQUE(std::vector<gem5::AddrRange>);
-#endif
+#endif // __PYTHON_PYBIND11_CORE_HH__
diff --git a/src/python/pybind11/debug.cc b/src/python/pybind11/debug.cc
index cca0f9c..e594176 100644
--- a/src/python/pybind11/debug.cc
+++ b/src/python/pybind11/debug.cc
@@ -52,6 +52,9 @@
namespace py = pybind11;
+namespace gem5
+{
+
namespace Debug {
extern int allFlagsVersion;
}
@@ -126,3 +129,5 @@
.def("disable", &Trace::disable)
;
}
+
+} // namespace gem5
diff --git a/src/python/pybind11/event.cc b/src/python/pybind11/event.cc
index 9d0621bb..794b6e3 100644
--- a/src/python/pybind11/event.cc
+++ b/src/python/pybind11/event.cc
@@ -51,6 +51,8 @@
namespace py = pybind11;
+namespace gem5
+{
/**
* PyBind wrapper for Events
@@ -183,3 +185,5 @@
PRIO(Sim_Exit_Pri);
PRIO(Maximum_Pri);
}
+
+} // namespace gem5
diff --git a/src/python/pybind11/object_file.cc b/src/python/pybind11/object_file.cc
index dbbeb9d..fcedeab 100644
--- a/src/python/pybind11/object_file.cc
+++ b/src/python/pybind11/object_file.cc
@@ -31,6 +31,9 @@
namespace py = pybind11;
+namespace gem5
+{
+
namespace
{
@@ -55,3 +58,4 @@
EmbeddedPyBind embed_("object_file", &objectfile_pybind);
} // anonymous namespace
+} // namespace gem5
diff --git a/src/python/pybind11/pybind.hh b/src/python/pybind11/pybind.hh
index 256120e..0f478da 100644
--- a/src/python/pybind11/pybind.hh
+++ b/src/python/pybind11/pybind.hh
@@ -41,10 +41,15 @@
#include "pybind11/pybind11.h"
#include "pybind11/stl.h"
+namespace gem5
+{
+
void pybind_init_core(pybind11::module_ &m_native);
void pybind_init_debug(pybind11::module_ &m_native);
void pybind_init_event(pybind11::module_ &m_native);
void pybind_init_stats(pybind11::module_ &m_native);
+} // namespace gem5
+
#endif
diff --git a/src/python/pybind11/stats.cc b/src/python/pybind11/stats.cc
index 91bf28c..2c60b47 100644
--- a/src/python/pybind11/stats.cc
+++ b/src/python/pybind11/stats.cc
@@ -54,6 +54,9 @@
namespace py = pybind11;
+namespace gem5
+{
+
static const py::object
cast_stat_info(const statistics::Info *info)
{
@@ -242,3 +245,5 @@
})
;
}
+
+} // namespace gem5
diff --git a/src/sim/ClockDomain.py b/src/sim/ClockDomain.py
index aad4736..61b2204 100644
--- a/src/sim/ClockDomain.py
+++ b/src/sim/ClockDomain.py
@@ -41,6 +41,7 @@
class ClockDomain(SimObject):
type = 'ClockDomain'
cxx_header = "sim/clock_domain.hh"
+ cxx_class = 'gem5::ClockDomain'
abstract = True
# Source clock domain with an actual clock, and a list of voltage and frequency
@@ -48,6 +49,7 @@
class SrcClockDomain(ClockDomain):
type = 'SrcClockDomain'
cxx_header = "sim/clock_domain.hh"
+ cxx_class = 'gem5::SrcClockDomain'
# Single clock frequency value, or list of frequencies for DVFS
# Frequencies must be ordered in descending order
@@ -73,5 +75,7 @@
class DerivedClockDomain(ClockDomain):
type = 'DerivedClockDomain'
cxx_header = "sim/clock_domain.hh"
+ cxx_class = 'gem5::DerivedClockDomain'
+
clk_domain = Param.ClockDomain("Parent clock domain")
clk_divider = Param.Unsigned(1, "Frequency divider")
diff --git a/src/sim/ClockedObject.py b/src/sim/ClockedObject.py
index 8732613..27a0e60 100644
--- a/src/sim/ClockedObject.py
+++ b/src/sim/ClockedObject.py
@@ -42,6 +42,7 @@
type = 'ClockedObject'
abstract = True
cxx_header = "sim/clocked_object.hh"
+ cxx_class = 'gem5::ClockedObject'
# The clock domain this clocked object belongs to, inheriting the
# parent's clock domain by default
diff --git a/src/sim/DVFSHandler.py b/src/sim/DVFSHandler.py
index 2c8f4dc..08e7f11 100644
--- a/src/sim/DVFSHandler.py
+++ b/src/sim/DVFSHandler.py
@@ -44,6 +44,7 @@
class DVFSHandler(SimObject):
type = 'DVFSHandler'
cxx_header = "sim/dvfs_handler.hh"
+ cxx_class = 'gem5::DVFSHandler'
# List of controllable clock domains which in turn reference the appropriate
# voltage domains
diff --git a/src/sim/InstTracer.py b/src/sim/InstTracer.py
index b7e6723..83fe077 100644
--- a/src/sim/InstTracer.py
+++ b/src/sim/InstTracer.py
@@ -29,6 +29,6 @@
class InstTracer(SimObject):
type = 'InstTracer'
- cxx_class = 'Trace::InstTracer'
- abstract = True
cxx_header = "sim/insttracer.hh"
+ cxx_class = 'gem5::Trace::InstTracer'
+ abstract = True
diff --git a/src/sim/PowerDomain.py b/src/sim/PowerDomain.py
index 9d45252..549d860 100644
--- a/src/sim/PowerDomain.py
+++ b/src/sim/PowerDomain.py
@@ -46,4 +46,4 @@
class PowerDomain(PowerState):
type = 'PowerDomain'
cxx_header = 'sim/power_domain.hh'
-
+ cxx_class = 'gem5::PowerDomain'
diff --git a/src/sim/PowerState.py b/src/sim/PowerState.py
index 30f62e0..e87a998 100644
--- a/src/sim/PowerState.py
+++ b/src/sim/PowerState.py
@@ -57,6 +57,7 @@
class PowerState(SimObject):
type = 'PowerState'
cxx_header = "sim/power_state.hh"
+ cxx_class = 'gem5::PowerState'
# Provide initial power state, should ideally get redefined in startup
# routine
diff --git a/src/sim/Process.py b/src/sim/Process.py
index 767dbfa..a20bdff 100644
--- a/src/sim/Process.py
+++ b/src/sim/Process.py
@@ -32,6 +32,7 @@
class Process(SimObject):
type = 'Process'
cxx_header = "sim/process.hh"
+ cxx_class = 'gem5::Process'
@cxxMethod
def map(self, vaddr, paddr, size, cacheable=False):
@@ -69,5 +70,6 @@
class EmulatedDriver(SimObject):
type = 'EmulatedDriver'
cxx_header = "sim/emul_driver.hh"
+ cxx_class = 'gem5::EmulatedDriver'
abstract = True
filename = Param.String("device file name (under /dev)")
diff --git a/src/sim/RedirectPath.py b/src/sim/RedirectPath.py
index b9e8b46..fb79c3d 100644
--- a/src/sim/RedirectPath.py
+++ b/src/sim/RedirectPath.py
@@ -36,6 +36,7 @@
"""
type = 'RedirectPath'
cxx_header = "sim/redirect_path.hh"
+ cxx_class = 'gem5::RedirectPath'
app_path = Param.String("/", "filesystem path from an app's perspective")
host_paths = VectorParam.String(["/"], "file path on host filesystem")
diff --git a/src/sim/Root.py b/src/sim/Root.py
index b818d43..bad3004 100644
--- a/src/sim/Root.py
+++ b/src/sim/Root.py
@@ -57,6 +57,7 @@
type = 'Root'
cxx_header = "sim/root.hh"
+ cxx_class = 'gem5::Root'
# By default, root sim object and hence all other sim objects schedule
# event on the eventq with index 0.
diff --git a/src/sim/SubSystem.py b/src/sim/SubSystem.py
index 735286d..8220ed6 100644
--- a/src/sim/SubSystem.py
+++ b/src/sim/SubSystem.py
@@ -47,6 +47,7 @@
class SubSystem(SimObject):
type = 'SubSystem'
cxx_header = "sim/sub_system.hh"
+ cxx_class = 'gem5::SubSystem'
abstract = False
# Thermal domain associated to this object, inheriting the parent's
diff --git a/src/sim/System.py b/src/sim/System.py
index 224a318..d7b88b0 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -56,6 +56,8 @@
class System(SimObject):
type = 'System'
cxx_header = "sim/system.hh"
+ cxx_class = 'gem5::System'
+
system_port = RequestPort("System port")
cxx_exports = [
diff --git a/src/sim/TickedObject.py b/src/sim/TickedObject.py
index 283edff..f6488df 100644
--- a/src/sim/TickedObject.py
+++ b/src/sim/TickedObject.py
@@ -39,3 +39,4 @@
type = 'TickedObject'
abstract = True
cxx_header = "sim/ticked_object.hh"
+ cxx_class = 'gem5::TickedObject'
diff --git a/src/sim/VoltageDomain.py b/src/sim/VoltageDomain.py
index 4ebdb18..4909e01 100644
--- a/src/sim/VoltageDomain.py
+++ b/src/sim/VoltageDomain.py
@@ -39,6 +39,7 @@
class VoltageDomain(SimObject):
type = 'VoltageDomain'
cxx_header = "sim/voltage_domain.hh"
+ cxx_class = 'gem5::VoltageDomain'
# Single or list of voltages for the voltage domain. If only a single
# voltage is specified, it is used for all different frequencies.
diff --git a/src/sim/Workload.py b/src/sim/Workload.py
index 91c1c55..62aa047 100644
--- a/src/sim/Workload.py
+++ b/src/sim/Workload.py
@@ -31,6 +31,7 @@
class Workload(SimObject):
type = 'Workload'
cxx_header = "sim/workload.hh"
+ cxx_class = 'gem5::Workload'
abstract = True
wait_for_remote_gdb = Param.Bool(False,
@@ -39,6 +40,7 @@
class KernelWorkload(Workload):
type = 'KernelWorkload'
cxx_header = "sim/kernel_workload.hh"
+ cxx_class = 'gem5::KernelWorkload'
object_file = Param.String("", "File that contains the kernel code")
extras = VectorParam.String([], "Additional object files to load")
@@ -64,7 +66,7 @@
class SEWorkload(Workload, metaclass=SEWorkloadMeta):
type = 'SEWorkload'
cxx_header = "sim/se_workload.hh"
- cxx_class = 'SEWorkload'
+ cxx_class = 'gem5::SEWorkload'
@classmethod
def _is_compatible_with(cls, obj):
diff --git a/src/sim/async.cc b/src/sim/async.cc
index d8cbfda..b69552d 100644
--- a/src/sim/async.cc
+++ b/src/sim/async.cc
@@ -26,6 +26,9 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+namespace gem5
+{
+
volatile bool async_event = false;
volatile bool async_statdump = false;
volatile bool async_statreset = false;
@@ -33,3 +36,4 @@
volatile bool async_io = false;
volatile bool async_exception = false;
+} // namespace gem5
diff --git a/src/sim/async.hh b/src/sim/async.hh
index 8a6f602..a271a9f 100644
--- a/src/sim/async.hh
+++ b/src/sim/async.hh
@@ -29,6 +29,9 @@
#ifndef __ASYNC_HH__
#define __ASYNC_HH__
+namespace gem5
+{
+
///
/// @file sim/async.hh
/// This file defines flags used to handle asynchronous simulator events.
@@ -46,4 +49,6 @@
extern volatile bool async_exception; ///< Python exception.
//@}
+} // namespace gem5
+
#endif // __ASYNC_HH__
diff --git a/src/sim/aux_vector.hh b/src/sim/aux_vector.hh
index 30b7777..7ab5e10 100644
--- a/src/sim/aux_vector.hh
+++ b/src/sim/aux_vector.hh
@@ -39,8 +39,7 @@
namespace gem5
{
-namespace auxv
-{
+namespace auxv {
template<class IntType>
class AuxVector
@@ -54,7 +53,7 @@
};
// Ensure the global versions of swap_byte are visible.
-using ::swap_byte;
+using gem5::swap_byte;
// Define swap_byte in this namespace, so argument dependent resolution can
// find it.
@@ -95,8 +94,6 @@
} // namespace auxv
-} // namespace gem5
-
#define GEM5_DEPRECATE_AT(NAME, name) M5_AT_##NAME \
GEM5_DEPRECATED_ENUM_VAL(\
"Replace M5_AT_" #NAME " with gem5::auxv::" #name) = gem5::auxv::name
@@ -138,4 +135,6 @@
"The AuxVector template is now in the gem5::auxv namespace.") =
gem5::auxv::AuxVector<IntType>;
+} // namespace gem5
+
#endif // __AUX_VECTOR_HH__
diff --git a/src/sim/backtrace.hh b/src/sim/backtrace.hh
index dc191fc..7090d0d 100644
--- a/src/sim/backtrace.hh
+++ b/src/sim/backtrace.hh
@@ -38,6 +38,9 @@
#ifndef __SIM_BACKTRACE_HH__
#define __SIM_BACKTRACE_HH__
+namespace gem5
+{
+
/**
* Print a gem5 post-mortem report
*
@@ -46,4 +49,6 @@
*/
void print_backtrace();
+} // namespace gem5
+
#endif // __SIM_BACKTRACE_HH__
diff --git a/src/sim/backtrace_glibc.cc b/src/sim/backtrace_glibc.cc
index 1c9425c..0257143 100644
--- a/src/sim/backtrace_glibc.cc
+++ b/src/sim/backtrace_glibc.cc
@@ -41,6 +41,9 @@
#include "base/atomicio.hh"
#include "sim/backtrace.hh"
+namespace gem5
+{
+
#define SAFE_MSG(m) \
do { \
static const char msg[] = m; \
@@ -61,3 +64,5 @@
STATIC_ERR("Warning: Backtrace may have been truncated.\n");
STATIC_ERR("--- END LIBC BACKTRACE ---\n");
}
+
+} // namespace gem5
diff --git a/src/sim/backtrace_none.cc b/src/sim/backtrace_none.cc
index 601b1ca..15dfb4c 100644
--- a/src/sim/backtrace_none.cc
+++ b/src/sim/backtrace_none.cc
@@ -37,7 +37,12 @@
#include "sim/backtrace.hh"
+namespace gem5
+{
+
void
print_backtrace()
{
}
+
+} // namespace gem5
diff --git a/src/sim/byteswap.hh b/src/sim/byteswap.hh
index 82282ec..222c2c2 100644
--- a/src/sim/byteswap.hh
+++ b/src/sim/byteswap.hh
@@ -58,8 +58,12 @@
struct vring_used_elem;
struct vring_desc;
+namespace gem5
+{
+
// These functions actually perform the swapping for parameters of various bit
// lengths.
+
inline uint64_t
swap_byte64(uint64_t x)
{
@@ -193,4 +197,6 @@
betoh(value) : letoh(value);
}
+} // namespace gem5
+
#endif // __SIM_BYTE_SWAP_HH__
diff --git a/src/sim/byteswap.test.cc b/src/sim/byteswap.test.cc
index 27e1fc6..0aacc3f 100644
--- a/src/sim/byteswap.test.cc
+++ b/src/sim/byteswap.test.cc
@@ -30,6 +30,8 @@
#include "sim/byteswap.hh"
+using namespace gem5;
+
TEST(ByteswapTest, swap_byte64)
{
EXPECT_EQ(0x0123456789abcdef, swap_byte64(0xefcdab8967452301));
diff --git a/src/sim/clock_domain.cc b/src/sim/clock_domain.cc
index 9d691e1..572cd4e 100644
--- a/src/sim/clock_domain.cc
+++ b/src/sim/clock_domain.cc
@@ -51,6 +51,9 @@
#include "sim/serialize.hh"
#include "sim/voltage_domain.hh"
+namespace gem5
+{
+
ClockDomain::ClockDomainStats::ClockDomainStats(ClockDomain &cd)
: statistics::Group(&cd),
ADD_STAT(clock, statistics::units::Tick::get(), "Clock period in ticks")
@@ -223,3 +226,5 @@
(*c)->updateClockPeriod();
}
}
+
+} // namespace gem5
diff --git a/src/sim/clock_domain.hh b/src/sim/clock_domain.hh
index 12ad6de..8789255 100644
--- a/src/sim/clock_domain.hh
+++ b/src/sim/clock_domain.hh
@@ -52,6 +52,9 @@
#include "params/SrcClockDomain.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
/**
* Forward declaration
*/
@@ -298,4 +301,6 @@
const uint64_t clockDivider;
};
+} // namespace gem5
+
#endif
diff --git a/src/sim/clocked_object.cc b/src/sim/clocked_object.cc
index e407519..78fc8cf 100644
--- a/src/sim/clocked_object.cc
+++ b/src/sim/clocked_object.cc
@@ -40,6 +40,9 @@
#include "base/logging.hh"
#include "sim/power/power_model.hh"
+namespace gem5
+{
+
ClockedObject::ClockedObject(const ClockedObjectParams &p) :
SimObject(p), Clocked(*p.clk_domain), powerState(p.power_state)
{
@@ -62,3 +65,5 @@
{
powerState->unserialize(cp);
}
+
+} // namespace gem5
diff --git a/src/sim/clocked_object.hh b/src/sim/clocked_object.hh
index 0f12143..a67449a 100644
--- a/src/sim/clocked_object.hh
+++ b/src/sim/clocked_object.hh
@@ -51,6 +51,9 @@
#include "sim/power_state.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
/**
* Helper class for objects that need to be clocked. Clocked objects
* typically inherit from this class. Objects that need SimObject
@@ -242,4 +245,6 @@
PowerState *powerState;
};
+} // namespace gem5
+
#endif //__SIM_CLOCKED_OBJECT_HH__
diff --git a/src/sim/core.cc b/src/sim/core.cc
index d0d0376..c388652 100644
--- a/src/sim/core.cc
+++ b/src/sim/core.cc
@@ -38,6 +38,9 @@
#include "base/logging.hh"
#include "base/output.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(SimClock, sim_clock);
namespace sim_clock
{
@@ -158,3 +161,4 @@
std::cout.flush();
}
+} // namespace gem5
diff --git a/src/sim/core.hh b/src/sim/core.hh
index 66f3fca..02ff137 100644
--- a/src/sim/core.hh
+++ b/src/sim/core.hh
@@ -44,6 +44,9 @@
// until the transitive includes are fixed
#include "sim/cur_tick.hh"
+namespace gem5
+{
+
/// These are variables that are set based on the simulator frequency
///@{
GEM5_DEPRECATED_NAMESPACE(SimClock, sim_clock);
@@ -105,4 +108,6 @@
void registerExitCallback(const std::function<void()> &callback);
void doExitCleanup();
+} // namespace gem5
+
#endif /* __SIM_CORE_HH__ */
diff --git a/src/sim/cur_tick.cc b/src/sim/cur_tick.cc
index 630a7fb..4c73d2b 100644
--- a/src/sim/cur_tick.cc
+++ b/src/sim/cur_tick.cc
@@ -28,9 +28,13 @@
#include "sim/cur_tick.hh"
+namespace gem5
+{
+
namespace Gem5Internal
{
__thread Tick *_curTickPtr;
} // namespace Gem5Internal
+} // namespace gem5
diff --git a/src/sim/cur_tick.hh b/src/sim/cur_tick.hh
index 0aee611..12d2372 100644
--- a/src/sim/cur_tick.hh
+++ b/src/sim/cur_tick.hh
@@ -31,6 +31,9 @@
#include "base/types.hh"
+namespace gem5
+{
+
namespace Gem5Internal
{
@@ -42,4 +45,6 @@
/// The universal simulation clock.
inline Tick curTick() { return *Gem5Internal::_curTickPtr; }
+} // namespace gem5
+
#endif /* __SIM_CUR_TICK_HH__ */
diff --git a/src/sim/cxx_config.cc b/src/sim/cxx_config.cc
index b5cd946..dc25402 100644
--- a/src/sim/cxx_config.cc
+++ b/src/sim/cxx_config.cc
@@ -37,7 +37,12 @@
#include "sim/cxx_config.hh"
+namespace gem5
+{
+
const std::string CxxConfigParams::invalidName = "<invalid>";
/** Directory of all SimObject classes config details */
std::map<std::string, CxxConfigDirectoryEntry *> cxx_config_directory;
+
+} // namespace gem5
diff --git a/src/sim/cxx_config.hh b/src/sim/cxx_config.hh
index 9a45e76..081860a 100644
--- a/src/sim/cxx_config.hh
+++ b/src/sim/cxx_config.hh
@@ -57,6 +57,9 @@
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class CxxConfigParams;
/** Config details entry for a SimObject. Instances of this class contain
@@ -129,7 +132,7 @@
/** Flags passable to setParam... to smooth over any parsing difference
* between different config files */
typedef uint32_t FlagsType;
- typedef ::Flags<FlagsType> Flags;
+ typedef gem5::Flags<FlagsType> Flags;
/** Example flag */
/* static const FlagsType MY_NEW_FLAG = 0x00000001; */
@@ -234,4 +237,6 @@
* auto-generated .../cxx_config/init.cc */
void cxxConfigInit();
+} // namespace gem5
+
#endif // __SIM_CXX_CONFIG_HH__
diff --git a/src/sim/cxx_config_ini.cc b/src/sim/cxx_config_ini.cc
index fbaa551..a991c30 100644
--- a/src/sim/cxx_config_ini.cc
+++ b/src/sim/cxx_config_ini.cc
@@ -39,6 +39,9 @@
#include "base/str.hh"
+namespace gem5
+{
+
bool
CxxIniFile::getParam(const std::string &object_name,
const std::string ¶m_name,
@@ -102,3 +105,5 @@
{
return iniFile.load(filename);
}
+
+} // namespace gem5
diff --git a/src/sim/cxx_config_ini.hh b/src/sim/cxx_config_ini.hh
index 2b9dcee..1705ae2 100644
--- a/src/sim/cxx_config_ini.hh
+++ b/src/sim/cxx_config_ini.hh
@@ -47,6 +47,9 @@
#include "base/inifile.hh"
#include "sim/cxx_config.hh"
+namespace gem5
+{
+
/** CxxConfigManager interface for using .ini files */
class CxxIniFile : public CxxConfigFileBase
{
@@ -81,4 +84,6 @@
bool load(const std::string &filename);
};
+} // namespace gem5
+
#endif // __SIM_CXX_CONFIG_INI_HH__
diff --git a/src/sim/cxx_manager.cc b/src/sim/cxx_manager.cc
index 7df3bca..9c25091 100644
--- a/src/sim/cxx_manager.cc
+++ b/src/sim/cxx_manager.cc
@@ -46,6 +46,9 @@
#include "sim/serialize.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
CxxConfigManager::CxxConfigManager(CxxConfigFileBase &configFile_) :
configFile(configFile_), flags(configFile_.getFlags()),
simObjectResolver(*this)
@@ -713,3 +716,5 @@
{
renamings.push_back(renaming);
}
+
+} // namespace gem5
diff --git a/src/sim/cxx_manager.hh b/src/sim/cxx_manager.hh
index e2cbadd..75df4fc 100644
--- a/src/sim/cxx_manager.hh
+++ b/src/sim/cxx_manager.hh
@@ -59,6 +59,9 @@
#include "base/cprintf.hh"
#include "sim/cxx_config.hh"
+namespace gem5
+{
+
class CheckpointIn;
/** This class allows a config file to be read into gem5 (generating the
@@ -151,7 +154,7 @@
/** Class for resolving SimObject names to SimObjects usable by the
* checkpoint restore mechanism */
- class SimObjectResolver : public ::SimObjectResolver
+ class SimObjectResolver : public gem5::SimObjectResolver
{
protected:
CxxConfigManager &configManager;
@@ -309,4 +312,6 @@
const std::vector<std::string> ¶m_values);
};
+} // namespace gem5
+
#endif // __SIM_CXX_MANAGER_HH__
diff --git a/src/sim/debug.cc b/src/sim/debug.cc
index 4144caf..6b9d873 100644
--- a/src/sim/debug.cc
+++ b/src/sim/debug.cc
@@ -40,6 +40,9 @@
#include "sim/sim_exit.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
//
// Debug event: place a breakpoint on the process function and
// schedule the event to break at a particular cycle
@@ -127,3 +130,4 @@
remote_gdb_base_port = port;
}
+} // namespace gem5
diff --git a/src/sim/debug.hh b/src/sim/debug.hh
index d265914..ed59304 100644
--- a/src/sim/debug.hh
+++ b/src/sim/debug.hh
@@ -36,6 +36,8 @@
* gdb.
*/
+namespace gem5
+{
/** Cause the simulator to execute a breakpoint
* @param when the tick to break
@@ -62,4 +64,6 @@
// Remote gdb base port. 0 disables remote gdb.
void setRemoteGDBPort(int port);
+} // namespace gem5
+
#endif // __SIM_DEBUG_HH__
diff --git a/src/sim/drain.cc b/src/sim/drain.cc
index 96d13d1..b15cdb6 100644
--- a/src/sim/drain.cc
+++ b/src/sim/drain.cc
@@ -45,6 +45,9 @@
#include "debug/Drain.hh"
#include "sim/sim_exit.hh"
+namespace gem5
+{
+
DrainManager DrainManager::_instance;
DrainManager::DrainManager()
@@ -224,3 +227,5 @@
_drainState = DrainState::Running;
drainResume();
}
+
+} // namespace gem5
diff --git a/src/sim/drain.hh b/src/sim/drain.hh
index ea44423..eb6712a 100644
--- a/src/sim/drain.hh
+++ b/src/sim/drain.hh
@@ -42,6 +42,9 @@
#include <mutex>
#include <vector>
+namespace gem5
+{
+
class Drainable;
/**
@@ -357,4 +360,6 @@
mutable DrainState _drainState;
};
+} // namespace gem5
+
#endif
diff --git a/src/sim/dvfs_handler.cc b/src/sim/dvfs_handler.cc
index 5213e0f..83a12aa 100644
--- a/src/sim/dvfs_handler.cc
+++ b/src/sim/dvfs_handler.cc
@@ -47,6 +47,9 @@
#include "sim/stat_control.hh"
#include "sim/voltage_domain.hh"
+namespace gem5
+{
+
//
//
// DVFSHandler methods implementation
@@ -249,3 +252,5 @@
}
UpdateEvent::dvfsHandler = this;
}
+
+} // namespace gem5
diff --git a/src/sim/dvfs_handler.hh b/src/sim/dvfs_handler.hh
index db32544..bf1b68b 100644
--- a/src/sim/dvfs_handler.hh
+++ b/src/sim/dvfs_handler.hh
@@ -58,6 +58,9 @@
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
/**
* DVFS Handler class, maintains a list of all the domains it can handle.
* Each entry of that list is an object of the DomainConfig class, and the
@@ -262,4 +265,6 @@
UpdatePerfLevelEvents updatePerfLevelEvents;
};
+} // namespace gem5
+
#endif // __SIM_DVFS_HANDLER_HH__
diff --git a/src/sim/emul_driver.hh b/src/sim/emul_driver.hh
index 1924b46..eb4365b 100644
--- a/src/sim/emul_driver.hh
+++ b/src/sim/emul_driver.hh
@@ -36,6 +36,9 @@
#include "params/EmulatedDriver.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class Process;
class ThreadContext;
@@ -97,4 +100,6 @@
{ return -EBADF; }
};
+} // namespace gem5
+
#endif // __SIM_EMUL_DRIVER_HH
diff --git a/src/sim/eventq.cc b/src/sim/eventq.cc
index f6eeb03..4d93adc 100644
--- a/src/sim/eventq.cc
+++ b/src/sim/eventq.cc
@@ -43,6 +43,9 @@
#include "debug/Checkpoint.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
Tick simQuantum = 0;
//
@@ -439,3 +442,5 @@
async_queue_mutex.unlock();
}
+
+} // namespace gem5
diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index 774881b..b996281 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -52,6 +52,9 @@
#include "sim/core.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
class EventQueue; // forward declaration
class BaseGlobalEvent;
@@ -94,7 +97,7 @@
{
protected:
typedef unsigned short FlagsType;
- typedef ::Flags<FlagsType> Flags;
+ typedef ::gem5::Flags<FlagsType> Flags;
static const FlagsType PublicRead = 0x003f; // public readable flags
static const FlagsType PublicWrite = 0x001d; // public writable flags
@@ -1170,4 +1173,6 @@
eventQueue()->checkpointReschedule(&event); \
} while (0)
+} // namespace gem5
+
#endif // __SIM_EVENTQ_HH__
diff --git a/src/sim/faults.cc b/src/sim/faults.cc
index e4f4ae1..fb63cf3 100644
--- a/src/sim/faults.cc
+++ b/src/sim/faults.cc
@@ -52,6 +52,9 @@
#include "sim/full_system.hh"
#include "sim/process.hh"
+namespace gem5
+{
+
void
FaultBase::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
@@ -128,3 +131,5 @@
// send abort packet to ruby (in final breath)
tc->htmAbortTransaction(htmUid, cause);
}
+
+} // namespace gem5
diff --git a/src/sim/faults.hh b/src/sim/faults.hh
index fc19b8e..b1c358c 100644
--- a/src/sim/faults.hh
+++ b/src/sim/faults.hh
@@ -47,6 +47,9 @@
#include "mem/htm.hh"
#include "sim/stats.hh"
+namespace gem5
+{
+
class ThreadContext;
typedef const char *FaultName;
@@ -153,4 +156,6 @@
nullStaticInstPtr) override;
};
+} // namespace gem5
+
#endif // __FAULTS_HH__
diff --git a/src/sim/fd_array.cc b/src/sim/fd_array.cc
index 0da9978..c371c4d 100644
--- a/src/sim/fd_array.cc
+++ b/src/sim/fd_array.cc
@@ -45,6 +45,9 @@
#include "params/Process.hh"
#include "sim/fd_entry.hh"
+namespace gem5
+{
+
FDArray::FDArray(std::string const& input, std::string const& output,
std::string const& errout)
: _fdArray(), _input(input), _output(output), _errout(errout),
@@ -429,3 +432,5 @@
lseek(sim_fd, file_offset, SEEK_SET);
}
}
+
+} // namespace gem5
diff --git a/src/sim/fd_array.hh b/src/sim/fd_array.hh
index e80673f..492865b 100644
--- a/src/sim/fd_array.hh
+++ b/src/sim/fd_array.hh
@@ -42,6 +42,9 @@
#include "sim/fd_entry.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
class FDArray : public Serializable
{
public:
@@ -162,4 +165,6 @@
std::map<std::string, int> _oemap;
};
+} // namespace gem5
+
#endif // __FD_ARRAY_HH__
diff --git a/src/sim/fd_entry.cc b/src/sim/fd_entry.cc
index 6861a94..a716002 100644
--- a/src/sim/fd_entry.cc
+++ b/src/sim/fd_entry.cc
@@ -35,6 +35,9 @@
#include "sim/serialize.hh"
+namespace gem5
+{
+
void
FDEntry::serialize(CheckpointOut &cp) const
{
@@ -98,3 +101,5 @@
//UNSERIALIZE_SCALAR(_driver);
UNSERIALIZE_SCALAR(_fileName);
}
+
+} // namespace gem5
diff --git a/src/sim/fd_entry.hh b/src/sim/fd_entry.hh
index 50a9e60..5301ee1 100644
--- a/src/sim/fd_entry.hh
+++ b/src/sim/fd_entry.hh
@@ -40,6 +40,9 @@
#include "sim/serialize.hh"
+namespace gem5
+{
+
class EmulatedDriver;
@@ -264,4 +267,6 @@
int _protocol;
};
+} // namespace gem5
+
#endif // __FD_ENTRY_HH__
diff --git a/src/sim/full_system.hh b/src/sim/full_system.hh
index a5d48b6..9f5a974 100644
--- a/src/sim/full_system.hh
+++ b/src/sim/full_system.hh
@@ -29,6 +29,9 @@
#ifndef __SIM_FULL_SYSTEM_HH__
#define __SIM_FULL_SYSTEM_HH__
+namespace gem5
+{
+
/**
* The FullSystem variable can be used to determine the current mode
* of simulation.
@@ -43,4 +46,6 @@
*/
extern unsigned int FullSystemInt;
+} // namespace gem5
+
#endif // __SIM_FULL_SYSTEM_HH__
diff --git a/src/sim/futex_map.cc b/src/sim/futex_map.cc
index 7dabaf2..8f622e2 100644
--- a/src/sim/futex_map.cc
+++ b/src/sim/futex_map.cc
@@ -28,6 +28,9 @@
#include <sim/futex_map.hh>
+namespace gem5
+{
+
FutexKey::FutexKey(uint64_t addr_in, uint64_t tgid_in)
: addr(addr_in), tgid(tgid_in) {}
@@ -37,18 +40,6 @@
return addr == in.addr && tgid == in.tgid;
}
-namespace std {
- size_t hash<FutexKey>::operator()(const FutexKey& in) const
- {
- size_t hash = 65521;
- for (int i = 0; i < sizeof(uint64_t) / sizeof(size_t); i++) {
- hash ^= (size_t)(in.addr >> sizeof(size_t) * i) ^
- (size_t)(in.tgid >> sizeof(size_t) * i);
- }
- return hash;
- }
-}
-
WaiterState::WaiterState(ThreadContext* _tc, int _bitmask)
: tc(_tc), bitmask(_bitmask) { }
@@ -195,3 +186,5 @@
{
return waitingTcs.find(tc) != waitingTcs.end();
}
+
+} // namespace gem5
diff --git a/src/sim/futex_map.hh b/src/sim/futex_map.hh
index a8a8141..9348c43 100644
--- a/src/sim/futex_map.hh
+++ b/src/sim/futex_map.hh
@@ -34,6 +34,9 @@
#include <cpu/thread_context.hh>
+namespace gem5
+{
+
/**
* FutexKey class defines an unique identifier for a particular futex in the
* system. The tgid and an address are the unique values needed as the key.
@@ -49,18 +52,32 @@
bool operator==(const FutexKey &in) const;
};
-namespace std {
+} // namespace gem5
+
+namespace std
+{
/**
* The unordered_map structure needs the parenthesis operator defined for
* std::hash if a user defined key is used. Our key is is user defined
* so we need to provide the hash functor.
*/
template <>
- struct hash<FutexKey>
+ struct hash<gem5::FutexKey>
{
- size_t operator()(const FutexKey& in) const;
+ size_t operator()(const gem5::FutexKey& in) const
+ {
+ size_t hash = 65521;
+ for (int i = 0; i < sizeof(uint64_t) / sizeof(size_t); i++) {
+ hash ^= (size_t)(in.addr >> sizeof(size_t) * i) ^
+ (size_t)(in.tgid >> sizeof(size_t) * i);
+ }
+ return hash;
+ }
};
-}
+} // namespace std
+
+namespace gem5
+{
/**
* WaiterState defines internal state of a waiter thread. The state
@@ -126,4 +143,6 @@
std::unordered_set<ThreadContext *> waitingTcs;
};
+} // namespace gem5
+
#endif // __FUTEX_MAP_HH__
diff --git a/src/sim/global_event.cc b/src/sim/global_event.cc
index 1f1bfc1..700d2c8 100644
--- a/src/sim/global_event.cc
+++ b/src/sim/global_event.cc
@@ -31,6 +31,9 @@
#include "sim/core.hh"
+namespace gem5
+{
+
std::mutex BaseGlobalEvent::globalQMutex;
BaseGlobalEvent::BaseGlobalEvent(Priority p, Flags f)
@@ -164,3 +167,5 @@
{
return "GlobalSyncEvent";
}
+
+} // namespace gem5
diff --git a/src/sim/global_event.hh b/src/sim/global_event.hh
index 8e4254b..05ae6ca 100644
--- a/src/sim/global_event.hh
+++ b/src/sim/global_event.hh
@@ -36,6 +36,9 @@
#include "base/barrier.hh"
#include "sim/eventq.hh"
+namespace gem5
+{
+
/**
* @file sim/global_event.hh
* Global events and related declarations.
@@ -233,5 +236,6 @@
Tick repeat;
};
+} // namespace gem5
#endif // __SIM_GLOBAL_EVENT_HH__
diff --git a/src/sim/globals.cc b/src/sim/globals.cc
index e3f0c21..f2962d9 100644
--- a/src/sim/globals.cc
+++ b/src/sim/globals.cc
@@ -48,6 +48,9 @@
#include "base/logging.hh"
#include "sim/cur_tick.hh"
+namespace gem5
+{
+
/// The version tags for this build of the simulator, to be stored in the
/// Globals section during serialization and compared upon unserialization.
extern std::set<std::string> version_tags;
@@ -119,3 +122,5 @@
warn(divider);
}
}
+
+} // namespace gem5
diff --git a/src/sim/globals.hh b/src/sim/globals.hh
index 8aca7d9..30b0b5f 100644
--- a/src/sim/globals.hh
+++ b/src/sim/globals.hh
@@ -46,6 +46,9 @@
#include "base/types.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
/// Container for serializing global variables (not associated with
/// any serialized object).
class Globals : public Serializable
@@ -60,4 +63,6 @@
Tick unserializedCurTick;
};
+} // namespace gem5
+
#endif // __SIM_GLOBALS_HH__
diff --git a/src/sim/guest_abi.hh b/src/sim/guest_abi.hh
index 96fcf89..2e5a901 100644
--- a/src/sim/guest_abi.hh
+++ b/src/sim/guest_abi.hh
@@ -35,6 +35,9 @@
#include "sim/guest_abi/layout.hh"
#include "sim/guest_abi/varargs.hh"
+namespace gem5
+{
+
class ThreadContext;
// These functions wrap a simulator level function with the given signature.
@@ -127,4 +130,6 @@
name, tc, std::function<Ret(ThreadContext *, Args...)>(target));
}
+} // namespace gem5
+
#endif // __SIM_GUEST_ABI_HH__
diff --git a/src/sim/guest_abi.test.cc b/src/sim/guest_abi.test.cc
index 19f3c30..7ba57ac 100644
--- a/src/sim/guest_abi.test.cc
+++ b/src/sim/guest_abi.test.cc
@@ -32,6 +32,10 @@
#include "sim/guest_abi.hh"
+using namespace gem5;
+
+namespace gem5
+{
// Fake ThreadContext which holds data and captures results.
class ThreadContext
{
@@ -58,6 +62,8 @@
const int ThreadContext::DefaultIntResult = 0;
const double ThreadContext::DefaultFloatResult = 0.0;
+} // namespace gem5
+
// ABI anchor for an ABI which has 1D progress. Conceptually, this could be
// because integer and floating point arguments are stored in the same
// registers.
@@ -89,6 +95,9 @@
};
};
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi);
namespace guest_abi
{
@@ -224,6 +233,7 @@
};
} // namespace guest_abi
+} // namespace gem5
// Test function which verifies that its arguments reflect the 1D ABI and
// which doesn't return anything.
diff --git a/src/sim/guest_abi/definition.hh b/src/sim/guest_abi/definition.hh
index 3f4fb21..2857b5b 100644
--- a/src/sim/guest_abi/definition.hh
+++ b/src/sim/guest_abi/definition.hh
@@ -30,6 +30,9 @@
#include "base/compiler.hh"
+namespace gem5
+{
+
class ThreadContext;
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi);
@@ -117,5 +120,6 @@
};
} // namespace guest_abi
+} // namespace gem5
#endif // __SIM_GUEST_ABI_DEFINITION_HH__
diff --git a/src/sim/guest_abi/dispatch.hh b/src/sim/guest_abi/dispatch.hh
index a420144..b29e5c8 100644
--- a/src/sim/guest_abi/dispatch.hh
+++ b/src/sim/guest_abi/dispatch.hh
@@ -38,6 +38,9 @@
#include "sim/guest_abi/definition.hh"
#include "sim/guest_abi/layout.hh"
+namespace gem5
+{
+
class ThreadContext;
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi);
@@ -109,5 +112,6 @@
}
} // namespace guest_abi
+} // namespace gem5
#endif // __SIM_GUEST_ABI_DISPATCH_HH__
diff --git a/src/sim/guest_abi/layout.hh b/src/sim/guest_abi/layout.hh
index 19d8ba8..ed86f57 100644
--- a/src/sim/guest_abi/layout.hh
+++ b/src/sim/guest_abi/layout.hh
@@ -33,6 +33,9 @@
#include "base/compiler.hh"
#include "sim/guest_abi/definition.hh"
+namespace gem5
+{
+
class ThreadContext;
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi);
@@ -170,5 +173,6 @@
}
} // namespace guest_abi
+} // namespace gem5
#endif // __SIM_GUEST_ABI_LAYOUT_HH__
diff --git a/src/sim/guest_abi/varargs.hh b/src/sim/guest_abi/varargs.hh
index f80cce6..a0f6b4e 100644
--- a/src/sim/guest_abi/varargs.hh
+++ b/src/sim/guest_abi/varargs.hh
@@ -34,6 +34,9 @@
#include "sim/guest_abi/definition.hh"
+namespace gem5
+{
+
class ThreadContext;
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi);
@@ -198,5 +201,6 @@
};
} // namespace guest_abi
+} // namespace gem5
#endif // __SIM_GUEST_ABI_VARARGS_HH__
diff --git a/src/sim/init.cc b/src/sim/init.cc
index 3b34ff6..8b3d46d 100644
--- a/src/sim/init.cc
+++ b/src/sim/init.cc
@@ -67,6 +67,9 @@
namespace py = pybind11;
+namespace gem5
+{
+
// The python library is totally messed up with respect to constness,
// so make a simple macro to make life a little easier
#define PyCC(x) (const_cast<char *>(x))
@@ -313,3 +316,5 @@
return 0;
}
+
+} // namespace gem5
diff --git a/src/sim/init.hh b/src/sim/init.hh
index 553d2c5..a20d3b6 100644
--- a/src/sim/init.hh
+++ b/src/sim/init.hh
@@ -54,6 +54,9 @@
typedef _object PyObject;
#endif
+namespace gem5
+{
+
/*
* Data structure describing an embedded python file.
*/
@@ -111,4 +114,6 @@
int m5Main(int argc, char **argv);
+} // namespace gem5
+
#endif // __SIM_INIT_HH__
diff --git a/src/sim/init_signals.cc b/src/sim/init_signals.cc
index db82682..803d7e2 100644
--- a/src/sim/init_signals.cc
+++ b/src/sim/init_signals.cc
@@ -61,6 +61,9 @@
#include "sim/core.hh"
#include "sim/eventq.hh"
+namespace gem5
+{
+
// Use an separate stack for fatal signal handlers
static uint8_t fatalSigStack[2 * SIGSTKSZ];
@@ -213,3 +216,4 @@
installSignalHandler(SIGIO, ioHandler);
}
+} // namespace gem5
diff --git a/src/sim/init_signals.hh b/src/sim/init_signals.hh
index e1e80a2..ea9f3d5 100644
--- a/src/sim/init_signals.hh
+++ b/src/sim/init_signals.hh
@@ -29,10 +29,15 @@
#ifndef __SIM_INIT_SIGNALS_HH__
#define __SIM_INIT_SIGNALS_HH__
+namespace gem5
+{
+
void dumpStatsHandler(int sigtype);
void dumprstStatsHandler(int sigtype);
void exitNowHandler(int sigtype);
void abortHandler(int sigtype);
void initSignals();
+} // namespace gem5
+
#endif // __SIM_INIT_SIGNALS_HH__
diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh
index 079e803..6c1e3b0 100644
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -48,6 +48,9 @@
#include "cpu/static_inst.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class ThreadContext;
namespace Trace {
@@ -268,8 +271,7 @@
const StaticInstPtr macroStaticInst = NULL) = 0;
};
-
-
} // namespace Trace
+} // namespace gem5
#endif // __INSTRECORD_HH__
diff --git a/src/sim/kernel_workload.cc b/src/sim/kernel_workload.cc
index cfe4816..c338b23 100644
--- a/src/sim/kernel_workload.cc
+++ b/src/sim/kernel_workload.cc
@@ -31,6 +31,9 @@
#include "params/KernelWorkload.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
KernelWorkload::KernelWorkload(const Params &p) : Workload(p),
_loadAddrMask(p.load_addr_mask), _loadAddrOffset(p.load_addr_offset),
commandLine(p.command_line)
@@ -142,3 +145,5 @@
{
kernelSymtab.unserialize("symtab", cp);
}
+
+} // namespace gem5
diff --git a/src/sim/kernel_workload.hh b/src/sim/kernel_workload.hh
index dfbbcb0..a1e8b98 100644
--- a/src/sim/kernel_workload.hh
+++ b/src/sim/kernel_workload.hh
@@ -37,6 +37,9 @@
#include "params/KernelWorkload.hh"
#include "sim/workload.hh"
+namespace gem5
+{
+
class System;
class KernelWorkload : public Workload
@@ -137,4 +140,6 @@
/** @} */
};
+} // namespace gem5
+
#endif // __SIM_KERNEL_WORKLOAD_HH__
diff --git a/src/sim/linear_solver.cc b/src/sim/linear_solver.cc
index 45d878d..0941406 100644
--- a/src/sim/linear_solver.cc
+++ b/src/sim/linear_solver.cc
@@ -37,6 +37,9 @@
#include "sim/linear_solver.hh"
+namespace gem5
+{
+
std::vector <double>
LinearSystem::solve() const
{
@@ -83,3 +86,5 @@
return ret;
}
+
+} // namespace gem5
diff --git a/src/sim/linear_solver.hh b/src/sim/linear_solver.hh
index 0ecf7f7..b166981 100644
--- a/src/sim/linear_solver.hh
+++ b/src/sim/linear_solver.hh
@@ -43,6 +43,9 @@
#include <string>
#include <vector>
+namespace gem5
+{
+
/**
* This class describes a linear equation with constant coefficients.
* The equation has a certain (variable) number of unkowns and it can hold
@@ -131,4 +134,6 @@
std::vector < LinearEquation > matrix;
};
+} // namespace gem5
+
#endif
diff --git a/src/sim/main.cc b/src/sim/main.cc
index 8ea4d2a..33b7742 100644
--- a/src/sim/main.cc
+++ b/src/sim/main.cc
@@ -31,6 +31,8 @@
#include "sim/init.hh"
#include "sim/init_signals.hh"
+using namespace gem5;
+
// main() is now pretty stripped down and just sets up python and then
// calls initM5Python which loads the various embedded python modules
// into the python environment and then starts things running by
diff --git a/src/sim/mathexpr.cc b/src/sim/mathexpr.cc
index 0cbcd90..f4ce07c 100644
--- a/src/sim/mathexpr.cc
+++ b/src/sim/mathexpr.cc
@@ -44,6 +44,9 @@
#include "base/logging.hh"
+namespace gem5
+{
+
MathExpr::MathExpr(std::string expr)
: ops(
std::array<OpSearch, uNeg + 1> {{
@@ -188,3 +191,4 @@
}
}
+} // namespace gem5
diff --git a/src/sim/mathexpr.hh b/src/sim/mathexpr.hh
index 20c5051..7abd50c 100644
--- a/src/sim/mathexpr.hh
+++ b/src/sim/mathexpr.hh
@@ -44,6 +44,9 @@
#include <string>
#include <vector>
+namespace gem5
+{
+
class MathExpr
{
public:
@@ -146,4 +149,6 @@
void getVariables(const Node *n, std::vector<std::string> &vars) const;
};
+} // namespace gem5
+
#endif
diff --git a/src/sim/mem_pool.cc b/src/sim/mem_pool.cc
index 87132dc..8e2dc86 100644
--- a/src/sim/mem_pool.cc
+++ b/src/sim/mem_pool.cc
@@ -35,6 +35,9 @@
#include "sim/system.hh"
+namespace gem5
+{
+
MemPool::MemPool(System *system, Addr ptr, Addr limit)
: sys(system), freePageNum(ptr >> sys->getPageShift()),
_totalPages(limit >> sys->getPageShift())
@@ -114,3 +117,5 @@
return return_addr;
}
+
+} // namespace gem5
diff --git a/src/sim/mem_pool.hh b/src/sim/mem_pool.hh
index 2c99ebc..e8bd439 100644
--- a/src/sim/mem_pool.hh
+++ b/src/sim/mem_pool.hh
@@ -36,6 +36,9 @@
#include "base/types.hh"
+namespace gem5
+{
+
class System;
/** Class for handling allocation of physical pages in SE mode. */
@@ -68,4 +71,6 @@
Addr allocate(Addr npages);
};
+} // namespace gem5
+
#endif // __MEM_POOL_HH__
diff --git a/src/sim/mem_state.cc b/src/sim/mem_state.cc
index 6d64f12..801226c 100644
--- a/src/sim/mem_state.cc
+++ b/src/sim/mem_state.cc
@@ -38,6 +38,9 @@
#include "sim/system.hh"
#include "sim/vma.hh"
+namespace gem5
+{
+
MemState::MemState(Process *owner, Addr brk_point, Addr stack_base,
Addr max_stack_size, Addr next_thread_stack_base,
Addr mmap_end)
@@ -489,3 +492,5 @@
return file_content.str();
}
+
+} // namespace gem5
diff --git a/src/sim/mem_state.hh b/src/sim/mem_state.hh
index b613b55..05f2239 100644
--- a/src/sim/mem_state.hh
+++ b/src/sim/mem_state.hh
@@ -40,6 +40,9 @@
#include "sim/serialize.hh"
#include "sim/vma.hh"
+namespace gem5
+{
+
class Process;
struct ProcessParams;
class System;
@@ -278,4 +281,6 @@
std::list<VMA> _vmaList;
};
+} // namespace gem5
+
#endif
diff --git a/src/sim/port.cc b/src/sim/port.cc
index 9131f84..580469a 100644
--- a/src/sim/port.cc
+++ b/src/sim/port.cc
@@ -47,6 +47,9 @@
#include "base/logging.hh"
+namespace gem5
+{
+
Port::Port(const std::string& _name, PortID _id) :
portName(_name), id(_id), _peer(nullptr), _connected(false)
{}
@@ -58,3 +61,5 @@
{
fatal("%s: Unconnected port!", name());
}
+
+} // namespace gem5
diff --git a/src/sim/port.hh b/src/sim/port.hh
index f265666..4f4a163 100644
--- a/src/sim/port.hh
+++ b/src/sim/port.hh
@@ -52,6 +52,9 @@
#include "base/types.hh"
+namespace gem5
+{
+
/**
* Ports are used to interface objects to each other.
*/
@@ -156,4 +159,6 @@
return os;
}
+} // namespace gem5
+
#endif //__SIM_PORT_HH__
diff --git a/src/sim/port.test.cc b/src/sim/port.test.cc
index 2543673..8858d41 100644
--- a/src/sim/port.test.cc
+++ b/src/sim/port.test.cc
@@ -35,6 +35,8 @@
#include "base/gtest/logging.hh"
#include "sim/port.hh"
+using namespace gem5;
+
class TestPort : public Port
{
public:
diff --git a/src/sim/power/MathExprPowerModel.py b/src/sim/power/MathExprPowerModel.py
index c4cc871..7f9f35e 100644
--- a/src/sim/power/MathExprPowerModel.py
+++ b/src/sim/power/MathExprPowerModel.py
@@ -41,6 +41,7 @@
class MathExprPowerModel(PowerModelState):
type = 'MathExprPowerModel'
cxx_header = "sim/power/mathexpr_powermodel.hh"
+ cxx_class = 'gem5::MathExprPowerModel'
# Equations for dynamic and static power in Watts
# Equations may use gem5 stats ie. "1.1*ipc + 2.3*l2_cache.overall_misses"
diff --git a/src/sim/power/PowerModel.py b/src/sim/power/PowerModel.py
index cfbd8cb..2eaafb8 100644
--- a/src/sim/power/PowerModel.py
+++ b/src/sim/power/PowerModel.py
@@ -46,6 +46,7 @@
class PowerModel(SimObject):
type = 'PowerModel'
cxx_header = "sim/power/power_model.hh"
+ cxx_class = 'gem5::PowerModel'
cxx_exports = [
PyBindMethod("getDynamicPower"),
diff --git a/src/sim/power/PowerModelState.py b/src/sim/power/PowerModelState.py
index cf24d0a..75d517b 100644
--- a/src/sim/power/PowerModelState.py
+++ b/src/sim/power/PowerModelState.py
@@ -40,8 +40,8 @@
class PowerModelState(SimObject):
type = 'PowerModelState'
cxx_header = "sim/power/power_model.hh"
+ cxx_class = 'gem5::PowerModelState'
abstract = True
- cxx_class = 'PowerModelState'
cxx_exports = [
PyBindMethod("getDynamicPower"),
diff --git a/src/sim/power/ThermalDomain.py b/src/sim/power/ThermalDomain.py
index 57c53b2..35ab31e 100644
--- a/src/sim/power/ThermalDomain.py
+++ b/src/sim/power/ThermalDomain.py
@@ -40,6 +40,7 @@
class ThermalDomain(SimObject):
type = 'ThermalDomain'
cxx_header = "sim/power/thermal_domain.hh"
+ cxx_class = 'gem5::ThermalDomain'
cxx_exports = [
PyBindMethod("setNode"),
diff --git a/src/sim/power/ThermalModel.py b/src/sim/power/ThermalModel.py
index 90710e1..6a01ba2 100644
--- a/src/sim/power/ThermalModel.py
+++ b/src/sim/power/ThermalModel.py
@@ -44,11 +44,13 @@
class ThermalNode(SimObject):
type = 'ThermalNode'
cxx_header = "sim/power/thermal_node.hh"
+ cxx_class = 'gem5::ThermalNode'
# Represents a thermal resistor
class ThermalResistor(SimObject):
type = 'ThermalResistor'
cxx_header = "sim/power/thermal_model.hh"
+ cxx_class = 'gem5::ThermalResistor'
cxx_exports = [
PyBindMethod("setNodes"),
@@ -60,6 +62,7 @@
class ThermalCapacitor(SimObject):
type = 'ThermalCapacitor'
cxx_header = "sim/power/thermal_model.hh"
+ cxx_class = 'gem5::ThermalCapacitor'
cxx_exports = [
PyBindMethod("setNodes"),
@@ -71,6 +74,7 @@
class ThermalReference(SimObject, object):
type = 'ThermalReference'
cxx_header = "sim/power/thermal_model.hh"
+ cxx_class = 'gem5::ThermalReference'
cxx_exports = [
PyBindMethod("setNode"),
@@ -84,6 +88,7 @@
class ThermalModel(ClockedObject):
type = 'ThermalModel'
cxx_header = "sim/power/thermal_model.hh"
+ cxx_class = 'gem5::ThermalModel'
cxx_exports = [
PyBindMethod("addCapacitor"),
diff --git a/src/sim/power/mathexpr_powermodel.cc b/src/sim/power/mathexpr_powermodel.cc
index 9d26237..93f1911 100644
--- a/src/sim/power/mathexpr_powermodel.cc
+++ b/src/sim/power/mathexpr_powermodel.cc
@@ -45,6 +45,9 @@
#include "sim/power/thermal_model.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
MathExprPowerModel::MathExprPowerModel(const Params &p)
: PowerModelState(p), dyn_expr(p.dyn), st_expr(p.st)
{
@@ -113,3 +116,5 @@
{
PowerModelState::regStats();
}
+
+} // namespace gem5
diff --git a/src/sim/power/mathexpr_powermodel.hh b/src/sim/power/mathexpr_powermodel.hh
index ec1b90f..25338ee 100644
--- a/src/sim/power/mathexpr_powermodel.hh
+++ b/src/sim/power/mathexpr_powermodel.hh
@@ -44,6 +44,9 @@
#include "sim/mathexpr.hh"
#include "sim/power/power_model.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
{
@@ -104,4 +107,6 @@
std::unordered_map<std::string, const statistics::Info*> statsMap;
};
+} // namespace gem5
+
#endif
diff --git a/src/sim/power/power_model.cc b/src/sim/power/power_model.cc
index 38ab08e..37142f5 100644
--- a/src/sim/power/power_model.cc
+++ b/src/sim/power/power_model.cc
@@ -43,6 +43,9 @@
#include "sim/clocked_object.hh"
#include "sim/sub_system.hh"
+namespace gem5
+{
+
PowerModelState::PowerModelState(const Params &p)
: SimObject(p), _temp(0), clocked_object(NULL),
ADD_STAT(dynamicPower, statistics::units::Watt::get(),
@@ -160,3 +163,5 @@
return power;
}
+
+} // namespace gem5
diff --git a/src/sim/power/power_model.hh b/src/sim/power/power_model.hh
index 21bc968..309b763 100644
--- a/src/sim/power/power_model.hh
+++ b/src/sim/power/power_model.hh
@@ -45,6 +45,9 @@
#include "params/PowerModelState.hh"
#include "sim/probe/probe.hh"
+namespace gem5
+{
+
class SimObject;
class ClockedObject;
@@ -164,4 +167,6 @@
statistics::Value dynamicPower, staticPower;
};
+} // namespace gem5
+
#endif
diff --git a/src/sim/power/thermal_domain.cc b/src/sim/power/thermal_domain.cc
index 70721c9..6c27c80 100644
--- a/src/sim/power/thermal_domain.cc
+++ b/src/sim/power/thermal_domain.cc
@@ -48,6 +48,9 @@
#include "sim/probe/probe.hh"
#include "sim/sub_system.hh"
+namespace gem5
+{
+
ThermalDomain::ThermalDomain(const Params &p)
: SimObject(p), _initTemperature(p.initial_temperature),
node(NULL), subsystem(NULL),
@@ -89,3 +92,5 @@
eq[eq.cnt()] = power;
return eq;
}
+
+} // namespace gem5
diff --git a/src/sim/power/thermal_domain.hh b/src/sim/power/thermal_domain.hh
index 1c58cb3..11b09e9 100644
--- a/src/sim/power/thermal_domain.hh
+++ b/src/sim/power/thermal_domain.hh
@@ -48,6 +48,9 @@
#include "sim/sim_object.hh"
#include "sim/sub_system.hh"
+namespace gem5
+{
+
template <class T> class ProbePointArg;
/**
@@ -107,4 +110,6 @@
};
+} // namespace gem5
+
#endif
diff --git a/src/sim/power/thermal_entity.hh b/src/sim/power/thermal_entity.hh
index 0236b4c..d9fedb2 100644
--- a/src/sim/power/thermal_entity.hh
+++ b/src/sim/power/thermal_entity.hh
@@ -40,6 +40,9 @@
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class LinearEquation;
class ThermalNode;
@@ -56,5 +59,6 @@
double step) const = 0;
};
+} // namespace gem5
#endif
diff --git a/src/sim/power/thermal_model.cc b/src/sim/power/thermal_model.cc
index 8f92c6f..fb19044 100644
--- a/src/sim/power/thermal_model.cc
+++ b/src/sim/power/thermal_model.cc
@@ -47,6 +47,9 @@
#include "sim/power/thermal_domain.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
/**
* ThermalReference
*/
@@ -243,3 +246,5 @@
temp = std::max(temp, n->temp);
return temp;
}
+
+} // namespace gem5
diff --git a/src/sim/power/thermal_model.hh b/src/sim/power/thermal_model.hh
index d3717df..b29dccd 100644
--- a/src/sim/power/thermal_model.hh
+++ b/src/sim/power/thermal_model.hh
@@ -47,6 +47,9 @@
#include "sim/power/thermal_node.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
struct ThermalCapacitorParams;
struct ThermalModelParams;
struct ThermalReferenceParams;
@@ -177,4 +180,6 @@
const double _step;
};
+} // namespace gem5
+
#endif
diff --git a/src/sim/power/thermal_node.cc b/src/sim/power/thermal_node.cc
index c8806d9..c3231bb 100644
--- a/src/sim/power/thermal_node.cc
+++ b/src/sim/power/thermal_node.cc
@@ -40,6 +40,9 @@
#include "params/ThermalNode.hh"
+namespace gem5
+{
+
/**
* ThermalNode
*/
@@ -47,3 +50,5 @@
: SimObject(p), id(-1), isref(false), temp(0.0f)
{
}
+
+} // namespace gem5
diff --git a/src/sim/power/thermal_node.hh b/src/sim/power/thermal_node.hh
index e9d4096..3a9e37e 100644
--- a/src/sim/power/thermal_node.hh
+++ b/src/sim/power/thermal_node.hh
@@ -41,6 +41,9 @@
#include "base/temperature.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
struct ThermalNodeParams;
/**
@@ -58,4 +61,6 @@
Temperature temp;
};
+} // namespace gem5
+
#endif
diff --git a/src/sim/power_domain.cc b/src/sim/power_domain.cc
index 9e48ba9..87b8fa7 100644
--- a/src/sim/power_domain.cc
+++ b/src/sim/power_domain.cc
@@ -42,6 +42,9 @@
#include "base/trace.hh"
#include "debug/PowerDomain.hh"
+namespace gem5
+{
+
PowerDomain::PowerDomain(const PowerDomainParams &p) :
PowerState(p),
leaders(p.leaders),
@@ -263,3 +266,5 @@
.flags(statistics::nozero)
;
}
+
+} // namespace gem5
diff --git a/src/sim/power_domain.hh b/src/sim/power_domain.hh
index 7a68e81..96233e4 100644
--- a/src/sim/power_domain.hh
+++ b/src/sim/power_domain.hh
@@ -47,6 +47,9 @@
#include "sim/clocked_object.hh"
#include "sim/power_state.hh"
+namespace gem5
+{
+
/**
* The PowerDomain groups PowerState objects together to regulate their
* power states. As the PowerDomain itself is a PowerState object, you can
@@ -163,4 +166,6 @@
} stats;
};
+} // namespace gem5
+
#endif // __SIM_POWER_DOMAIN_HH__
diff --git a/src/sim/power_state.cc b/src/sim/power_state.cc
index 8603cc7..3e20c69 100644
--- a/src/sim/power_state.cc
+++ b/src/sim/power_state.cc
@@ -45,6 +45,9 @@
#include "sim/power_domain.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
PowerState::PowerState(const PowerStateParams &p) :
SimObject(p), _currState(p.default_state),
possibleStates(p.possible_states.begin(),
@@ -277,3 +280,5 @@
*/
powerState.computeStats();
}
+
+} // namespace gem5
diff --git a/src/sim/power_state.hh b/src/sim/power_state.hh
index 40b2724..03f3a60 100644
--- a/src/sim/power_state.hh
+++ b/src/sim/power_state.hh
@@ -53,6 +53,9 @@
#include "sim/core.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class PowerDomain;
/**
@@ -148,4 +151,6 @@
} stats;
};
+} // namespace gem5
+
#endif //__SIM_POWER_STATE_HH__
diff --git a/src/sim/probe/Probe.py b/src/sim/probe/Probe.py
index c1b98e3..00de928 100644
--- a/src/sim/probe/Probe.py
+++ b/src/sim/probe/Probe.py
@@ -42,4 +42,6 @@
class ProbeListenerObject(SimObject):
type = 'ProbeListenerObject'
cxx_header = 'sim/probe/probe.hh'
+ cxx_class = 'gem5::ProbeListenerObject'
+
manager = Param.SimObject(Parent.any, "ProbeManager")
diff --git a/src/sim/probe/mem.hh b/src/sim/probe/mem.hh
index a129d66..df3280c 100644
--- a/src/sim/probe/mem.hh
+++ b/src/sim/probe/mem.hh
@@ -43,6 +43,9 @@
#include "mem/packet.hh"
#include "sim/probe/probe.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(ProbePoints, probing);
namespace probing
{
@@ -106,6 +109,8 @@
typedef ProbePointArg<PacketInfo> Packet;
typedef std::unique_ptr<Packet> PacketUPtr;
-}
+} // namespace probing
+
+} // namespace gem5
#endif
diff --git a/src/sim/probe/pmu.hh b/src/sim/probe/pmu.hh
index 505ce91..acf4750 100644
--- a/src/sim/probe/pmu.hh
+++ b/src/sim/probe/pmu.hh
@@ -42,6 +42,9 @@
#include "sim/probe/probe.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(ProbePoints, probing);
namespace probing
{
@@ -59,4 +62,6 @@
}
+} // namespace gem5
+
#endif
diff --git a/src/sim/probe/probe.cc b/src/sim/probe/probe.cc
index b764db0..3101f76 100644
--- a/src/sim/probe/probe.cc
+++ b/src/sim/probe/probe.cc
@@ -40,6 +40,9 @@
#include "debug/ProbeVerbose.hh"
#include "params/ProbeListenerObject.hh"
+namespace gem5
+{
+
ProbePoint::ProbePoint(ProbeManager *manager, const std::string& _name)
: name(_name)
{
@@ -121,3 +124,5 @@
}
points.push_back(&point);
}
+
+} // namespace gem5
diff --git a/src/sim/probe/probe.hh b/src/sim/probe/probe.hh
index 4357d63..89b0a97 100644
--- a/src/sim/probe/probe.hh
+++ b/src/sim/probe/probe.hh
@@ -66,6 +66,9 @@
#include "base/trace.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
/** Forward declare the ProbeManager. */
class ProbeManager;
class ProbeListener;
@@ -305,4 +308,7 @@
}
}
};
+
+} // namespace gem5
+
#endif//__SIM_PROBE_PROBE_HH__
diff --git a/src/sim/process.cc b/src/sim/process.cc
index a77bef3a..207c275 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -66,6 +66,9 @@
#include "sim/syscall_desc.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
namespace
{
@@ -526,3 +529,5 @@
return process;
}
+
+} // namespace gem5
diff --git a/src/sim/process.hh b/src/sim/process.hh
index 9686b3f..632ba90 100644
--- a/src/sim/process.hh
+++ b/src/sim/process.hh
@@ -46,6 +46,9 @@
#include "sim/mem_state.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Loader, loader);
namespace loader
{
@@ -285,4 +288,6 @@
statistics::Scalar numSyscalls;
};
+} // namespace gem5
+
#endif // __PROCESS_HH__
diff --git a/src/sim/process_impl.hh b/src/sim/process_impl.hh
index f5148ff..3988a5b 100644
--- a/src/sim/process_impl.hh
+++ b/src/sim/process_impl.hh
@@ -34,6 +34,9 @@
#include "mem/se_translating_port_proxy.hh"
+namespace gem5
+{
+
//This needs to be templated for cases where 32 bit pointers are needed.
template<class AddrType>
void
@@ -55,4 +58,6 @@
memProxy.writeBlob(array_ptr, &data_ptr, sizeof(AddrType));
}
+} // namespace gem5
+
#endif
diff --git a/src/sim/proxy_ptr.hh b/src/sim/proxy_ptr.hh
index b3bbfd4..4fe4355 100644
--- a/src/sim/proxy_ptr.hh
+++ b/src/sim/proxy_ptr.hh
@@ -37,6 +37,9 @@
#include "base/types.hh"
#include "sim/guest_abi.hh"
+namespace gem5
+{
+
template <typename Proxy>
class ProxyPtrBuffer
{
@@ -397,4 +400,6 @@
template <typename T=void>
using VPtr = ProxyPtr<T, SETranslatingPortProxy>;
+} // namespace gem5
+
#endif // __SIM_PROXY_PTR_HH__
diff --git a/src/sim/proxy_ptr.test.cc b/src/sim/proxy_ptr.test.cc
index 85d3e99..d93df14 100644
--- a/src/sim/proxy_ptr.test.cc
+++ b/src/sim/proxy_ptr.test.cc
@@ -31,6 +31,8 @@
#include "sim/proxy_ptr.hh"
+using namespace gem5;
+
struct Access
{
bool read;
@@ -469,6 +471,9 @@
using State = int;
};
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi);
namespace guest_abi
{
@@ -484,6 +489,7 @@
};
} // namespace guest_abi
+} // namespace gem5
bool abiCalled = false;
bool abiCalledConst = false;
@@ -502,7 +508,7 @@
EXPECT_EQ(ptr.addr(), 0x1000);
}
-TEST(ProxyPtr, guest_abi)
+TEST(ProxyPtrTest, GuestABI)
{
BackingStore store(0x1000, 0x1000);
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index 2c7deb7..6a39ceb 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -68,6 +68,9 @@
#include "sim/stats.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
using namespace statistics;
GEM5_DEPRECATED_NAMESPACE(PseudoInst, pseudo_inst);
@@ -586,3 +589,4 @@
}
} // namespace pseudo_inst
+} // namespace gem5
diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh
index de8a709..4794a41 100644
--- a/src/sim/pseudo_inst.hh
+++ b/src/sim/pseudo_inst.hh
@@ -43,8 +43,6 @@
#include <gem5/asm/generic/m5ops.h>
-class ThreadContext;
-
#include "base/bitfield.hh"
#include "base/compiler.hh"
#include "base/logging.hh"
@@ -54,6 +52,9 @@
#include "debug/PseudoInst.hh"
#include "sim/guest_abi.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(PseudoInst, pseudo_inst);
namespace pseudo_inst
{
@@ -252,5 +253,6 @@
}
} // namespace pseudo_inst
+} // namespace gem5
#endif // __SIM_PSEUDO_INST_HH__
diff --git a/src/sim/py_interact.cc b/src/sim/py_interact.cc
index 87c5765..7f9ce48 100644
--- a/src/sim/py_interact.cc
+++ b/src/sim/py_interact.cc
@@ -30,6 +30,9 @@
#include "sim/py_interact.hh"
+namespace gem5
+{
+
void
py_interact()
{
@@ -46,3 +49,4 @@
Py_DECREF(locals);
}
+} // namespace gem5
diff --git a/src/sim/py_interact.hh b/src/sim/py_interact.hh
index b5f4710..a8a92e3 100644
--- a/src/sim/py_interact.hh
+++ b/src/sim/py_interact.hh
@@ -33,6 +33,11 @@
* embedded Python content in a debugger such as gdb.
*/
+namespace gem5
+{
+
void py_interact();
+} // namespace gem5
+
#endif // __SIM_PY_INTERACT_HH__
diff --git a/src/sim/python.cc b/src/sim/python.cc
index f56da93..d1ebd0d 100644
--- a/src/sim/python.cc
+++ b/src/sim/python.cc
@@ -29,6 +29,9 @@
#include "sim/init.hh"
#include "sim/port.hh"
+namespace gem5
+{
+
namespace
{
@@ -44,3 +47,4 @@
EmbeddedPyBind embed_("sim", &sim_pybind);
} // anonymous namespace
+} // namespace gem5
diff --git a/src/sim/redirect_path.cc b/src/sim/redirect_path.cc
index 57286f7..f82039e 100644
--- a/src/sim/redirect_path.cc
+++ b/src/sim/redirect_path.cc
@@ -32,6 +32,9 @@
#include "base/str.hh"
+namespace gem5
+{
+
static std::string
normalizePath(std::string path)
{
@@ -55,3 +58,5 @@
_hostPaths.push_back(normalizePath(hp));
}
}
+
+} // namespace gem5
diff --git a/src/sim/redirect_path.hh b/src/sim/redirect_path.hh
index e7e684b..fc41e31 100644
--- a/src/sim/redirect_path.hh
+++ b/src/sim/redirect_path.hh
@@ -35,6 +35,9 @@
#include "params/RedirectPath.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
/**
* RedirectPath stores a mapping from one 'appPath' to a vector of
* 'hostPath'. Each 'appPath' and 'hostPath' is a filesystem path.
@@ -60,4 +63,6 @@
std::vector<std::string> _hostPaths;
};
+} // namespace gem5
+
#endif
diff --git a/src/sim/root.cc b/src/sim/root.cc
index 6750341..7fe1159 100644
--- a/src/sim/root.cc
+++ b/src/sim/root.cc
@@ -48,6 +48,9 @@
#include "sim/full_system.hh"
#include "sim/root.hh"
+namespace gem5
+{
+
Root *Root::_root = NULL;
Root::RootStats Root::RootStats::instance;
Root::RootStats &rootStats = Root::RootStats::instance;
@@ -232,3 +235,5 @@
return new Root(*this, 0);
}
+
+} // namespace gem5
diff --git a/src/sim/root.hh b/src/sim/root.hh
index 14861d4..ce2245f 100644
--- a/src/sim/root.hh
+++ b/src/sim/root.hh
@@ -59,6 +59,9 @@
#include "sim/globals.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class Root : public SimObject
{
private:
@@ -155,4 +158,6 @@
*/
extern Root::RootStats &rootStats;
+} // namespace gem5
+
#endif // __SIM_ROOT_HH__
diff --git a/src/sim/se_signal.cc b/src/sim/se_signal.cc
index f448c76..8d0f10c 100644
--- a/src/sim/se_signal.cc
+++ b/src/sim/se_signal.cc
@@ -30,6 +30,9 @@
#include "sim/se_signal.hh"
+namespace gem5
+{
+
BasicSignal::BasicSignal(Process *send, Process *receive, int signal_val)
: sender(send),
receiver(receive),
@@ -41,3 +44,5 @@
BasicSignal::~BasicSignal()
{
}
+
+} // namespace gem5
diff --git a/src/sim/se_signal.hh b/src/sim/se_signal.hh
index f5f1675..b2168a5 100644
--- a/src/sim/se_signal.hh
+++ b/src/sim/se_signal.hh
@@ -31,6 +31,9 @@
#ifndef __SE_SIGNAL_HH__
#define __SE_SIGNAL_HH__
+namespace gem5
+{
+
class Process;
class BasicSignal
@@ -44,4 +47,6 @@
~BasicSignal();
};
+} // namespace gem5
+
#endif // __SE_SIGNAL_HH__
diff --git a/src/sim/se_workload.cc b/src/sim/se_workload.cc
index 655682f..4148250 100644
--- a/src/sim/se_workload.cc
+++ b/src/sim/se_workload.cc
@@ -31,6 +31,9 @@
#include "params/SEWorkload.hh"
#include "sim/process.hh"
+namespace gem5
+{
+
SEWorkload::SEWorkload(const Params &p) : Workload(p)
{}
@@ -39,3 +42,5 @@
{
tc->getProcessPtr()->syscall(tc);
}
+
+} // namespace gem5
diff --git a/src/sim/se_workload.hh b/src/sim/se_workload.hh
index 2edc086..a3e4df0 100644
--- a/src/sim/se_workload.hh
+++ b/src/sim/se_workload.hh
@@ -31,6 +31,9 @@
#include "params/SEWorkload.hh"
#include "sim/workload.hh"
+namespace gem5
+{
+
class SEWorkload : public Workload
{
public:
@@ -77,4 +80,6 @@
void event(ThreadContext *tc) override { syscall(tc); }
};
+} // namespace gem5
+
#endif // __SIM_SE_WORKLOAD_HH__
diff --git a/src/sim/serialize.cc b/src/sim/serialize.cc
index 014e50d..2b1bd35 100644
--- a/src/sim/serialize.cc
+++ b/src/sim/serialize.cc
@@ -52,6 +52,9 @@
#include "base/trace.hh"
#include "debug/Checkpoint.hh"
+namespace gem5
+{
+
int ckptMaxCount = 0;
int ckptCount = 0;
int ckptPrevCount = -1;
@@ -205,3 +208,5 @@
{
db.visitSection(section, cb);
}
+
+} // namespace gem5
diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh
index 0acda32..9687423 100644
--- a/src/sim/serialize.hh
+++ b/src/sim/serialize.hh
@@ -60,6 +60,9 @@
#include "base/logging.hh"
#include "sim/serialize_handlers.hh"
+namespace gem5
+{
+
typedef std::ostream CheckpointOut;
class CheckpointIn
@@ -663,4 +666,6 @@
#define UNSERIALIZE_MAPPING(member, names, size) \
mappingParamIn(cp, #member, names, member, size)
+} // namespace gem5
+
#endif // __SERIALIZE_HH__
diff --git a/src/sim/serialize_handlers.hh b/src/sim/serialize_handlers.hh
index 5e5c3ff..6802b91 100644
--- a/src/sim/serialize_handlers.hh
+++ b/src/sim/serialize_handlers.hh
@@ -52,6 +52,9 @@
#include "base/str.hh"
+namespace gem5
+{
+
/**
* @ingroup api_serialize
* @{
@@ -154,4 +157,6 @@
/** @} */
+} // namespace gem5
+
#endif // __SERIALIZE_HANDLERS_HH__
diff --git a/src/sim/sim_events.cc b/src/sim/sim_events.cc
index ba2cda2..66379d2 100644
--- a/src/sim/sim_events.cc
+++ b/src/sim/sim_events.cc
@@ -49,6 +49,9 @@
#include "sim/sim_exit.hh"
#include "sim/stats.hh"
+namespace gem5
+{
+
GlobalSimLoopExitEvent::GlobalSimLoopExitEvent(Tick when,
const std::string &_cause,
int c, Tick r)
@@ -170,3 +173,5 @@
{
return "counted exit";
}
+
+} // namespace gem5
diff --git a/src/sim/sim_events.hh b/src/sim/sim_events.hh
index 71792d5..06a8e65 100644
--- a/src/sim/sim_events.hh
+++ b/src/sim/sim_events.hh
@@ -46,6 +46,9 @@
#include "sim/global_event.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
//
// Event to terminate simulation at a particular cycle/instruction
//
@@ -112,5 +115,6 @@
const char *description() const override;
};
+} // namespace gem5
#endif // __SIM_SIM_EVENTS_HH__
diff --git a/src/sim/sim_exit.hh b/src/sim/sim_exit.hh
index d1791f5..b811d1d 100644
--- a/src/sim/sim_exit.hh
+++ b/src/sim/sim_exit.hh
@@ -34,6 +34,9 @@
#include "base/types.hh"
+namespace gem5
+{
+
Tick curTick();
/// Register a callback to be called when Python exits. Defined in
@@ -52,4 +55,6 @@
void exitSimLoopNow(const std::string &message, int exit_code = 0,
Tick repeat = 0, bool serialize = false);
+} // namespace gem5
+
#endif // __SIM_EXIT_HH__
diff --git a/src/sim/sim_object.cc b/src/sim/sim_object.cc
index f1f88a9..d10be92 100644
--- a/src/sim/sim_object.cc
+++ b/src/sim/sim_object.cc
@@ -37,6 +37,9 @@
#include "debug/Checkpoint.hh"
#include "sim/probe/probe.hh"
+namespace gem5
+{
+
////////////////////////////////////////////////////////////////////////
//
// SimObject member definitions
@@ -214,3 +217,5 @@
{
SimObject::serializeAll(cpt_dir);
}
+
+} // namespace gem5
diff --git a/src/sim/sim_object.hh b/src/sim/sim_object.hh
index cec2743..c2c5d4d 100644
--- a/src/sim/sim_object.hh
+++ b/src/sim/sim_object.hh
@@ -57,6 +57,9 @@
#include "sim/port.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
class EventManager;
class ProbeManager;
class SimObjectResolver;
@@ -406,4 +409,6 @@
void debug_serialize(const std::string &cpt_dir);
+} // namespace gem5
+
#endif // __SIM_OBJECT_HH__
diff --git a/src/sim/simulate.cc b/src/sim/simulate.cc
index be0048b..4a00869 100644
--- a/src/sim/simulate.cc
+++ b/src/sim/simulate.cc
@@ -42,6 +42,9 @@
#include "sim/sim_exit.hh"
#include "sim/stat_control.hh"
+namespace gem5
+{
+
//! Mutex for handling async events.
std::mutex asyncEventMutex;
@@ -221,3 +224,5 @@
// not reached... only exit is return on SimLoopExitEvent
}
+
+} // namespace gem5
diff --git a/src/sim/simulate.hh b/src/sim/simulate.hh
index be40fa5..0817bbd 100644
--- a/src/sim/simulate.hh
+++ b/src/sim/simulate.hh
@@ -28,7 +28,12 @@
#include "base/types.hh"
+namespace gem5
+{
+
class GlobalSimLoopExitEvent;
GlobalSimLoopExitEvent *simulate(Tick num_cycles = MaxTick);
extern GlobalSimLoopExitEvent *simulate_limit_event;
+
+} // namespace gem5
diff --git a/src/sim/stat_control.cc b/src/sim/stat_control.cc
index c38bcd3..c388539 100644
--- a/src/sim/stat_control.cc
+++ b/src/sim/stat_control.cc
@@ -54,6 +54,9 @@
#include "base/time.hh"
#include "sim/global_event.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
{
@@ -157,3 +160,4 @@
}
} // namespace statistics
+} // namespace gem5
diff --git a/src/sim/stat_control.hh b/src/sim/stat_control.hh
index 209773c..20b967c 100644
--- a/src/sim/stat_control.hh
+++ b/src/sim/stat_control.hh
@@ -45,6 +45,9 @@
#include "base/types.hh"
#include "sim/core.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
{
@@ -80,5 +83,6 @@
*/
void periodicStatDump(Tick period = 0);
} // namespace statistics
+} // namespace gem5
#endif // __SIM_STAT_CONTROL_HH__
diff --git a/src/sim/stat_register.cc b/src/sim/stat_register.cc
index b31f2c2..fb3db1e 100644
--- a/src/sim/stat_register.cc
+++ b/src/sim/stat_register.cc
@@ -39,6 +39,9 @@
#include "base/statistics.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
{
@@ -52,3 +55,4 @@
}
} // namespace statistics
+} // namespace gem5
diff --git a/src/sim/stat_register.hh b/src/sim/stat_register.hh
index 2ff1411..d2504f3 100644
--- a/src/sim/stat_register.hh
+++ b/src/sim/stat_register.hh
@@ -44,6 +44,9 @@
#include "base/compiler.hh"
+namespace gem5
+{
+
GEM5_DEPRECATED_NAMESPACE(Stats, statistics);
namespace statistics
{
@@ -52,5 +55,6 @@
void registerPythonStatsHandlers();
} // namespace statistics
+} // namespace gem5
#endif // __SIM_STAT_REGISTER_H__
diff --git a/src/sim/stats.cc b/src/sim/stats.cc
index ff13e08..2bcbc30 100644
--- a/src/sim/stats.cc
+++ b/src/sim/stats.cc
@@ -39,7 +39,12 @@
#include "sim/root.hh"
+namespace gem5
+{
+
statistics::Formula &simSeconds = rootStats.simSeconds;
statistics::Value &simTicks = rootStats.simTicks;
statistics::Value &simFreq = rootStats.simFreq;
statistics::Value &hostSeconds = rootStats.hostSeconds;
+
+} // namespace gem5
diff --git a/src/sim/stats.hh b/src/sim/stats.hh
index 9c1ebea..c84200f 100644
--- a/src/sim/stats.hh
+++ b/src/sim/stats.hh
@@ -31,9 +31,14 @@
#include "base/statistics.hh"
+namespace gem5
+{
+
extern statistics::Formula &simSeconds;
extern statistics::Value &simTicks;
extern statistics::Value &simFreq;
extern statistics::Value &hostSeconds;
+} // namespace gem5
+
#endif // __SIM_SIM_STATS_HH__
diff --git a/src/sim/sub_system.cc b/src/sim/sub_system.cc
index e543541..174568d 100644
--- a/src/sim/sub_system.cc
+++ b/src/sim/sub_system.cc
@@ -41,6 +41,9 @@
#include "sim/power/power_model.hh"
#include "sim/power/thermal_domain.hh"
+namespace gem5
+{
+
SubSystem::SubSystem(const Params &p)
: SimObject(p)
{
@@ -66,3 +69,5 @@
ret += obj->getStaticPower();
return ret;
}
+
+} // namespace gem5
diff --git a/src/sim/sub_system.hh b/src/sim/sub_system.hh
index dfa9761..57cb59b 100644
--- a/src/sim/sub_system.hh
+++ b/src/sim/sub_system.hh
@@ -48,6 +48,9 @@
#include "params/SubSystem.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
class PowerModel;
/**
@@ -72,4 +75,6 @@
std::vector<PowerModel*> powerProducers;
};
+} // namespace gem5
+
#endif
diff --git a/src/sim/syscall_abi.hh b/src/sim/syscall_abi.hh
index 150d837..f51b178 100644
--- a/src/sim/syscall_abi.hh
+++ b/src/sim/syscall_abi.hh
@@ -34,6 +34,9 @@
#include "sim/guest_abi.hh"
#include "sim/syscall_return.hh"
+namespace gem5
+{
+
class SyscallDesc;
struct GenericSyscallABI
@@ -106,5 +109,6 @@
};
} // namespace guest_abi
+} // namespace gem5
#endif // __SIM_SYSCALL_ABI_HH__
diff --git a/src/sim/syscall_desc.cc b/src/sim/syscall_desc.cc
index 2658717..7499102 100644
--- a/src/sim/syscall_desc.cc
+++ b/src/sim/syscall_desc.cc
@@ -32,6 +32,9 @@
#include "base/types.hh"
#include "sim/syscall_debug_macros.hh"
+namespace gem5
+{
+
class ThreadContext;
void
@@ -48,3 +51,5 @@
else
DPRINTF_SYSCALL(Base, "Returned %d.\n", retval.encodedValue());
}
+
+} // namespace gem5
diff --git a/src/sim/syscall_desc.hh b/src/sim/syscall_desc.hh
index 67dd028..0740632 100644
--- a/src/sim/syscall_desc.hh
+++ b/src/sim/syscall_desc.hh
@@ -53,6 +53,9 @@
#include "sim/process.hh"
#include "sim/syscall_return.hh"
+namespace gem5
+{
+
class SyscallDesc;
SyscallReturn unimplementedFunc(SyscallDesc *desc, ThreadContext *tc);
@@ -206,4 +209,6 @@
}
};
+} // namespace gem5
+
#endif // __SIM_SYSCALL_DESC_HH__
diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc
index bb8b42a..147cb39 100644
--- a/src/sim/syscall_emul.cc
+++ b/src/sim/syscall_emul.cc
@@ -51,6 +51,9 @@
#include "sim/syscall_desc.hh"
#include "sim/system.hh"
+namespace gem5
+{
+
void
warnUnsupportedOS(std::string syscall_name)
{
@@ -1650,3 +1653,5 @@
return 0;
}
+
+} // namespace gem5
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 3c1ad04..802f547 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -114,6 +114,9 @@
#define CMSG_ALIGN(n) _ALIGN(n)
#endif
+namespace gem5
+{
+
//////////////////////////////////////////////////////////////////////
//
// The following emulation functions are generic enough that they
@@ -2626,4 +2629,7 @@
return -1;
#endif
}
+
+} // namespace gem5
+
#endif // __SIM_SYSCALL_EMUL_HH__
diff --git a/src/sim/syscall_emul_buf.hh b/src/sim/syscall_emul_buf.hh
index 8e2f3ac..d28d0c1 100644
--- a/src/sim/syscall_emul_buf.hh
+++ b/src/sim/syscall_emul_buf.hh
@@ -40,6 +40,9 @@
#include "base/types.hh"
#include "mem/se_translating_port_proxy.hh"
+namespace gem5
+{
+
/**
* Base class for BufferArg and TypedBufferArg, Not intended to be
* used directly.
@@ -165,5 +168,6 @@
T &operator[](int i) { return ((T *)bufPtr)[i]; }
};
+} // namespace gem5
#endif // __SIM_SYSCALL_EMUL_BUF_HH__
diff --git a/src/sim/syscall_return.hh b/src/sim/syscall_return.hh
index 7c6a0c6..40452b5 100644
--- a/src/sim/syscall_return.hh
+++ b/src/sim/syscall_return.hh
@@ -31,6 +31,9 @@
#include <inttypes.h>
+namespace gem5
+{
+
/**
* This class represents the return value from an emulated system call,
* including any errno setting.
@@ -126,4 +129,6 @@
bool retryFlag = false;
};
+} // namespace gem5
+
#endif
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 04dce5e..4619de9 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -69,6 +69,9 @@
#include "sim/full_system.hh"
#include "sim/redirect_path.hh"
+namespace gem5
+{
+
std::vector<System *> System::systemList;
void
@@ -638,3 +641,5 @@
const auto& requestor_info = requestors[requestor_id];
return requestor_info.req_name;
}
+
+} // namespace gem5
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 66e138e..e5215a6 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -67,6 +67,9 @@
#include "sim/sim_object.hh"
#include "sim/workload.hh"
+namespace gem5
+{
+
class BaseRemoteGDB;
class KvmVM;
class ThreadContext;
@@ -639,4 +642,6 @@
void printSystems();
+} // namespace gem5
+
#endif // __SYSTEM_HH__
diff --git a/src/sim/ticked_object.cc b/src/sim/ticked_object.cc
index e6bd146..a9ee2c8 100644
--- a/src/sim/ticked_object.cc
+++ b/src/sim/ticked_object.cc
@@ -41,6 +41,9 @@
#include "sim/clocked_object.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
Ticked::Ticked(ClockedObject &object_,
statistics::Scalar *imported_num_cycles,
Event::Priority priority) :
@@ -133,3 +136,5 @@
Ticked::unserialize(cp);
ClockedObject::unserialize(cp);
}
+
+} // namespace gem5
diff --git a/src/sim/ticked_object.hh b/src/sim/ticked_object.hh
index 33402ad..a6566f0 100644
--- a/src/sim/ticked_object.hh
+++ b/src/sim/ticked_object.hh
@@ -48,6 +48,9 @@
#include "sim/clocked_object.hh"
+namespace gem5
+{
+
struct TickedObjectParams;
/** Ticked attaches gem5's event queue/scheduler to evaluate
@@ -177,4 +180,6 @@
void unserialize(CheckpointIn &cp) override;
};
+} // namespace gem5
+
#endif /* __SIM_TICKED_OBJECT_HH__ */
diff --git a/src/sim/vma.cc b/src/sim/vma.cc
index e26cc38..7e5ed1c 100644
--- a/src/sim/vma.cc
+++ b/src/sim/vma.cc
@@ -33,6 +33,9 @@
#include "base/types.hh"
+namespace gem5
+{
+
void
VMA::fillMemPages(Addr start, Addr size, PortProxy &port) const
{
@@ -152,3 +155,5 @@
strerror(errno));
}
}
+
+} // namespace gem5
diff --git a/src/sim/vma.hh b/src/sim/vma.hh
index 8dd3853..b238a2e 100644
--- a/src/sim/vma.hh
+++ b/src/sim/vma.hh
@@ -37,6 +37,9 @@
#include "debug/Vma.hh"
#include "mem/se_translating_port_proxy.hh"
+namespace gem5
+{
+
class VMA
{
class MappedFileBuffer;
@@ -195,4 +198,6 @@
};
};
+} // namespace gem5
+
#endif // __SRC_MEM_VMA_HH__
diff --git a/src/sim/voltage_domain.cc b/src/sim/voltage_domain.cc
index ce9de47..b8debaa 100644
--- a/src/sim/voltage_domain.cc
+++ b/src/sim/voltage_domain.cc
@@ -45,6 +45,9 @@
#include "params/VoltageDomain.hh"
#include "sim/serialize.hh"
+namespace gem5
+{
+
VoltageDomain::VoltageDomain(const Params &p)
: SimObject(p), voltageOpPoints(p.voltage), _perfLevel(0), stats(*this)
{
@@ -143,3 +146,5 @@
{
voltage.method(&vd, &VoltageDomain::voltage);
}
+
+} // namespace gem5
diff --git a/src/sim/voltage_domain.hh b/src/sim/voltage_domain.hh
index 7b227fa..5fbfa53 100644
--- a/src/sim/voltage_domain.hh
+++ b/src/sim/voltage_domain.hh
@@ -45,6 +45,9 @@
#include "sim/clock_domain.hh"
#include "sim/sim_object.hh"
+namespace gem5
+{
+
/**
* A VoltageDomain is used to group clock domains that operate under
* the same voltage. The class provides methods for setting and
@@ -156,4 +159,6 @@
SrcClockChildren srcClockChildren;
};
+} // namespace gem5
+
#endif
diff --git a/src/sim/workload.cc b/src/sim/workload.cc
index 0951a87..d208a58 100644
--- a/src/sim/workload.cc
+++ b/src/sim/workload.cc
@@ -32,6 +32,9 @@
#include "cpu/thread_context.hh"
#include "sim/debug.hh"
+namespace gem5
+{
+
void
Workload::registerThreadContext(ThreadContext *tc)
{
@@ -100,3 +103,5 @@
}
# endif
}
+
+} // namespace gem5
diff --git a/src/sim/workload.hh b/src/sim/workload.hh
index a30020a..fa62555 100644
--- a/src/sim/workload.hh
+++ b/src/sim/workload.hh
@@ -37,6 +37,9 @@
#include "sim/sim_object.hh"
#include "sim/stats.hh"
+namespace gem5
+{
+
class BaseRemoteGDB;
class System;
class ThreadContext;
@@ -156,4 +159,6 @@
/** @} */
};
+} // namespace gem5
+
#endif // __SIM_WORKLOAD_HH__
diff --git a/src/systemc/channel/sc_in_resolved.cc b/src/systemc/channel/sc_in_resolved.cc
index 4b65dcd..fa9d0c0 100644
--- a/src/systemc/channel/sc_in_resolved.cc
+++ b/src/systemc/channel/sc_in_resolved.cc
@@ -45,7 +45,7 @@
{
sc_in<sc_dt::sc_logic>::end_of_elaboration();
if (!dynamic_cast<sc_signal_resolved *>(get_interface())) {
- std::string msg = csprintf("port '%s' (%s)", name(), kind());
+ std::string msg = gem5::csprintf("port '%s' (%s)", name(), kind());
SC_REPORT_ERROR("(E117) resolved port not bound to resolved signal",
msg.c_str());
}
diff --git a/src/systemc/channel/sc_inout_resolved.cc b/src/systemc/channel/sc_inout_resolved.cc
index c5313fd..43e4f85 100644
--- a/src/systemc/channel/sc_inout_resolved.cc
+++ b/src/systemc/channel/sc_inout_resolved.cc
@@ -47,7 +47,7 @@
{
sc_inout<sc_dt::sc_logic>::end_of_elaboration();
if (!dynamic_cast<sc_signal_resolved *>(get_interface())) {
- std::string msg = csprintf("port '%s' (%s)", name(), kind());
+ std::string msg = gem5::csprintf("port '%s' (%s)", name(), kind());
SC_REPORT_ERROR(SC_ID_RESOLVED_PORT_NOT_BOUND_, msg.c_str());
}
}
diff --git a/src/systemc/core/kernel.cc b/src/systemc/core/kernel.cc
index 3bb27f2..a9ff4bb 100644
--- a/src/systemc/core/kernel.cc
+++ b/src/systemc/core/kernel.cc
@@ -55,7 +55,8 @@
void Kernel::status(sc_core::sc_status s) { _status = s; }
Kernel::Kernel(const Params ¶ms, int) :
- SimObject(params), t0Event(this, false, EventBase::Default_Pri - 1)
+ gem5::SimObject(params),
+ t0Event(this, false, gem5::EventBase::Default_Pri - 1)
{
// Install ourselves as the scheduler's event manager.
::sc_gem5::scheduler.setEventQueue(eventQueue());
@@ -111,7 +112,7 @@
if (scMainFiber.finished())
return;
- schedule(t0Event, curTick());
+ schedule(t0Event, gem5::curTick());
if (stopAfterCallbacks)
return;
@@ -183,8 +184,9 @@
} // namespace sc_gem5
sc_gem5::Kernel *
-SystemC_KernelParams::create() const
+gem5::SystemC_KernelParams::create() const
{
+ using namespace gem5;
panic_if(sc_gem5::kernel,
"Only one systemc kernel object may be defined.\n");
sc_gem5::kernel = new sc_gem5::Kernel(*this, 0);
diff --git a/src/systemc/core/kernel.hh b/src/systemc/core/kernel.hh
index 9bea0db..9dba903 100644
--- a/src/systemc/core/kernel.hh
+++ b/src/systemc/core/kernel.hh
@@ -42,10 +42,10 @@
* accordingly. It also acts as a collecting point for systemc related
* control functionality.
*/
-class Kernel : public SimObject
+class Kernel : public gem5::SimObject
{
public:
- typedef SystemC_KernelParams Params;
+ typedef gem5::SystemC_KernelParams Params;
Kernel(const Params ¶ms, int);
void init() override;
@@ -65,7 +65,7 @@
private:
static void stopWork();
- EventWrapper<Kernel, &Kernel::t0Handler> t0Event;
+ gem5::EventWrapper<Kernel, &Kernel::t0Handler> t0Event;
};
extern Kernel *kernel;
diff --git a/src/systemc/core/module.cc b/src/systemc/core/module.cc
index 16553b6..d6f992c 100644
--- a/src/systemc/core/module.cc
+++ b/src/systemc/core/module.cc
@@ -52,6 +52,7 @@
_name(name), _sc_mod(nullptr), _obj(nullptr), _ended(false),
_deprecatedConstructor(false), bindingIndex(0)
{
+ using namespace gem5;
panic_if(_new_module, "Previous module not finished.\n");
_new_module = this;
}
@@ -95,6 +96,7 @@
if (_modules.empty() || _modules.back() != this)
return;
+ using namespace gem5;
panic_if(_new_module, "Pop with unfinished module.\n");
_modules.pop_back();
@@ -104,6 +106,7 @@
void
Module::bindPorts(std::vector<const ::sc_core::sc_bind_proxy *> &proxies)
{
+ using namespace gem5;
panic_if(proxies.size() > ports.size(),
"Trying to bind %d interfaces/ports to %d ports.\n",
proxies.size(), ports.size());
@@ -141,7 +144,7 @@
Module::endOfElaboration()
{
if (_deprecatedConstructor && !_ended) {
- std::string msg = csprintf("module '%s'", name());
+ std::string msg = gem5::csprintf("module '%s'", name());
SC_REPORT_WARNING(sc_core::SC_ID_END_MODULE_NOT_CALLED_, msg.c_str());
}
pushParentModule(this);
diff --git a/src/systemc/core/process.cc b/src/systemc/core/process.cc
index 023f09d..08c0d6a 100644
--- a/src/systemc/core/process.cc
+++ b/src/systemc/core/process.cc
@@ -382,7 +382,7 @@
_needsStart(true), _isUnwinding(false), _terminated(false),
_scheduled(false), _suspended(false), _disabled(false),
_syncReset(false), syncResetCount(0), asyncResetCount(0), _waitCount(0),
- refCount(0), stackSize(::Fiber::DefaultStackSize),
+ refCount(0), stackSize(gem5::Fiber::DefaultStackSize),
dynamicSensitivity(nullptr)
{
_dynamic =
diff --git a/src/systemc/core/process.hh b/src/systemc/core/process.hh
index 77fa18a..e83f155 100644
--- a/src/systemc/core/process.hh
+++ b/src/systemc/core/process.hh
@@ -118,7 +118,7 @@
void ready();
- virtual Fiber *fiber() { return Fiber::primaryFiber(); }
+ virtual gem5::Fiber *fiber() { return gem5::Fiber::primaryFiber(); }
static Process *newest() { return _newest; }
diff --git a/src/systemc/core/process_types.hh b/src/systemc/core/process_types.hh
index 8849ec8..748b35a 100644
--- a/src/systemc/core/process_types.hh
+++ b/src/systemc/core/process_types.hh
@@ -67,7 +67,7 @@
return sc_core::SC_THREAD_PROC_;
}
- Fiber *
+ gem5::Fiber *
fiber() override
{
if (!ctx)
@@ -76,10 +76,12 @@
}
private:
- class Context : public Fiber
+ class Context : public gem5::Fiber
{
public:
- Context(Thread *thread, size_t size) : Fiber(size), thread(thread) {}
+ Context(Thread *thread, size_t size)
+ : gem5::Fiber(size), thread(thread)
+ {}
private:
Thread *thread;
diff --git a/src/systemc/core/python.cc b/src/systemc/core/python.cc
index 363b634..8f2d56b 100644
--- a/src/systemc/core/python.cc
+++ b/src/systemc/core/python.cc
@@ -67,7 +67,7 @@
for (auto ptr = firstInitFunc(); ptr; ptr = ptr->next)
ptr->run(m);
}
-EmbeddedPyBind embed_("systemc", &systemc_pybind);
+gem5::EmbeddedPyBind embed_("systemc", &systemc_pybind);
} // anonymous namespace
diff --git a/src/systemc/core/sc_export.cc b/src/systemc/core/sc_export.cc
index 04af4d9..fdfd930 100644
--- a/src/systemc/core/sc_export.cc
+++ b/src/systemc/core/sc_export.cc
@@ -44,9 +44,9 @@
{
std::string msg;
if (add_msg)
- msg = csprintf("%s: export '%s' (%s)", add_msg, name, kind);
+ msg = gem5::csprintf("%s: export '%s' (%s)", add_msg, name, kind);
else
- msg = csprintf("export '%s' (%s)", name, kind);
+ msg = gem5::csprintf("export '%s' (%s)", name, kind);
SC_REPORT_ERROR(id, msg.c_str());
}
diff --git a/src/systemc/core/sc_main.cc b/src/systemc/core/sc_main.cc
index d5c3e21..d95b1b9 100644
--- a/src/systemc/core/sc_main.cc
+++ b/src/systemc/core/sc_main.cc
@@ -60,8 +60,8 @@
void
sc_start()
{
- Tick now = ::sc_gem5::scheduler.getCurTick();
- sc_start(sc_time::from_value(MaxTick - now), SC_EXIT_ON_STARVATION);
+ gem5::Tick now = ::sc_gem5::scheduler.getCurTick();
+ sc_start(sc_time::from_value(gem5::MaxTick - now), SC_EXIT_ON_STARVATION);
}
void
@@ -77,8 +77,8 @@
if (time.value() == 0) {
::sc_gem5::scheduler.oneCycle();
} else {
- Tick now = ::sc_gem5::scheduler.getCurTick();
- if (MaxTick - now < time.value())
+ gem5::Tick now = ::sc_gem5::scheduler.getCurTick();
+ if (gem5::MaxTick - now < time.value())
SC_REPORT_ERROR(SC_ID_SIMULATION_TIME_OVERFLOW_, "");
::sc_gem5::scheduler.start(now + time.value(), p == SC_RUN_TO_TIME);
}
@@ -228,7 +228,7 @@
}
os << ")";
} else {
- ccprintf(os, "%#x", s);
+ gem5::ccprintf(os, "%#x", s);
}
}
diff --git a/src/systemc/core/sc_main_fiber.cc b/src/systemc/core/sc_main_fiber.cc
index c3bd74f..3d1cb73 100644
--- a/src/systemc/core/sc_main_fiber.cc
+++ b/src/systemc/core/sc_main_fiber.cc
@@ -47,6 +47,8 @@
void
ScMainFiber::main()
{
+ using namespace gem5;
+
_called = true;
if (::sc_main) {
diff --git a/src/systemc/core/sc_main_fiber.hh b/src/systemc/core/sc_main_fiber.hh
index dc46cdb..d12c00f 100644
--- a/src/systemc/core/sc_main_fiber.hh
+++ b/src/systemc/core/sc_main_fiber.hh
@@ -34,7 +34,7 @@
namespace sc_gem5
{
-class ScMainFiber : public Fiber
+class ScMainFiber : public gem5::Fiber
{
private:
int _argc = 0;
@@ -45,7 +45,7 @@
bool _called = false;
public:
- ScMainFiber() : Fiber(8 * 1024 * 1024) {}
+ ScMainFiber() : gem5::Fiber(8 * 1024 * 1024) {}
int argc() { return _argc; }
const char *const *argv() { return _argv; }
diff --git a/src/systemc/core/sc_main_python.cc b/src/systemc/core/sc_main_python.cc
index 4b17223..1697efe 100644
--- a/src/systemc/core/sc_main_python.cc
+++ b/src/systemc/core/sc_main_python.cc
@@ -42,6 +42,7 @@
void
sc_main(pybind11::args args)
{
+ using namespace gem5;
panic_if(::sc_gem5::scMainFiber.called(),
"sc_main called more than once.");
diff --git a/src/systemc/core/sc_module.cc b/src/systemc/core/sc_module.cc
index 99fec31..41426ac 100644
--- a/src/systemc/core/sc_module.cc
+++ b/src/systemc/core/sc_module.cc
@@ -113,7 +113,7 @@
const sc_bind_proxy SC_BIND_PROXY_NIL;
-::Port &
+gem5::Port &
sc_module::gem5_getPort(const std::string &if_name, int idx)
{
fatal("%s does not have any port named %s\n", name(), if_name);
@@ -664,7 +664,7 @@
wait(int n)
{
if (n <= 0) {
- std::string msg = csprintf("n = %d", n);
+ std::string msg = gem5::csprintf("n = %d", n);
SC_REPORT_ERROR(SC_ID_WAIT_N_INVALID_, msg.c_str());
}
sc_gem5::Process *p = sc_gem5::scheduler.current();
diff --git a/src/systemc/core/sc_port.cc b/src/systemc/core/sc_port.cc
index 7d7d0ef..44b739e 100644
--- a/src/systemc/core/sc_port.cc
+++ b/src/systemc/core/sc_port.cc
@@ -47,9 +47,9 @@
{
std::string msg;
if (add_msg)
- msg = csprintf("%s: port '%s' (%s)", add_msg, name, kind);
+ msg = gem5::csprintf("%s: port '%s' (%s)", add_msg, name, kind);
else
- msg = csprintf("port '%s' (%s)", name, kind);
+ msg = gem5::csprintf("port '%s' (%s)", name, kind);
SC_REPORT_ERROR(id, msg.c_str());
}
diff --git a/src/systemc/core/sc_time.cc b/src/systemc/core/sc_time.cc
index 4c620e1..f74a343 100644
--- a/src/systemc/core/sc_time.cc
+++ b/src/systemc/core/sc_time.cc
@@ -48,9 +48,9 @@
set(::sc_core::sc_time *time, double d, ::sc_core::sc_time_unit tu)
{
if (d != 0)
- fixClockFrequency();
+ gem5::fixClockFrequency();
- double scale = sc_gem5::TimeUnitScale[tu] * sim_clock::as_float::s;
+ double scale = sc_gem5::TimeUnitScale[tu] * gem5::sim_clock::as_float::s;
// Accellera claims there is a linux bug, and that these next two
// lines work around them.
volatile double tmp = d * scale + 0.5;
@@ -94,13 +94,13 @@
sc_time::sc_time(double d, bool scale)
{
- double scaler = scale ? defaultUnit : sim_clock::as_float::Hz;
+ double scaler = scale ? defaultUnit : gem5::sim_clock::as_float::Hz;
set(this, d * scaler, SC_SEC);
}
sc_time::sc_time(sc_dt::uint64 v, bool scale)
{
- double scaler = scale ? defaultUnit : sim_clock::as_float::Hz;
+ double scaler = scale ? defaultUnit : gem5::sim_clock::as_float::Hz;
set(this, static_cast<double>(v) * scaler, SC_SEC);
}
@@ -125,7 +125,7 @@
double
sc_time::to_seconds() const
{
- return to_double() * sim_clock::as_float::Hz;
+ return to_double() * gem5::sim_clock::as_float::Hz;
}
const std::string
@@ -210,7 +210,7 @@
sc_time::from_value(sc_dt::uint64 u)
{
if (u)
- fixClockFrequency();
+ gem5::fixClockFrequency();
sc_time t;
t.val = u;
return t;
@@ -309,7 +309,7 @@
// This won't detect the timescale being fixed outside of systemc, but
// it's at least some protection.
- if (clockFrequencyFixed()) {
+ if (gem5::clockFrequencyFixed()) {
SC_REPORT_ERROR(SC_ID_SET_TIME_RESOLUTION_,
"sc_time object(s) constructed");
}
@@ -329,9 +329,9 @@
tu = (sc_time_unit)(tu - 1);
}
- Tick ticks_per_second =
- sc_gem5::TimeUnitFrequency[tu] / static_cast<Tick>(d);
- setClockFrequency(ticks_per_second);
+ gem5::Tick ticks_per_second =
+ sc_gem5::TimeUnitFrequency[tu] / static_cast<gem5::Tick>(d);
+ gem5::setClockFrequency(ticks_per_second);
specified = true;
}
@@ -344,7 +344,7 @@
const sc_time &
sc_max_time()
{
- static const sc_time MaxScTime = sc_time::from_value(MaxTick);
+ static const sc_time MaxScTime = sc_time::from_value(gem5::MaxTick);
return MaxScTime;
}
@@ -368,7 +368,7 @@
}
// This won't detect the timescale being fixed outside of systemc, but
// it's at least some protection.
- if (clockFrequencyFixed()) {
+ if (gem5::clockFrequencyFixed()) {
SC_REPORT_ERROR(SC_ID_SET_DEFAULT_TIME_UNIT_,
"sc_time object(s) constructed");
}
@@ -377,7 +377,7 @@
defaultUnit = d * sc_gem5::TimeUnitScale[tu];
specified = true;
- double resolution = sim_clock::as_float::Hz;
+ double resolution = gem5::sim_clock::as_float::Hz;
if (resolution == 0.0)
resolution = sc_gem5::TimeUnitScale[SC_PS];
if (defaultUnit < resolution) {
@@ -398,7 +398,7 @@
if (!t.value())
return;
- Tick frequency = sim_clock::Frequency;
+ gem5::Tick frequency = gem5::sim_clock::Frequency;
// Shrink the frequency by scaling down the time period, ie converting
// it from cycles per second to cycles per millisecond, etc.
@@ -408,7 +408,7 @@
}
// Convert the frequency into a period.
- Tick period;
+ gem5::Tick period;
if (frequency > 1) {
_unit = (sc_time_unit)((int)_unit - 1);
period = 1000 / frequency;
diff --git a/src/systemc/core/sched_event.hh b/src/systemc/core/sched_event.hh
index b21b6b2..f972ab6 100644
--- a/src/systemc/core/sched_event.hh
+++ b/src/systemc/core/sched_event.hh
@@ -44,14 +44,14 @@
{
private:
std::function<void()> work;
- Tick _when;
+ gem5::Tick _when;
ScEvents *_events;
ScEvents::iterator _it;
friend class Scheduler;
void
- schedule(ScEvents &events, Tick w)
+ schedule(ScEvents &events, gem5::Tick w)
{
when(w);
assert(!scheduled());
@@ -70,7 +70,7 @@
}
public:
ScEvent(std::function<void()> work) :
- work(work), _when(MaxTick), _events(nullptr)
+ work(work), _when(gem5::MaxTick), _events(nullptr)
{}
~ScEvent();
@@ -78,8 +78,8 @@
bool scheduled() { return _events != nullptr; }
ScEvents *scheduledOn() { return _events; }
- void when(Tick w) { _when = w; }
- Tick when() { return _when; }
+ void when(gem5::Tick w) { _when = w; }
+ gem5::Tick when() { return _when; }
void run() { deschedule(); work(); }
};
diff --git a/src/systemc/core/scheduler.cc b/src/systemc/core/scheduler.cc
index cc0be7c..42a2ca4 100644
--- a/src/systemc/core/scheduler.cc
+++ b/src/systemc/core/scheduler.cc
@@ -49,7 +49,7 @@
stopEvent(this, false, StopPriority), _throwUp(nullptr),
starvationEvent(this, false, StarvationPriority),
_elaborationDone(false), _started(false), _stopNow(false),
- _status(StatusOther), maxTick(::MaxTick),
+ _status(StatusOther), maxTick(gem5::MaxTick),
maxTickEvent(this, false, MaxTickPriority),
timeAdvancesEvent(this, false, TimeAdvancesPriority), _numCycles(0),
_changeStamp(0), _current(nullptr), initDone(false), runToTime(true),
@@ -163,7 +163,7 @@
_current = getNextReady();
if (!_current) {
// There are no more processes, so return control to evaluate.
- Fiber::primaryFiber()->run();
+ gem5::Fiber::primaryFiber()->run();
} else {
_current->popListNode();
_current->scheduled(false);
@@ -362,6 +362,8 @@
void
Scheduler::pause()
{
+ using namespace gem5;
+
status(StatusPaused);
kernel->status(::sc_core::SC_PAUSED);
runOnce = false;
@@ -372,13 +374,15 @@
if (scMainFiber.finished())
fatal("Pausing systemc after sc_main completed.");
else
- exitSimLoopNow("systemc pause");
+ gem5::exitSimLoopNow("systemc pause");
}
}
void
Scheduler::stop()
{
+ using namespace gem5;
+
status(StatusStopped);
kernel->stop();
@@ -392,12 +396,12 @@
if (scMainFiber.finished())
fatal("Stopping systemc after sc_main completed.");
else
- exitSimLoopNow("systemc stop");
+ gem5::exitSimLoopNow("systemc stop");
}
}
void
-Scheduler::start(Tick max_tick, bool run_to_time)
+Scheduler::start(gem5::Tick max_tick, bool run_to_time)
{
_started = true;
status(StatusOther);
@@ -416,7 +420,7 @@
scheduleTimeAdvancesEvent();
// Return to gem5 to let it run events, etc.
- Fiber::primaryFiber()->run();
+ gem5::Fiber::primaryFiber()->run();
if (pauseEvent.scheduled())
deschedule(&pauseEvent);
@@ -439,7 +443,7 @@
{
runOnce = true;
scheduleReadyEvent();
- start(::MaxTick, false);
+ start(gem5::MaxTick, false);
}
void
diff --git a/src/systemc/core/scheduler.hh b/src/systemc/core/scheduler.hh
index 13f35ed..c73a6f1 100644
--- a/src/systemc/core/scheduler.hh
+++ b/src/systemc/core/scheduler.hh
@@ -150,15 +150,15 @@
public:
typedef std::list<ScEvent *> ScEvents;
- class TimeSlot : public ::Event
+ class TimeSlot : public gem5::Event
{
public:
- TimeSlot(Scheduler* scheduler) : ::Event(Default_Pri, AutoDelete),
+ TimeSlot(Scheduler* scheduler) : gem5::Event(Default_Pri, AutoDelete),
parent_scheduler(scheduler) {}
// Event::when() is only set after it's scheduled to an event queue.
// However, TimeSlot won't be scheduled before init is done. We need
// to keep the real 'targeted_when' information before scheduled.
- Tick targeted_when;
+ gem5::Tick targeted_when;
Scheduler* parent_scheduler;
ScEvents events;
void process() override;
@@ -238,12 +238,12 @@
}
// Set an event queue for scheduling events.
- void setEventQueue(EventQueue *_eq) { eq = _eq; }
+ void setEventQueue(gem5::EventQueue *_eq) { eq = _eq; }
// Get the current time according to gem5.
- Tick getCurTick() { return eq ? eq->getCurTick() : 0; }
+ gem5::Tick getCurTick() { return eq ? eq->getCurTick() : 0; }
- Tick
+ gem5::Tick
delayed(const ::sc_core::sc_time &delay)
{
return getCurTick() + delay.value();
@@ -253,7 +253,7 @@
void
schedule(ScEvent *event, const ::sc_core::sc_time &delay)
{
- Tick tick = delayed(delay);
+ gem5::Tick tick = delayed(delay);
if (tick < getCurTick())
tick = getCurTick();
@@ -280,6 +280,8 @@
void
deschedule(ScEvent *event)
{
+ using namespace gem5;
+
ScEvents *on = event->scheduledOn();
if (on == &deltas) {
@@ -341,14 +343,14 @@
}
// Return how many ticks there are until the first pending event, if any.
- Tick
+ gem5::Tick
timeToPending()
{
if (pendingCurr())
return 0;
if (pendingFuture())
return timeSlots.front()->targeted_when - getCurTick();
- return MaxTick - getCurTick();
+ return gem5::MaxTick - getCurTick();
}
// Run scheduled channel updates.
@@ -357,7 +359,7 @@
// Run delta events.
void runDelta();
- void start(Tick max_tick, bool run_to_time);
+ void start(gem5::Tick max_tick, bool run_to_time);
void oneCycle();
void schedulePause();
@@ -398,7 +400,7 @@
void unregisterTraceFile(TraceFile *tf) { traceFiles.erase(tf); }
TimeSlot*
- acquireTimeSlot(Tick tick)
+ acquireTimeSlot(gem5::Tick tick)
{
TimeSlot *ts = nullptr;
if (!freeTimeSlots.empty()) {
@@ -419,21 +421,21 @@
}
private:
- typedef const EventBase::Priority Priority;
- static Priority DefaultPriority = EventBase::Default_Pri;
+ typedef const gem5::EventBase::Priority Priority;
+ static Priority DefaultPriority = gem5::EventBase::Default_Pri;
static Priority StopPriority = DefaultPriority - 1;
static Priority PausePriority = DefaultPriority + 1;
static Priority MaxTickPriority = DefaultPriority + 2;
static Priority ReadyPriority = DefaultPriority + 3;
static Priority StarvationPriority = ReadyPriority;
- static Priority TimeAdvancesPriority = EventBase::Maximum_Pri;
+ static Priority TimeAdvancesPriority = gem5::EventBase::Maximum_Pri;
- EventQueue *eq;
+ gem5::EventQueue *eq;
// For gem5 style events.
void
- schedule(::Event *event, Tick tick)
+ schedule(gem5::Event *event, gem5::Tick tick)
{
if (initDone)
eq->schedule(event, tick);
@@ -441,10 +443,10 @@
eventsToSchedule[event] = tick;
}
- void schedule(::Event *event) { schedule(event, getCurTick()); }
+ void schedule(gem5::Event *event) { schedule(event, getCurTick()); }
void
- deschedule(::Event *event)
+ deschedule(gem5::Event *event)
{
if (initDone)
eq->deschedule(event);
@@ -464,13 +466,13 @@
}
void runReady();
- EventWrapper<Scheduler, &Scheduler::runReady> readyEvent;
+ gem5::EventWrapper<Scheduler, &Scheduler::runReady> readyEvent;
void scheduleReadyEvent();
void pause();
void stop();
- EventWrapper<Scheduler, &Scheduler::pause> pauseEvent;
- EventWrapper<Scheduler, &Scheduler::stop> stopEvent;
+ gem5::EventWrapper<Scheduler, &Scheduler::pause> pauseEvent;
+ gem5::EventWrapper<Scheduler, &Scheduler::stop> stopEvent;
const ::sc_core::sc_report *_throwUp;
@@ -483,7 +485,7 @@
timeSlots.front()->targeted_when > maxTick) &&
initList.empty());
}
- EventWrapper<Scheduler, &Scheduler::pause> starvationEvent;
+ gem5::EventWrapper<Scheduler, &Scheduler::pause> starvationEvent;
void scheduleStarvationEvent();
bool _elaborationDone;
@@ -492,8 +494,8 @@
Status _status;
- Tick maxTick;
- Tick lastReadyTick;
+ gem5::Tick maxTick;
+ gem5::Tick lastReadyTick;
void
maxTickFunc()
{
@@ -501,10 +503,10 @@
_changeStamp++;
pause();
}
- EventWrapper<Scheduler, &Scheduler::maxTickFunc> maxTickEvent;
+ gem5::EventWrapper<Scheduler, &Scheduler::maxTickFunc> maxTickEvent;
void timeAdvances() { trace(false); }
- EventWrapper<Scheduler, &Scheduler::timeAdvances> timeAdvancesEvent;
+ gem5::EventWrapper<Scheduler, &Scheduler::timeAdvances> timeAdvancesEvent;
void
scheduleTimeAdvancesEvent()
{
@@ -532,7 +534,7 @@
std::mutex asyncListMutex;
std::atomic<bool> hasAsyncUpdate;
- std::map<::Event *, Tick> eventsToSchedule;
+ std::map<gem5::Event *, gem5::Tick> eventsToSchedule;
std::set<TraceFile *> traceFiles;
diff --git a/src/systemc/core/time.cc b/src/systemc/core/time.cc
index 0434c6d..10e9cb0 100644
--- a/src/systemc/core/time.cc
+++ b/src/systemc/core/time.cc
@@ -59,7 +59,7 @@
[::sc_core::SC_SEC] = 1.0
};
-Tick TimeUnitFrequency[] = {
+gem5::Tick TimeUnitFrequency[] = {
[::sc_core::SC_FS] = 1ULL * 1000 * 1000 * 1000 * 1000 * 1000,
[::sc_core::SC_PS] = 1ULL * 1000 * 1000 * 1000 * 1000,
[::sc_core::SC_NS] = 1ULL * 1000 * 1000 * 1000,
diff --git a/src/systemc/core/time.hh b/src/systemc/core/time.hh
index 7744a41..a962b38 100644
--- a/src/systemc/core/time.hh
+++ b/src/systemc/core/time.hh
@@ -36,7 +36,7 @@
extern const char *TimeUnitNames[];
extern const char *TimeUnitConstantNames[];
extern double TimeUnitScale[];
-extern Tick TimeUnitFrequency[];
+extern gem5::Tick TimeUnitFrequency[];
} // namespace sc_gem5
diff --git a/src/systemc/ext/core/sc_module.hh b/src/systemc/ext/core/sc_module.hh
index 93a1653..e92b681 100644
--- a/src/systemc/ext/core/sc_module.hh
+++ b/src/systemc/ext/core/sc_module.hh
@@ -31,6 +31,7 @@
#include <string>
#include <vector>
+#include "mem/port.hh"
#include "sc_object.hh"
#include "sc_process_handle.hh"
#include "sc_sensitive.hh"
@@ -98,7 +99,7 @@
{
public:
// Gem5 specific extensions
- virtual ::Port &gem5_getPort(const std::string &if_name, int idx=-1);
+ virtual gem5::Port &gem5_getPort(const std::string &if_name, int idx=-1);
public:
friend class ::sc_gem5::Kernel;
diff --git a/src/systemc/sc_port_wrapper.hh b/src/systemc/sc_port_wrapper.hh
index ab8d9ea..1500d06 100644
--- a/src/systemc/sc_port_wrapper.hh
+++ b/src/systemc/sc_port_wrapper.hh
@@ -49,13 +49,13 @@
class ScExportWrapper;
template <typename IF>
-class ScPortWrapper : public ::Port
+class ScPortWrapper : public gem5::Port
{
public:
using ScPort = sc_core::sc_port_b<IF>;
- ScPortWrapper(ScPort& p, const std::string& name, PortID id)
- : Port(name, id), port_(p)
+ ScPortWrapper(ScPort& p, const std::string& name, gem5::PortID id)
+ : gem5::Port(name, id), port_(p)
{}
ScPort&
@@ -67,12 +67,16 @@
void
unbind() override
{
+ using namespace gem5;
+
panic("sc_port can't be unbound.");
}
void
- bind(::Port& peer) override
+ bind(gem5::Port& peer) override
{
+ using namespace gem5;
+
// Try ScPortWrapper or ScInterfaceWrapper
if (auto* beer = dynamic_cast<ScPortWrapper<IF>*>(&peer)) {
port_.bind(beer->port());
@@ -83,7 +87,7 @@
fatal("Attempt to bind sc_port %s to incompatible port %s.",
name(), peer.name());
}
- Port::bind(peer);
+ gem5::Port::bind(peer);
}
private:
@@ -91,11 +95,11 @@
};
template <typename IF>
-class ScInterfaceWrapper : public ::Port
+class ScInterfaceWrapper : public gem5::Port
{
public:
- ScInterfaceWrapper(IF& i, const std::string name, PortID id)
- : Port(name, id), iface_(i)
+ ScInterfaceWrapper(IF& i, const std::string name, gem5::PortID id)
+ : gem5::Port(name, id), iface_(i)
{}
IF&
@@ -107,12 +111,16 @@
void
unbind() override
{
+ using namespace gem5;
+
panic("sc_interface can't be unbound.");
}
void
- bind(::Port& peer) override
+ bind(gem5::Port& peer) override
{
+ using namespace gem5;
+
// fatal error if peer is neither ScPortWrapper nor ScExportWrapper
fatal_if(!dynamic_cast<ScPortWrapper<IF>*>(&peer) &&
!dynamic_cast<ScExportWrapper<IF>*>(&peer),
@@ -122,7 +130,7 @@
// Don't bind to peer otherwise we may have error messages saying that
// this interface has already be bound since the peer may already did
// that. Just let sc_port or sc_export do the binding
- Port::bind(peer);
+ gem5::Port::bind(peer);
}
private:
@@ -130,13 +138,13 @@
};
template <typename IF>
-class ScExportWrapper : public ::Port
+class ScExportWrapper : public gem5::Port
{
public:
using ScExport = sc_core::sc_export<IF>;
- ScExportWrapper(ScExport& p, const std::string& name, PortID id)
- : Port(name, id), port_(p)
+ ScExportWrapper(ScExport& p, const std::string& name, gem5::PortID id)
+ : gem5::Port(name, id), port_(p)
{}
ScExport&
@@ -148,19 +156,23 @@
void
unbind() override
{
+ using namespace gem5;
+
panic("sc_export cannot be unbound.");
}
void
- bind(::Port& peer) override
+ bind(gem5::Port& peer) override
{
+ using namespace gem5;
+
auto* iface = dynamic_cast<ScInterfaceWrapper<IF>*>(&peer);
fatal_if(!iface,
"Attempt to bind sc_export %s to incompatible port %s.",
name(), peer.name());
port_.bind(iface->interface());
- Port::bind(peer);
+ gem5::Port::bind(peer);
}
private:
diff --git a/src/systemc/tlm_bridge/gem5_to_tlm.cc b/src/systemc/tlm_bridge/gem5_to_tlm.cc
index bde7537..37da822 100644
--- a/src/systemc/tlm_bridge/gem5_to_tlm.cc
+++ b/src/systemc/tlm_bridge/gem5_to_tlm.cc
@@ -70,6 +70,8 @@
#include "systemc/tlm_bridge/sc_ext.hh"
#include "systemc/tlm_bridge/sc_mm.hh"
+using namespace gem5;
+
namespace sc_gem5
{
@@ -511,7 +513,7 @@
}
template <unsigned int BITWIDTH>
-::Port &
+gem5::Port &
Gem5ToTlmBridge<BITWIDTH>::gem5_getPort(const std::string &if_name, int idx)
{
if (if_name == "gem5")
@@ -537,35 +539,35 @@
} // namespace sc_gem5
sc_gem5::Gem5ToTlmBridge<32> *
-Gem5ToTlmBridge32Params::create() const
+gem5::Gem5ToTlmBridge32Params::create() const
{
return new sc_gem5::Gem5ToTlmBridge<32>(
*this, sc_core::sc_module_name(name.c_str()));
}
sc_gem5::Gem5ToTlmBridge<64> *
-Gem5ToTlmBridge64Params::create() const
+gem5::Gem5ToTlmBridge64Params::create() const
{
return new sc_gem5::Gem5ToTlmBridge<64>(
*this, sc_core::sc_module_name(name.c_str()));
}
sc_gem5::Gem5ToTlmBridge<128> *
-Gem5ToTlmBridge128Params::create() const
+gem5::Gem5ToTlmBridge128Params::create() const
{
return new sc_gem5::Gem5ToTlmBridge<128>(
*this, sc_core::sc_module_name(name.c_str()));
}
sc_gem5::Gem5ToTlmBridge<256> *
-Gem5ToTlmBridge256Params::create() const
+gem5::Gem5ToTlmBridge256Params::create() const
{
return new sc_gem5::Gem5ToTlmBridge<256>(
*this, sc_core::sc_module_name(name.c_str()));
}
sc_gem5::Gem5ToTlmBridge<512> *
-Gem5ToTlmBridge512Params::create() const
+gem5::Gem5ToTlmBridge512Params::create() const
{
return new sc_gem5::Gem5ToTlmBridge<512>(
*this, sc_core::sc_module_name(name.c_str()));
diff --git a/src/systemc/tlm_bridge/gem5_to_tlm.hh b/src/systemc/tlm_bridge/gem5_to_tlm.hh
index d29bfd7..0cb925e 100644
--- a/src/systemc/tlm_bridge/gem5_to_tlm.hh
+++ b/src/systemc/tlm_bridge/gem5_to_tlm.hh
@@ -75,11 +75,11 @@
{
using PacketToPayloadConversionStep =
- std::function<void(PacketPtr pkt, tlm::tlm_generic_payload &trans)>;
+ std::function<void(gem5::PacketPtr pkt, tlm::tlm_generic_payload &trans)>;
void addPacketToPayloadConversionStep(PacketToPayloadConversionStep step);
-tlm::tlm_generic_payload *packet2payload(PacketPtr packet);
+tlm::tlm_generic_payload *packet2payload(gem5::PacketPtr packet);
class Gem5ToTlmBridgeBase : public sc_core::sc_module
{
@@ -91,43 +91,44 @@
class Gem5ToTlmBridge : public Gem5ToTlmBridgeBase
{
private:
- class BridgeResponsePort : public ResponsePort
+ class BridgeResponsePort : public gem5::ResponsePort
{
protected:
Gem5ToTlmBridge<BITWIDTH> &bridge;
- AddrRangeList
+ gem5::AddrRangeList
getAddrRanges() const override
{
return bridge.getAddrRanges();
}
- Tick
- recvAtomic(PacketPtr pkt) override
+ gem5::Tick
+ recvAtomic(gem5::PacketPtr pkt) override
{
return bridge.recvAtomic(pkt);
}
- Tick
- recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor) override
+ gem5::Tick
+ recvAtomicBackdoor(gem5::PacketPtr pkt,
+ gem5::MemBackdoorPtr &backdoor) override
{
return bridge.recvAtomicBackdoor(pkt, backdoor);
}
void
- recvFunctional(PacketPtr pkt) override
+ recvFunctional(gem5::PacketPtr pkt) override
{
return bridge.recvFunctional(pkt);
}
bool
- recvTimingReq(PacketPtr pkt) override
+ recvTimingReq(gem5::PacketPtr pkt) override
{
return bridge.recvTimingReq(pkt);
}
bool
- tryTiming(PacketPtr pkt) override
+ tryTiming(gem5::PacketPtr pkt) override
{
return bridge.tryTiming(pkt);
}
bool
- recvTimingSnoopResp(PacketPtr pkt) override
+ recvTimingSnoopResp(gem5::PacketPtr pkt) override
{
return bridge.recvTimingSnoopResp(pkt);
}
@@ -145,7 +146,7 @@
Gem5ToTlmBridge<BITWIDTH>, BITWIDTH> socket;
sc_gem5::TlmInitiatorWrapper<BITWIDTH> wrapper;
- System *system;
+ gem5::System *system;
/**
* A transaction after BEGIN_REQ has been sent but before END_REQ, which
@@ -165,24 +166,25 @@
*/
tlm::tlm_generic_payload *blockingResponse;
- AddrRangeList addrRanges;
+ gem5::AddrRangeList addrRanges;
protected:
void pec(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase);
- MemBackdoorPtr getBackdoor(tlm::tlm_generic_payload &trans);
- AddrRangeMap<MemBackdoorPtr> backdoorMap;
+ gem5::MemBackdoorPtr getBackdoor(tlm::tlm_generic_payload &trans);
+ gem5::AddrRangeMap<gem5::MemBackdoorPtr> backdoorMap;
// The gem5 port interface.
- Tick recvAtomic(PacketPtr packet);
- Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor);
- void recvFunctional(PacketPtr packet);
- bool recvTimingReq(PacketPtr packet);
- bool tryTiming(PacketPtr packet);
- bool recvTimingSnoopResp(PacketPtr packet);
+ gem5::Tick recvAtomic(gem5::PacketPtr packet);
+ gem5::Tick recvAtomicBackdoor(gem5::PacketPtr pkt,
+ gem5::MemBackdoorPtr &backdoor);
+ void recvFunctional(gem5::PacketPtr packet);
+ bool recvTimingReq(gem5::PacketPtr packet);
+ bool tryTiming(gem5::PacketPtr packet);
+ bool recvTimingSnoopResp(gem5::PacketPtr packet);
void recvRespRetry();
- void recvFunctionalSnoop(PacketPtr packet);
- AddrRangeList getAddrRanges() const { return addrRanges; }
+ void recvFunctionalSnoop(gem5::PacketPtr packet);
+ gem5::AddrRangeList getAddrRanges() const { return addrRanges; }
// The TLM initiator interface.
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans,
@@ -192,9 +194,9 @@
sc_dt::uint64 start_range, sc_dt::uint64 end_range);
public:
- ::Port &gem5_getPort(const std::string &if_name, int idx=-1) override;
+ gem5::Port &gem5_getPort(const std::string &if_name, int idx=-1) override;
- typedef Gem5ToTlmBridgeBaseParams Params;
+ typedef gem5::Gem5ToTlmBridgeBaseParams Params;
Gem5ToTlmBridge(const Params &p, const sc_core::sc_module_name &mn);
tlm_utils::simple_initiator_socket<Gem5ToTlmBridge<BITWIDTH>, BITWIDTH> &
diff --git a/src/systemc/tlm_bridge/sc_ext.cc b/src/systemc/tlm_bridge/sc_ext.cc
index 18591d5..ba4078a 100644
--- a/src/systemc/tlm_bridge/sc_ext.cc
+++ b/src/systemc/tlm_bridge/sc_ext.cc
@@ -35,6 +35,8 @@
#include "systemc/ext/utils/sc_report_handler.hh"
+using namespace gem5;
+
namespace Gem5SystemC
{
@@ -78,7 +80,7 @@
}
AtomicExtension::AtomicExtension(
- std::shared_ptr<AtomicOpFunctor> amo_op, bool need_return)
+ std::shared_ptr<gem5::AtomicOpFunctor> amo_op, bool need_return)
: _op(amo_op), _needReturn(need_return)
{
}
@@ -117,7 +119,7 @@
return _needReturn;
}
-AtomicOpFunctor*
+gem5::AtomicOpFunctor*
AtomicExtension::getAtomicOpFunctor() const
{
return _op.get();
diff --git a/src/systemc/tlm_bridge/sc_ext.hh b/src/systemc/tlm_bridge/sc_ext.hh
index 0cdf195..25e6a1c 100644
--- a/src/systemc/tlm_bridge/sc_ext.hh
+++ b/src/systemc/tlm_bridge/sc_ext.hh
@@ -46,7 +46,7 @@
class Gem5Extension: public tlm::tlm_extension<Gem5Extension>
{
public:
- Gem5Extension(PacketPtr _packet);
+ Gem5Extension(gem5::PacketPtr _packet);
virtual tlm_extension_base *clone() const;
virtual void copy_from(const tlm_extension_base &ext);
@@ -55,17 +55,17 @@
const tlm::tlm_generic_payload *payload);
static Gem5Extension &getExtension(
const tlm::tlm_generic_payload &payload);
- PacketPtr getPacket();
+ gem5::PacketPtr getPacket();
private:
- PacketPtr packet;
+ gem5::PacketPtr packet;
};
class AtomicExtension: public tlm::tlm_extension<AtomicExtension>
{
public:
AtomicExtension(
- std::shared_ptr<AtomicOpFunctor> amo_op, bool need_return);
+ std::shared_ptr<gem5::AtomicOpFunctor> amo_op, bool need_return);
virtual tlm_extension_base *clone() const;
virtual void copy_from(const tlm_extension_base &ext);
@@ -76,10 +76,10 @@
const tlm::tlm_generic_payload &payload);
bool needReturn() const;
- AtomicOpFunctor* getAtomicOpFunctor() const;
+ gem5::AtomicOpFunctor* getAtomicOpFunctor() const;
private:
- std::shared_ptr<AtomicOpFunctor> _op;
+ std::shared_ptr<gem5::AtomicOpFunctor> _op;
bool _needReturn;
};
diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.cc b/src/systemc/tlm_bridge/tlm_to_gem5.cc
index 23a2358..3095fd3 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.cc
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.cc
@@ -68,6 +68,8 @@
#include "systemc/ext/core/sc_module_name.hh"
#include "systemc/ext/core/sc_time.hh"
+using namespace gem5;
+
namespace sc_gem5
{
@@ -264,7 +266,7 @@
template <unsigned int BITWIDTH>
void
-TlmToGem5Bridge<BITWIDTH>::invalidateDmi(const ::MemBackdoor &backdoor)
+TlmToGem5Bridge<BITWIDTH>::invalidateDmi(const gem5::MemBackdoor &backdoor)
{
socket->invalidate_direct_mem_ptr(
backdoor.range().start(), backdoor.range().end());
@@ -508,7 +510,7 @@
}
template <unsigned int BITWIDTH>
-::Port &
+gem5::Port &
TlmToGem5Bridge<BITWIDTH>::gem5_getPort(const std::string &if_name, int idx)
{
if (if_name == "gem5")
@@ -568,35 +570,35 @@
} // namespace sc_gem5
sc_gem5::TlmToGem5Bridge<32> *
-TlmToGem5Bridge32Params::create() const
+gem5::TlmToGem5Bridge32Params::create() const
{
return new sc_gem5::TlmToGem5Bridge<32>(
*this, sc_core::sc_module_name(name.c_str()));
}
sc_gem5::TlmToGem5Bridge<64> *
-TlmToGem5Bridge64Params::create() const
+gem5::TlmToGem5Bridge64Params::create() const
{
return new sc_gem5::TlmToGem5Bridge<64>(
*this, sc_core::sc_module_name(name.c_str()));
}
sc_gem5::TlmToGem5Bridge<128> *
-TlmToGem5Bridge128Params::create() const
+gem5::TlmToGem5Bridge128Params::create() const
{
return new sc_gem5::TlmToGem5Bridge<128>(
*this, sc_core::sc_module_name(name.c_str()));
}
sc_gem5::TlmToGem5Bridge<256> *
-TlmToGem5Bridge256Params::create() const
+gem5::TlmToGem5Bridge256Params::create() const
{
return new sc_gem5::TlmToGem5Bridge<256>(
*this, sc_core::sc_module_name(name.c_str()));
}
sc_gem5::TlmToGem5Bridge<512> *
-TlmToGem5Bridge512Params::create() const
+gem5::TlmToGem5Bridge512Params::create() const
{
return new sc_gem5::TlmToGem5Bridge<512>(
*this, sc_core::sc_module_name(name.c_str()));
diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.hh b/src/systemc/tlm_bridge/tlm_to_gem5.hh
index 13a6f24..b0fe62a 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.hh
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.hh
@@ -74,11 +74,12 @@
{
using PayloadToPacketConversionStep =
- std::function<void(PacketPtr pkt, tlm::tlm_generic_payload &trans)>;
+ std::function<void(gem5::PacketPtr pkt, tlm::tlm_generic_payload &trans)>;
void addPayloadToPacketConversionStep(PayloadToPacketConversionStep step);
-PacketPtr payload2packet(RequestorID _id, tlm::tlm_generic_payload &trans);
+gem5::PacketPtr payload2packet(gem5::RequestorID _id,
+ tlm::tlm_generic_payload &trans);
class TlmToGem5BridgeBase : public sc_core::sc_module
{
@@ -90,19 +91,19 @@
class TlmToGem5Bridge : public TlmToGem5BridgeBase
{
private:
- struct TlmSenderState : public Packet::SenderState
+ struct TlmSenderState : public gem5::Packet::SenderState
{
tlm::tlm_generic_payload &trans;
TlmSenderState(tlm::tlm_generic_payload &trans) : trans(trans) {}
};
- class BridgeRequestPort : public RequestPort
+ class BridgeRequestPort : public gem5::RequestPort
{
protected:
TlmToGem5Bridge<BITWIDTH> &bridge;
bool
- recvTimingResp(PacketPtr pkt) override
+ recvTimingResp(gem5::PacketPtr pkt) override
{
return bridge.recvTimingResp(pkt);
}
@@ -120,7 +121,7 @@
bool waitForRetry;
tlm::tlm_generic_payload *pendingRequest;
- PacketPtr pendingPacket;
+ gem5::PacketPtr pendingPacket;
bool needToSendRetry;
@@ -131,7 +132,7 @@
TlmToGem5Bridge<BITWIDTH>, BITWIDTH> socket;
sc_gem5::TlmTargetWrapper<BITWIDTH> wrapper;
- System *system;
+ gem5::System *system;
void sendEndReq(tlm::tlm_generic_payload &trans);
void sendBeginResp(tlm::tlm_generic_payload &trans,
@@ -140,11 +141,11 @@
void handleBeginReq(tlm::tlm_generic_payload &trans);
void handleEndResp(tlm::tlm_generic_payload &trans);
- void destroyPacket(PacketPtr pkt);
+ void destroyPacket(gem5::PacketPtr pkt);
void checkTransaction(tlm::tlm_generic_payload &trans);
- void invalidateDmi(const ::MemBackdoor &backdoor);
+ void invalidateDmi(const gem5::MemBackdoor &backdoor);
protected:
// payload event call back
@@ -160,14 +161,14 @@
tlm::tlm_dmi &dmi_data);
// Gem5 port interface.
- bool recvTimingResp(PacketPtr pkt);
+ bool recvTimingResp(gem5::PacketPtr pkt);
void recvReqRetry();
void recvRangeChange();
public:
- ::Port &gem5_getPort(const std::string &if_name, int idx=-1) override;
+ gem5::Port &gem5_getPort(const std::string &if_name, int idx=-1) override;
- typedef TlmToGem5BridgeBaseParams Params;
+ typedef gem5::TlmToGem5BridgeBaseParams Params;
TlmToGem5Bridge(const Params &p, const sc_core::sc_module_name &mn);
tlm_utils::simple_target_socket<TlmToGem5Bridge<BITWIDTH>, BITWIDTH> &
@@ -178,7 +179,7 @@
void before_end_of_elaboration() override;
- const RequestorID _id;
+ const gem5::RequestorID _id;
};
} // namespace sc_gem5
diff --git a/src/systemc/tlm_port_wrapper.hh b/src/systemc/tlm_port_wrapper.hh
index cdf899b..1253737 100644
--- a/src/systemc/tlm_port_wrapper.hh
+++ b/src/systemc/tlm_port_wrapper.hh
@@ -45,7 +45,7 @@
template <unsigned int BUSWIDTH, typename FW_IF, typename BW_IF, int N,
sc_core::sc_port_policy POL>
-class TlmInitiatorBaseWrapper : public ::Port
+class TlmInitiatorBaseWrapper : public gem5::Port
{
public:
typedef tlm::tlm_base_initiator_socket<BUSWIDTH, FW_IF, BW_IF, N, POL>
@@ -56,24 +56,28 @@
InitiatorSocket &initiator() { return _initiator; }
TlmInitiatorBaseWrapper(
- InitiatorSocket &i, const std::string &_name, PortID _id) :
- Port(_name, _id), _initiator(i)
+ InitiatorSocket &i, const std::string &_name, gem5::PortID _id) :
+ gem5::Port(_name, _id), _initiator(i)
{}
void
- bind(::Port &peer) override
+ bind(gem5::Port &peer) override
{
+ using namespace gem5;
+
auto *target = dynamic_cast<TargetWrapper *>(&peer);
fatal_if(!target, "Attempt to bind TLM initiator socket %s to "
"incompatible port %s.", name(), peer.name());
initiator().bind(target->target());
- Port::bind(peer);
+ gem5::Port::bind(peer);
}
void
unbind() override
{
+ using namespace gem5;
+
panic("TLM sockets can't be unbound.");
}
@@ -83,7 +87,7 @@
template <unsigned int BUSWIDTH, typename FW_IF, typename BW_IF, int N,
sc_core::sc_port_policy POL>
-class TlmTargetBaseWrapper : public ::Port
+class TlmTargetBaseWrapper : public gem5::Port
{
public:
typedef tlm::tlm_base_target_socket<BUSWIDTH, FW_IF, BW_IF, N, POL>
@@ -92,21 +96,23 @@
TargetSocket &target() { return _target; }
TlmTargetBaseWrapper(TargetSocket &t, const std::string &_name,
- PortID _id) :
- Port(_name, _id), _target(t)
+ gem5::PortID _id) :
+ gem5::Port(_name, _id), _target(t)
{}
void
- bind(::Port &peer) override
+ bind(gem5::Port &peer) override
{
// Ignore attempts to bind a target socket. The initiator will
// handle it.
- Port::bind(peer);
+ gem5::Port::bind(peer);
}
void
unbind() override
{
+ using namespace gem5;
+
panic("TLM sockets can't be unbound.");
}
diff --git a/src/systemc/utils/sc_report_handler.cc b/src/systemc/utils/sc_report_handler.cc
index 45c5222..b893b1d 100644
--- a/src/systemc/utils/sc_report_handler.cc
+++ b/src/systemc/utils/sc_report_handler.cc
@@ -279,10 +279,10 @@
const sc_report &report, const sc_actions &actions)
{
if (actions & SC_DISPLAY)
- cprintf("\n%s\n", sc_report_compose_message(report));
+ gem5::cprintf("\n%s\n", sc_report_compose_message(report));
if ((actions & SC_LOG) && logFile) {
- ccprintf(*logFile, "%s: %s\n", report.get_time().to_string(),
+ gem5::ccprintf(*logFile, "%s: %s\n", report.get_time().to_string(),
sc_report_compose_message(report));
}
if (actions & SC_STOP) {
@@ -376,7 +376,7 @@
str << sevName << ": ";
if (id >= 0) {
- ccprintf(str, "(%c%d) ", sevName[0], id);
+ gem5::ccprintf(str, "(%c%d) ", sevName[0], id);
}
str << report.get_msg_type();
@@ -385,13 +385,13 @@
str << ": " << msg;
if (report.get_severity() > SC_INFO) {
- ccprintf(str, "\nIn file: %s:%d", report.get_file_name(),
+ gem5::ccprintf(str, "\nIn file: %s:%d", report.get_file_name(),
report.get_line_number());
::sc_gem5::Process *current = ::sc_gem5::scheduler.current();
const char *name = report.get_process_name();
if (current && sc_is_running() && name) {
- ccprintf(str, "\nIn process: %s @ %s", name,
+ gem5::ccprintf(str, "\nIn process: %s @ %s", name,
report.get_time().to_string());
}
}
diff --git a/src/systemc/utils/sc_vector.cc b/src/systemc/utils/sc_vector.cc
index df4d158..ff62a07 100644
--- a/src/systemc/utils/sc_vector.cc
+++ b/src/systemc/utils/sc_vector.cc
@@ -74,7 +74,7 @@
{
if (index >= size()) {
std::ostringstream ss;
- ccprintf(ss, "%s[%d] >= size() = %d", name(), index, size());
+ gem5::ccprintf(ss, "%s[%d] >= size() = %d", name(), index, size());
SC_REPORT_ERROR(sc_core::SC_ID_OUT_OF_BOUNDS_, ss.str().c_str());
sc_abort();
}
diff --git a/src/systemc/utils/tracefile.cc b/src/systemc/utils/tracefile.cc
index e8f844d..2a74459 100644
--- a/src/systemc/utils/tracefile.cc
+++ b/src/systemc/utils/tracefile.cc
@@ -30,7 +30,6 @@
#include <ctime>
#include <iomanip>
-#include "base/output.hh"
#include "sim/core.hh"
#include "systemc/core/time.hh"
#include "systemc/ext/core/sc_main.hh"
@@ -41,13 +40,13 @@
{
TraceFile::TraceFile(const std::string &name) :
- _os(simout.create(name, true, true)), timeUnitTicks(0),
+ _os(gem5::simout.create(name, true, true)), timeUnitTicks(0),
timeUnitValue(0.0), timeUnitUnit(::sc_core::SC_PS), _traceDeltas(false)
{}
TraceFile::~TraceFile()
{
- simout.close(_os);
+ gem5::simout.close(_os);
}
std::ostream &TraceFile::stream() { return *_os->stream(); }
diff --git a/src/systemc/utils/tracefile.hh b/src/systemc/utils/tracefile.hh
index e592aa4..9f9466c 100644
--- a/src/systemc/utils/tracefile.hh
+++ b/src/systemc/utils/tracefile.hh
@@ -32,6 +32,7 @@
#include <string>
#include <vector>
+#include "base/output.hh"
#include "systemc/core/event.hh"
#include "systemc/ext/channel/sc_signal_in_if.hh"
#include "systemc/ext/core/sc_event.hh"
@@ -190,7 +191,7 @@
class TraceFile : public sc_core::sc_trace_file
{
protected:
- OutputStream *_os;
+ gem5::OutputStream *_os;
uint64_t timeUnitTicks;
double timeUnitValue;
::sc_core::sc_time_unit timeUnitUnit;
diff --git a/src/systemc/utils/vcd.cc b/src/systemc/utils/vcd.cc
index 827e1a1..9cf0bac 100644
--- a/src/systemc/utils/vcd.cc
+++ b/src/systemc/utils/vcd.cc
@@ -164,7 +164,7 @@
int w = value->width();
if (w <= 0) {
- std::string msg = csprintf("'%s' has 0 bits", name);
+ std::string msg = gem5::csprintf("'%s' has 0 bits", name);
// The typo in this error message is intentional to match the
// Accellera output.
SC_REPORT_ERROR("(E710) object cannot not be traced", msg.c_str());
@@ -173,10 +173,10 @@
std::string clean_name = cleanName(name);
if (w == 1) {
- ccprintf(os, "$var %s % 3d %s %s $end\n",
+ gem5::ccprintf(os, "$var %s % 3d %s %s $end\n",
value->vcdType(), w, value->vcdName(), clean_name);
} else {
- ccprintf(os, "$var %s % 3d %s %s [%d:0] $end\n",
+ gem5::ccprintf(os, "$var %s % 3d %s %s [%d:0] $end\n",
value->vcdType(), w, value->vcdName(), clean_name, w - 1);
}
}
@@ -249,12 +249,12 @@
stream() << "$enddefinitions $end" << std::endl << std::endl;
- Tick now = scheduler.getCurTick();
+ gem5::Tick now = scheduler.getCurTick();
std::string timedump_comment =
- csprintf("All initial values are dumped below at time "
+ gem5::csprintf("All initial values are dumped below at time "
"%g sec = %g timescale units.",
- static_cast<double>(now) / sim_clock::as_float::s,
+ static_cast<double>(now) / gem5::sim_clock::as_float::s,
static_cast<double>(now / timeUnitTicks));
writeComment(timedump_comment);
@@ -274,8 +274,10 @@
delete tv;
traceVals.clear();
- if (timeUnitTicks)
- ccprintf(stream(), "#%u\n", scheduler.getCurTick() / timeUnitTicks);
+ if (timeUnitTicks) {
+ gem5::ccprintf(stream(), "#%u\n",
+ scheduler.getCurTick() / timeUnitTicks);
+ }
}
void
@@ -297,7 +299,7 @@
return;
}
- Tick now = scheduler.getCurTick() / timeUnitTicks + deltaOffset;
+ gem5::Tick now = scheduler.getCurTick() / timeUnitTicks + deltaOffset;
if (now <= lastPrintedTime) {
// TODO warn about reversed time?
@@ -309,7 +311,7 @@
if (tv->check()) {
if (!time_printed) {
lastPrintedTime = now;
- ccprintf(stream(), "#%u\n", now);
+ gem5::ccprintf(stream(), "#%u\n", now);
time_printed = true;
}
@@ -349,7 +351,7 @@
void
output(std::ostream &os) override
{
- ccprintf(os, "r%.16g %s\n", this->value(), this->vcdName());
+ gem5::ccprintf(os, "r%.16g %s\n", this->value(), this->vcdName());
}
};
@@ -480,7 +482,7 @@
void
output(std::ostream &os) override
{
- ccprintf(os, "r%.16g %s\n",
+ gem5::ccprintf(os, "r%.16g %s\n",
this->value().to_double(), this->vcdName());
}
};
@@ -577,7 +579,7 @@
const uint64_t val = value().value();
for (int i = 0; i < TimeWidth; i++)
- str[i] = ::bits(val, TimeWidth - i - 1) ? '1' : '0';
+ str[i] = gem5::bits(val, TimeWidth - i - 1) ? '1' : '0';
printVal(os, str);
}
@@ -602,14 +604,14 @@
str[w] = '\0';
const uint64_t val =
- static_cast<uint64_t>(this->value()) & ::mask(sizeof(T) * 8);
+ static_cast<uint64_t>(this->value()) & gem5::mask(sizeof(T) * 8);
- if (::mask(w) < val) {
+ if (gem5::mask(w) < val) {
for (int i = 0; i < w; i++)
str[i] = 'x';
} else {
for (int i = 0; i < w; i++)
- str[i] = ::bits(val, w - i - 1) ? '1' : '0';
+ str[i] = gem5::bits(val, w - i - 1) ? '1' : '0';
}
this->printVal(os, str);
diff --git a/src/systemc/utils/vcd.hh b/src/systemc/utils/vcd.hh
index b3023a8..d673cf1 100644
--- a/src/systemc/utils/vcd.hh
+++ b/src/systemc/utils/vcd.hh
@@ -30,6 +30,7 @@
#include <map>
+#include "base/types.hh"
#include "systemc/utils/tracefile.hh"
namespace sc_gem5
@@ -51,7 +52,7 @@
class VcdTraceFile : public TraceFile
{
private:
- Tick lastPrintedTime;
+ gem5::Tick lastPrintedTime;
uint64_t deltasAtNow;
static const int NextNameChars = 5;
diff --git a/util/cpt_upgrader.py b/util/cpt_upgrader.py
index 6629806..e091af4 100755
--- a/util/cpt_upgrader.py
+++ b/util/cpt_upgrader.py
@@ -293,10 +293,15 @@
print("#include <string>")
print("#include <set>")
print()
+ print("namespace gem5")
+ print("{")
+ print()
print("std::set<std::string> version_tags = {")
for tag in Upgrader.tag_set:
print(" \"{}\",".format(tag))
print("};")
+ print()
+ print("} // namespace gem5")
exit(0)
elif not args.checkpoint:
parser.error("You must specify a checkpoint file to modify or a "
diff --git a/util/cxx_config/main.cc b/util/cxx_config/main.cc
index 2fe4075..ede2d1d 100644
--- a/util/cxx_config/main.cc
+++ b/util/cxx_config/main.cc
@@ -72,6 +72,8 @@
#include "sim/system.hh"
#include "stats.hh"
+using namespace gem5;
+
void
usage(const std::string &prog_name)
{
diff --git a/util/cxx_config/stats.cc b/util/cxx_config/stats.cc
index 80f2479..33a5849 100644
--- a/util/cxx_config/stats.cc
+++ b/util/cxx_config/stats.cc
@@ -40,7 +40,7 @@
*
* C++-only configuration stats handling example
*
- * Register with: statistics::registerHandlers(statsReset, statsDump)
+ * Register with: gem5::statistics::registerHandlers(statsReset, statsDump)
*/
#include <iostream>
@@ -54,7 +54,7 @@
void statsPrepare()
{
- std::list<statistics::Info *> stats = statistics::statsList();
+ std::list<gem5::statistics::Info *> stats = gem5::statistics::statsList();
/* gather_stats -> prepare */
for (auto i = stats.begin(); i != stats.end(); ++i)
@@ -65,26 +65,26 @@
{
std::cerr << "Stats dump\n";
- statistics::processDumpQueue();
+ gem5::statistics::processDumpQueue();
- std::list<statistics::Info *> stats = statistics::statsList();
+ std::list<gem5::statistics::Info *> stats = gem5::statistics::statsList();
statsPrepare();
/* gather_stats -> convert_value */
for (auto i = stats.begin(); i != stats.end(); ++i) {
- statistics::Info *stat = *i;
+ gem5::statistics::Info *stat = *i;
- statistics::ScalarInfo *scalar =
- dynamic_cast<statistics::ScalarInfo *>(stat);
- statistics::VectorInfo *vector =
- dynamic_cast<statistics::VectorInfo *>(stat);
+ gem5::statistics::ScalarInfo *scalar =
+ dynamic_cast<gem5::statistics::ScalarInfo *>(stat);
+ gem5::statistics::VectorInfo *vector =
+ dynamic_cast<gem5::statistics::VectorInfo *>(stat);
if (scalar) {
std::cerr << "SCALAR " << stat->name << ' '
<< scalar->value() << '\n';
} else if (vector) {
- statistics::VResult results = vector->value();
+ gem5::statistics::VResult results = vector->value();
unsigned int index = 0;
for (auto e = results.begin(); e != results.end(); ++e) {
@@ -104,12 +104,12 @@
{
std::cerr << "Stats reset\n";
- statistics::processResetQueue();
+ gem5::statistics::processResetQueue();
}
void statsEnable()
{
- std::list<statistics::Info *> stats = statistics::statsList();
+ std::list<gem5::statistics::Info *> stats = gem5::statistics::statsList();
for (auto i = stats.begin(); i != stats.end(); ++i)
(*i)->enable();
diff --git a/util/systemc/gem5_within_systemc/main.cc b/util/systemc/gem5_within_systemc/main.cc
index 6e2bd55..e9e2dd5 100644
--- a/util/systemc/gem5_within_systemc/main.cc
+++ b/util/systemc/gem5_within_systemc/main.cc
@@ -71,6 +71,8 @@
#include "sim/system.hh"
#include "stats.hh"
+using namespace gem5;
+
// Defining global string variable decalred in stats.hh
std::string filename;
diff --git a/util/systemc/gem5_within_systemc/sc_gem5_control.cc b/util/systemc/gem5_within_systemc/sc_gem5_control.cc
index 253d7f8..18aec6a 100644
--- a/util/systemc/gem5_within_systemc/sc_gem5_control.cc
+++ b/util/systemc/gem5_within_systemc/sc_gem5_control.cc
@@ -59,8 +59,8 @@
friend class Gem5Control;
protected:
- CxxConfigFileBase *config_file;
- CxxConfigManager *root_manager;
+ gem5::CxxConfigFileBase *config_file;
+ gem5::CxxConfigManager *root_manager;
Gem5SystemC::Logger logger;
/** Things to do at end_of_elaborate */
@@ -87,13 +87,13 @@
void end_of_elaboration();
};
-Gem5System::Gem5System(CxxConfigManager *manager_,
+Gem5System::Gem5System(gem5::CxxConfigManager *manager_,
const std::string &system_name, const std::string &instance_name) :
manager(manager_),
systemName(system_name),
instanceName(instance_name)
{
- manager->addRenaming(CxxConfigManager::Renaming(
+ manager->addRenaming(gem5::CxxConfigManager::Renaming(
system_name, instance_name));
}
@@ -124,7 +124,7 @@
{
try {
/* Make a new System */
- SimObject *obj = manager->findObject(systemName, true);
+ gem5::SimObject *obj = manager->findObject(systemName, true);
/* Add the System's objects to the list of managed
* objects for initialisation */
@@ -142,7 +142,7 @@
manager->instantiate(false);
manager->initState();
manager->startup();
- } catch (CxxConfigManager::Exception &e) {
+ } catch (gem5::CxxConfigManager::Exception &e) {
fatal("Config problem in Gem5System: %s: %s",
e.name, e.message);
}
@@ -165,19 +165,19 @@
void
Gem5Control::setDebugFlag(const char *flag)
{
- ::setDebugFlag(flag);
+ ::gem5::setDebugFlag(flag);
}
void
Gem5Control::clearDebugFlag(const char *flag)
{
- ::clearDebugFlag(flag);
+ ::gem5::clearDebugFlag(flag);
}
void
Gem5Control::setRemoteGDBPort(unsigned int port)
{
- ::setRemoteGDBPort(port);
+ ::gem5::setRemoteGDBPort(port);
}
Gem5System *
@@ -185,7 +185,7 @@
const std::string &instance_name)
{
Gem5System *ret = new Gem5System(
- new CxxConfigManager(*(module->config_file)),
+ new gem5::CxxConfigManager(*(module->config_file)),
system_name, instance_name);
return ret;
@@ -214,10 +214,10 @@
{
SC_THREAD(run);
- cxxConfigInit();
+ gem5::cxxConfigInit();
/* Pass DPRINTF messages to SystemC */
- Trace::setDebugLogger(&logger);
+ gem5::Trace::setDebugLogger(&logger);
/* @todo need this as an option */
Gem5SystemC::setTickFrequency();
@@ -233,13 +233,14 @@
}
/* Enable keyboard interrupt, async I/O etc. */
- initSignals();
+ gem5::initSignals();
/* Enable stats */
- statistics::initSimStats();
- statistics::registerHandlers(CxxConfig::statsReset, CxxConfig::statsDump);
+ gem5::statistics::initSimStats();
+ gem5::statistics::registerHandlers(gem5::CxxConfig::statsReset,
+ gem5::CxxConfig::statsDump);
- Trace::enable();
+ gem5::Trace::enable();
config_file = new CxxIniFile();
@@ -248,13 +249,13 @@
config_filename);
}
- root_manager = new CxxConfigManager(*config_file);
+ root_manager = new gem5::CxxConfigManager(*config_file);
- CxxConfig::statsEnable();
+ gem5::CxxConfig::statsEnable();
/* Make the root object */
try {
- SimObject *root = root_manager->findObject("root", false);
+ gem5::SimObject *root = root_manager->findObject("root", false);
/* Make sure we don't traverse into root's children */
root_manager->objectsInOrder.push_back(root);
@@ -262,7 +263,7 @@
root_manager->instantiate(false);
root_manager->initState();
root_manager->startup();
- } catch (CxxConfigManager::Exception &e) {
+ } catch (gem5::CxxConfigManager::Exception &e) {
fatal("Config problem in Gem5TopLevelModule: %s: %s",
e.name, e.message);
}
@@ -277,11 +278,11 @@
void
Gem5TopLevelModule::run()
{
- GlobalSimLoopExitEvent *exit_event = NULL;
+ gem5::GlobalSimLoopExitEvent *exit_event = NULL;
exit_event = simulate();
- std::cerr << "Exit at tick " << curTick()
+ std::cerr << "Exit at tick " << gem5::curTick()
<< ", cause: " << exit_event->getCause() << '\n';
getEventQueue(0)->dump();
@@ -304,4 +305,3 @@
{
return new Gem5SystemC::Gem5Control(config_filename);
}
-
diff --git a/util/systemc/gem5_within_systemc/sc_gem5_control.hh b/util/systemc/gem5_within_systemc/sc_gem5_control.hh
index e0b6287..f74e001 100644
--- a/util/systemc/gem5_within_systemc/sc_gem5_control.hh
+++ b/util/systemc/gem5_within_systemc/sc_gem5_control.hh
@@ -55,7 +55,10 @@
#include <string>
#include <vector>
+namespace gem5
+{
class CxxConfigManager;
+} // namespace gem5
namespace Gem5SystemC
{
@@ -63,7 +66,7 @@
class Gem5TopLevelModule;
class Gem5Control;
-/** Gem5System's wrap CxxConfigManager's instantiating a gem5 System
+/** Gem5System's wrap gem5::CxxConfigManager's instantiating a gem5 System
* object (and its children). New Gem5Systems are created by
* Gem5Control::makeSystem. A new system can have its parameters
* tweaked using setParam{,Vector} before being instantiated using
@@ -85,7 +88,7 @@
private:
/** Config management for *just* this system's objects (notably
* excluding root */
- CxxConfigManager *manager;
+ gem5::CxxConfigManager *manager;
/** The config file prototype for the system */
std::string systemName;
@@ -95,7 +98,7 @@
public:
/** A constructor only used by Gem5Control */
- Gem5System(CxxConfigManager *manager_,
+ Gem5System(gem5::CxxConfigManager *manager_,
const std::string &system_name, const std::string &instance_name);
virtual ~Gem5System();
@@ -110,7 +113,7 @@
/** Build the system's gem5 infrastructure, bind its ports (note
* that all ports *must* be internal to the system), init and
- * SimObject::startup the system */
+ * gem5::SimObject::startup the system */
virtual void instantiate();
};
diff --git a/util/systemc/gem5_within_systemc/sc_logger.cc b/util/systemc/gem5_within_systemc/sc_logger.cc
index 92b82db..e184b16 100644
--- a/util/systemc/gem5_within_systemc/sc_logger.cc
+++ b/util/systemc/gem5_within_systemc/sc_logger.cc
@@ -60,9 +60,9 @@
std::ostringstream line;
/** Logger to send complete lines to */
- Trace::Logger *logger;
+ gem5::Trace::Logger *logger;
- CuttingStreambuf(Trace::Logger *logger_) : logger(logger_)
+ CuttingStreambuf(gem5::Trace::Logger *logger_) : logger(logger_)
{ }
/** Accumulate to line up to \n and then emit */
@@ -130,7 +130,7 @@
/** Log a single message as a single sc_report call */
void
-Logger::logMessage(Tick when, const std::string &name,
+Logger::logMessage(gem5::Tick when, const std::string &name,
const std::string &flag, const std::string &message)
{
/* Need to chop the newline off the message */
@@ -147,4 +147,4 @@
return stream;
}
-}
+} // namespace Gem5SystemC
diff --git a/util/systemc/gem5_within_systemc/sc_logger.hh b/util/systemc/gem5_within_systemc/sc_logger.hh
index 1f41255..cbcea31 100644
--- a/util/systemc/gem5_within_systemc/sc_logger.hh
+++ b/util/systemc/gem5_within_systemc/sc_logger.hh
@@ -53,7 +53,7 @@
{
/** sc_report logging class */
-class Logger : public Trace::Logger
+class Logger : public gem5::Trace::Logger
{
protected:
/** Stream to offer getOstream. This will cut messages up newlines and
@@ -67,7 +67,7 @@
~Logger();
/** Log a single message as a single sc_report call */
- void logMessage(Tick when, const std::string &name,
+ void logMessage(gem5::Tick when, const std::string &name,
const std::string &flag, const std::string &message) override;
std::ostream &getOstream();
diff --git a/util/systemc/gem5_within_systemc/sc_module.cc b/util/systemc/gem5_within_systemc/sc_module.cc
index 86e10e76..dcd61c7 100644
--- a/util/systemc/gem5_within_systemc/sc_module.cc
+++ b/util/systemc/gem5_within_systemc/sc_module.cc
@@ -51,6 +51,9 @@
* most one Gem5Module instantiated in any simulation.
*/
+#include <cassert>
+
+#include "base/compiler.hh"
#include "base/logging.hh"
#include "base/pollevent.hh"
#include "base/trace.hh"
@@ -70,8 +73,8 @@
void
setTickFrequency()
{
- ::setClockFrequency(1000000000000);
- ::fixClockFrequency();
+ ::gem5::setClockFrequency(1000000000000);
+ ::gem5::fixClockFrequency();
}
Module::Module(sc_core::sc_module_name name) : sc_core::sc_channel(name),
@@ -87,7 +90,7 @@
}
void
-Module::SCEventQueue::wakeup(Tick when)
+Module::SCEventQueue::wakeup(gem5::Tick when)
{
DPRINTF(Event, "waking up SCEventQueue\n");
/* Don't bother to use 'when' for now */
@@ -101,17 +104,17 @@
"Gem5SystemC::Module::setupEventQueues must be called"
" before any gem5 event queues are set up");
- numMainEventQueues = 1;
- mainEventQueue.push_back(new SCEventQueue("events", module));
- curEventQueue(getEventQueue(0));
+ gem5::numMainEventQueues = 1;
+ gem5::mainEventQueue.push_back(new SCEventQueue("events", module));
+ gem5::curEventQueue(getEventQueue(0));
}
void
Module::catchup()
{
- EventQueue *eventq = getEventQueue(0);
- Tick systemc_time = sc_core::sc_time_stamp().value();
- Tick gem5_time = curTick();
+ gem5::EventQueue *eventq = getEventQueue(0);
+ gem5::Tick systemc_time = sc_core::sc_time_stamp().value();
+ gem5::Tick gem5_time = gem5::curTick();
/* gem5 time *must* lag SystemC as SystemC is the master */
fatal_if(gem5_time > systemc_time, "gem5 time must lag SystemC time"
@@ -120,7 +123,7 @@
eventq->setCurTick(systemc_time);
if (!eventq->empty()) {
- Tick next_event_time M5_VAR_USED = eventq->nextTick();
+ gem5::Tick next_event_time M5_VAR_USED = eventq->nextTick();
fatal_if(gem5_time > next_event_time,
"Missed an event at time %d gem5: %d, SystemC: %d",
@@ -137,14 +140,14 @@
void
Module::serviceAsyncEvent()
{
- EventQueue *eventq = getEventQueue(0);
- std::lock_guard<EventQueue> lock(*eventq);
+ gem5::EventQueue *eventq = gem5::getEventQueue(0);
+ std::lock_guard<gem5::EventQueue> lock(*eventq);
assert(async_event);
/* Catch up gem5 time with SystemC time so that any event here won't
* be in the past relative to the current time */
- Tick systemc_time = sc_core::sc_time_stamp().value();
+ gem5::Tick systemc_time = sc_core::sc_time_stamp().value();
/* Move time on to match SystemC */
catchup();
@@ -158,7 +161,7 @@
if (async_exit) {
async_exit = false;
- exitSimLoop("user interrupt received");
+ gem5::exitSimLoop("user interrupt received");
}
if (async_io) {
@@ -173,7 +176,7 @@
void
Module::serviceExternalEvent()
{
- EventQueue *eventq = getEventQueue(0);
+ gem5::EventQueue *eventq = getEventQueue(0);
if (!in_simulate && !async_event)
warn("Gem5SystemC external event received while not in simulate");
@@ -188,7 +191,7 @@
void
Module::eventLoop()
{
- EventQueue *eventq = getEventQueue(0);
+ gem5::EventQueue *eventq = getEventQueue(0);
fatal_if(!in_simulate, "Gem5SystemC event loop entered while"
" outside Gem5SystemC::Module::simulate");
@@ -197,12 +200,12 @@
serviceAsyncEvent();
while (!eventq->empty()) {
- Tick next_event_time = eventq->nextTick();
+ gem5::Tick next_event_time = eventq->nextTick();
/* Move time on to match SystemC */
catchup();
- Tick gem5_time = curTick();
+ gem5::Tick gem5_time = gem5::curTick();
/* Woken up early */
if (wait_exit_time > sc_core::sc_time_stamp().value()) {
@@ -211,7 +214,7 @@
}
if (gem5_time < next_event_time) {
- Tick wait_period = next_event_time - gem5_time;
+ gem5::Tick wait_period = next_event_time - gem5_time;
wait_exit_time = gem5_time + wait_period;
DPRINTF(Event, "Waiting for %d ticks for next gem5 event\n",
@@ -224,7 +227,7 @@
return;
} else if (gem5_time > next_event_time) {
- Tick systemc_time = sc_core::sc_time_stamp().value();
+ gem5::Tick systemc_time = sc_core::sc_time_stamp().value();
/* Missed event, for some reason the above test didn't work
* or an event was scheduled in the past */
@@ -247,14 +250,15 @@
GlobalSimLoopExitEvent *
Module::simulate(Tick num_cycles)
{
- inform("Entering event queue @ %d. Starting simulation...", curTick());
+ inform("Entering event queue @ %d. Starting simulation...",
+ gem5::curTick());
- if (num_cycles < MaxTick - curTick())
- num_cycles = curTick() + num_cycles;
+ if (num_cycles < gem5::MaxTick - gem5::curTick())
+ num_cycles = gem5::curTick() + num_cycles;
else /* counter would roll over or be set to MaxTick anyhow */
- num_cycles = MaxTick;
+ num_cycles = gem5::MaxTick;
- GlobalEvent *limit_event = new GlobalSimLoopExitEvent(num_cycles,
+ gem5::GlobalEvent *limit_event = new GlobalSimLoopExitEvent(num_cycles,
"simulate() limit reached", 0, 0);
exitEvent = NULL;
@@ -277,10 +281,10 @@
in_simulate = false;
/* Locate the global exit event */
- BaseGlobalEvent *global_event = exitEvent->globalEvent();
+ gem5::BaseGlobalEvent *global_event = exitEvent->globalEvent();
assert(global_event != NULL);
- GlobalSimLoopExitEvent *global_exit_event =
+ gem5::GlobalSimLoopExitEvent *global_exit_event =
dynamic_cast<GlobalSimLoopExitEvent *>(global_event);
assert(global_exit_event != NULL);
@@ -292,4 +296,4 @@
return global_exit_event;
}
-}
+} // namespace Gem5SystemC
diff --git a/util/systemc/gem5_within_systemc/sc_module.hh b/util/systemc/gem5_within_systemc/sc_module.hh
index 7893742..4ca6afb 100644
--- a/util/systemc/gem5_within_systemc/sc_module.hh
+++ b/util/systemc/gem5_within_systemc/sc_module.hh
@@ -56,6 +56,7 @@
#include <systemc>
+#include "base/types.hh"
#include "sim/eventq.hh"
#include "sim/sim_events.hh"
@@ -93,7 +94,7 @@
sc_core::sc_event eventLoopEnterEvent;
/** Expected exit time of last eventLoop sleep */
- Tick wait_exit_time;
+ gem5::Tick wait_exit_time;
/** Are we in Module::simulate? Used to mask events when not inside
* the simulate loop */
@@ -101,18 +102,18 @@
/** Placeholder base class for a variant event queue if this becomes
* useful */
- class SCEventQueue : public EventQueue
+ class SCEventQueue : public gem5::EventQueue
{
protected:
Module &module;
public:
SCEventQueue(const std::string &name,
- Module &module_) : EventQueue(name), module(module_)
+ Module &module_) : gem5::EventQueue(name), module(module_)
{ }
/** Signal module to wakeup */
- void wakeup(Tick when);
+ void wakeup(gem5::Tick when);
};
/** Service any async event marked up in the globals event_... */
@@ -125,7 +126,7 @@
Module(sc_core::sc_module_name name);
/** Last exitEvent from eventLoop */
- Event *exitEvent;
+ gem5::Event *exitEvent;
/** Setup global event queues. Call this before any other event queues
* are created */
@@ -148,13 +149,14 @@
void eventLoop();
/** Run eventLoop up to num_cycles and return the final event */
- GlobalSimLoopExitEvent *simulate(Tick num_cycles = MaxTick);
+ gem5::GlobalSimLoopExitEvent *
+ simulate(gem5::Tick num_cycles = gem5::MaxTick);
};
/** There are assumptions throughout Gem5SystemC file that a tick is 1ps.
* Make this the case */
void setTickFrequency();
-}
+} // namespace Gem5SystemC
#endif // __SIM_SC_MODULE_HH__
diff --git a/util/systemc/gem5_within_systemc/stats.cc b/util/systemc/gem5_within_systemc/stats.cc
index 0bb3253..387a204 100644
--- a/util/systemc/gem5_within_systemc/stats.cc
+++ b/util/systemc/gem5_within_systemc/stats.cc
@@ -40,7 +40,7 @@
*
* C++-only configuration stats handling example
*
- * Register with: statistics::registerHandlers(statsReset, statsDump)
+ * Register with: gem5::statistics::registerHandlers(statsReset, statsDump)
*/
#include <iostream>
@@ -57,15 +57,15 @@
void statsPrepare()
{
- std::list<statistics::Info *> stats = statistics::statsList();
+ std::list<gem5::statistics::Info *> stats = gem5::statistics::statsList();
/* gather_stats -> prepare */
for (auto i = stats.begin(); i != stats.end(); ++i){
- statistics::Info *stat = *i;
- statistics::VectorInfo *vector =
- dynamic_cast<statistics::VectorInfo *>(stat);
+ gem5::statistics::Info *stat = *i;
+ gem5::statistics::VectorInfo *vector =
+ dynamic_cast<gem5::statistics::VectorInfo *>(stat);
if (vector){
- (dynamic_cast<statistics::VectorInfo *>(*i))->prepare();
+ (dynamic_cast<gem5::statistics::VectorInfo *>(*i))->prepare();
}
else {
(*i)->prepare();
@@ -77,11 +77,12 @@
void statsDump()
{
bool desc = true;
- statistics::Output *output = statistics::initText(filename, desc, true);
+ gem5::statistics::Output *output =
+ gem5::statistics::initText(filename, desc, true);
- statistics::processDumpQueue();
+ gem5::statistics::processDumpQueue();
- std::list<statistics::Info *> stats = statistics::statsList();
+ std::list<gem5::statistics::Info *> stats = gem5::statistics::statsList();
statsEnable();
statsPrepare();
@@ -89,32 +90,33 @@
output->begin();
/* gather_stats -> convert_value */
for (auto i = stats.begin(); i != stats.end(); ++i) {
- statistics::Info *stat = *i;
+ gem5::statistics::Info *stat = *i;
- const statistics::ScalarInfo *scalar =
- dynamic_cast<statistics::ScalarInfo *>(stat);
- statistics::VectorInfo *vector =
- dynamic_cast<statistics::VectorInfo *>(stat);
- const statistics::Vector2dInfo *vector2d =
- dynamic_cast<statistics::Vector2dInfo *>(vector);
- const statistics::DistInfo *dist =
- dynamic_cast<statistics::DistInfo *>(stat);
- const statistics::VectorDistInfo *vectordist =
- dynamic_cast<statistics::VectorDistInfo *>(stat);
- const statistics::SparseHistInfo *sparse =
- dynamic_cast<statistics::SparseHistInfo *>(stat);
- const statistics::InfoProxy <statistics::Vector2d,
- statistics::Vector2dInfo> *info =
- dynamic_cast<statistics::InfoProxy
- <statistics::Vector2d,statistics::Vector2dInfo>*>(stat);
+ const gem5::statistics::ScalarInfo *scalar =
+ dynamic_cast<gem5::statistics::ScalarInfo *>(stat);
+ gem5::statistics::VectorInfo *vector =
+ dynamic_cast<gem5::statistics::VectorInfo *>(stat);
+ const gem5::statistics::Vector2dInfo *vector2d =
+ dynamic_cast<gem5::statistics::Vector2dInfo *>(vector);
+ const gem5::statistics::DistInfo *dist =
+ dynamic_cast<gem5::statistics::DistInfo *>(stat);
+ const gem5::statistics::VectorDistInfo *vectordist =
+ dynamic_cast<gem5::statistics::VectorDistInfo *>(stat);
+ const gem5::statistics::SparseHistInfo *sparse =
+ dynamic_cast<gem5::statistics::SparseHistInfo *>(stat);
+ const gem5::statistics::InfoProxy <gem5::statistics::Vector2d,
+ gem5::statistics::Vector2dInfo> *info =
+ dynamic_cast<gem5::statistics::InfoProxy
+ <gem5::statistics::Vector2d,
+ gem5::statistics::Vector2dInfo>*>(stat);
if (vector) {
- const statistics::FormulaInfo *formula =
- dynamic_cast<statistics::FormulaInfo *>(vector);
+ const gem5::statistics::FormulaInfo *formula =
+ dynamic_cast<gem5::statistics::FormulaInfo *>(vector);
if (formula){
output->visit(*formula);
} else {
- const statistics::VectorInfo *vector1 = vector;
+ const gem5::statistics::VectorInfo *vector1 = vector;
output->visit(*vector1);
}
} else if (vector2d) {
@@ -140,19 +142,19 @@
{
std::cerr << "Stats reset\n";
- statistics::processResetQueue();
+ gem5::statistics::processResetQueue();
}
void statsEnable()
{
- std::list<statistics::Info *> stats = statistics::statsList();
+ std::list<gem5::statistics::Info *> stats = gem5::statistics::statsList();
for (auto i = stats.begin(); i != stats.end(); ++i){
- statistics::Info *stat = *i;
- statistics::VectorInfo *vector =
- dynamic_cast<statistics::VectorInfo *>(stat);
+ gem5::statistics::Info *stat = *i;
+ gem5::statistics::VectorInfo *vector =
+ dynamic_cast<gem5::statistics::VectorInfo *>(stat);
if (vector){
- (dynamic_cast<statistics::VectorInfo *>(*i))->enable();
+ (dynamic_cast<gem5::statistics::VectorInfo *>(*i))->enable();
}
else {
(*i)->enable();
diff --git a/util/systemc/systemc_within_gem5/systemc_sc_main/sc_main.cc b/util/systemc/systemc_within_gem5/systemc_sc_main/sc_main.cc
index f4c3515..51639cf 100644
--- a/util/systemc/systemc_within_gem5/systemc_sc_main/sc_main.cc
+++ b/util/systemc/systemc_within_gem5/systemc_sc_main/sc_main.cc
@@ -31,6 +31,8 @@
#include "systemc/ext/systemc"
+using namespace gem5;
+
class Printer : public sc_core::sc_module
{
public:
diff --git a/util/systemc/systemc_within_gem5/systemc_simple_object/feeder.cc b/util/systemc/systemc_within_gem5/systemc_simple_object/feeder.cc
index 7719503..6ffcab2 100644
--- a/util/systemc/systemc_within_gem5/systemc_simple_object/feeder.cc
+++ b/util/systemc/systemc_within_gem5/systemc_simple_object/feeder.cc
@@ -29,8 +29,8 @@
#include "sim/sim_exit.hh"
#include "systemc_simple_object/feeder.hh"
-Feeder::Feeder(const Gem5_FeederParams ¶ms) :
- SimObject(params), printer(params.printer), delay(params.delay),
+Feeder::Feeder(const gem5::Gem5_FeederParams ¶ms) :
+ gem5::SimObject(params), printer(params.printer), delay(params.delay),
strings(params.strings), index(0), event(this)
{
// Bind the printer objects "input" port to our sc_buffer. This will let
@@ -46,16 +46,16 @@
void
Feeder::startup()
{
- schedule(&event, curTick() + delay);
+ schedule(&event, gem5::curTick() + delay);
}
void
Feeder::feed()
{
if (index >= strings.size())
- exitSimLoop("Printed all the words.");
+ gem5::exitSimLoop("Printed all the words.");
else
buf.write(strings[index++].c_str());
- schedule(&event, curTick() + delay);
+ schedule(&event, gem5::curTick() + delay);
}
diff --git a/util/systemc/systemc_within_gem5/systemc_simple_object/feeder.hh b/util/systemc/systemc_within_gem5/systemc_simple_object/feeder.hh
index be5b3ff..c843c83 100644
--- a/util/systemc/systemc_within_gem5/systemc_simple_object/feeder.hh
+++ b/util/systemc/systemc_within_gem5/systemc_simple_object/feeder.hh
@@ -42,18 +42,21 @@
#include "systemc/ext/channel/sc_buffer.hh"
// This implementation (mostly) just uses standard gem5 mechanisms.
+namespace gem5
+{
class Gem5_FeederParams;
+} // namespace gem5
-class Feeder : public SimObject
+class Feeder : public gem5::SimObject
{
public:
- Feeder(const Gem5_FeederParams ¶ms);
+ Feeder(const gem5::Gem5_FeederParams ¶ms);
void feed();
private:
Printer *printer;
- Tick delay;
+ gem5::Tick delay;
std::vector<std::string> strings;
int index;
@@ -61,7 +64,7 @@
// except to help interact with systemc objects/models.
sc_core::sc_buffer<const char *> buf;
- EventWrapper<Feeder, &Feeder::feed> event;
+ gem5::EventWrapper<Feeder, &Feeder::feed> event;
void startup() override;
};
diff --git a/util/systemc/systemc_within_gem5/systemc_simple_object/printer.cc b/util/systemc/systemc_within_gem5/systemc_simple_object/printer.cc
index 4f15372..00a36ba 100644
--- a/util/systemc/systemc_within_gem5/systemc_simple_object/printer.cc
+++ b/util/systemc/systemc_within_gem5/systemc_simple_object/printer.cc
@@ -36,7 +36,7 @@
// systemc object could accept those parameters however it likes, for instance
// through its constructor or by assigning them to a member variable.
Printer *
-SystemC_PrinterParams::create() const
+gem5::SystemC_PrinterParams::create() const
{
Printer *printer = new Printer(name.c_str());
printer->prefix = prefix;
diff --git a/util/systemc/systemc_within_gem5/systemc_simple_object/printer.hh b/util/systemc/systemc_within_gem5/systemc_simple_object/printer.hh
index 2f2c7ff..dd49e3c 100644
--- a/util/systemc/systemc_within_gem5/systemc_simple_object/printer.hh
+++ b/util/systemc/systemc_within_gem5/systemc_simple_object/printer.hh
@@ -71,7 +71,7 @@
}
}
- statistics::Scalar numWords;
+ gem5::statistics::Scalar numWords;
// Gem5 statistics should be set up during the "end_of_elabortion"
// callback.
diff --git a/util/tlm/examples/common/cli_parser.cc b/util/tlm/examples/common/cli_parser.cc
index 841e88b..5434694 100644
--- a/util/tlm/examples/common/cli_parser.cc
+++ b/util/tlm/examples/common/cli_parser.cc
@@ -105,7 +105,7 @@
usage(prog_name);
}
}
- } catch (CxxConfigManager::Exception &e) {
+ } catch (gem5::CxxConfigManager::Exception &e) {
std::cerr << e.name << ": " << e.message << "\n";
std::exit(EXIT_FAILURE);
}
diff --git a/util/tlm/examples/common/report_handler.cc b/util/tlm/examples/common/report_handler.cc
index 7902936..4d2f8bf 100644
--- a/util/tlm/examples/common/report_handler.cc
+++ b/util/tlm/examples/common/report_handler.cc
@@ -33,8 +33,7 @@
#include <iostream>
#include <systemc>
-#include <sim/core.hh>
-#include <sim/simulate.hh>
+#include <sim/cur_tick.hh>
#include "report_handler.hh"
@@ -44,7 +43,7 @@
reportHandler(const sc_report &report, const sc_actions &actions)
{
uint64_t systemc_time = report.get_time().value();
- uint64_t gem5_time = curTick();
+ uint64_t gem5_time = gem5::curTick();
if (actions & SC_DO_NOTHING)
return;
diff --git a/util/tlm/examples/master_port/traffic_generator.cc b/util/tlm/examples/master_port/traffic_generator.cc
index 3809581..7c51fcf 100644
--- a/util/tlm/examples/master_port/traffic_generator.cc
+++ b/util/tlm/examples/master_port/traffic_generator.cc
@@ -45,7 +45,7 @@
void
TrafficGenerator::process()
{
- auto rnd = Random(time(NULL));
+ auto rnd = gem5::Random(time(NULL));
unsigned const memSize = (1 << 10); // 512 MB
diff --git a/util/tlm/src/sc_ext.cc b/util/tlm/src/sc_ext.cc
index fb9613f..19d1db8 100644
--- a/util/tlm/src/sc_ext.cc
+++ b/util/tlm/src/sc_ext.cc
@@ -38,7 +38,7 @@
namespace Gem5SystemC
{
-Gem5Extension::Gem5Extension(PacketPtr packet)
+Gem5Extension::Gem5Extension(gem5::PacketPtr packet)
{
Packet = packet;
}
@@ -56,7 +56,7 @@
return Gem5Extension::getExtension(&payload);
}
-PacketPtr Gem5Extension::getPacket()
+gem5::PacketPtr Gem5Extension::getPacket()
{
return Packet;
}
diff --git a/util/tlm/src/sc_ext.hh b/util/tlm/src/sc_ext.hh
index b370208..3f854c2 100644
--- a/util/tlm/src/sc_ext.hh
+++ b/util/tlm/src/sc_ext.hh
@@ -47,7 +47,7 @@
class Gem5Extension: public tlm::tlm_extension<Gem5Extension>
{
public:
- Gem5Extension(PacketPtr packet);
+ Gem5Extension(gem5::PacketPtr packet);
virtual tlm_extension_base* clone() const;
virtual void copy_from(const tlm_extension_base& ext);
@@ -56,10 +56,10 @@
getExtension(const tlm::tlm_generic_payload *payload);
static Gem5Extension&
getExtension(const tlm::tlm_generic_payload &payload);
- PacketPtr getPacket();
+ gem5::PacketPtr getPacket();
private:
- PacketPtr Packet;
+ gem5::PacketPtr Packet;
};
}
diff --git a/util/tlm/src/sc_master_port.cc b/util/tlm/src/sc_master_port.cc
index f17fc3f..2e10828 100644
--- a/util/tlm/src/sc_master_port.cc
+++ b/util/tlm/src/sc_master_port.cc
@@ -41,22 +41,22 @@
namespace Gem5SystemC
{
-PacketPtr
+gem5::PacketPtr
SCMasterPort::generatePacket(tlm::tlm_generic_payload& trans)
{
- Request::Flags flags;
- auto req = std::make_shared<Request>(
+ gem5::Request::Flags flags;
+ auto req = std::make_shared<gem5::Request>(
trans.get_address(), trans.get_data_length(), flags,
owner.id);
- MemCmd cmd;
+ gem5::MemCmd cmd;
switch (trans.get_command()) {
case tlm::TLM_READ_COMMAND:
- cmd = MemCmd::ReadReq;
+ cmd = gem5::MemCmd::ReadReq;
break;
case tlm::TLM_WRITE_COMMAND:
- cmd = MemCmd::WriteReq;
+ cmd = gem5::MemCmd::WriteReq;
break;
default:
SC_REPORT_FATAL("SCMasterPort",
@@ -67,23 +67,23 @@
* Allocate a new Packet. The packet will be deleted when it returns from
* the gem5 world as a response.
*/
- auto pkt = new Packet(req, cmd);
+ auto pkt = new gem5::Packet(req, cmd);
pkt->dataStatic(trans.get_data_ptr());
return pkt;
}
void
-SCMasterPort::destroyPacket(PacketPtr pkt)
+SCMasterPort::destroyPacket(gem5::PacketPtr pkt)
{
delete pkt;
}
SCMasterPort::SCMasterPort(const std::string& name_,
const std::string& systemc_name,
- ExternalMaster& owner_,
+ gem5::ExternalMaster& owner_,
Gem5SimControl& simControl)
- : ExternalMaster::ExternalPort(name_, owner_),
+ : gem5::ExternalMaster::ExternalPort(name_, owner_),
peq(this, &SCMasterPort::peq_cb),
waitForRetry(false),
pendingRequest(nullptr),
@@ -93,7 +93,8 @@
transactor(nullptr),
simControl(simControl)
{
- system = dynamic_cast<const ExternalMasterParams&>(owner_.params()).system;
+ system = dynamic_cast<const gem5::ExternalMasterParams&>(
+ owner_.params()).system;
}
void
@@ -169,7 +170,7 @@
{
// catch up with SystemC time
simControl.catchup();
- assert(curTick() == sc_core::sc_time_stamp().value());
+ assert(gem5::curTick() == sc_core::sc_time_stamp().value());
switch (phase) {
case tlm::BEGIN_REQ:
@@ -196,7 +197,7 @@
trans.acquire();
- PacketPtr pkt = nullptr;
+ gem5::PacketPtr pkt = nullptr;
Gem5Extension* extension = nullptr;
trans.get_extension(extension);
@@ -256,7 +257,7 @@
Gem5Extension* extension = nullptr;
trans.get_extension(extension);
- PacketPtr pkt = nullptr;
+ gem5::PacketPtr pkt = nullptr;
// If there is an extension, this transaction was initiated by the gem5
// world and we can pipe through the original packet.
@@ -266,15 +267,15 @@
pkt = generatePacket(trans);
}
- Tick ticks = sendAtomic(pkt);
+ gem5::Tick ticks = sendAtomic(pkt);
// send an atomic request to gem5
panic_if(pkt->needsResponse() && !pkt->isResponse(),
"Packet sending failed!\n");
// one tick is a pico second
- auto delay = sc_core::sc_time((double)(ticks / sim_clock::as_int::ps),
- sc_core::SC_PS);
+ auto delay = sc_core::sc_time(
+ (double)(ticks / gem5::sim_clock::as_int::ps), sc_core::SC_PS);
// update time
t += delay;
@@ -312,7 +313,7 @@
}
bool
-SCMasterPort::recvTimingResp(PacketPtr pkt)
+SCMasterPort::recvTimingResp(gem5::PacketPtr pkt)
{
// exclusion rule
// We need to Wait for END_RESP before sending next BEGIN_RESP
@@ -404,9 +405,9 @@
"received address range change but ignored it");
}
-ExternalMaster::ExternalPort*
+gem5::ExternalMaster::ExternalPort*
SCMasterPortHandler::getExternalPort(const std::string &name,
- ExternalMaster &owner,
+ gem5::ExternalMaster &owner,
const std::string &port_data)
{
// Create and register a new SystemC master port
diff --git a/util/tlm/src/sc_master_port.hh b/util/tlm/src/sc_master_port.hh
index 93f5194..3f01c2a 100644
--- a/util/tlm/src/sc_master_port.hh
+++ b/util/tlm/src/sc_master_port.hh
@@ -71,10 +71,10 @@
* It is assumed that the mode (atomic/timing) does not change during
* execution.
*/
-class SCMasterPort : public ExternalMaster::ExternalPort
+class SCMasterPort : public gem5::ExternalMaster::ExternalPort
{
private:
- struct TlmSenderState : public Packet::SenderState
+ struct TlmSenderState : public gem5::Packet::SenderState
{
tlm::tlm_generic_payload& trans;
TlmSenderState(tlm::tlm_generic_payload& trans)
@@ -87,7 +87,7 @@
bool waitForRetry;
tlm::tlm_generic_payload* pendingRequest;
- PacketPtr pendingPacket;
+ gem5::PacketPtr pendingPacket;
bool needToSendRetry;
@@ -95,7 +95,7 @@
Gem5MasterTransactor* transactor;
- System* system;
+ gem5::System* system;
Gem5SimControl& simControl;
@@ -113,14 +113,14 @@
tlm::tlm_dmi& dmi_data);
// Gem5 SCMasterPort interface
- bool recvTimingResp(PacketPtr pkt);
+ bool recvTimingResp(gem5::PacketPtr pkt);
void recvReqRetry();
void recvRangeChange();
public:
SCMasterPort(const std::string& name_,
const std::string& systemc_name,
- ExternalMaster& owner_,
+ gem5::ExternalMaster& owner_,
Gem5SimControl& simControl);
void bindToTransactor(Gem5MasterTransactor* transactor);
@@ -135,13 +135,13 @@
void handleBeginReq(tlm::tlm_generic_payload& trans);
void handleEndResp(tlm::tlm_generic_payload& trans);
- PacketPtr generatePacket(tlm::tlm_generic_payload& trans);
- void destroyPacket(PacketPtr pkt);
+ gem5::PacketPtr generatePacket(tlm::tlm_generic_payload& trans);
+ void destroyPacket(gem5::PacketPtr pkt);
void checkTransaction(tlm::tlm_generic_payload& trans);
};
-class SCMasterPortHandler : public ExternalMaster::Handler
+class SCMasterPortHandler : public gem5::ExternalMaster::Handler
{
private:
Gem5SimControl& control;
@@ -149,8 +149,8 @@
public:
SCMasterPortHandler(Gem5SimControl& control) : control(control) {}
- ExternalMaster::ExternalPort *
- getExternalPort(const std::string &name, ExternalMaster &owner,
+ gem5::ExternalMaster::ExternalPort *
+ getExternalPort(const std::string &name, gem5::ExternalMaster &owner,
const std::string &port_data);
};
diff --git a/util/tlm/src/sc_peq.hh b/util/tlm/src/sc_peq.hh
index f5d1b41..f488a5b 100644
--- a/util/tlm/src/sc_peq.hh
+++ b/util/tlm/src/sc_peq.hh
@@ -46,7 +46,7 @@
* transactors to schedule events in gem5.
*/
template <typename OWNER>
-class PayloadEvent : public Event
+class PayloadEvent : public gem5::Event
{
public:
OWNER& port;
@@ -88,7 +88,8 @@
* Get time from SystemC as this will always be more up to date
* than gem5's
*/
- Tick nextEventTick = sc_core::sc_time_stamp().value() + delay.value();
+ gem5::Tick nextEventTick =
+ sc_core::sc_time_stamp().value() + delay.value();
port.owner.wakeupEventQueue(nextEventTick);
port.owner.schedule(this, nextEventTick);
diff --git a/util/tlm/src/sc_slave_port.cc b/util/tlm/src/sc_slave_port.cc
index 4b1075f..21a6340 100644
--- a/util/tlm/src/sc_slave_port.cc
+++ b/util/tlm/src/sc_slave_port.cc
@@ -50,7 +50,7 @@
* information to a previously allocated tlm payload
*/
void
-packet2payload(PacketPtr packet, tlm::tlm_generic_payload &trans)
+packet2payload(gem5::PacketPtr packet, tlm::tlm_generic_payload &trans)
{
trans.set_address(packet->getAddr());
@@ -79,8 +79,8 @@
/**
* Similar to TLM's blocking transport (LT)
*/
-Tick
-SCSlavePort::recvAtomic(PacketPtr packet)
+gem5::Tick
+SCSlavePort::recvAtomic(gem5::PacketPtr packet)
{
CAUGHT_UP;
SC_REPORT_INFO("SCSlavePort", "recvAtomic hasn't been tested much");
@@ -105,7 +105,7 @@
trans->set_auto_extension(extension);
/* Execute b_transport: */
- if (packet->cmd == MemCmd::SwapReq) {
+ if (packet->cmd == gem5::MemCmd::SwapReq) {
SC_REPORT_FATAL("SCSlavePort", "SwapReq not supported");
} else if (packet->isRead()) {
transactor->socket->b_transport(*trans, delay);
@@ -130,7 +130,7 @@
* Similar to TLM's debug transport
*/
void
-SCSlavePort::recvFunctional(PacketPtr packet)
+SCSlavePort::recvFunctional(gem5::PacketPtr packet)
{
/* Prepare the transaction */
tlm::tlm_generic_payload * trans = mm.allocate();
@@ -151,7 +151,7 @@
}
bool
-SCSlavePort::recvTimingSnoopResp(PacketPtr packet)
+SCSlavePort::recvTimingSnoopResp(gem5::PacketPtr packet)
{
/* Snooping should be implemented with tlm_dbg_transport */
SC_REPORT_FATAL("SCSlavePort","unimplemented func.: recvTimingSnoopResp");
@@ -159,7 +159,7 @@
}
void
-SCSlavePort::recvFunctionalSnoop(PacketPtr packet)
+SCSlavePort::recvFunctionalSnoop(gem5::PacketPtr packet)
{
/* Snooping should be implemented with tlm_dbg_transport */
SC_REPORT_FATAL("SCSlavePort","unimplemented func.: recvFunctionalSnoop");
@@ -169,7 +169,7 @@
* Similar to TLM's non-blocking transport (AT)
*/
bool
-SCSlavePort::recvTimingReq(PacketPtr packet)
+SCSlavePort::recvTimingReq(gem5::PacketPtr packet)
{
CAUGHT_UP;
@@ -330,7 +330,7 @@
tlm::tlm_generic_payload *trans = blockingResponse;
blockingResponse = NULL;
- PacketPtr packet = Gem5Extension::getExtension(trans).getPacket();
+ gem5::PacketPtr packet = Gem5Extension::getExtension(trans).getPacket();
bool need_retry = !sendTimingResp(packet);
@@ -356,8 +356,8 @@
SCSlavePort::SCSlavePort(const std::string &name_,
const std::string &systemc_name,
- ExternalSlave &owner_) :
- ExternalSlave::ExternalPort(name_, owner_),
+ gem5::ExternalSlave &owner_) :
+ gem5::ExternalSlave::ExternalPort(name_, owner_),
blockingRequest(NULL),
needToSendRequestRetry(false),
blockingResponse(NULL),
@@ -376,9 +376,9 @@
&SCSlavePort::nb_transport_bw);
}
-ExternalSlave::ExternalPort*
+gem5::ExternalSlave::ExternalPort*
SCSlavePortHandler::getExternalPort(const std::string &name,
- ExternalSlave &owner,
+ gem5::ExternalSlave &owner,
const std::string &port_data)
{
// Create and register a new SystemC slave port
diff --git a/util/tlm/src/sc_slave_port.hh b/util/tlm/src/sc_slave_port.hh
index ef75aab..664ba01 100644
--- a/util/tlm/src/sc_slave_port.hh
+++ b/util/tlm/src/sc_slave_port.hh
@@ -52,7 +52,7 @@
* Test that gem5 is at the same time as SystemC
*/
#define CAUGHT_UP do { \
- assert(curTick() == sc_core::sc_time_stamp().value()); \
+ assert(gem5::curTick() == sc_core::sc_time_stamp().value()); \
} while (0)
/**
@@ -65,7 +65,7 @@
* original packet as a payload extension, the packet can be restored and send
* back to the gem5 world upon receiving a response from the SystemC world.
*/
-class SCSlavePort : public ExternalSlave::ExternalPort
+class SCSlavePort : public gem5::ExternalSlave::ExternalPort
{
public:
/** One instance of pe and the related callback needed */
@@ -93,12 +93,12 @@
protected:
/** The gem5 Port slave interface */
- Tick recvAtomic(PacketPtr packet);
- void recvFunctional(PacketPtr packet);
- bool recvTimingReq(PacketPtr packet);
- bool recvTimingSnoopResp(PacketPtr packet);
+ gem5::Tick recvAtomic(gem5::PacketPtr packet);
+ void recvFunctional(gem5::PacketPtr packet);
+ bool recvTimingReq(gem5::PacketPtr packet);
+ bool recvTimingSnoopResp(gem5::PacketPtr packet);
void recvRespRetry();
- void recvFunctionalSnoop(PacketPtr packet);
+ void recvFunctionalSnoop(gem5::PacketPtr packet);
Gem5SlaveTransactor* transactor;
@@ -110,14 +110,14 @@
SCSlavePort(const std::string &name_,
const std::string &systemc_name,
- ExternalSlave &owner_);
+ gem5::ExternalSlave &owner_);
void bindToTransactor(Gem5SlaveTransactor* transactor);
friend PayloadEvent<SCSlavePort>;
};
-class SCSlavePortHandler : public ExternalSlave::Handler
+class SCSlavePortHandler : public gem5::ExternalSlave::Handler
{
private:
Gem5SimControl& control;
@@ -125,8 +125,8 @@
public:
SCSlavePortHandler(Gem5SimControl& control) : control(control) {}
- ExternalSlave::ExternalPort *
- getExternalPort(const std::string &name, ExternalSlave &owner,
+ gem5::ExternalSlave::ExternalPort *
+ getExternalPort(const std::string &name, gem5::ExternalSlave &owner,
const std::string &port_data);
};
diff --git a/util/tlm/src/sim_control.cc b/util/tlm/src/sim_control.cc
index 50a2aea..c706fd9 100644
--- a/util/tlm/src/sim_control.cc
+++ b/util/tlm/src/sim_control.cc
@@ -72,28 +72,30 @@
}
instance = this;
- cxxConfigInit();
+ gem5::cxxConfigInit();
// register the systemc slave and master port handler
- ExternalSlave::registerHandler("tlm_slave", new SCSlavePortHandler(*this));
- ExternalMaster::registerHandler("tlm_master",
- new SCMasterPortHandler(*this));
+ gem5::ExternalSlave::registerHandler("tlm_slave",
+ new SCSlavePortHandler(*this));
+ gem5::ExternalMaster::registerHandler("tlm_master",
+ new SCMasterPortHandler(*this));
- Trace::setDebugLogger(&logger);
+ gem5::Trace::setDebugLogger(&logger);
Gem5SystemC::setTickFrequency();
assert(sc_core::sc_get_time_resolution()
== sc_core::sc_time(1,sc_core::SC_PS));
Gem5SystemC::Module::setupEventQueues(*this);
- initSignals();
+ gem5::initSignals();
- statistics::initSimStats();
- statistics::registerHandlers(CxxConfig::statsReset, CxxConfig::statsDump);
+ gem5::statistics::initSimStats();
+ gem5::statistics::registerHandlers(CxxConfig::statsReset,
+ CxxConfig::statsDump);
- Trace::enable();
+ gem5::Trace::enable();
- CxxConfigFileBase* conf = new CxxIniFile();
+ gem5::CxxConfigFileBase* conf = new gem5::CxxIniFile();
if (configFile.empty()) {
std::cerr << "No gem5 config file specified!\n";
@@ -105,7 +107,7 @@
std::exit(EXIT_FAILURE);
}
- config_manager = new CxxConfigManager(*conf);
+ config_manager = new gem5::CxxConfigManager(*conf);
// parse debug flags string and clear/set flags accordingly
std::stringstream ss;
@@ -114,19 +116,19 @@
while (std::getline(ss, flag, ' ')) {
if (flag.at(0) == '-') {
flag.erase(0, 1); // remove the '-'
- clearDebugFlag(flag.c_str());
+ gem5::clearDebugFlag(flag.c_str());
}
else {
- setDebugFlag(flag.c_str());
+ gem5::setDebugFlag(flag.c_str());
}
}
CxxConfig::statsEnable();
- getEventQueue(0)->dump();
+ gem5::getEventQueue(0)->dump();
try {
config_manager->instantiate();
- } catch (CxxConfigManager::Exception &e) {
+ } catch (gem5::CxxConfigManager::Exception &e) {
std::cerr << "Config problem in sim object "
<< e.name << ": " << e.message << "\n";
std::exit(EXIT_FAILURE);
@@ -139,7 +141,7 @@
try {
config_manager->initState();
config_manager->startup();
- } catch (CxxConfigManager::Exception &e) {
+ } catch (gem5::CxxConfigManager::Exception &e) {
std::cerr << "Config problem in sim object "
<< e.name << ": " << e.message << "\n";
std::exit(EXIT_FAILURE);
@@ -152,7 +154,7 @@
// notify callback
beforeSimulate();
- GlobalSimLoopExitEvent *exit_event = NULL;
+ gem5::GlobalSimLoopExitEvent *exit_event = NULL;
if (simulationEnd == 0) {
exit_event = simulate();
@@ -160,10 +162,10 @@
exit_event = simulate(simulationEnd);
}
- std::cerr << "Exit at tick " << curTick()
+ std::cerr << "Exit at tick " << gem5::curTick()
<< ", cause: " << exit_event->getCause() << '\n';
- getEventQueue(0)->dump();
+ gem5::getEventQueue(0)->dump();
// notify callback
afterSimulate();
diff --git a/util/tlm/src/sim_control.hh b/util/tlm/src/sim_control.hh
index 9cf8303..f76182e 100644
--- a/util/tlm/src/sim_control.hh
+++ b/util/tlm/src/sim_control.hh
@@ -59,10 +59,10 @@
class Gem5SimControl : public Module, public Gem5SimControlInterface
{
protected:
- CxxConfigManager* config_manager;
+ gem5::CxxConfigManager* config_manager;
Gem5SystemC::Logger logger;
- Tick simulationEnd;
+ gem5::Tick simulationEnd;
/*
* Keep track of the slave and master ports that are created by gem5
