src/arch/generic/traits.hh

/*
 * Copyright (c) 2016, 2020 ARM Limited
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 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
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 * this software without specific prior written permission.
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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/* Auxiliary structs for architecture traits. */

#ifndef __ARCH_COMMON_TRAITS_HH__
#define __ARCH_COMMON_TRAITS_HH__

#include "arch/generic/isa.hh"
#include "arch/types.hh"
#include "enums/VecRegRenameMode.hh"

/** Helper structure to get the vector register mode for a given ISA.
 * This way we implement a default 'full' mode, and only those ISA that care
 * have to actually specialise the template to forward the call to the
 * appropriate member of the ISA.
 */
template <typename ISA>
struct RenameMode
{
    static Enums::VecRegRenameMode init(const BaseISA*) { return Enums::Full; }

    static Enums::VecRegRenameMode
    mode(const TheISA::PCState&)
    { return Enums::Full; }

    /**
     * Compare the initial rename mode of two instances of the ISA.
     * Result is true by definition, as the default mode is Full.
     * */
    static bool equalsInit(const BaseISA*, const BaseISA*) { return true; }
};

#endif /* __ARCH_COMMON_TRAITS_HH__ */