| // Copyright (c) 2014,2017 ARM Limited |
| // All rights reserved |
| // |
| // The license below extends only to copyright in the software and shall |
| // not be construed as granting a license to any other intellectual |
| // property including but not limited to intellectual property relating |
| // to a hardware implementation of the functionality of the software |
| // licensed hereunder. You may use the software subject to the license |
| // terms below provided that you ensure that this notice is replicated |
| // unmodified and in its entirety in all distributions of the software, |
| // modified or unmodified, in source code or in binary form. |
| // |
| // Redistribution and use in source and binary forms, with or without |
| // modification, are permitted provided that the following conditions are |
| // met: redistributions of source code must retain the above copyright |
| // notice, this list of conditions and the following disclaimer; |
| // redistributions in binary form must reproduce the above copyright |
| // notice, this list of conditions and the following disclaimer in the |
| // documentation and/or other materials provided with the distribution; |
| // neither the name of the copyright holders nor the names of its |
| // contributors may be used to endorse or promote products derived from |
| // this software without specific prior written permission. |
| // |
| // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| // |
| // Authors: Ali Saidi |
| |
| syntax = "proto2"; |
| |
| // Put all the generated messages in a namespace |
| package ProtoMessage; |
| |
| // Packet header with the identifier describing what object captured |
| // the trace, the version of this file format, and the tick frequency |
| // for all the packet time stamps. |
| message InstHeader { |
| required string obj_id = 1; |
| required uint32 ver = 2 [default = 0]; |
| required uint64 tick_freq = 3; |
| required bool has_mem = 4; |
| } |
| |
| message Inst { |
| required uint64 pc = 1; |
| |
| // Either inst or inst_bytes must be used, but never both. That should be |
| // enforced by the oneof keyword, but that's not supported in all versions |
| // of protobuf syntax we need to work with for now. |
| optional fixed32 inst = 2; |
| optional bytes inst_bytes = 9; |
| |
| optional uint32 nodeid = 3; |
| optional uint32 cpuid = 4; |
| optional fixed64 tick = 5; |
| |
| enum InstType { |
| None = 0; |
| IntAlu = 1; |
| IntMul = 2; |
| IntDiv = 3; |
| FloatAdd = 4; |
| FloatCmp = 5; |
| FloatCvt = 6; |
| FloatMult = 7; |
| FloatDiv = 8; |
| FloatSqrt = 9; |
| SIMDIntAdd = 10; |
| SIMDIntAddAcc = 11; |
| SIMDIntAlu = 12; |
| SIMDIntCmp = 13; |
| SIMDIntCvt = 14; |
| SIMDMisc = 15; |
| SIMDIntMult = 16; |
| SIMDIntMultAcc = 17; |
| SIMDIntShift = 18; |
| SIMDIntShiftAcc = 19; |
| SIMDSqrt = 20; |
| SIMDFloatAdd = 21; |
| SIMDFloatAlu = 22; |
| SIMDFloatCmp = 23; |
| SIMDFloatCvt = 24; |
| SIMDFloatDiv = 25; |
| SIMDFloatMisc = 26; |
| SIMDFloatMult = 27; |
| SIMDFloatMultAdd = 28; |
| SIMDFloatSqrt = 29; |
| MemRead = 30; |
| MemWrite = 31; |
| IprAccess = 32; |
| InstPrefetch = 33; |
| } |
| |
| optional InstType type = 6; // add, mul, fp add, load, store, simd add, … |
| |
| // Deprecated: |
| optional uint32 inst_flags = 7; // execution mode information |
| |
| // If the operation does one or more memory accesses |
| message MemAccess { |
| required uint64 addr = 1; |
| required uint32 size = 2; |
| optional uint32 mem_flags = 3; |
| } |
| repeated MemAccess mem_access = 8; |
| } |
| |