fastmodel: Ensure unset vec reg bits are zero/false.
These bits won't be overwritten with values from IRIS, and so we should
make sure they're cleared and don't have old values or junk.
Change-Id: Ib81780ab523f00d6a4d31841d68a3d83924982a9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24327
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc b/src/arch/arm/fastmodel/iris/thread_context.cc
index f487ebc..f3b4c95 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -572,12 +572,14 @@
ThreadContext::readVecReg(const RegId ®_id) const
{
const RegIndex idx = reg_id.index();
+ ArmISA::VecRegContainer ® = vecRegs.at(idx);
+ reg.zero();
+
// Ignore accesses to registers which aren't architected. gem5 defines a
// few extra registers which it uses internally in the implementation of
// some instructions.
if (idx >= vecRegIds.size())
- return vecRegs.at(idx);
- ArmISA::VecRegContainer ® = vecRegs.at(idx);
+ return reg;
iris::ResourceReadResult result;
call().resource_read(_instId, result, vecRegIds.at(idx));
@@ -598,10 +600,12 @@
ThreadContext::readVecPredReg(const RegId ®_id) const
{
RegIndex idx = reg_id.index();
- if (idx >= vecPredRegIds.size())
- return vecPredRegs.at(idx);
ArmISA::VecPredRegContainer ® = vecPredRegs.at(idx);
+ reg.reset();
+
+ if (idx >= vecPredRegIds.size())
+ return reg;
iris::ResourceReadResult result;
call().resource_read(_instId, result, vecPredRegIds.at(idx));