commit 9e821b323334bf6611e10559cbfe29d231f0fdc6
author Gabe Black <gabe.black@gmail.com> Sun Aug 29 00:43:39 2021 -0700
committer Gabe Black <gabe.black@gmail.com> Wed Jun 08 22:11:36 2022 +0000
tree 10f1888a137113b019d7a282f05416d194288681
parent 87c2f36fa831b9530f4ad0ff7f8f2d91ae534de6

cpu: Switch to the (get|set)Reg API in the checker CPU.

Change-Id: I7ab1319ae6fc6d0d5bc62322fbe92c7131ce6403
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49777
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/cpu/checker/cpu_impl.hh

diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 61128e1..a68b6f4 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -584,19 +584,16 @@
           case InvalidRegClass:
             break;
           case IntRegClass:
-            thread->setIntReg(idx.index(), mismatch_val.as<RegVal>());
-            break;
           case FloatRegClass:
-            thread->setFloatReg(idx.index(), mismatch_val.as<RegVal>());
+          case VecElemClass:
+          case CCRegClass:
+            thread->setReg(idx, mismatch_val.as<RegVal>());
             break;
           case VecRegClass:
-            thread->setVecReg(idx, mismatch_val.as<TheISA::VecRegContainer>());
-            break;
-          case VecElemClass:
-            thread->setVecElem(idx, mismatch_val.as<RegVal>());
-            break;
-          case CCRegClass:
-            thread->setCCReg(idx.index(), mismatch_val.as<RegVal>());
+            {
+                auto val = mismatch_val.as<TheISA::VecRegContainer>();
+                thread->setReg(idx, &val);
+            }
             break;
           case MiscRegClass:
             thread->setMiscReg(idx.index(), mismatch_val.as<RegVal>());
@@ -614,19 +611,16 @@
           case InvalidRegClass:
             break;
           case IntRegClass:
-            thread->setIntReg(idx.index(), res.as<RegVal>());
-            break;
           case FloatRegClass:
-            thread->setFloatReg(idx.index(), res.as<RegVal>());
+          case VecElemClass:
+          case CCRegClass:
+            thread->setReg(idx, res.as<RegVal>());
             break;
           case VecRegClass:
-            thread->setVecReg(idx, res.as<TheISA::VecRegContainer>());
-            break;
-          case VecElemClass:
-            thread->setVecElem(idx, res.as<RegVal>());
-            break;
-          case CCRegClass:
-            thread->setCCReg(idx.index(), res.as<RegVal>());
+            {
+                auto val = res.as<TheISA::VecRegContainer>();
+                thread->setReg(idx, &val);
+            }
             break;
           case MiscRegClass:
             // Try to get the proper misc register index for ARM here...