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# -*- coding: utf-8 -*-
# Copyright (c) 2015 Jason Power
# All rights reserved.
#
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# met: redistributions of source code must retain the above copyright
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# redistributions in binary form must reproduce the above copyright
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# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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""" This file creates a system with Ruby caches and executes 'threads', a
simple multi-threaded application with false sharing to stress the Ruby
protocol.
See Part 3 in the Learning gem5 book:
http://gem5.org/documentation/learning_gem5/part3/MSIintro
IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
also needs to be updated. For now, email Jason <jason@lowepower.com>
"""
from __future__ import print_function
from __future__ import absolute_import
# import the m5 (gem5) library created when gem5 is built
import m5
# import all of the SimObjects
from m5.objects import *
# Needed for running C++ threads
m5.util.addToPath('../../')
from common.FileSystemConfig import config_filesystem
# You can import ruby_caches_MI_example to use the MI_example protocol instead
# of the MSI protocol
from msi_caches import MyCacheSystem
# create the system we are going to simulate
system = System()
# Set the clock fequency of the system (and all of its children)
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()
# Set up the system
system.mem_mode = 'timing' # Use timing accesses
system.mem_ranges = [AddrRange('512MB')] # Create an address range
# Create a pair of simple CPUs
system.cpu = [TimingSimpleCPU() for i in range(2)]
# Create a DDR3 memory controller and connect it to the membus
system.mem_ctrl = MemCtrl()
system.mem_ctrl.dram = DDR3_1600_8x8()
system.mem_ctrl.dram.range = system.mem_ranges[0]
# create the interrupt controller for the CPU and connect to the membus
for cpu in system.cpu:
cpu.createInterruptController()
# Create the Ruby System
system.caches = MyCacheSystem()
system.caches.setup(system, system.cpu, [system.mem_ctrl])
# get ISA for the binary to run.
isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
# Run application and use the compiled ISA to find the binary
# grab the specific path to the binary
thispath = os.path.dirname(os.path.realpath(__file__))
binary = os.path.join(thispath, '../../../', 'tests/test-progs/threads/bin/',
isa, 'linux/threads')
# Create a process for a simple "multi-threaded" application
process = Process()
# Set the command
# cmd is a list which begins with the executable (like argv)
process.cmd = [binary]
# Set the cpu to use the process as its workload and create thread contexts
for cpu in system.cpu:
cpu.workload = process
cpu.createThreads()
# Set up the pseudo file system for the threads function above
config_filesystem(system)
# set up the root SimObject and start the simulation
root = Root(full_system = False, system = system)
# instantiate all of the objects we've created above
m5.instantiate()
print("Beginning simulation!")
exit_event = m5.simulate()
print('Exiting @ tick {} because {}'.format(
m5.curTick(), exit_event.getCause())
)