arch-arm: Stage1&2 TableWalkers sharing same port This patch reverts part of the changes made by the removal of the Stage2MMU class [1]: Prior to that patch the stage1 and stage2 walkers were sharing the same port (which was instantiated in the Stage2MMU). By removing the Stage2MMU we provided every table walker a unique port. With this patch we are reintroducing port sharing to temporarily fix existing platforms using walker caches. (The long term design goal will be to have a unique page table walker) Those complain if we try to connect a single ported cache to 2 table walker ports (stage1 and stage2) [1]: https://gem5-review.googlesource.com/c/public/gem5/+/45780 Change-Id: Ib68ef97f1e9772a698771269c9a4ec4514f5d4d7 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48200 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/arch/arm/ArmMMU.py b/src/arch/arm/ArmMMU.py index 00a0b31..1880f6f 100644 --- a/src/arch/arm/ArmMMU.py +++ b/src/arch/arm/ArmMMU.py
@@ -65,6 +65,8 @@ itb = ArmITB() dtb = ArmDTB() + sys = Param.System(Parent.any, "system object parameter") + stage2_itb = Param.ArmTLB(ArmStage2TLB(), "Stage 2 Instruction TLB") stage2_dtb = Param.ArmTLB(ArmStage2TLB(), "Stage 2 Data TLB") @@ -80,12 +82,8 @@ @classmethod def walkerPorts(cls): - return ["mmu.itb_walker.port", "mmu.dtb_walker.port", - "mmu.stage2_itb_walker.port", "mmu.stage2_dtb_walker.port"] + return ["mmu.itb_walker.port", "mmu.dtb_walker.port"] def connectWalkerPorts(self, iport, dport): self.itb_walker.port = iport self.dtb_walker.port = dport - - self.stage2_itb_walker.port = iport - self.stage2_dtb_walker.port = dport
diff --git a/src/arch/arm/mmu.cc b/src/arch/arm/mmu.cc index 7392947..30164b6 100644 --- a/src/arch/arm/mmu.cc +++ b/src/arch/arm/mmu.cc
@@ -47,10 +47,17 @@ MMU::MMU(const ArmMMUParams &p) : BaseMMU(p), itbStage2(p.stage2_itb), dtbStage2(p.stage2_dtb), + iport(p.itb_walker, p.sys->getRequestorId(p.itb_walker)), + dport(p.dtb_walker, p.sys->getRequestorId(p.dtb_walker)), itbWalker(p.itb_walker), dtbWalker(p.dtb_walker), itbStage2Walker(p.stage2_itb_walker), dtbStage2Walker(p.stage2_dtb_walker) -{} +{ + itbWalker->setPort(&iport); + dtbWalker->setPort(&dport); + itbStage2Walker->setPort(&iport); + dtbStage2Walker->setPort(&dport); +} void MMU::init()
diff --git a/src/arch/arm/mmu.hh b/src/arch/arm/mmu.hh index f9ebeb3..a129831 100644 --- a/src/arch/arm/mmu.hh +++ b/src/arch/arm/mmu.hh
@@ -38,6 +38,7 @@ #ifndef __ARCH_ARM_MMU_HH__ #define __ARCH_ARM_MMU_HH__ +#include "arch/arm/table_walker.hh" #include "arch/arm/tlb.hh" #include "arch/generic/mmu.hh" @@ -69,6 +70,9 @@ TLB *itbStage2; TLB *dtbStage2; + TableWalker::Port iport; + TableWalker::Port dport; + TableWalker *itbWalker; TableWalker *dtbWalker; TableWalker *itbStage2Walker;
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index 5632be1..6dc00eb 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc
@@ -61,7 +61,7 @@ TableWalker::TableWalker(const Params &p) : ClockedObject(p), requestorId(p.sys->getRequestorId(this)), - port(new Port(this, requestorId)), + port(nullptr), isStage2(p.is_stage2), tlb(NULL), currState(NULL), pending(false), numSquashable(p.num_squash_per_cycle),
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh index 992e224..165a922 100644 --- a/src/arch/arm/table_walker.hh +++ b/src/arch/arm/table_walker.hh
@@ -1037,6 +1037,7 @@ void setMmu(MMU *_mmu) { mmu = _mmu; } void setTlb(TLB *_tlb) { tlb = _tlb; } + void setPort(Port *_port) { port = _port; } TLB* getTlb() { return tlb; } void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, uint8_t texcb, bool s);