cpu, arch: Replace the CCReg type with RegVal.
Most architectures weren't using the CCReg type, and in x86 and arm
it was already a uint64_t.
Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6
Reviewed-on: https://gem5-review.googlesource.com/c/14515
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index e2e8fed..d87d245 100644
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -46,9 +46,6 @@
// Locked read/write flags are can't be detected by the ISA parser
const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1;
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
// Not applicable to Alpha
using VecElem = ::DummyVecElem;
using VecReg = ::DummyVecReg;
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 8960f9f..fd59f3e 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -77,9 +77,6 @@
constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
-// condition code register; must be at least 32 bits for FpCondCodes
-typedef uint64_t CCReg;
-
// Constants Related to the number of registers
const int NumIntArchRegs = NUM_ARCH_INTREGS;
// The number of single precision floating point registers
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index 702e486..27536ba 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -283,9 +283,6 @@
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
// Not applicable to MIPS
using VecElem = ::DummyVecElem;
using VecReg = ::DummyVecReg;
diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh
index 49ea4c7..0ad0ea4 100644
--- a/src/arch/null/registers.hh
+++ b/src/arch/null/registers.hh
@@ -47,7 +47,6 @@
namespace NullISA {
-typedef uint8_t CCReg;
const RegIndex ZeroReg = 0;
// Not applicable to null
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 9d793d3..a494425 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -46,9 +46,6 @@
// be detected by it. Manually add it here.
const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1;
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
// Not applicable to Power
using VecElem = ::DummyVecElem;
using VecReg = ::DummyVecReg;
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index e2d1d15..c2e1fd2 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -64,8 +64,6 @@
using RiscvISAInst::MaxInstDestRegs;
const int MaxMiscDestRegs = 1;
-typedef uint8_t CCReg; // Not applicable to Riscv
-
// Not applicable to RISC-V
using VecElem = ::DummyVecElem;
using VecReg = ::DummyVecReg;
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index d9b182e..0c11f66 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -46,9 +46,6 @@
using SparcISAInst::MaxInstDestRegs;
using SparcISAInst::MaxMiscDestRegs;
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
// Not applicable to SPARC
using VecElem = ::DummyVecElem;
using VecReg = ::DummyVecReg;
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index ea75ec9..0590abe 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -96,8 +96,6 @@
// value
const int SyscallPseudoReturnReg = INTREG_RDX;
-typedef uint64_t CCReg;
-
// Not applicable to x86
using VecElem = ::DummyVecElem;
using VecReg = ::DummyVecReg;
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index b87fd8b..c245179 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -662,7 +662,7 @@
}
/** Records a CC register being set to a value. */
- void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
+ void setCCRegOperand(const StaticInst *si, int idx, RegVal val)
{
setScalarResult(val);
}
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 30d17bd..e32c015 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -320,7 +320,7 @@
return thread->getWritableVecPredReg(reg);
}
- CCReg
+ RegVal
readCCRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
@@ -379,7 +379,7 @@
}
void
- setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
+ setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isCCReg());
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 99506c1..0983d03 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -269,7 +269,7 @@
VecPredRegContainer& getWritableVecPredReg(const RegId& reg) override
{ return actualTC->getWritableVecPredReg(reg); }
- CCReg readCCReg(int reg_idx)
+ RegVal readCCReg(int reg_idx)
{ return actualTC->readCCReg(reg_idx); }
void
@@ -308,7 +308,7 @@
}
void
- setCCReg(int reg_idx, CCReg val)
+ setCCReg(int reg_idx, RegVal val)
{
actualTC->setCCReg(reg_idx, val);
checkerTC->setCCReg(reg_idx, val);
@@ -450,10 +450,10 @@
void setVecPredRegFlat(int idx, const VecPredRegContainer& val) override
{ actualTC->setVecPredRegFlat(idx, val); }
- CCReg readCCRegFlat(int idx)
+ RegVal readCCRegFlat(int idx)
{ return actualTC->readCCRegFlat(idx); }
- void setCCRegFlat(int idx, CCReg val)
+ void setCCRegFlat(int idx, RegVal val)
{ actualTC->setCCRegFlat(idx, val); }
};
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 87af916..1c1c895 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -74,7 +74,6 @@
public:
typedef TheISA::PCState PCState;
- typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
using VecPredRegContainer = TheISA::VecPredRegContainer;
@@ -189,8 +188,9 @@
* @{
* @name Condition Code Registers
*/
- virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
- virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0;
+ virtual RegVal readCCRegOperand(const StaticInst *si, int idx) = 0;
+ virtual void setCCRegOperand(
+ const StaticInst *si, int idx, RegVal val) = 0;
/** @} */
/**
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 051cf41..34bd71d 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -401,7 +401,7 @@
thread.getDTBPtr()->demapPage(vaddr, asn);
}
- TheISA::CCReg
+ RegVal
readCCRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
@@ -410,7 +410,7 @@
}
void
- setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val) override
+ setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isCCReg());
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 0cea748..f5aa9f7 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1379,7 +1379,7 @@
}
template <class Impl>
-CCReg
+RegVal
FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
{
ccRegfileReads++;
@@ -1429,7 +1429,7 @@
template <class Impl>
void
-FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
+FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, RegVal val)
{
ccRegfileWrites++;
regFile.setCCReg(phys_reg, val);
@@ -1508,7 +1508,7 @@
}
template <class Impl>
-CCReg
+RegVal
FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
{
ccRegfileReads++;
@@ -1572,7 +1572,7 @@
template <class Impl>
void
-FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
+FullO3CPU<Impl>::setArchCCReg(int reg_idx, RegVal val, ThreadID tid)
{
ccRegfileWrites++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 9612b36..aabac5f 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -463,7 +463,7 @@
VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx);
- TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg);
+ RegVal readCCReg(PhysRegIdPtr phys_reg);
void setIntReg(PhysRegIdPtr phys_reg, RegVal val);
@@ -475,7 +475,7 @@
void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val);
- void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val);
+ void setCCReg(PhysRegIdPtr phys_reg, RegVal val);
RegVal readArchIntReg(int reg_idx, ThreadID tid);
@@ -514,7 +514,7 @@
VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid);
- TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
+ RegVal readArchCCReg(int reg_idx, ThreadID tid);
/** Architectural register accessors. Looks up in the commit
* rename table to obtain the true physical index of the
@@ -533,7 +533,7 @@
void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
const VecElem& val, ThreadID tid);
- void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
+ void setArchCCReg(int reg_idx, RegVal val, ThreadID tid);
/** Sets the commit PC state of a specific thread. */
void pcState(const TheISA::PCState &newPCState, ThreadID tid);
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index e6dffc8..fc9abb9 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -66,7 +66,6 @@
/** Binary machine instruction type. */
typedef TheISA::MachInst MachInst;
/** Register types. */
- typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
@@ -378,7 +377,8 @@
return this->cpu->getWritableVecPredReg(this->_destRegIdx[idx]);
}
- CCReg readCCRegOperand(const StaticInst *si, int idx)
+ RegVal
+ readCCRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readCCReg(this->_srcRegIdx[idx]);
}
@@ -424,7 +424,7 @@
BaseDynInst<Impl>::setVecPredRegOperand(si, idx, val);
}
- void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
+ void setCCRegOperand(const StaticInst *si, int idx, RegVal val)
{
this->cpu->setCCReg(this->_destRegIdx[idx], val);
BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 163a13a..d2fcd07 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -65,7 +65,6 @@
{
private:
- typedef TheISA::CCReg CCReg;
using VecElem = TheISA::VecElem;
using VecRegContainer = TheISA::VecRegContainer;
using PhysIds = std::vector<PhysRegId>;
@@ -95,7 +94,7 @@
std::vector<PhysRegId> vecPredRegIds;
/** Condition-code register file. */
- std::vector<CCReg> ccRegFile;
+ std::vector<RegVal> ccRegFile;
std::vector<PhysRegId> ccRegIds;
/** Misc Reg Ids */
@@ -290,7 +289,7 @@
}
/** Reads a condition-code register. */
- CCReg
+ RegVal
readCCReg(PhysRegIdPtr phys_reg)
{
assert(phys_reg->isCCPhysReg());
@@ -365,7 +364,7 @@
/** Sets a condition-code register to the given value. */
void
- setCCReg(PhysRegIdPtr phys_reg, CCReg val)
+ setCCReg(PhysRegIdPtr phys_reg, RegVal val)
{
assert(phys_reg->isCCPhysReg());
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 1ab1a08..5a05c02 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -271,7 +271,9 @@
return getWritableVecPredRegFlat(flattenRegId(id).index());
}
- virtual CCReg readCCReg(int reg_idx) {
+ virtual RegVal
+ readCCReg(int reg_idx)
+ {
return readCCRegFlat(flattenRegId(RegId(CCRegClass,
reg_idx)).index());
}
@@ -310,7 +312,7 @@
}
virtual void
- setCCReg(int reg_idx, CCReg val)
+ setCCReg(int reg_idx, RegVal val)
{
setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
}
@@ -424,8 +426,8 @@
virtual void setVecPredRegFlat(int idx,
const VecPredRegContainer& val) override;
- virtual CCReg readCCRegFlat(int idx);
- virtual void setCCRegFlat(int idx, CCReg val);
+ virtual RegVal readCCRegFlat(int idx);
+ virtual void setCCRegFlat(int idx, RegVal val);
};
#endif
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 2f653fa..473e2e2 100644
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -247,7 +247,7 @@
}
template <class Impl>
-TheISA::CCReg
+RegVal
O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
{
return cpu->readArchCCReg(reg_idx, thread->threadId());
@@ -301,7 +301,7 @@
template <class Impl>
void
-O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
+O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, RegVal val)
{
cpu->setArchCCReg(reg_idx, val, thread->threadId());
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 3090f38..0552dc0 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -60,7 +60,6 @@
class SimpleExecContext : public ExecContext {
protected:
- typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
@@ -365,7 +364,7 @@
thread->setVecPredReg(reg, val);
}
- CCReg
+ RegVal
readCCRegOperand(const StaticInst *si, int idx) override
{
numCCRegReads++;
@@ -375,7 +374,7 @@
}
void
- setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
+ setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
{
numCCRegWrites++;
const RegId& reg = si->destRegIdx(idx);
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 5c52ba2..3dddc67 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -100,7 +100,6 @@
{
protected:
typedef TheISA::MachInst MachInst;
- typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
using VecPredRegContainer = TheISA::VecPredRegContainer;
@@ -113,7 +112,7 @@
VecRegContainer vecRegs[TheISA::NumVecRegs];
VecPredRegContainer vecPredRegs[TheISA::NumVecPredRegs];
#ifdef ISA_HAS_CC_REGS
- TheISA::CCReg ccRegs[TheISA::NumCCRegs];
+ RegVal ccRegs[TheISA::NumCCRegs];
#endif
TheISA::ISA *const isa; // one "instance" of the current ISA.
@@ -379,7 +378,8 @@
return regVal;
}
- CCReg readCCReg(int reg_idx)
+ RegVal
+ readCCReg(int reg_idx)
{
#ifdef ISA_HAS_CC_REGS
int flatIndex = isa->flattenCCIndex(reg_idx);
@@ -449,7 +449,7 @@
}
void
- setCCReg(int reg_idx, CCReg val)
+ setCCReg(int reg_idx, RegVal val)
{
#ifdef ISA_HAS_CC_REGS
int flatIndex = isa->flattenCCIndex(reg_idx);
@@ -622,13 +622,13 @@
}
#ifdef ISA_HAS_CC_REGS
- CCReg readCCRegFlat(int idx) { return ccRegs[idx]; }
- void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; }
+ RegVal readCCRegFlat(int idx) { return ccRegs[idx]; }
+ void setCCRegFlat(int idx, RegVal val) { ccRegs[idx] = val; }
#else
- CCReg readCCRegFlat(int idx)
+ RegVal readCCRegFlat(int idx)
{ panic("readCCRegFlat w/no CC regs!\n"); }
- void setCCRegFlat(int idx, CCReg val)
+ void setCCRegFlat(int idx, RegVal val)
{ panic("setCCRegFlat w/no CC regs!\n"); }
#endif
};
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index 3f5781b..d122dd6 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -108,8 +108,8 @@
// loop through the Condition Code registers.
for (int i = 0; i < TheISA::NumCCRegs; ++i) {
- TheISA::CCReg t1 = one->readCCReg(i);
- TheISA::CCReg t2 = two->readCCReg(i);
+ RegVal t1 = one->readCCReg(i);
+ RegVal t2 = two->readCCReg(i);
if (t1 != t2)
panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
i, t1, t2);
@@ -192,7 +192,7 @@
SERIALIZE_ARRAY(intRegs, NumIntRegs);
#ifdef ISA_HAS_CC_REGS
- CCReg ccRegs[NumCCRegs];
+ RegVal ccRegs[NumCCRegs];
for (int i = 0; i < NumCCRegs; ++i)
ccRegs[i] = tc.readCCRegFlat(i);
SERIALIZE_ARRAY(ccRegs, NumCCRegs);
@@ -233,7 +233,7 @@
tc.setIntRegFlat(i, intRegs[i]);
#ifdef ISA_HAS_CC_REGS
- CCReg ccRegs[NumCCRegs];
+ RegVal ccRegs[NumCCRegs];
UNSERIALIZE_ARRAY(ccRegs, NumCCRegs);
for (int i = 0; i < NumCCRegs; ++i)
tc.setCCRegFlat(i, ccRegs[i]);
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 098fe3b..a570b9a 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -95,7 +95,6 @@
{
protected:
typedef TheISA::MachInst MachInst;
- typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
using VecPredRegContainer = TheISA::VecPredRegContainer;
@@ -248,7 +247,7 @@
const = 0;
virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0;
- virtual CCReg readCCReg(int reg_idx) = 0;
+ virtual RegVal readCCReg(int reg_idx) = 0;
virtual void setIntReg(int reg_idx, RegVal val) = 0;
@@ -261,7 +260,7 @@
virtual void setVecPredReg(const RegId& reg,
const VecPredRegContainer& val) = 0;
- virtual void setCCReg(int reg_idx, CCReg val) = 0;
+ virtual void setCCReg(int reg_idx, RegVal val) = 0;
virtual TheISA::PCState pcState() = 0;
@@ -355,8 +354,8 @@
virtual void setVecPredRegFlat(int idx,
const VecPredRegContainer& val) = 0;
- virtual CCReg readCCRegFlat(int idx) = 0;
- virtual void setCCRegFlat(int idx, CCReg val) = 0;
+ virtual RegVal readCCRegFlat(int idx) = 0;
+ virtual void setCCRegFlat(int idx, RegVal val) = 0;
/** @} */
};
@@ -522,7 +521,7 @@
VecPredRegContainer& getWritableVecPredReg(const RegId& reg)
{ return actualTC->getWritableVecPredReg(reg); }
- CCReg readCCReg(int reg_idx)
+ RegVal readCCReg(int reg_idx)
{ return actualTC->readCCReg(reg_idx); }
void setIntReg(int reg_idx, RegVal val)
@@ -540,7 +539,7 @@
void setVecElem(const RegId& reg, const VecElem& val)
{ actualTC->setVecElem(reg, val); }
- void setCCReg(int reg_idx, CCReg val)
+ void setCCReg(int reg_idx, RegVal val)
{ actualTC->setCCReg(reg_idx, val); }
TheISA::PCState pcState() { return actualTC->pcState(); }
@@ -622,10 +621,10 @@
void setVecPredRegFlat(int idx, const VecPredRegContainer& val)
{ actualTC->setVecPredRegFlat(idx, val); }
- CCReg readCCRegFlat(int idx)
+ RegVal readCCRegFlat(int idx)
{ return actualTC->readCCRegFlat(idx); }
- void setCCRegFlat(int idx, CCReg val)
+ void setCCRegFlat(int idx, RegVal val)
{ actualTC->setCCRegFlat(idx, val); }
};
