commit a4dcd5856933b580e9f55bd1609e8b7412b83d9b
author Giacomo Travaglini <giacomo.travaglini@arm.com> Fri Oct 14 11:51:06 2022 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Mon Oct 17 09:00:16 2022 +0000
tree 8c128cdd54a6c8e162f12e8f9b3b8c7d578e0062
parent 21020aa778e8a26633c8820b1c89d52f0a4fff23

arch-arm: Fix QDADD/QDSUB implementation

This got broken by a recent commit [1] which converted a bitwise
OR into the boolean version. While it conceptually made sense
as the saturateOp returns a boolean value, it is not taking
into consideration that saturateOp modifies the first argument
and the boolean version short-circuits the expression preventing
the second expression from being run if the first one is true

Therefore providing an incorrect midRes value.

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/64172

Change-Id: Ibb9b3d37dcccda006006650ef759cdfe385dcfe2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64612
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>

src/arch/arm/isa/insts/data.isa

diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa
index 066a2ab..31fc172 100644
--- a/src/arch/arm/isa/insts/data.isa
+++ b/src/arch/arm/isa/insts/data.isa
@@ -342,8 +342,9 @@
         ''', flagType="none", buildCc=False)
     buildRegDataInst("qdadd", '''
             int32_t midRes;
-            resTemp = saturateOp<32>(midRes, Op2_sw, Op2_sw) ||
-                      saturateOp<32>(midRes, Op1_sw, midRes);
+            const bool res0 = saturateOp<32>(midRes, Op2_sw, Op2_sw);
+            const bool res1 = saturateOp<32>(midRes, Op1_sw, midRes);
+            resTemp = (res0 || res1) ? 1 : 0;
             Dest = midRes;
         ''', flagType="saturate", buildNonCc=False)
     buildRegDataInst("qsub", '''
@@ -377,8 +378,9 @@
         ''', flagType="none", buildCc=False)
     buildRegDataInst("qdsub", '''
             int32_t midRes;
-            resTemp = saturateOp<32>(midRes, Op2_sw, Op2_sw) ||
-                      saturateOp<32>(midRes, Op1_sw, midRes, true);
+            const bool res0 = saturateOp<32>(midRes, Op2_sw, Op2_sw);
+            const bool res1 = saturateOp<32>(midRes, Op1_sw, midRes, true);
+            resTemp = (res0 || res1) ? 1 : 0;
             Dest = midRes;
         ''', flagType="saturate", buildNonCc=False)
     buildRegDataInst("qasx", '''