arch-riscv: Update FS field of mstatus register where approriate.

Per RISC-V ISA Manual, vol II, section, page 25, the
FS field of the mstatus register encodes the status of the floating
point unit, including the floating point registers. Per page 27,
microarchitecture can choose to set the FS field to Dirty even if
the floating point unit has not been modified.

Per section 3.1.6, page 20, the FS field is located at bits 14..13
of the mstatus register.

Per section, page 27, the FS field is used for saving

Upon a system call, the Linux kernel relies on mstatus for
choosing registers to save for switching to kernel code.
In particular, if the SD bit (updating this bit is also a bug
in gem5 and will be explained in the next commit) is not set
properly due to the FS field being incorrect, the process of saving
the context and restoring the context result in the floating
point registers being zeroed out. I.e., upon the saving context
function call, the floating point registers are not saved, while
in restore context function call, the floating point registers
are overwritten with zero bits.

Previously, in gem5 RISC-V ISA, the FS field is not updated upon
floating point instruction execution. This caused issue on context
saving described above.

This change conservatively updates the FS field to Dirty on
the execution of any floating point instruction.

Change-Id: I8b3b4922e8da483cff3a2210ee80c163cace182a
Signed-off-by: Hoa Nguyen <>
Reviewed-by: Jason Lowe-Power <>
Maintainer: Jason Lowe-Power <>
Tested-by: kokoro <>
1 file changed