blob: db4d152457492a23de622efff64652ec61666c4b [file] [log] [blame]
/*
* Copyright (c) 2022 EXAscale Performance SYStems (EXAPSYS)
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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*/
#ifndef __DEV_RISCV_PCI_HOST_HH__
#define __DEV_RISCV_PCI_HOST_HH__
#include "dev/pci/host.hh"
#include "params/GenericRiscvPciHost.hh"
namespace gem5
{
class GenericRiscvPciHost : public GenericPciHost
{
private:
const uint32_t intBase;
const uint32_t intCount;
public:
PARAMS(GenericRiscvPciHost);
GenericRiscvPciHost(const GenericRiscvPciHostParams &p);
protected:
uint32_t mapPciInterrupt(const PciBusAddr &addr,
PciIntPin pin) const override;
};
}
#endif // __DEV_RISCV_PCI_HOST_HH__