arch-arm: Set CM bit in DataAbort
The CM bit in a DataAbort ISS indicates whether the Data Abort came from
a cache maintenance or address translation instruction.
Change-Id: I8888520446550581c8dd0507a8989935db7047be
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21305
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index c5858c9..b006d12 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1369,6 +1369,9 @@
// Add on the data abort specific fields to the generic abort ISS value
val = AbortFault<DataAbort>::iss();
+
+ val |= cm << 8;
+
// ISS is valid if not caused by a stage 1 page table walk, and when taken
// to AArch64 only when directed to EL2
if (!s1ptw && stage2 && (!to64 || toEL == EL2)) {
@@ -1412,6 +1415,9 @@
isv = true;
ar = val;
break;
+ case CM:
+ cm = val;
+ break;
// Just ignore unknown ID's
default:
break;
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 5e68875..645a461 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -136,6 +136,7 @@
SAS, // DataAbort: Syndrome Access Size
SSE, // DataAbort: Syndrome Sign Extend
SRT, // DataAbort: Syndrome Register Transfer
+ CM, // DataAbort: Cache Maintenance/Address Translation Op
// AArch64 only
SF, // DataAbort: width of the accessed register is SixtyFour
@@ -482,6 +483,7 @@
uint8_t sas;
uint8_t sse;
uint8_t srt;
+ uint8_t cm;
// AArch64 only
bool sf;
@@ -491,7 +493,7 @@
bool _stage2 = false, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2,
_tranMethod),
- isv(false), sas (0), sse(0), srt(0), sf(false), ar(false)
+ isv(false), sas (0), sse(0), srt(0), cm(0), sf(false), ar(false)
{}
ExceptionClass ec(ThreadContext *tc) const override;