gpu-compute: Fix ABI init for DispatchId
DispatchId should allocate two SGPRs instead of one. Allocating one was
causing all subsequent SGPR index values to be off by one, leading to
bad addresses for things like flat scratch and private segment. This
field is not used very often so it was not impacting most applications.
Change-Id: I17744e2d099fbc0447f400211ba7f8a42675ea06
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66711
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/gpu-compute/wavefront.cc b/src/gpu-compute/wavefront.cc
index 7e4b36f..8a1adfe 100644
--- a/src/gpu-compute/wavefront.cc
+++ b/src/gpu-compute/wavefront.cc
@@ -118,8 +118,10 @@
{
int regInitIdx = 0;
- // iterate over all the init fields and check which
- // bits are enabled
+ // Iterate over all the init fields and check which
+ // bits are enabled. Useful information can be found here:
+ // https://github.com/ROCm-Developer-Tools/ROCm-ComputeABI-Doc/
+ // blob/master/AMDGPU-ABI.md
for (int en_bit = 0; en_bit < NumScalarInitFields; ++en_bit) {
if (task->sgprBitEnabled(en_bit)) {
@@ -263,6 +265,12 @@
computeUnit->cu_id, simdId,
wfSlotId, wfDynId, physSgprIdx,
task->dispatchId());
+
+ // Dispatch ID in gem5 is an int. Set upper 32-bits to zero.
+ physSgprIdx
+ = computeUnit->registerManager->mapSgpr(this, regInitIdx);
+ computeUnit->srf[simdId]->write(physSgprIdx, 0);
+ ++regInitIdx;
break;
case FlatScratchInit:
physSgprIdx
