cpu: Fix VecElemClass bugs in cpu models
This patch is:
* Adding a missing VecElemClass entry
* Fixing assertion in rename map which was checking the number of free
vector registers rather than free vector element registers
* Fixing assertion in read/setVecElemOperand APIs.
* Using the right register index in SimpleThread
* Using VecElem instead of VecReg on O3 readArchVecElem
Change-Id: I265320dcbe35eb47075991301dfc99333c5190c4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15598
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 76d46e9..b9ed397 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -157,7 +157,7 @@
readVecElemOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->srcRegIdx(idx);
- assert(reg.isVecReg());
+ assert(reg.isVecElem());
return thread.readVecElem(reg);
}
@@ -268,7 +268,7 @@
const TheISA::VecElem val) override
{
const RegId& reg = si->destRegIdx(idx);
- assert(reg.isVecReg());
+ assert(reg.isVecElem());
thread.setVecElem(reg, val);
}
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 7261f0c..9e1efa1 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1410,7 +1410,7 @@
ThreadID tid) const -> const VecElem&
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
- RegId(VecRegClass, reg_idx, ldx));
+ RegId(VecElemClass, reg_idx, ldx));
return readVecElem(phys_reg);
}
diff --git a/src/cpu/o3/free_list.hh b/src/cpu/o3/free_list.hh
index 3ad08ee..e7a899c 100644
--- a/src/cpu/o3/free_list.hh
+++ b/src/cpu/o3/free_list.hh
@@ -234,6 +234,9 @@
/** Returns the number of free vector registers. */
unsigned numFreeVecRegs() const { return vecList.numFreeRegs(); }
+ /** Returns the number of free vector registers. */
+ unsigned numFreeVecElems() const { return vecElemList.numFreeRegs(); }
+
/** Returns the number of free cc registers. */
unsigned numFreeCCRegs() const { return ccList.numFreeRegs(); }
};
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 4331b6d..c5be404 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -1039,6 +1039,7 @@
fpRenameLookups++;
break;
case VecRegClass:
+ case VecElemClass:
vecRenameLookups++;
break;
case CCRegClass:
diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc
index 1194b55..d1876a9 100644
--- a/src/cpu/o3/rename_map.cc
+++ b/src/cpu/o3/rename_map.cc
@@ -161,7 +161,7 @@
/* The free list should currently be tracking register elems. */
panic_if(freeList->hasFreeVecRegs(),
"The free list is already tracking full Vec");
- panic_if(freeList->numFreeVecRegs() !=
+ panic_if(freeList->numFreeVecElems() !=
regFile->numVecElemPhysRegs() - TheISA::NumFloatRegs,
"The free list has lost vector register elements");
/* To rebuild the arch regs we take the easy road:
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 7db7d20..cbca341 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -317,7 +317,7 @@
readVecElemOperand(const StaticInst *si, int idx) const override
{
numVecRegReads++;
- const RegId& reg = si->destRegIdx(idx);
+ const RegId& reg = si->srcRegIdx(idx);
assert(reg.isVecElem());
return thread->readVecElem(reg);
}