| # Copyright (c) 2021 The Regents of the University of California |
| # All rights reserved. |
| # |
| # Redistribution and use in source and binary forms, with or without |
| # modification, are permitted provided that the following conditions are |
| # met: redistributions of source code must retain the above copyright |
| # notice, this list of conditions and the following disclaimer; |
| # redistributions in binary form must reproduce the above copyright |
| # notice, this list of conditions and the following disclaimer in the |
| # documentation and/or other materials provided with the distribution; |
| # neither the name of the copyright holders nor the names of its |
| # contributors may be used to endorse or promote products derived from |
| # this software without specific prior written permission. |
| # |
| # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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| # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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| |
| """ |
| This script creates a simple traffic generator. |
| |
| The simulator starts with a linear traffic generator, and ends with a random |
| traffic generator. |
| """ |
| |
| import m5 |
| |
| from m5.objects import Root |
| |
| import sys |
| import os |
| |
| # This is a lame hack to get the imports working correctly. |
| # TODO: This needs fixed. |
| sys.path.append( |
| os.path.join( |
| os.path.dirname(os.path.abspath(__file__)), |
| os.pardir, |
| os.pardir, |
| os.pardir, |
| ) |
| ) |
| |
| from components_library.boards.test_board import TestBoard |
| from components_library.cachehierarchies.classic.no_cache import NoCache |
| from components_library.memory.single_channel import SingleChannelDDR3_1600 |
| from components_library.processors.complex_generator import ComplexGenerator |
| |
| # This setup does not require a cache heirarchy. We therefore use the `NoCache` |
| # setup. |
| cache_hierarchy = NoCache() |
| |
| # We test a Single Channel DDR3_1600. |
| memory = SingleChannelDDR3_1600(size="512MiB") |
| |
| cmxgen = ComplexGenerator(num_cores=1) |
| cmxgen.add_linear(rate="100GB/s") |
| cmxgen.add_random(block_size=32, rate="50MB/s") |
| |
| # We use the Test Board. This is a special board to run traffic generation |
| # tasks |
| motherboard = TestBoard( |
| clk_freq="3GHz", |
| processor=cmxgen, # We pass the traffic generator as the processor. |
| memory=memory, |
| cache_hierarchy=cache_hierarchy, |
| ) |
| |
| motherboard.connect_things() |
| |
| root = Root(full_system=False, system=motherboard) |
| |
| m5.instantiate() |
| |
| cmxgen.start_traffic() |
| print("Beginning simulation!") |
| exit_event = m5.simulate() |
| print( |
| "Exiting @ tick {} because {}.".format(m5.curTick(), exit_event.getCause()) |
| ) |
| cmxgen.start_traffic() |
| print("The Linear taffic has finished. Swiching to random traffic!") |
| exit_event = m5.simulate() |
| print( |
| "Exiting @ tick {} because {}.".format(m5.curTick(), exit_event.getCause()) |
| ) |