| # Copyright (c) 2010, 2017-2018, 2022 ARM Limited |
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| # |
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| # modified or unmodified, in source code or in binary form. |
| # |
| # Copyright (c) 2006-2007 The Regents of The University of Michigan |
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| |
| from m5.SimObject import SimObject |
| from m5.params import * |
| |
| |
| class OpClass(Enum): |
| vals = [ |
| "No_OpClass", |
| "IntAlu", |
| "IntMult", |
| "IntDiv", |
| "FloatAdd", |
| "FloatCmp", |
| "FloatCvt", |
| "FloatMult", |
| "FloatMultAcc", |
| "FloatDiv", |
| "FloatMisc", |
| "FloatSqrt", |
| "SimdAdd", |
| "SimdAddAcc", |
| "SimdAlu", |
| "SimdCmp", |
| "SimdCvt", |
| "SimdMisc", |
| "SimdMult", |
| "SimdMultAcc", |
| "SimdShift", |
| "SimdShiftAcc", |
| "SimdDiv", |
| "SimdSqrt", |
| "SimdFloatAdd", |
| "SimdFloatAlu", |
| "SimdFloatCmp", |
| "SimdFloatCvt", |
| "SimdFloatDiv", |
| "SimdFloatMisc", |
| "SimdFloatMult", |
| "SimdFloatMultAcc", |
| "SimdFloatSqrt", |
| "SimdReduceAdd", |
| "SimdReduceAlu", |
| "SimdReduceCmp", |
| "SimdFloatReduceAdd", |
| "SimdFloatReduceCmp", |
| "SimdAes", |
| "SimdAesMix", |
| "SimdSha1Hash", |
| "SimdSha1Hash2", |
| "SimdSha256Hash", |
| "SimdSha256Hash2", |
| "SimdShaSigma2", |
| "SimdShaSigma3", |
| "SimdPredAlu", |
| "Matrix", |
| "MatrixMov", |
| "MatrixOP", |
| "MemRead", |
| "MemWrite", |
| "FloatMemRead", |
| "FloatMemWrite", |
| "IprAccess", |
| "InstPrefetch", |
| ] |
| |
| |
| class OpDesc(SimObject): |
| type = "OpDesc" |
| cxx_header = "cpu/func_unit.hh" |
| cxx_class = "gem5::OpDesc" |
| |
| opClass = Param.OpClass("type of operation") |
| opLat = Param.Cycles(1, "cycles until result is available") |
| pipelined = Param.Bool( |
| True, |
| "set to true when the functional unit for" |
| "this op is fully pipelined. False means not pipelined at all.", |
| ) |
| |
| |
| class FUDesc(SimObject): |
| type = "FUDesc" |
| cxx_header = "cpu/func_unit.hh" |
| cxx_class = "gem5::FUDesc" |
| |
| count = Param.Int("number of these FU's available") |
| opList = VectorParam.OpDesc("operation classes for this FU type") |