| # -*- mode:python -*- |
| |
| # Copyright (c) 2006 The Regents of The University of Michigan |
| # All rights reserved. |
| # |
| # Redistribution and use in source and binary forms, with or without |
| # modification, are permitted provided that the following conditions are |
| # met: redistributions of source code must retain the above copyright |
| # notice, this list of conditions and the following disclaimer; |
| # redistributions in binary form must reproduce the above copyright |
| # notice, this list of conditions and the following disclaimer in the |
| # documentation and/or other materials provided with the distribution; |
| # neither the name of the copyright holders nor the names of its |
| # contributors may be used to endorse or promote products derived from |
| # this software without specific prior written permission. |
| # |
| # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| # |
| # Authors: Nathan Binkert |
| |
| Import('*') |
| |
| SimObject('ClockedObject.py') |
| SimObject('TickedObject.py') |
| SimObject('Root.py') |
| SimObject('ClockDomain.py') |
| SimObject('VoltageDomain.py') |
| SimObject('System.py') |
| SimObject('DVFSHandler.py') |
| SimObject('SubSystem.py') |
| |
| Source('arguments.cc') |
| Source('async.cc') |
| Source('backtrace_%s.cc' % env['BACKTRACE_IMPL']) |
| Source('core.cc') |
| Source('tags.cc') |
| Source('cxx_config.cc') |
| Source('cxx_manager.cc') |
| Source('cxx_config_ini.cc') |
| Source('debug.cc') |
| Source('py_interact.cc', skip_no_python=True) |
| Source('eventq.cc') |
| Source('global_event.cc') |
| Source('init.cc', skip_no_python=True) |
| Source('init_signals.cc') |
| Source('main.cc', main=True, skip_lib=True) |
| Source('root.cc') |
| Source('serialize.cc') |
| Source('drain.cc') |
| Source('sim_events.cc') |
| Source('sim_object.cc') |
| Source('sub_system.cc') |
| Source('ticked_object.cc') |
| Source('simulate.cc') |
| Source('stat_control.cc') |
| Source('stat_register.cc', skip_no_python=True) |
| Source('clock_domain.cc') |
| Source('voltage_domain.cc') |
| Source('se_signal.cc') |
| Source('linear_solver.cc') |
| Source('system.cc') |
| Source('dvfs_handler.cc') |
| Source('clocked_object.cc') |
| Source('mathexpr.cc') |
| |
| if env['TARGET_ISA'] != 'null': |
| SimObject('InstTracer.py') |
| SimObject('Process.py') |
| Source('aux_vector.cc') |
| Source('faults.cc') |
| Source('process.cc') |
| Source('fd_array.cc') |
| Source('fd_entry.cc') |
| Source('pseudo_inst.cc') |
| Source('syscall_emul.cc') |
| Source('syscall_desc.cc') |
| |
| if env['TARGET_ISA'] != 'x86': |
| Source('microcode_rom.cc') |
| |
| DebugFlag('Checkpoint') |
| DebugFlag('Config') |
| DebugFlag('CxxConfig') |
| DebugFlag('Drain') |
| DebugFlag('Event') |
| DebugFlag('Fault') |
| DebugFlag('Flow') |
| DebugFlag('IPI') |
| DebugFlag('IPR') |
| DebugFlag('Interrupt') |
| DebugFlag('Loader') |
| DebugFlag('PseudoInst') |
| DebugFlag('Stack') |
| DebugFlag('SyscallBase') |
| DebugFlag('SyscallVerbose') |
| DebugFlag('TimeSync') |
| DebugFlag('Thread') |
| DebugFlag('Timer') |
| DebugFlag('VtoPhys') |
| DebugFlag('WorkItems') |
| DebugFlag('ClockDomain') |
| DebugFlag('VoltageDomain') |
| DebugFlag('DVFS') |
| |
| CompoundFlag('SyscallAll', [ 'SyscallBase', 'SyscallVerbose']) |
